Semiconductor device and forming method thereof

Abstract

A semiconductor device is formed by bonding a first semiconductor die and a second semiconductor die with bonding vias in the second semiconductor die at bonding pads in the first semiconductor die and by bonding dielectric layers in the first semiconductor die and in the second semiconductor die. Bonding pads are omitted from the second semiconductor device, but bonding vias are used to bond the first semiconductor die and the second semiconductor die, providing a greater amount of spacing between the bonding vias of the second semiconductor die because the bonding vias have a smaller width than the bonding pads. This enables a greater amount of dielectric material of the dielectric layer of the second semiconductor device to be placed between the bond vias without (or to a minimum) increase in the lateral dimension of the second semiconductor die. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Bonding in the semiconductor industry is a technique that can be used to form stacked semiconductor devices and three-dimensional integrated circuits. Some examples of bonding include wafer-to-wafer bonding, die-to-wafer bonding, and die-to-die bonding, among others. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, comprising: a first semiconductor die, comprising a first bonding structure, wherein the first bonding structure comprises: a first plurality of dielectric layers; and a first bonding through-hole included in the first plurality of dielectric layers; and a second semiconductor die, comprising a second bonding structure, wherein the second bonding structure comprises: a second plurality of dielectric layers; a second bonding through-hole included in the second plurality of dielectric layers; and a bonding pad included in the second plurality of dielectric layers, wherein the first semiconductor die and the second semiconductor die are bonded at a first bonding surface of the first bonding through-hole and a second bonding surface of the bonding pad, wherein the entire first bonding surface is bonded to the second bonding surface, and wherein less than the entire second bonding surface is bonded to the first bonding surface.

[0004] Some other embodiments of the present application provide a semiconductor device, comprising: a first semiconductor die, comprising: a first device layer; a first interconnect structure, located above the first device layer, comprising a first metal layer; and a first bonding structure, located above the first interconnect structure, comprising: a first plurality of dielectric layers; and a first bonding via, included in the first plurality of dielectric layers, wherein the first bonding via is located above the first metal layer and coupled to the first metal layer; and a second semiconductor die, comprising: a second device layer; a second interconnect structure, located below the second device layer, comprising a second metal layer; and a second bonding structure, located below the second interconnect structure, comprising: a second plurality of dielectric layers; a second bonding via, included in the second plurality of dielectric layers, wherein the second bonding via is coupled to the second metal layer; and a bonding pad, included in the second plurality of dielectric layers, wherein the bonding pad is located below the second bonding via and coupled to the second bonding via, wherein the first semiconductor die and the second semiconductor die are bonded at the first bonding via and the bonding pad, and wherein a bonding surface area of ​​the bonding pad is greater than a bonding surface area of ​​the first bonding via.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: providing a first semiconductor die, the first semiconductor die comprising a first bonding through-hole located in a first plurality of dielectric layers of the first semiconductor die; providing a second semiconductor die, the second semiconductor die comprising a second bonding through-hole located in a second plurality of dielectric layers of the second semiconductor die and a bonding pad coupled to the second bonding through-hole; aligning the first semiconductor die and the second semiconductor die so that a first bonding surface of the first bonding through-hole is located within a second perimeter of a second bonding surface of the bonding pad, and so that a first perimeter of the first bonding surface and a second perimeter of the second bonding surface partially overlap; and after aligning the first semiconductor die and the second semiconductor die, bonding the first semiconductor die and the second semiconductor die at the first bonding surface and the second bonding surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 and FIG. 2A to FIG. 2C is a diagram of an example of a semiconductor device described herein.

[0008] FIG. 3A to FIG. 3J is a diagram of an exemplary embodiment of forming a semiconductor die described herein.

[0009] 4A to 4F is a diagram of an exemplary embodiment of forming a semiconductor die described herein.

[0010] Figure 5A and Figure 5B are diagrams of exemplary embodiments of forming semiconductor devices described herein.

[0011] FIG. 6A to FIG. 6C is a diagram of an exemplary embodiment of a semiconductor die bonding via and a semiconductor die bonding pad as described herein.

[0012] 7A to 7C is a diagram of an exemplary embodiment of a semiconductor die bonding via and a semiconductor die bonding pad as described herein.

[0013] FIG. 8A to FIG. 8E is a diagram of an exemplary embodiment of a semiconductor die bonding via and a semiconductor die bonding pad as described herein.

[0014] 9A to 9Cis a diagram of an exemplary embodiment of a semiconductor die bonding via and a semiconductor die bonding pad as described herein.

[0015] FIG. 10A to FIG. 10C is a diagram of an exemplary embodiment of a semiconductor die bonding via and a semiconductor die bonding pad as described herein.

[0016] Fig.11 is a flow chart of an exemplary process associated with forming the semiconductor devices described herein. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] Bonding pads and bonding vias are widely used to bond semiconductor dies. The bonding of the first semiconductor die to the second semiconductor die can be achieved by bonding a bonding pad on the first semiconductor die to a bonding pad on the second semiconductor die to form a metal-to-metal bond and by bonding a dielectric layer surrounding the bonding pads on the first semiconductor die and the second semiconductor die to form a dielectric-to-dielectric bond.

[0020] As semiconductor processing nodes advance, the spacing between adjacent bonding pads on a semiconductor die may decrease. In some instances, the reduced spacing between adjacent bonding pads on a semiconductor die may cause undesirable and / or undesirable electrical effects, such as electrical coupling between adjacent bonding pads. Such electrical coupling may result in increased parasitic capacitance in the semiconductor die and / or another type of performance degradation in the semiconductor die.

[0021] In some embodiments described herein, a semiconductor device is formed by joining a first semiconductor die and a second semiconductor die at a bonding pad in the first semiconductor die with a bonding via in the second semiconductor die and by joining dielectric layers in the first semiconductor die and in the second semiconductor die. The first semiconductor die may include a shielding grid around the bonding pads of the first semiconductor die. The shielding grid provides electrical isolation for the bonding pads of the first semiconductor die, which makes the electrical coupling between the bonding pads of the first semiconductor die less than if the shielding grid is not included.

[0022] The bonding vias of the second semiconductor die may have a size and / or shape that is different from the size and / or shape of the bonding pads of the first semiconductor die. For example, the bonding vias of the second semiconductor die may have a width that is less than the width of the bonding pads of the first semiconductor die. Omitting the bonding pads from the second semiconductor device and instead using bonding vias to bond the first semiconductor die and the second semiconductor die provides a greater amount of spacing between the bonding vias of the second semiconductor die because the bonding vias have a smaller width than the bonding pads. This enables a greater amount of dielectric material of the dielectric layer of the second semiconductor device to be placed between the bonding vias without (or minimally) increasing the lateral dimensions of the second semiconductor die. The increased spacing between the bonding vias of the second semiconductor die reduces the electrical coupling between the bonding vias of the second semiconductor die without using another shielding grid in the second semiconductor die. Therefore, the increased spacing between the bonding vias of the second semiconductor die enables the use of a less complex manufacturing process to achieve reduced electrical coupling between the bonding vias of the second semiconductor die.

[0023] Additionally and / or optionally, different sizes of the bonding pads of the first semiconductor die and the bonding vias of the second semiconductor die provide greater flexibility and a larger process window for aligning the bonding pads of the first semiconductor die and the bonding vias of the second semiconductor die for bonding. This can reduce the rate and / or likelihood of defect formation for bonding semiconductor dies and / or can increase the bonding yield for bonding semiconductor dies.

[0024] Figure 1 and FIG. 2A to FIG. 2C is a diagram of an example of a semiconductor device 200 described herein. Figure 1An exemplary embodiment of forming a semiconductor device 200 by bonding a semiconductor wafer 202 and a semiconductor wafer 204 is shown. For example, a bonding operation may be performed using a bonding tool to bond the semiconductor wafer 202 and the semiconductor wafer 204 by forming a metal-to-metal bond and / or a dielectric-to-dielectric bond between the semiconductor wafer 202 and the semiconductor wafer 204. In the bonding operation, the semiconductor die 206 on the semiconductor wafer 202 is bonded to the associated semiconductor die 208 on the semiconductor wafer 204 to form the semiconductor device 200 (e.g., a stacked semiconductor device). The semiconductor device 200 is then diced and packaged. Other processing steps may be performed to form the semiconductor device 200.

[0025] like Figure 1 As shown in , semiconductor die 206 and semiconductor die 208 can be bonded at bonding interface 210, so that semiconductor die 206 and semiconductor die 208 are stacked or arranged vertically in the semiconductor device 200 in the z direction. Semiconductor die 206 may include a SoC die, such as a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a digital signal processing (DSP) die, an application-specific integrated circuit (ASIC) die, and / or another type of SoC die. Additionally and / or optionally, semiconductor die 206 may include a memory die, an input / output (I / O) die, a pixel sensor die, and / or another type of semiconductor die. The memory die may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, a NAND die, a high bandwidth memory (HBM) die, and / or another type of memory die. Semiconductor die 208 may include a semiconductor die of the same type as semiconductor die 206, or may include a semiconductor die of a different type.

[0026] like Figure 1 As further shown in FIG. 2 , semiconductor die 206 may include device layer 212, and semiconductor die 208 may include device layer 214. Semiconductor die 206 may include interconnect structure 216 above device layer 212. Semiconductor die 208 may include interconnect structure 218 below device layer 214. Bonding interface 210 may be located between interconnect structures 216 and 218.

[0027] Figure 2A A cross-sectional view of semiconductor device 200 is shown, showing details of device layers 212 and 214 and details of interconnect structures 216 and 218 . Figure 2AAlso shown are details of bonding structure 220 of semiconductor die 206 and bonding structure 222 of semiconductor die 208. Bonding structure 220 may be included above interconnect structure 216 of semiconductor die 206, and bonding structure 222 may be included below interconnect structure 218 of semiconductor die 208. Bonding interface 210 may be located between bonding structure 220 and bonding structure 222.

[0028] like Figure 2A , the device layer 212 of the semiconductor die 206 includes a substrate 224. The substrate 224 corresponds to a portion of the semiconductor wafer 202 on which the semiconductor die 206 is formed. The substrate 224 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, or another type of semiconductor substrate. The substrate 224 can extend in the semiconductor die 206 in the x-direction and / or in the y-direction.

[0029] Semiconductor die 206 includes integrated circuit devices 226 in and / or on substrate 224. Integrated circuit devices 226 may include active devices, passive devices, and / or another type of integrated circuit device. Examples of active devices include transistors (e.g., planar transistors, fin field effect transistors (finFETs), gate-all-around (GAA) transistors), pixel sensors, modulators, photodetectors, transceivers, and / or transmitters, among other examples. Examples of passive devices include capacitors, resistors, and / or inductors, among other examples.

[0030] A dielectric layer 228 is included over the substrate 224. The dielectric layer 228 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or another type of dielectric layer. The dielectric layer 228 includes a dielectric material that enables selective etching of the substrate 224 and / or various portions of the integrated circuit device 226 or protects the substrate 224 and / or various portions of the integrated circuit device 226 from etching, and / or electrically isolates the integrated circuit device 226 in the device layer 212. The dielectric layer 228 includes silicon nitride (Si x N y ), oxides (e.g., silicon oxide (SiO x ) and / or another oxide material) and / or another type of dielectric material. Dielectric layer 228 may extend in semiconductor die 206 in the x-direction and / or in the y-direction.

[0031] The interconnect structure 216 of the semiconductor die 206 is included on the substrate 224 and on the integrated circuit device 226. In some embodiments, one or more integrated circuit devices 226 are included in the interconnect structure 216 (e.g., memory devices, resistors, capacitors, radio frequency (RF) switches, optical modulators, waveguides). The interconnect structure 216 includes a plurality of dielectric layers arranged in a direction approximately perpendicular to the substrate 224 (e.g., the z-direction). The dielectric layers may include ILD layers 230 and ESL 232 arranged in an alternating manner in the z-direction. The ILD layers 230 may each include an oxide (e.g., silicon oxide (SiO x ) and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorine silicate glass (FSG), and / or another suitable dielectric material. In some embodiments, the ILD layer 230 includes an extremely low dielectric constant (ELK) dielectric material having a dielectric constant of less than about 2.5. The ESL 232 may each include silicon nitride (Si x N y ), silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some embodiments, the ILD layer 230 and the ESL 232 include different dielectric materials to provide etch selectivity to enable formation of various structures in the interconnect structure 216. The ILD layer 230 and the ESL 232 can extend in the semiconductor die 206 in the x-direction and / or in the y-direction.

[0032] The interconnect structure 216 includes a plurality of metallization layers 234. The metallization layers 234 are electrically coupled and / or physically coupled to one or more of the integrated circuit devices 226 in the device layer 212 and / or the interconnect structure 216. The metallization layers 234 correspond to circuits that enable signals and / or power to be provided to and / or provided from the integrated circuit devices 226. Each of the metallization layers 234 includes a through hole, a trench, a contact, a plug, an interconnect, and / or another type of conductive structure. Each of the metallization layers 234 includes one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof and other examples of conductive materials.

[0033] In some embodiments, the metallization layers 234 of the interconnect structure 216 can be arranged in a vertical manner (e.g., in the z-direction). In other words, multiple stacked metallization layers 234 extend between the device layer 212 and the bonding structure 220 to facilitate routing of electrical signals and / or power between the device layer 212 and the semiconductor die 208. The multiple stacked metallization layers 234 can be referred to as M layers. For example, a metal 0 (M0) layer can be located at the bottom of the interconnect structure 216 and can be directly coupled to the device layer 212 (e.g., to a contact or interconnect of an integrated circuit device 226 in the device layer 212), a metal 1 layer (M1) layer can be located above the M0 layer in the interconnect structure 216, a metal 2 layer (M2) layer can be located above the M1 layer, and so on. In some embodiments, the interconnect structure 216 includes nine (9) stacked metallization layers 234 (e.g., M0-M8). In some embodiments, the interconnect structure 216 includes another number of stacked metallization layers 234.

[0034] like Figure 2A As further shown in FIG. 1 , the interconnect structure 216 may include an ESL 236 above and / or on the topmost ILD layer 230 and a dielectric layer 238 above and / or on the ESL 236. The ESL 236 may include silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and / or another nitride-containing dielectric material. Dielectric layer 238 may include one or more ELK dielectric materials, such as carbon-doped silicon oxide (C-SiO x ), amorphous fluorinated carbon (aC x F y ), polyparaxylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE) and / or silicon oxycarbide (SiOC) polymer. In some embodiments, the ELK dielectric material used for dielectric layer 238 includes porous hydrogen silsesquioxane (HSQ), porous methyl silsesquioxane (MSQ), porous polyarylether (PAE) and / or porous silicon oxide (SiO x ) and other examples. Additionally and / or alternatively, the dielectric layer 238 may include silicon oxide (SiO x , such as SiO2), USG, BSG and / or another suitable dielectric material.

[0035] Metal interconnect 240 is included in and / or extends through ESL 236 and dielectric layer 238. Metal interconnect 240 is electrically and / or physically coupled to one or more metallization layers 234 in interconnect structure 216. Metal layer 242 is electrically and / or physically coupled to metal interconnect 240. Metal layer 242 is also included in dielectric layer 238.

[0036] Bonding structure 220 includes a plurality of dielectric layers 244-250 located above and / or on dielectric layer 238 and / or above and / or on metal layer 242. Dielectric layer 244 may be included above and / or on dielectric layer 238, dielectric layer 246 may be included above and / or on dielectric layer 244, dielectric layer 248 may be included above and / or on dielectric layer 246, and dielectric layer 250 may be included above and / or on dielectric layer 248. Bonding dielectric layer 252 may be included in bonding structure 220 above and / or on dielectric layer 250.

[0037] Dielectric layers 244 and 248 may be included in bonding structure 220 as ESL. Dielectric layers 244 and 248 may each include a carbon-containing dielectric material, such as silicon carbide (SiC). Additionally and / or alternatively, dielectric layer 244 and / or dielectric layer 248 may include another dielectric material. Dielectric layer 246 may include a high density plasma (HDP) dielectric material and / or another suitable dielectric material. Dielectric layer 250 may include a nitride-containing dielectric material, such as silicon nitride (SiC). x N y , such as Si3N4), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and / or another nitride-containing dielectric material. The bonding dielectric layer 252 may include silicon oxynitride (SiON) and / or another suitable bonding dielectric material.

[0038] The bonding vias 254 extend through and / or are included in the dielectric layers 244-250 and the bonding dielectric layer 252. The bonding vias 254 are electrically and / or physically coupled to the metal layer 242. Each of the bonding vias 254 includes a via, an interconnect, a conductive column, a plug, and / or another type of elongated conductive structure. Each of the bonding vias 254 includes one or more conductive metals, such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), gold (Au), and / or combinations thereof and other examples of conductive materials.

[0039] The z-direction thickness of the bonding via 254 may be greater than the x-direction and / or y-direction width of the bonding via 254. For example, the z-direction thickness of the bonding via 254 may be at least two times greater than the x-direction and / or y-direction width of the bonding via 254.

[0040] like Figure 2A As further shown in FIG. 2 , device layer 214 of semiconductor die 208 includes substrate 256. Substrate 256 corresponds to a portion of semiconductor wafer 204 on which semiconductor die 208 is formed. Substrate 256 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of semiconductor substrate. Substrate 256 may extend in the semiconductor die 208 in the x-direction and / or in the y-direction.

[0041] Semiconductor device 258 is included in and / or below substrate 256 in device layer 214 of semiconductor die 208. Semiconductor device 258 includes a transistor (e.g., a planar transistor, a finFET, a GAA transistor), a pixel sensor, a capacitor, a resistor, an inductor, a photodetector, a transceiver, a transmitter, a receiver, an optical circuit, and / or another type of semiconductor device.

[0042] A dielectric layer 260 is included below the substrate 256. The dielectric layer 260 includes an ILD layer, an ESL, and / or another type of dielectric layer. The dielectric layer 260 includes a dielectric material that enables selective etching of the substrate 256 and / or various portions of the semiconductor device 258 or protects the substrate 256 and / or various portions of the semiconductor device 258 from etching, and / or electrically isolates the semiconductor device 258 in the device layer 214. The dielectric layer 260 includes silicon nitride (Si x N y ), oxides (e.g., silicon oxide (SiO x ) and / or another oxide material) and / or another type of dielectric material.

[0043] The interconnect structure 218 of the semiconductor die 208 is included below / under the substrate 256 and below the semiconductor device 258. In some embodiments, one or more semiconductor devices 258 are included in the interconnect structure 218 (e.g., memory devices, resistors, capacitors, RF switches, optical modulators, waveguides). The interconnect structure 218 includes a plurality of dielectric layers arranged in a direction approximately perpendicular to the substrate 256. The dielectric layers may include ILD layers 262 and ESL 264 arranged in an alternating manner in the z-direction in the semiconductor die 208. The ILD layers 262 may each include an oxide (e.g., silicon oxide (SiO x ) and / or another oxide material), USG, BSG, FSG and / or another suitable dielectric material. In some embodiments, the ILD layer 262 includes an ELK dielectric material having a dielectric constant of less than about 2.5. The ESL 264 may each include silicon nitride (Si x Ny ), silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some embodiments, ILD layer 262 and ESL 264 include different dielectric materials to provide etch selectivity to enable formation of various structures in interconnect structure 218. ILD layer 262 and ESL 264 can extend in the semiconductor die 208 in the x-direction and / or in the y-direction.

[0044] The interconnect structure 218 includes a plurality of metallization layers 266. The metallization layers 266 are electrically coupled and / or physically coupled to one or more of the semiconductor devices 258 in the device layer 214 and / or the interconnect structure 218. The metallization layers 266 correspond to circuits that enable signals and / or power to be provided to and / or provided from the semiconductor devices 258. Each of the metallization layers 266 includes a through hole, a trench, a contact, a plug, an interconnect, and / or another type of conductive structure. Each of the metallization layers 266 includes one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof and other examples of conductive materials.

[0045] In some embodiments, the metallization layers 266 of the interconnect structure 218 can be arranged in a vertical manner in the z-direction in the semiconductor die 208. In other words, multiple stacked metallization layers 266 extend between the device layer 214 and the bonding structure 222 to facilitate routing of electrical signals and / or power between the device layer 214 and the semiconductor die 206. The multiple stacked metallization layers 266 can be referred to as M layers. In some embodiments, the interconnect structure 218 includes nine (9) stacked metallization layers 266 (e.g., M0-M8). In some embodiments, the interconnect structure 218 includes another number of stacked metallization layers 266.

[0046] like Figure 2A As further shown in FIG. 1 , interconnect structure 218 may include ESL 268 below and / or under ILD layer 262 and dielectric layer 270 below and / or under ESL 268. ESL 268 may include silicon nitride (Si x N y , such as Si3N4), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and / or another nitride-containing dielectric material. Dielectric layer 270 may include one or more ELK dielectric materials, such as carbon-doped silicon oxide (c-SiO x ), amorphous fluorinated carbon (aC x F y), polyparaxylene, BCB, PTFE and / or silicon oxycarbide (SiOC) polymer. Additionally and / or alternatively, the dielectric layer 270 may include porous HSQ, porous MSQ, porous PAE, silicon oxide (SiO x ), USG and / or BSG and other instances.

[0047] Metal interconnect 272 may be included in ESL 268 and dielectric layer 270 and / or may extend through ESL 268 and dielectric layer 270. Metal interconnect 272 is electrically and / or physically coupled to one or more metallization layers 266. Metal layer 274 is electrically and / or physically coupled to metal interconnect 272. Metal layer 274 is also included in dielectric layer 270.

[0048] Bonding structure 222 includes a plurality of dielectric layers, such as dielectric layers 276-282 below interconnect structure 218 and bonding dielectric layer 284 below dielectric layers 276-282. Dielectric layer 276 is included below and / or below dielectric layer 270, dielectric layer 278 is included below and / or below dielectric layer 276, dielectric layer 280 is included below and / or below dielectric layer 278, and dielectric layer 282 is included below and / or below dielectric layer 280.

[0049] Dielectric layers 276 and 280 may be included in the bonding structure 222 as an ESL. Dielectric layers 276 and 280 may each include a carbon-containing dielectric material such as silicon carbide (SiC), a nitride-containing material such as silicon carbonitride (SiCN), and / or another suitable ESL material. Dielectric layers 278 and 282 may each include an HDP dielectric material and / or another suitable dielectric material. Bonding dielectric layer 284 may include silicon oxynitride (SiON) and / or another suitable bonding dielectric material.

[0050] The bonding vias 286 extend through and / or are included in the dielectric layers 276 and 278. The bonding vias 286 are electrically and / or physically coupled to the metal layer 274. The bonding vias 286 each include a via, an interconnect, a conductive column, a plug, and / or another type of conductive structure. The bonding vias 286 each include one or more conductive metals, such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), gold (Au), and / or combinations thereof and other examples of conductive materials.

[0051] The bonding pads 288 extend through and / or are included in the dielectric layer 280, the dielectric layer 282, and the bonding dielectric layer 284. The bonding pads 288 are electrically and / or physically coupled to the bonding vias 286. Each of the bonding pads 288 includes a groove, a pad, a contact, and / or another type of conductive bonding structure. Each of the bonding pads 288 includes one or more conductive metals, such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), gold (Au), and / or combinations thereof and other examples of conductive materials.

[0052] At the bonding interface 210, the bonding dielectric layer 252 and the bonding dielectric layer 284 are bonded by dielectric-to-dielectric bonding. The bonding via 254 of the semiconductor die 206 is bonded to the bonding pad 288 of the semiconductor die 208 by metal-to-metal bonding. The combination of dielectric-to-dielectric bonding and metal-to-metal bonding is sometimes referred to as "hybrid bonding". Figure 2A Front-side to front-side bonding of semiconductor die 206 and 208 is shown, wherein bonding interface 210 is located between interconnect structures 216 and 218, which are located on the front sides of semiconductor die 206 and 208, respectively. In other embodiments, bonding interface 210 can be located between the back sides of semiconductor die 206 and 208, and thus can include back-side to back-side bonding. Alternatively, bonding interface 210 can be located between the front side of semiconductor die 206 and the back side of semiconductor die 208 or between the front side of semiconductor die 208 and the back side of semiconductor die 206, as well as other examples.

[0053] like Figure 2A As further shown in FIG. 2 , a shielding grid 290 may be included between bonding pads 288 in bonding structure 222 of semiconductor die 208. Shielding grid 290 includes a plurality of intersecting trenches of a conductive material, such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), gold (Au), and / or combinations thereof and other examples of conductive materials. Shielding grid 290 may be included in dielectric layers 280 and 282, and thus may be located above bonding vias 254 in semiconductor device 200. Bonding dielectric layer 284 may be included between shielding grid 290 and semiconductor die 206. Shielding grid 290 may be physically and / or electrically coupled to grounding vias 292, which electrically connect shielding grid 290 to metal layer 274 for electrical grounding. The ground vias 292 include a conductive material such as copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), gold (Au), and / or combinations thereof and other examples of conductive materials.

[0054] Shielding grid 290 provides electrical isolation between bonding pads 288 and reduces electrical coupling between bonding pads 288 in semiconductor die 208. Bonding bonding vias 254 directly to bonding pads 288, rather than including additional bonding pads in semiconductor die 206 for bonding to bonding pads 288, provides an increased distance (or increased spacing) between adjacent bonding vias 254 in semiconductor die 206. The increased distance reduces electrical coupling between bonding vias 254 in semiconductor die 206 without including an additional shielding grid in semiconductor die 206. For example, the increased distance can reduce electrical coupling between bonding vias 254 in semiconductor die 206 by about 4% to about 5% or more than if bonding pads were used to bond semiconductor die 206 to bonding pads 288 of semiconductor die 208. Thus, bonding bonding vias 254 directly to bonding pads 288 may reduce the complexity, time, and cost of forming semiconductor die 206 because fewer semiconductor processing operations are performed to form semiconductor die 206 than if bonding pads and additional shielding grids were included.

[0055] Figure 2B 2 shows a top view of the semiconductor device 200, wherein the location of the cross section along line AA is shown. Figure 2B As shown in FIG, a cross section along line AA extends through a plurality of bonding vias 254 of semiconductor die 206, through a plurality of bonding pads 288 of semiconductor die 208, through a shielding grid 290 of semiconductor die 208, and through ground vias 292 of semiconductor die 208. Shielding grid 290 surrounds bonding pads 288 in the xy plane of semiconductor die 208.

[0056] The bonding via 254 of the semiconductor die 206 and the bonding pad 288 of the semiconductor die 208 are bonded at a bonding surface 294 of the bonding via 254 and a bonding surface 296 of the bonding pad 288. The size (e.g., surface area) of the bonding surface 294 in the xy plane of the semiconductor device 200 is smaller than the size (e.g., surface area) of the bonding surface 296 of the bonding pad 288 in the xy plane. The bonding via 254 and the bonding pad 288 are bonded such that the entire bonding surface 294 of the bonding via 254 is within the perimeter of the bonding surface 296 of the bonding pad 288 and is bonded to the bonding surface 296. Due to the smaller size of the bonding surface 294 of the bonding via 254, the bonding surface 294 of the bonding via 254 partially overlaps with the bonding surface 296 of the bonding pad 288. The bonding via 254 and the bonding pad 288 are bonded such that less than the entire bonding surface 296 of the bonding pad 288 is located within the perimeter of the bonding surface 294 of the bonding via 254 and is bonded with the bonding surface 294. This occurs due to the larger size of the bonding surface 296. In some embodiments, due to the larger size of the bonding surface 296 of the bonding pad 288, the bonding surface 296 of the bonding pad 288 completely overlaps the bonding surface 294 of the bonding via 254. However, in other embodiments, some misalignment occurs in bonding the semiconductor die 206 and the semiconductor die 208, and the bonding surface 296 of the bonding pad 288 may partially overlap the bonding surface 294 of the bonding via 254.

[0057] The smaller size of the bonding surface 294 of the bonding via 254 provides greater flexibility in achieving a satisfactory overlap (e.g., xy alignment) between the bonding via 254 and the bonding pad 288, so that sufficient bonding quality can be achieved. This provides greater flexibility and a larger process window for aligning the bonding via 254 of the semiconductor die 206 and the bonding pad 288 of the semiconductor die 208 for bonding, which can reduce the rate and / or probability of defect formation for bonding semiconductor dies on the semiconductor wafers 202 and 204, and / or can increase the bonding yield of the semiconductor dies bonded on the semiconductor wafers 202 and 204.

[0058] Figure 2C One or more dimensions of the semiconductor device 200 are shown. Additionally and / or alternatively, Figure 2COne or more dimensions shown in are the dimensions of the bonding via 254 and / or the bonding pad 288. Exemplary dimension D1 includes the cross-sectional width (e.g., x-direction width, y-direction width) of the top of the bonding via 254. In some embodiments, dimension D1 is included in the range of about 0.1 micron to 0.3 micron. However, other values ​​for ranges are within the scope of the disclosed embodiments. Another exemplary dimension D2 includes the cross-sectional width (e.g., x-direction width, y-direction width) of the bonding pad 288. In some embodiments, dimension D2 is included in the range of about 0.3 micron to 0.5 micron. However, other values ​​for ranges are within the scope of the disclosed embodiments.

[0059] The cross-sectional width (e.g., in the x-direction and / or the y-direction) of the bonding pad 288 can be greater than the cross-sectional width (e.g., in the x-direction and / or the y-direction) of the bonding via 254. This provides a greater distance (or greater spacing) between adjacent bonding vias 254 in the semiconductor die 206 relative to the distance or spacing between adjacent bonding pads 288 in the semiconductor die 208. The increased distance reduces the electrical coupling between the bonding vias 254 in the semiconductor die 206 without including an additional shielding grid in the semiconductor die 206. In some embodiments, the ratio of dimension D2 to dimension D1 is greater than about 1:1, and up to 5:1 or greater. However, other values ​​for the ranges are within the scope of the disclosed embodiments.

[0060] Another exemplary dimension D3 includes the cross-sectional width (e.g., x-direction width, y-direction width) of a segment of the shielding grid 290. In some embodiments, the dimension D3 is included in the range of about 0.1 micron to 0.5 micron. However, other values ​​for the range are within the scope of the disclosed embodiments. Another exemplary dimension D4 includes the distance (e.g., x-direction distance, y-direction distance) between the bonding pad 288 and the shielding grid 290. In some embodiments, the dimension D4 is included in the range of about 0.1 micron to about 0.2 micron. If the dimension D4 is less than about 0.1 micron, when the shielding grid 290 and / or the bonding pad 288 are formed, pattern defects may occur, and those pattern defects may produce an electrical short circuit between the bonding pad 288 and the shielding grid 290. If the dimension D4 is greater than about 0.2 micron, the bonding pad 288 and the shielding grid 290 may be too far apart to achieve a high density of bonding pads 288 in the semiconductor die 208. If dimension D4 is included in the range of about 0.1 microns to about 0.2 microns, a high density of bonding pads 288 can be achieved in semiconductor die 208 without unduly increasing the likelihood of electrical shorts between bonding pads 288 and shield grid 290. However, other values ​​for dimension D4 and ranges other than about 0.1 microns to about 0.2 microns are within the scope of the disclosed embodiments.

[0061] Another exemplary dimension D5 includes the spacing between adjacent bonding pads 288 (e.g., the distance between the centers of adjacent bonding pads 288). In some embodiments, dimension D5 is included in the range of about 0.75 microns to about 1 micron. If dimension D5 is less than about 0.75 microns, pattern defects may occur when forming shielding grid 290 and / or bonding pads 288 due to insufficient spacing between bonding pads 288, and those pattern defects may create electrical shorts between bonding pads 288 and shielding grid 290. If dimension D5 is greater than about 1 micron, bonding pads 288 may be spaced too far apart to achieve a high density of bonding pads 288 in semiconductor die 208. If dimension D5 is included in the range of about 0.75 microns to about 1 micron, a high density of bonding pads 288 may be achieved in semiconductor die 208 without excessively increasing the likelihood of electrical shorts between bonding pads 288 and shielding grid 290. However, other values ​​for dimension D5 and ranges other than about 0.75 microns to about 1 micron are within the scope of embodiments of the present disclosure.

[0062] Another exemplary dimension D6 includes the distance (or spacing) between adjacent bonding vias 254. Dimension D6 is greater than dimension D4 (e.g., the distance between shield grid 290 and bonding pads 288 is less than the distance between adjacent bonding pads 254), and is greater than the distance between adjacent bonding pads 288. This enables a low amount of electrical coupling between bonding vias 254 while enabling a high density of bonding vias 254 to be included in semiconductor die 206.

[0063] As noted above, Figure 1 and FIG. 2A to FIG. 2C Provided as an example. Other examples may be related to Figure 1 and FIG. 2A to FIG. 2C The content described is different.

[0064] FIG. 3A to FIG. 3J is a diagram of an exemplary embodiment 300 of forming a semiconductor die 206 as described herein. In some embodiments, one or more of the semiconductor processing tools may be used to implement the bonding FIG. 3A to FIG. 3J One or more of the semiconductor processing operations described.

[0065] Go to Figure 3A , a substrate 224 may be provided. The substrate 224 may be provided in the form of a semiconductor wafer (eg, semiconductor wafer 202 ) such as a silicon (Si) wafer. The semiconductor die 206 may be formed on the substrate 224 along with a plurality of other semiconductor dies 206 .

[0066] like Figure 3BAs shown in , the integrated circuit device 226 can be formed in and / or on the substrate 224 in the device layer 212 of the semiconductor die 206. One or more semiconductor processing tools can be used to form one or more parts of the integrated circuit device 226. For example, a deposition tool can be used to perform various deposition operations to deposit the layers of the integrated circuit device 226, and / or to deposit a photoresist layer for etching the substrate 224 and / or the portion of the deposited layer. As another example, an exposure tool can be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, a development tool can develop the pattern in the photoresist layer. As another example, an etching tool can be used to etch the substrate 224 and / or the portion of the deposited layer to form the semiconductor device 226. As another example, a planarization tool can be used to planarize the portion of the integrated circuit device 226. As another example, a plating tool can be used to deposit the metal structure and / or layer of the integrated circuit device 226.

[0067] like Figure 3C As shown in , a deposition tool is used to deposit dielectric layer 228 over and / or on substrate 224 and over and / or on integrated circuit device 226. The deposition tool is also used to deposit alternating layers of ESL 232 and ILD layer 230 of interconnect structure 216 of semiconductor die 206. Deposition tools, exposure tools, development tools, etching tools, planarization tools, and / or plating tools are used to perform various operations to form metallization layer 234 in interconnect structure 216 of semiconductor die 206. Metallization layer 234 can be formed in ILD layer 230 and / or ESL 232, and can be electrically coupled with integrated circuit device 226 in device layer 212. For example, a groove can be formed in ESL 232 and / or in ILD layer 230, and metallization layer 234 can be formed in the groove.

[0068] like Figure 3D As shown in , ESL 236 can be formed over and / or on ILD layer 230 and over and / or on one or more metallization layers 234. Dielectric layer 238 is formed over ESL 236. A deposition tool can be used to deposit ESL 236 and / or dielectric layer 238 using a PVD technique, an ALD technique, a CVD technique, an oxidation technique, and / or another suitable deposition technique. In some embodiments, a planarization tool can be used to planarize ESL 236 and / or dielectric layer 238 after depositing ESL 236 and / or dielectric layer 238.

[0069] like Figure 3E and Figure 3FAs shown in FIG. 1 , a recess 302 is formed in and / or through the dielectric layer 238 and the ESL 236. The top surface of the topmost metallization layer 234 in the interconnect structure 216 is exposed through the recess 302. In some embodiments, a dual damascene process is used to form the recess 302. For example, as shown in FIG. Figure 3E , a through-hole portion of the groove 302 can be formed in and / or through the dielectric layer 238 and the ESL 236. In particular, the through-hole portion can be formed from the top surface of the dielectric layer 238 through the dielectric layer 238 and through the ESL 236. A deposition tool can be used to form a photoresist layer on the dielectric layer 238. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose a pattern. An etching tool can be used to etch the dielectric layer 238 and the ESL 236 to form a through-hole portion of the groove 302. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0070] The trench portion of the recess 302 can be formed in the dielectric layer 238 above the through hole portion. In particular, the trench portion can be formed from the top surface of the dielectric layer 238 and formed into the portion of the dielectric layer 238. A deposition tool can be used to form a photoresist layer on the dielectric layer 238. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose a pattern. An etching tool can be used to etch the dielectric layer 238 to form the trench portion of the recess 302 in the dielectric layer 238. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0071] Figure 3E and Figure 3F An exemplary via-first dual damascene process is shown, where recess 302 is formed by forming a via portion before forming a trench portion. In some implementations, a trench-first dual damascene process may be implemented, where recess 302 is formed by forming a trench portion before forming a via portion.

[0072] like Figure 3GAs shown in , metal interconnect 240 is formed in the through-hole portion of recess 302, so that metal interconnect 240 is bonded to (and electrically and / or physically coupled to) topmost metallization layer 234. Metal layer 242 is formed in the trench portion of recess 302 on metal interconnect 240. Metal interconnect 240 and metal layer 242 include one or more liner layers 304 and conductive structure 306. One or more liner layers 304 may include an adhesion layer, a barrier layer, and / or another type of liner conformally deposited on the sidewalls and / or bottom surface of recess 302. Examples of materials for one or more liner layers 304 include tantalum nitride (TaN), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), and / or ruthenium oxide (RuO x ) and other examples.

[0073] The deposition tool may be used to deposit one or more liner layers 304 using a PVD technique, an ALD technique, a CVD technique, and / or another suitable deposition technique. The deposition tool and / or the plating tool may be used to deposit the metal interconnect 240 and the metal layer 242 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, and / or another suitable deposition technique. In some embodiments, a seed layer is deposited first, and the metal interconnect 240 and / or the metal layer 242 are deposited on the seed layer. In some embodiments, a planarization tool is used to planarize the metal layer 242 after the metal layer 242 is deposited.

[0074] like Figure 3H As shown in , dielectric layers 244-250 and bonding dielectric layer 252 are formed over and / or on dielectric layer 238. Dielectric layers 244-250 and bonding dielectric layer 252 are formed over and / or on metal layer 242. A deposition tool may be used to deposit dielectric layers 244-250 and / or bonding dielectric layer 252 using a PVD technique, an ALD technique, a CVD technique, and / or another suitable deposition technique. In some embodiments, a planarization tool is used to planarize one or more of dielectric layers 244-250 and / or bonding dielectric layer 252 after depositing one or more of dielectric layers 244-250 and / or bonding dielectric layer 252.

[0075] like Fig. 3IAs shown in , a groove 308 is formed in and / or through the dielectric layers 244-250 and the bonding dielectric layer 252. The top surface of the metal layer 242 is exposed through the groove 308. In some embodiments, the pattern is used to etch the dielectric layers 244-250 and / or the bonding dielectric layer 252 to form the groove 308. The deposition tool can be used to form a photoresist layer on the bonding dielectric layer 252. The exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool can be used to etch the dielectric layers 244-250 and the bonding dielectric layer 252 based on the pattern to form the groove 308. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper and / or another technique). Additionally and / or alternatively, a hard mask layer is used to form the recesses 308 based on a pattern.

[0076] like Figure 3J As shown in , the bonding via 254 is formed in the groove 308, so that the bonding via 254 is bonded to the metal layer 242 (and electrically and / or physically coupled to the metal layer 242). The bonding vias 254 each include one or more liner layers 310 and a conductive structure 312. The one or more liner layers 310 may include an adhesion layer, a barrier layer, and / or another type of liner conformally deposited on the sidewalls and / or bottom surface of the groove 308. Examples of materials for the one or more liner layers 310 include tantalum nitride (TaN), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), and / or ruthenium oxide (RuO x ) and other examples.

[0077] The deposition tool may be used to deposit one or more liner layers 310 using a PVD technique, an ALD technique, a CVD technique, and / or another suitable deposition technique. The deposition tool and / or the plating tool may be used to deposit the conductive structure 312 of the bonding via 254 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, and / or another suitable deposition technique. In some embodiments, a seed layer is deposited first, and the bonding via 254 is deposited on the seed layer. In some embodiments, a planarization tool is used to planarize the bonding via 254 after the bonding via 254 is deposited.

[0078] As noted above, FIG. 3A to FIG. 3J Provided as an example. Other examples may be related to FIG. 3A to FIG. 3J The content described is different.

[0079] 4A to 4F is a diagram of an exemplary embodiment 400 of forming a semiconductor die 208 as described herein. In some embodiments, one or more semiconductor processing tools may be used to implement the bonding 4A to 4F One or more of the semiconductor processing operations described.

[0080] Go to Figure 4A , can be implemented as a combination of FIG. 3A to FIG. 3H Similar semiconductor processing operations are described to form semiconductor device 258 in and / or on substrate 256 in device layer 214 of semiconductor die 208, to deposit dielectric layer 260 over and / or over substrate 256 and over and / or over semiconductor device 258, to deposit alternating layers of ESL 264 and ILD layer 262 of interconnect structure 218 of semiconductor die 208, to form metallization layers 266 in ILD layers 262 and / or ESL 264, to form ESL 268 and dielectric layers 270, to form metal interconnects 272 in dielectric layers 268 and 270, to form metal layers 274 on metal interconnects 272 in dielectric layers 270, and to form dielectric layers 276-282 of bonding structure 222 of semiconductor die 208.

[0081] like Figure 4B As shown in FIG. 4 , recesses 402, 404, and 406 are formed in and / or through dielectric layers 280 and 282 in bonding structure 222. Recesses 402 and 404 are further formed through dielectric layers 278 and 276 in bonding structure 222. A top surface of metal layer 274 is exposed through recess 402 in preparation for forming bonding vias 286 on metal layer 274. A top surface of one or more metal layers 274 may also be exposed through recess 404 in preparation for forming one or more grounding vias 292 on one or more metal layers 274. Recess 406 is formed in preparation for forming shielding grid 290 around bonding pads 288 of semiconductor die 208.

[0082] In some embodiments, a dual damascene process is used to form recesses 402 and 404. In these embodiments, the via portions of recesses 402 and 404 and the trench portions of recesses 402 and 404 are formed sequentially. For example, a via-first dual damascene process may be implemented, wherein the via portions of recesses 402 and 404 may be formed from the top surface of dielectric layer 282 through dielectric layer 282, through dielectric layer 280, through dielectric layer 278, and through dielectric layer 276 to metal layer 274. The trench portions of recesses 402 and 404 may be formed such that the trench portions are formed by laterally extending (e.g., in the x-direction and / or y-direction) the top sections of the via portions. Recess 406 may also be formed together with (e.g., simultaneously with) the trench portions of recesses 402 and 404. Alternatively, a trench-first dual damascene process may be implemented, wherein recesses 402 and 404 are formed by forming the trench portions before forming the via portions.

[0083] The deposition tool can be used to form a photoresist layer on the dielectric layer 282. The exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool can be used to etch the dielectric layers 276-282 to form the through-hole portions of the recesses 402 and 404. In some embodiments, the photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0084] Subsequently, a deposition tool may be used to form a photoresist layer on dielectric layer 282. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose a pattern. An etching tool may be used to etch dielectric layers 280 and 282 to form groove portions of recesses 402 and 404 and recess 406. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper and / or another technique).

[0085] like Figure 4C As shown in , the bonding via 286 is formed in the through-hole portion of the groove 402, so that the bonding via 286 is bonded to the metal layer 274 (and electrically and / or physically coupled to the metal layer 274). The bonding pad 288 is formed in the groove portion of the groove 402 above the bonding via 286. The bonding via 286 and the bonding pad 288 can each include one or more liner layers 408 and a conductive structure 410. The one or more liner layers 408 may include an adhesion layer, a barrier layer, and / or another type of liner conformally deposited on the sidewalls and / or bottom surface of the groove 402. Examples of materials for the one or more liner layers 408 include tantalum nitride (TaN), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), and / or ruthenium oxide (RuO x ) and other examples.

[0086] The deposition tool may be used to deposit one or more liner layers 408 using a PVD technique, an ALD technique, a CVD technique, and / or another suitable deposition technique. The deposition tool and / or the plating tool may be used to deposit the conductive structures 410 of the bonding vias 286 and the bonding pads 288 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, and / or another suitable deposition technique. In some embodiments, a seed layer is first deposited on the one or more liner layers 408, and the bonding vias 286 and / or the bonding pads 288 are deposited on the seed layer. In some embodiments, a planarization tool is used to planarize the bonding pads 288 after the bonding pads 288 are deposited.

[0087] like Figure 4CAs further shown in FIG. 4 , the ground via 292 is formed in the through-hole portion of the recess 404, such that the ground via 292 is engaged on (and electrically and / or physically coupled to) the metal layer 274. The shielding grid 290 is formed in the trench portion of the recess 404 and in the recess 406. The ground via 292 and the shielding grid 290 may each include one or more liner layers 408 and a conductive structure 410. The one or more liner layers 408 may include an adhesion layer, a barrier layer, and / or another type of liner conformally deposited on the sidewalls and / or bottom surface of the recess 404 and / or 406.

[0088] The deposition tool and / or plating tool can be used to deposit the conductive structures 410 of the ground vias 292 and the shield grid 290 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, and / or another suitable deposition technique. In some embodiments, a seed layer is first deposited on the one or more liner layers 408, and the ground vias 292 and / or the shield grid 290 are deposited on the seed layer. In some embodiments, a planarization tool is used to planarize the shield grid 290 after the shield grid 290 is deposited.

[0089] like Figure 4D As shown in , a bonding dielectric layer 284 is formed over and / or on dielectric layer 282. Bonding dielectric layer 284 is also formed over and / or on bonding pads 288 and shielding grid 290. A deposition tool may be used to deposit bonding dielectric layer 284 using a PVD technique, an ALD technique, a CVD technique, and / or another suitable deposition technique. In some embodiments, a planarization tool is used to planarize bonding dielectric layer 284 after deposition of bonding dielectric layer 284.

[0090] like Figure 4E , removing the portion of the bonding dielectric layer 284 to expose the bonding pad 288 through the bonding dielectric layer 284. In some embodiments, the pattern in the photoresist layer is used to etch the bonding dielectric layer 284 to remove the portion of the bonding dielectric layer 284. In these embodiments, a deposition tool can be used to form a photoresist layer on the bonding dielectric layer 284. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool can be used to develop and remove the portion of the photoresist layer to expose the pattern. An etching tool can be used to etch the bonding dielectric layer 284 based on a pattern to remove the portion of the bonding dielectric layer 284. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remainder of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technique). In some embodiments, a hard mask layer is used as an optional technique for etching the bonding dielectric layer 284 based on a pattern.

[0091] like Figure 4F , depositing additional material for bonding pad 288. The additional material may be planarized using a planarization tool so that the top surface of bonding pad 288 is coplanar with the top surface of bonding dielectric layer 284. A deposition tool and / or a plating tool may be used to deposit the additional material for bonding pad 288 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, or another deposition technique.

[0092] As noted above, 4A to 4F Provided as an example. Other examples may be related to 4A to 4F The content described is different.

[0093] Figure 5A and Figure 5B 2 is a diagram of an exemplary embodiment 500 of forming the semiconductor device 200 described herein. In particular, the exemplary embodiment 500 includes an example of bonding the semiconductor die 206 and the semiconductor die 208 to form the semiconductor device 200. In some embodiments, one or more semiconductor processing tools may be used to implement the bonding. Figure 5A and Figure 5B One or more of the semiconductor processing operations described.

[0094] like Figure 5A and Figure 5B As shown in , a bonding operation is performed to bond semiconductor die 206 and semiconductor die 208 at a bonding interface 210, so that semiconductor die 206 and semiconductor die 208 are arranged or stacked vertically. Semiconductor die 206 and semiconductor die 208 can be arranged or stacked vertically in a wafer-on-wafer (WoW) configuration, a die-on-wafer configuration, a die-on-die configuration, and / or another direct bonding configuration. A bonding tool can be used to perform a bonding operation to bond semiconductor die 206 and semiconductor die 208 at a bonding interface 210. The bonding operation can include forming a direct bond between semiconductor die 206 and semiconductor die 208 through a physical connection of a bonding via 254 of semiconductor die 206 and a bonding pad 288 of semiconductor die 208 and a physical connection of a bonding dielectric layer 252 of semiconductor die 206 and a bonding dielectric layer 284 of semiconductor die 208. At the bonding interface 210, a direct metal-to-metal bond is formed between the bonding via 254 and the bonding pad 288, and a direct dielectric-to-dielectric bond is formed between the bonding dielectric layers 252 and 284. Therefore, the bonding operation may be referred to as a "hybrid bonding" operation because different types of material-to-material bonds are formed in the bonding operation.

[0095] In some embodiments, semiconductor die 206 and semiconductor die 208 are bonded as part of a bonding operation to bond semiconductor wafer 202 and semiconductor wafer 204. Thus, semiconductor device 200 (and other semiconductor devices 200) may be diced or sawed from bonded semiconductor wafer 202 and semiconductor wafer 204 and packaged.

[0096] To bond semiconductor dies 206 and 208, a bonding tool may be used to align semiconductor dies 206 and 208 such that a bonding surface (e.g., bonding surface 294) of bonding via 254 is located on and / or within a perimeter of a bonding surface (e.g., bonding surface 296) of bonding pad 288. In other words, a bonding tool may be used to align semiconductor dies 206 and 208 such that a perimeter of the bonding surface of bonding via 254 and a perimeter of the bonding surface of bonding pad 288 partially overlap. Due to the smaller size of the bonding surface of bonding via 254 than the size of the bonding surface of bonding pad 288, the perimeters of the bonding surfaces of bonding via 254 and bonding pad 288 do not completely overlap. The smaller size of the bonding surface of the bonding via 254 provides greater flexibility in achieving a satisfactory overlap percentage between the bonding via 254 and the bonding pad 288, because sufficient bonding quality can be achieved if there is a threshold amount of overlap between the perimeters of the bonding surface of the bonding via 254 and the bonding surface of the bonding pad 288. This provides greater flexibility and a larger process window for aligning the bonding via 254 of the semiconductor die 206 and the bonding pad 288 of the semiconductor die 208 for bonding, which can reduce the rate and / or likelihood of defect formation for bonding semiconductor dies on the semiconductor wafers 202 and 204, and / or can increase the bonding yield of the semiconductor dies bonded on the semiconductor wafers 202 and 204.

[0097] As noted above, Figure 5A and Figure 5B Provided as an example. Other examples may be related to Figure 5A and Figure 5B The content described is different.

[0098] FIG. 6A to FIG. 6C is a diagram of an exemplary implementation 600 of bonding vias 254 of semiconductor die 206 and bonding pads 288 of semiconductor die 208 as described herein. Fig. 6A is a top view of bonding via 254 and bonding pad 288 . Figure 6B is along Fig. 6A Cross-sectional view of line BB in the x direction. Figure 6C is along Fig. 6A Cross-sectional view along line CC in the y direction.

[0099] like Fig. 6AAs shown in FIG, the bonding via 254 and the bonding pad 288 are bonded at a bonding surface 602 of the bonding via 254 and a bonding surface 604 of the bonding pad 288. The bonding surface 604 is bonded with the entire surface area of ​​the bonding surface 602. Due to the smaller size of the bonding surface 602, the bonding surface 602 is bonded with less than the entire surface area of ​​the bonding surface 604. The bonding surface 602 has a circular top view shape in the top view of the bonding via 254, and the bonding surface 604 also has a circular top view shape in the top view of the bonding pad 288.

[0100] The bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane such that the bonding surface 602 is located within the perimeter (e.g., circumference) 606 of the bonding surface 604. Therefore, the perimeter (e.g., circumference) 608 of the bonding surface 602 is smaller than the perimeter 606 of the bonding pads 288. In addition, the bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane such that the perimeter 608 of the bonding surface 602 overlaps a portion of the perimeter 606 of the bonding surface 604. Fig. 6A and Figure 6B As shown in FIG. 6 , the engagement surface 602 is offset relative to a center 610 of the engagement surface 604 such that an overlapping section 612 occurs between the perimeter 608 and the perimeter 606. Additionally and / or alternatively, as Fig. 6A As shown in , a portion 614 of the perimeter 608 of the bonding surface 602 can be located within a distance D7 that satisfies a distance threshold. The distance threshold can be included in a range of about 9 nanometers to about 10 nanometers. The distance D7 of the portion 614 that satisfies the distance threshold enables sufficient bonding strength to be achieved between the bonding via 254 and the bonding pad 288. However, other values ​​for the range are within the scope of the disclosed embodiments.

[0101] The size of the bonding surface 602 of the bonding via 254 and / or the bonding surface 604 of the bonding pad 288 may be changed so that the overlap section 612 and / or the portion 614 that meets the distance threshold covers about 40% to about 90% of the perimeter 608 of the bonding surface 602 and / or about 40% to about 90% of the perimeter 606 of the bonding surface 604. The overlap section 612 and / or the portion 614 that meets the distance threshold provides sufficient bonding strength between the bonding via 254 and the bonding pad 288 for about 40% to about 90% of the perimeter 608 of the bonding surface 602 and / or for about 40% to about 90% of the perimeter 606 of the bonding surface 604, which reduces the possibility of bonding defects in the semiconductor device 200 and / or increases the yield of the semiconductor device 200. Additionally and / or alternatively, the overlap segments 612 and / or portions 614 that meet the distance threshold are about 40% to about 90% of the perimeter 608 of the bonding surface 602 and / or about 40% to about 90% of the perimeter 606 of the bonding surface 604 so that the bonding vias 254 can be spaced far enough apart to achieve a low amount of electrical coupling between the bonding vias 254. However, other values ​​for these ranges are within the scope of the disclosed embodiments.

[0102] As noted above, FIG. 6A to FIG. 6C Provided as an example. Other examples may be related to FIG. 6A to FIG. 6C The content described is different.

[0103] 7A to 7C is a diagram of an exemplary implementation 700 of bonding vias 254 of semiconductor die 206 and bonding pads 288 of semiconductor die 208 as described herein. Fig. 7A is a top view of bonding via 254 and bonding pad 288 . Figure 7B is along Fig. 7A Cross-sectional view along line DD in the x direction. Figure 7C is along Fig. 7A Cross-sectional view along line EE in the y direction.

[0104] like Fig. 7AAs shown in , the bonding through hole 254 and the bonding pad 288 are bonded at the bonding surface 702 of the bonding through hole 254 and the bonding surface 704 of the bonding pad 288. The bonding surface 704 is bonded to the entire surface area of ​​the bonding surface 702. Due to the smaller size of the bonding surface 702, the bonding surface 702 is bonded to less than the entire surface area of ​​the bonding surface 704. The bonding surface 702 has an oblong (or stadium) top view shape in the top view of the bonding through hole 254. In particular, the bonding surface 702 includes a rounded end (e.g., a semicircular end) connected by a side that is approximately parallel to the end point of the rounded end. In other words, the bonding surface 702 includes a rectangular top view shape with a rounded end. The bonding surface 704 has a circular top view shape in the top view of the bonding pad 288.

[0105] The bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane such that the bonding surface 702 is within a perimeter (e.g., circumference) 706 of the bonding surface 704. Thus, the perimeter 708 of the bonding surface 702 of the bonding vias 254 is smaller than the perimeter 706 of the bonding surface 704 of the bonding pads 288. Fig. 7A and Figure 7C , the bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane such that the perimeter 708 of the bonding surface 702 overlaps a portion of the perimeter 706 of the bonding surface 704. The rounded end of the bonding surface 702 overlaps a portion of the perimeter 706 of the bonding surface 704 such that an overlapping section 710 occurs between the perimeter 708 and the perimeter 706. The size of the bonding surface 702 of the bonding vias 254 and / or the bonding surface 704 of the bonding pads 288 may be varied such that the overlapping section 710 covers about 40% to about 90% of the perimeter 708 of the bonding surface 702 and / or about 40% to about 90% of the perimeter 706 of the bonding surface 704.

[0106] As noted above, 7A to 7C Provided as an example. Other examples may be related to 7A to 7C The content described is different.

[0107] FIG. 8A to FIG. 8E is a diagram of an exemplary implementation 800 of bonding vias 254 of semiconductor die 206 and bonding pads 288 of semiconductor die 208 as described herein. Fig. 8A is a top view of bonding pad 288 . Figure 8B is a top view of the engagement through-hole 254 . Figure 8C is a top view of bonding via 254 bonding to bonding pad 288 . Fig.8D is along Figure 8C Cross-sectional view along line FF in the x direction. Fig. 8E is along Figure 8C Cross-sectional view of line GG in the y direction.

[0108] like Fig. 8A As shown in , the bonding pad 288 has a bonding surface 802, and the bonding surface 802 has a cross-shaped (or cross-shaped) top view shape. The bonding surface 802 includes a plurality of segments 802a-802d extending in a cross pattern from the central area of ​​the bonding surface 802. One or more of the segments 802a-802d can have rounded ends. For example, segment 802a can have a rounded end 804a, segment 802b can have a rounded end 804b, segment 802c can have a rounded end 804c, and / or segment 802d can have a rounded end 804d. Segment 802a can also include approximately parallel sidewalls 806a tangent to the endpoints of the rounded end 804a. Segment 802b can also include approximately parallel sidewalls 806b tangent to the endpoints of the rounded end 804b. Segment 802c can also include approximately parallel sidewalls 806c tangent to the endpoints of the rounded end 804c. Segment 802d may also include approximately parallel sidewalls 806d that are tangential to an endpoint of rounded end 804d. Rounded end portions 802a-802d and approximately parallel sidewalls 806a-806d correspond to the perimeter of bonding surface 802 of bonding pad 288.

[0109] like Figure 8B As shown in FIG. 1 , the engagement through hole 254 has an engagement surface 808 having an oblong (or stadium) top view shape in a top view of the engagement through hole 254. In particular, the engagement surface 808 includes a rounded end (e.g., a semicircular end) 810 connected by approximately parallel side walls 812 tangential to the endpoints of the rounded end 810. The rounded end 810 and the approximately parallel side walls 812 correspond to the perimeter of the engagement surface 808.

[0110] like Figure 8C , the bonding via 254 and the bonding pad 288 are bonded at a bonding surface 802 of the bonding pad 288 and a bonding surface 808 of the bonding via 254. The bonding surface 802 is bonded to the entire surface area of ​​the bonding surface 808. Due to the smaller size of the bonding surface 808, the bonding surface 808 is bonded to less than the entire surface area of ​​the bonding surface 802.

[0111] The bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane such that the bonding surface 808 is within the perimeter of the bonding surface 802. Thus, the perimeter of the bonding surface 808 of the bonding vias 254 is smaller than the perimeter of the bonding surface 802 of the bonding pads 288. Figure 8C and Fig. 8EAs shown in , the bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane so that the perimeter of the bonding surface 808 overlaps with a portion of the perimeter of the bonding surface 802. The rounded end 810 and the portion of the approximately parallel sidewalls 812 of the bonding surface 808 overlap with the rounded end and the approximately parallel sidewalls of one or more segments 802a-802d of the bonding surface 802, so that an overlapping section 814 appears between the perimeter of the bonding surface 802 and the perimeter of the bonding surface 808. For example, the rounded end 810 and the portion of the approximately parallel sidewalls 812 of the bonding surface 808 can overlap with the rounded end 804b and the approximately parallel sidewalls 806b of the segment 802b. As another example, the rounded end 810 and the portion of the approximately parallel sidewalls 812 of the bonding surface 808 can overlap with the rounded end 804d and the approximately parallel sidewalls 806d of the segment 802d. The dimensions of bonding surface 808 of bonding via 254 and / or bonding surface 802 of bonding pad 288 may be varied such that overlapping segment 814 covers approximately 40% to approximately 90% of the perimeter of bonding surface 802 and / or approximately 40% to approximately 90% of the perimeter of bonding surface 808 .

[0112] As noted above, FIG. 8A to FIG. 8E Provided as an example. Other examples may be related to FIG. 8A to FIG. 8E The content described is different.

[0113] 9A to 9C is a diagram of an exemplary implementation 900 of bonding vias 254 of semiconductor die 206 and bonding pads 288 of semiconductor die 208 as described herein. Fig. 9A is a top view of bonding via 254 and bonding pad 288 . Fig. 9B is along Fig. 9A Cross-sectional view of line HH in the x direction. Fig. 9C is along Fig. 9A Cross-sectional view along line II in the y direction.

[0114] like Fig. 9AAs shown in , the bonding through hole 254 and the bonding pad 288 are bonded at the bonding surface 902 of the bonding through hole 254 and the bonding surface 904 of the bonding pad 288. The bonding surface 904 is bonded to the entire surface area of ​​the bonding surface 902. Due to the smaller size of the bonding surface 902, the bonding surface 902 is bonded to less than the entire surface area of ​​the bonding surface 904. The bonding surface 902 has an oblong (or stadium) top view shape in the top view of the bonding through hole 254. In particular, the bonding surface 902 includes a rounded end (e.g., a semicircular end) connected by a side that is approximately parallel to the end point of the rounded end. The bonding surface 904 also has an oblong (or stadium) top view shape in the top view of the bonding pad 288. In particular, the bonding surface 904 includes a rounded end (e.g., a semicircular end) connected by a side that is approximately parallel to the end point of the rounded end. The top view length of the oblong top view shape of the bonding surface 902 is less than the top view length of the oblong top view shape of the bonding surface 904.

[0115] The bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane such that the bonding surface 902 is within a perimeter (e.g., circumference) 906 of the bonding surface 904. Thus, the perimeter 908 of the bonding surface 902 of the bonding vias 254 is smaller than the perimeter 906 of the bonding surface 904 of the bonding pads 288. In addition, and as Fig. 9A and Fig. 9C , the bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane such that the perimeter 908 of the bonding surface 902 overlaps a portion of the perimeter 906 of the bonding surface 904. The approximately parallel sidewalls of the bonding surface 902 overlap a portion of the approximately parallel sidewalls of the bonding surface 904 such that an overlap section 910 occurs between the perimeter 908 and the perimeter 906. The dimensions of the bonding surface 902 of the bonding vias 254 and / or the bonding surface 904 of the bonding pads 288 may be varied such that the overlap section 910 covers approximately 40% to approximately 90% of the perimeter 908 of the bonding surface 902 and / or approximately 40% to approximately 90% of the perimeter 906 of the bonding surface 904.

[0116] As noted above, 9A to 9C Provided as an example. Other examples may be related to 9A to 9C The content described is different.

[0117] FIG. 10A to FIG. 10C is a diagram of an exemplary implementation 1000 of bonding vias 254 of semiconductor die 206 and bonding pads 288 of semiconductor die 208 as described herein. Fig. 10A is a top view of bonding via 254 and bonding pad 288 . Fig. 10B is along Fig. 10A Cross-sectional view of line JJ in the x direction. Fig. 10C is along Fig. 10A Cross-sectional view of line KK in the y direction.

[0118] like Fig. 10A As shown in FIG. 1 , the bonding via 254 and the bonding pad 288 are bonded at a bonding surface 1002 of the bonding via 254 and a bonding surface 1004 of the bonding pad 288. The bonding surface 1004 is bonded to the entire surface area of ​​the bonding surface 1002. Due to the smaller size of the bonding surface 1002, the bonding surface 1002 is bonded to less than the entire surface area of ​​the bonding surface 1004. The bonding surface 1002 has a semicircular top view shape in the top view of the bonding via 254. The bonding surface 1004 also has a circular top view shape in the top view of the bonding pad 288.

[0119] The bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane such that the bonding surface 1002 is within a perimeter (e.g., circumference) 1006 of the bonding surface 1004. Thus, the perimeter 1008 of the bonding surface 1002 of the bonding vias 254 is smaller than the perimeter 1006 of the bonding surface 1004 of the bonding pads 288. FIG. 10A to FIG. 10C , the bonding vias 254 and / or the bonding pads 288 are aligned in the xy plane such that the perimeter 1008 of the bonding surface 1002 overlaps a portion of the perimeter 1006 of the bonding surface 1004. The circular portion of the bonding surface 1002 overlaps a portion of the perimeter 1006 of the bonding surface 1004 such that an overlapping section 1010 occurs between the perimeter 1006 and the perimeter 1008. The size of the bonding surface 1002 of the bonding vias 254 and / or the bonding surface 1004 of the bonding pads 288 may be varied such that the overlapping section 1010 covers about 40% to about 90% of the perimeter 1008 of the bonding surface 1002 and / or about 40% to about 90% of the perimeter 1006 of the bonding surface 1004.

[0120] As noted above, FIG. 10A to FIG. 10C Provided as an example. Other examples may be related to FIG. 10A to FIG. 10C The description is different. In addition, you can also use FIG. 6A to FIG. 6C , 7A to 7C , FIG. 8A to FIG. 8E , 9A to 9C and FIG. 10A to FIG. 10CThe top view shapes and / or dimensions other than those shown and described may be shaped and / or the dimensions of the bonding surfaces of the bonding vias 254 and / or the bonding surfaces of the bonding pads 288 may be varied to achieve a certain amount of overlap between the perimeters of the bonding vias 254 and the perimeters of the bonding pads 288 to achieve sufficient bonding strength while providing sufficient spacing between the bonding vias 254 to achieve a low amount of coupling between the bonding vias 254 without including an additional shielding grid around the bonding vias 254. Additionally and / or alternatively, the semiconductor device 200 may include bonding vias 254 and / or bonding pads 288. FIG. 6A to FIG. 6C , 7A to 7C , FIG. 8A to FIG. 8E , 9A to 9C and / or FIG. 10A to FIG. 10C Combinations of two or more exemplary embodiments of bonding vias 254 and / or combinations of two or more exemplary embodiments of bonding pads 288 , among other examples, are shown and described.

[0121] Fig.11 is a flow chart of an exemplary process 1100 associated with forming a semiconductor device described herein. In some embodiments, Fig.11 One or more process blocks of the method are implemented using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, plating tools, planarization tools, ion implantation tools, and / or wafer / die transport tools, among other examples.

[0122] like Fig.11 As shown in , the process 1100 may include providing a first semiconductor die including a first bonding via located in a first plurality of dielectric layers of the first semiconductor die (block 1110). For example, one or more semiconductor processing tools may be used to provide a semiconductor die 206 including a bonding via 254 located in a plurality of dielectric layers 244-252 of the semiconductor die 206, as described herein.

[0123] like Fig.11 As further shown in FIG. 1 , process 1100 may include providing a second semiconductor die including a second bonding via located in a second plurality of dielectric layers of the second semiconductor die and a bonding pad coupled to the second bonding via (block 1120). For example, one or more semiconductor processing tools may be used to provide semiconductor die 208 including bonding via 286 located in a plurality of dielectric layers 276-284 of semiconductor die 208 and a bonding pad 288 coupled to bonding via 286, as described herein.

[0124] like Fig.11As further shown in FIG. 1 , process 1100 may include aligning first semiconductor die 206 and second semiconductor die such that a first bonding surface of first bonding via 254 is within a second perimeter of a second bonding surface of bonding pad 288 and such that a first perimeter of the first bonding surface and a second perimeter of the second bonding surface partially overlap (block 1130). For example, one or more semiconductor processing tools may be used to align semiconductor die 206 and semiconductor die 208 such that a first bonding surface of bonding via 254 is within a second perimeter of a second bonding surface of bonding pad 288 and such that a first perimeter of the first bonding surface and a second perimeter of the second bonding surface partially overlap, as described herein.

[0125] like Fig.11 As further shown in , process 1100 may include, after aligning the first semiconductor die and the second semiconductor die, bonding the first semiconductor die and the second semiconductor die at the first bonding surface and the second bonding surface (block 1140). For example, after aligning semiconductor die 206 and semiconductor die 208, one or more semiconductor processing tools may be used to bond semiconductor die 206 and semiconductor die 208 at the first bonding surface and the second bonding surface, as described herein.

[0126] Process 1100 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in connection with one or more other processes described elsewhere herein.

[0127] In a first embodiment, the process 1100 includes: forming a second bonding via; forming a bonding pad on the second bonding via; and forming a shielding grid 290, wherein the shielding grid 290 surrounds the bonding pad.

[0128] In a second embodiment, alone or in combination with the first embodiment, forming the bond pads and forming the shield grid includes depositing the bond pads and depositing the shield grid in the same deposition operation.

[0129] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming the first bonding via includes forming the first bonding via to have a semicircular top view shape, and forming the bonding pad includes forming the bonding pad to have a circular top view shape.

[0130] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming a first bonding through hole includes forming the first bonding through hole to have an oblong top view shape, and forming a bonding pad includes forming a bonding pad to have at least one of another oblong top view shape, a circular top view shape, or a cross top view shape.

[0131] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, forming the first bonding via includes forming the first bonding via such that a first surface area of ​​the first bonding surface is smaller than a second surface of the second bonding surface of the bonding pad. Thus, the bonding surface area of ​​the bonding pad is larger than the bonding surface area of ​​the first bonding via.

[0132] Although Fig.11 An exemplary block diagram of process 1100 is shown, but in some embodiments, process 1100 includes Fig.11 Additional blocks, fewer blocks, different blocks, or differently arranged blocks may be included in the process 1100. Additionally or alternatively, two or more of the blocks of the process 1100 may be implemented in parallel.

[0133] In this way, a semiconductor device is formed by joining a bonding pad in a first semiconductor die to a bonding through hole in a second semiconductor die and by joining a dielectric layer in the first semiconductor die and in the second semiconductor die. The bonding through hole of the second semiconductor die may have a size and / or shape different from the size and / or shape of the bonding pad of the first semiconductor die. For example, the bonding through hole of the second semiconductor die may have a width less than the width of the bonding pad of the first semiconductor die. The bonding pad is omitted from the second semiconductor device, and the bonding through hole is used to join the first semiconductor die and the second semiconductor die, providing a larger amount of spacing between the bonding through holes of the second semiconductor die because the bonding through hole has a smaller width than the bonding pad. This enables a larger amount of dielectric material of the dielectric layer of the second semiconductor device to be placed between the bonding through holes without (or minimally) increasing the lateral size of the second semiconductor die. The increased spacing between the bonding through holes of the second semiconductor die reduces the electrical coupling between the bonding through holes of the second semiconductor die without using another shielding grid in the second semiconductor die. Thus, the increased spacing between the bonding vias of the second semiconductor die enables the use of a less complex manufacturing process to achieve reduced electrical coupling between the bonding vias of the second semiconductor die.

[0134] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first semiconductor die. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first plurality of dielectric layers and a first bonding through-hole included in the first plurality of dielectric layers. The semiconductor device includes a second semiconductor die. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second plurality of dielectric layers, a second bonding through-hole included in the second plurality of dielectric layers, and a bonding pad included in the second plurality of dielectric layers. The first semiconductor die and the second semiconductor die are bonded at a first bonding surface of the first bonding through-hole and a second bonding surface of the bonding pad. The entire first bonding surface is bonded to the second bonding surface, and less than the entire second bonding surface is bonded to the first bonding surface.

[0135] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a first semiconductor die. The first semiconductor die includes a first device layer and a first interconnect structure located above the first device layer. The first interconnect structure includes a first metal layer. The first interconnect structure includes a first bonding structure located above the first interconnect structure. The first bonding structure includes a first plurality of dielectric layers and a first bonding via included in the first plurality of dielectric layers, wherein the first bonding via is located above the first metal layer and coupled to the first metal layer. The semiconductor device includes a second semiconductor die. The second semiconductor die includes a second device layer. The second semiconductor die includes a second interconnect structure located below the second device layer. The second interconnect structure includes a second metal layer. The second semiconductor die includes a second bonding structure located below the second interconnect structure. The second bonding structure includes a second plurality of dielectric layers and a second bonding via included in the second plurality of dielectric layers, wherein the second bonding via is coupled to the second metal layer. The second bonding structure includes: a bonding pad included in the second plurality of dielectric layers. The bonding pad is located below the second bonding via and coupled to the second bonding via. The first semiconductor die and the second semiconductor die are bonded at the first bonding via and the bonding pad. The bonding surface area of ​​the bonding pad is larger than the bonding surface area of ​​the first bonding via.

[0136] As described in more detail above, some embodiments described herein provide methods. The method includes providing a first semiconductor die, the first semiconductor die including a first bonding via located in a first plurality of dielectric layers of the first semiconductor die. The method includes providing a second semiconductor die, the second semiconductor die including a second bonding via located in a second plurality of dielectric layers of the second semiconductor die and a bonding pad coupled to the second bonding via. The method includes aligning the first semiconductor die and the second semiconductor die so that a first bonding surface of the first bonding via is located within a second perimeter of a second bonding surface of the bonding pad, and so that a first perimeter of the first bonding surface and a second perimeter of the second bonding surface partially overlap. The method includes, after aligning the first semiconductor die and the second semiconductor die, bonding the first semiconductor die and the second semiconductor die at the first bonding surface and the second bonding surface.

[0137] Some embodiments of the present application provide a semiconductor device, comprising: a first semiconductor die, comprising a first bonding structure, wherein the first bonding structure comprises: a first plurality of dielectric layers; and a first bonding through-hole included in the first plurality of dielectric layers; and a second semiconductor die, comprising a second bonding structure, wherein the second bonding structure comprises: a second plurality of dielectric layers; a second bonding through-hole included in the second plurality of dielectric layers; and a bonding pad included in the second plurality of dielectric layers, wherein the first semiconductor die and the second semiconductor die are bonded at a first bonding surface of the first bonding through-hole and a second bonding surface of the bonding pad, wherein the entire first bonding surface is bonded to the second bonding surface, and wherein less than the entire second bonding surface is bonded to the first bonding surface.

[0138] In some embodiments, the first engagement surface has a rectangular top view shape with rounded ends;

[0139] wherein the second engagement surface has a circular top view shape; and

[0140] Wherein the rounded end of the first engagement surface overlaps a portion of the circumference of the second engagement surface.

[0141] In some embodiments, the first engagement surface has an oblong top view shape;

[0142] wherein the second engagement surface has a cross-shaped top view shape; and

[0143] Wherein, the first joint surface overlaps with a segment of the second joint surface.

[0144] In some embodiments, the first engagement surface has a first oblong top view shape;

[0145] wherein the second engagement surface has a second oblong top view shape; and

[0146] Wherein, a first top view length of the first joint surface is smaller than a second top view length of the second joint surface.

[0147] In some embodiments, the first engagement surface has a semicircular top view shape; wherein the second engagement surface has a circular top view shape; and

[0148] The first joint surface partially overlaps with the second joint surface.

[0149] In some embodiments, the first engagement surface has a first circular top view shape;

[0150] wherein the second engagement surface has a second circular top view shape; and

[0151] Wherein, a first circumference of the first joint surface is smaller than a second circumference of the second joint surface.

[0152] In some embodiments, the first engagement surface is offset relative to a center of the second engagement surface.

[0153] Some other embodiments of the present application provide a semiconductor device, comprising: a first semiconductor die, comprising: a first device layer; a first interconnect structure, located above the first device layer, comprising a first metal layer; and a first bonding structure, located above the first interconnect structure, comprising: a first plurality of dielectric layers; and a first bonding via, included in the first plurality of dielectric layers, wherein the first bonding via is located above the first metal layer and coupled to the first metal layer; and a second semiconductor die, comprising: a second device layer; a second interconnect structure, located below the second device layer, comprising a second metal layer; and a second bonding structure, located below the second interconnect structure, comprising: a second plurality of dielectric layers; a second bonding via, included in the second plurality of dielectric layers, wherein the second bonding via is coupled to the second metal layer; and a bonding pad, included in the second plurality of dielectric layers, wherein the bonding pad is located below the second bonding via and coupled to the second bonding via, wherein the first semiconductor die and the second semiconductor die are bonded at the first bonding via and the bonding pad, and wherein a bonding surface area of ​​the bonding pad is greater than a bonding surface area of ​​the first bonding via.

[0154] In some embodiments, the second interconnect structure further comprises:

[0155] A shielding grid surrounds the bonding pads.

[0156] In some embodiments, a distance between the shielding grid and the bonding pad is smaller than a distance between the first bonding via and a third bonding via included in the first plurality of dielectric layers.

[0157] In some embodiments, the shielding grid is located above the first bonding via.

[0158] In some embodiments, the first semiconductor die and the second semiconductor die are bonded at a first bonding surface of the first bonding via and a second bonding surface of the bonding pad; and

[0159] Wherein a first portion of a first perimeter of the first engagement surface is located within a distance threshold from a second portion of a second perimeter of the second engagement surface.

[0160] In some embodiments, the distance threshold is comprised within a range of about 9 nanometers to about 10 nanometers.

[0161] In some embodiments, the first engagement surface is offset relative to a center of the second engagement surface.

[0162] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: providing a first semiconductor die, the first semiconductor die comprising a first bonding through-hole located in a first plurality of dielectric layers of the first semiconductor die; providing a second semiconductor die, the second semiconductor die comprising a second bonding through-hole located in a second plurality of dielectric layers of the second semiconductor die and a bonding pad coupled to the second bonding through-hole; aligning the first semiconductor die and the second semiconductor die so that a first bonding surface of the first bonding through-hole is located within a second perimeter of a second bonding surface of the bonding pad, and so that a first perimeter of the first bonding surface and a second perimeter of the second bonding surface partially overlap; and after aligning the first semiconductor die and the second semiconductor die, bonding the first semiconductor die and the second semiconductor die at the first bonding surface and the second bonding surface.

[0163] In some embodiments, the method further comprises:

[0164] forming the second bonding through hole;

[0165] forming the bonding pad on the second bonding through hole; and

[0166] Forming a shielding grid,

[0167] Wherein, the shielding grid surrounds the bonding pad.

[0168] In some embodiments, forming the bonding pad and forming the shielding grid include:

[0169] The bond pads are deposited and the shield grid is deposited in the same deposition operation.

[0170] In some embodiments, forming the first bonding via includes:

[0171] forming the first engaging through-hole to have a semicircular top view shape; and

[0172] Wherein, forming the bonding pad comprises:

[0173] The bonding pad is formed to have a circular top view shape.

[0174] In some embodiments, forming the first bonding via includes:

[0175] forming the first engaging through-hole to have an oblong top view shape; and

[0176] Wherein, forming the bonding pad comprises:

[0177] The bonding pad is formed to have at least one of the following:

[0178] Another oblong top view shape;

[0179] a circular top view shape; or

[0180] Cross top view shape.

[0181] In some embodiments, forming the first bonding via includes:

[0182] The first bonding via is formed such that a first surface area of ​​the first bonding surface is smaller than a second surface of the second bonding surface of the bonding pad.

[0183] The terms "about" and "substantially" may indicate a value of a given amount that varies within ±5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that according to embodiments of the present disclosure, the terms "about" and "substantially" may refer to a percentage of the value of a given amount.

[0184] As used herein, "satisfying a threshold" may (depending on the context) mean that a value is greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc.

[0185] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: a first semiconductor die including a first bonding structure, Wherein, the first bonding structure comprises: a first plurality of dielectric layers; and a first bonding via included in the first plurality of dielectric layers; and a second semiconductor die including a second bonding structure, Wherein, the second bonding structure comprises: a second plurality of dielectric layers; a second bonding via included in the second plurality of dielectric layers; and a bonding pad included in the second plurality of dielectric layers, wherein the first semiconductor die and the second semiconductor die are bonded at a first bonding surface of the first bonding via and a second bonding surface of the bonding pad, wherein the entire first engagement surface engages with the second engagement surface, and Wherein less than the entire second engagement surface engages with the first engagement surface.

2. The semiconductor device according to claim 1, wherein the first engagement surface having a rectangular top view shape with rounded ends; wherein the second engagement surface has a circular top view shape; and Wherein the rounded end of the first engaging surface overlaps a portion of the circumference of the second engaging surface.

3. The semiconductor device according to claim 1, wherein The first engagement surface has an oblong top view shape; wherein the second engagement surface has a cross-shaped top view shape; and Wherein, the first joint surface overlaps with a segment of the second joint surface.

4. The semiconductor device according to claim 1, wherein the first engagement surface having a first oblong top view shape; wherein the second engagement surface has a second oblong top view shape; and Wherein, a first top view length of the first joint surface is smaller than a second top view length of the second joint surface.

5. The semiconductor device according to claim 1, wherein the first engagement surface having a semicircular top view shape; wherein the second engagement surface has a circular top view shape; and The first joint surface partially overlaps with the second joint surface.

6. The semiconductor device according to claim 1, wherein the first engagement surface having a first circular top view shape; wherein the second engagement surface has a second circular top view shape; and Wherein, a first circumference of the first joint surface is smaller than a second circumference of the second joint surface.

7. The semiconductor device according to claim 6, wherein: The first engagement surface is offset relative to a center of the second engagement surface.

8. A semiconductor device comprising: A first semiconductor die comprising: a first device layer; a first interconnect structure, located on the first device layer, comprising a first metal layer; and A first bonding structure, located on the first interconnection structure, comprises: a first plurality of dielectric layers; and a first bonding via included in the first plurality of dielectric layers, wherein the first bonding via is located on the first metal layer and is coupled to the first metal layer; and A second semiconductor die comprising: a second device layer; a second interconnect structure, located below the second device layer, comprising a second metal layer; and A second bonding structure, located below the second interconnection structure, comprises: a second plurality of dielectric layers; a second bonding via included in the second plurality of dielectric layers, wherein the second bonding via is coupled to the second metal layer; and a bonding pad included in the second plurality of dielectric layers, wherein the bonding pad is located below the second bonding through hole and is coupled to the second bonding through hole, wherein the first semiconductor die and the second semiconductor die are bonded at the first bonding via and the bonding pad, and The bonding surface area of ​​the bonding pad is larger than the bonding surface area of ​​the first bonding through hole.

9. The semiconductor device according to claim 8, wherein: The second interconnect structure further comprises: A shielding grid surrounds the bonding pads.

10. A method of forming a semiconductor device, comprising: providing a first semiconductor die including a first bonding via in a first plurality of dielectric layers of the first semiconductor die; providing a second semiconductor die including a second bonding via in a second plurality of dielectric layers of the second semiconductor die and a bonding pad coupled to the second bonding via; aligning the first semiconductor die and the second semiconductor die such that a first bonding surface of the first bonding via is within a second perimeter of a second bonding surface of the bonding pad and such that a first perimeter of the first bonding surface and a second perimeter of the second bonding surface partially overlap; as well as After aligning the first semiconductor die and the second semiconductor die, the first semiconductor die and the second semiconductor die are bonded at the first bonding surface and the second bonding surface.

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