Photoelectric sensor test structure, forming method and test method

Abstract

The invention discloses a photoelectric sensor test structure, a forming method and a test method, and the structure comprises a substrate which comprises a first test region, a second test region and a device region located between the first test region and the second test region, and comprises a first surface and a second surface which are opposite to each other; the photoelectric doped regions and the charge collection regions are located in the device region, the photoelectric doped regions are separated from one another, the charge collection regions and the photoelectric doped regions are separated from one another, and the photoelectric doped regions are exposed out of the first surface; a first test structure located in the first test area; a second test structure located in the second test area; a plurality of isolation structures located between the photoelectric doped regions and between the charge collection regions and the photoelectric doped regions, wherein each isolation structure comprises a shielding layer; the first interconnection structure is located on the surface of the first face, the second interconnection structure is located on the surface of the first face, and the third interconnection structure is located on the surface of the second face. The test structure can test interface state characterization data.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a photoelectric sensor test structure, a forming method and a testing method. Background Art

[0002] In the chip manufacturing of direct imaging ranging sensors, the backside illumination sensor (BSI) process structure is usually adopted to improve the comprehensive optical performance. Among them, in the back-illuminated process, the back-illuminated film layer structure design is crucial to the photoelectric conversion rate of the photodiode, thus affecting the sensor's photon capture ability, the sensor's imaging quality and ranging accuracy.

[0003] Direct imaging ranging sensor products with backside illumination (BSI) architecture are mainly used in 3D depth imaging. The technical challenge lies in reducing the pixel size and increasing the density while ensuring the device's photon detection efficiency (PDE) and dark count rate (DRC) performance.

[0004] Deep Trench Isolation (DTI) is a structure commonly used in direct imaging ranging sensors. It can achieve electrical and optical crosstalk isolation between single photon avalanche diodes (SPADs) and optimize device performance. At present, one of the key technologies in the industry to reduce photon detection efficiency and increase dark count rate is to control the sidewall interface state of deep trench isolation, specifically by improving related parameters through backside ion implantation or optimizing High-K dielectric material process.

[0005] However, in the prior art, there is a lack of effective interface state characterization equipment, so it is impossible to directly obtain interface state characterization data. The only way to qualitatively infer the change trend of the interface state is through changes in chip performance, and the credibility of the qualitative inference is low. Summary of the invention

[0006] The technical problem solved by the present invention is that it is impossible to accurately test the characterization data of the interface state.

[0007] To solve the above technical problems, an embodiment of the present invention provides a photoelectric sensor test structure, comprising: a substrate, the substrate comprising a first test area, a second test area and a device area located between the first test area and the second test area, the substrate comprising a first surface and a second surface opposite to each other; a plurality of photoelectric doping areas and a charge collection area located in the device area, the plurality of photoelectric doping areas and the charge collection areas and the photoelectric doping areas are separated from each other, and the first surface exposes the photoelectric doping areas; a first test structure located in the first test area; a second test structure located in the second test area; a plurality of isolation structures located between the photoelectric doping areas and between the charge collection areas and the photoelectric doping areas, the isolation structures comprising a shielding layer; a first interconnection structure located on the surface of the first surface, the first interconnection structure being electrically connected to the charge collection area and the first test structure respectively; a second interconnection structure located on the surface of the first surface, the second interconnection structure being electrically connected to the photoelectric doping area and the second test structure respectively; a third interconnection structure located on the surface of the second surface, the third interconnection structure being electrically connected to the shielding layer and the charge collection area respectively.

[0008] Optionally, the photoelectric sensor test structure also includes: a first opening located in the first test area, the first opening is recessed relative to the second surface, and the first opening exposes the first test structure; a second opening located in the second test area, the second opening is recessed relative to the second surface, and the second opening exposes the second test structure; a third opening located in the charge collection area, the third opening is recessed relative to the second surface, and a portion of the third interconnection structure is located in the third opening.

[0009] Optionally, the photoelectric sensor test structure further includes: a contact layer located on the inner wall surface of the third opening.

[0010] Optionally, the first interconnection structure includes: a plurality of first conductive plugs respectively located on the surface of the charge collection region on the first surface and a first conductive layer located on the surface of the first conductive plugs; the second interconnection structure includes: a plurality of second conductive plugs respectively located on the surface of the photoelectric doping region on the first surface and a second conductive layer located on the surface of the second conductive plugs; the third interconnection structure includes: a plurality of third conductive plugs located on the surface of each shielding layer, a fourth conductive plug located in the third opening, and a third conductive layer located on the surface of the third conductive plug and the surface of the fourth conductive plug.

[0011] Optionally, the first test structure includes: a fourth conductive layer located in the first test area, the first surface exposing the fourth conductive layer; a first conductive plug located between the fourth conductive layer and the first interconnect structure; the second test structure includes: a fifth conductive layer located in the second test area, the first surface exposing the fifth conductive layer; and a second conductive plug located between the fifth conductive layer and the second interconnect structure.

[0012] Optionally, the isolation structure includes: a first isolation structure and a second isolation structure located on both sides of the photoelectric doping region.

[0013] Optionally, the isolation structure further includes: an insulating structure located between the shielding layer and the substrate.

[0014] Optionally, the insulating structure includes: a first insulating layer located on the surface of the shielding layer and a second insulating layer located between the first insulating layer and the shielding layer, and the shielding layer, the first insulating layer and the second insulating layer are made of different materials.

[0015] Optionally, the first test area further includes: a first insulating dielectric layer located on the surface of the first opening; and the second test area further includes: a second insulating dielectric layer located on the surface of the second opening.

[0016] Optionally, the photoelectric sensor test structure further includes: a passivation structure located on the surface of the second surface, the surface of the first test structure, the surface of the charge collection area, the surface of the third interconnection structure and the surface of the second test structure.

[0017] The technical solution of the present invention also provides a method for forming a photoelectric sensor test structure, comprising: providing a substrate, the substrate having a first test area, a second test area and a device area located between the first test area and the second test area, the substrate comprising a first surface and a second surface opposite to each other; forming a plurality of photoelectric doping areas and charge collection areas in the device area, the plurality of photoelectric doping areas and the charge collection areas and the photoelectric doping areas are separated from each other, and the first surface exposes the photoelectric doping areas; forming a first test structure in the first test area, the first surface exposes the first test structure; forming a second test structure in the second test area, the first surface exposes the first test structure; forming a first interconnection structure on the surface of the first surface, the first interconnection structure is electrically connected to the charge collection area and the first test structure respectively; forming a second interconnection structure on the surface of the first surface, the second interconnection structure is electrically connected to the photoelectric doping area and the second test structure respectively; forming a plurality of isolation structures between the photoelectric doping areas and between the charge collection area and the photoelectric doping areas, and forming a shielding layer in the isolation structure; forming a third interconnection structure on the surface of the second surface, the third interconnection structure is electrically connected to the shielding layer and the charge collection area respectively.

[0018] Optionally, the method for forming the photoelectric sensor test structure also includes: before or after forming the first test structure, etching on the second surface of the first test area to form a first opening, and the first opening exposes the first test structure; before or after forming the second test structure, etching on the second surface of the second test area to form a second opening, and the second opening exposes the second test structure; etching on the second surface of the charge collection area to form a third opening, and part of the third interconnection structure is located in the third opening.

[0019] Optionally, the method for forming the photoelectric sensor test structure further includes: forming a contact layer on the inner wall surface of the third opening.

[0020] Optionally, the method for forming a first interconnection structure on the surface of the first surface includes: forming a plurality of first conductive plugs on the surface of the charge collection region of the first surface respectively; forming a first conductive layer on the surface of the first conductive plugs; the method for forming a second interconnection structure on the surface of the first surface includes: forming a plurality of second conductive plugs on the surface of the photoelectric doping region of the first surface respectively; forming a second conductive layer on the surface of the second conductive plugs; the method for forming a third interconnection structure on the surface of the second surface includes: forming a plurality of third conductive plugs on the surface of each shielding layer; forming a third conductive layer on the surface of the third conductive plug; forming a fourth conductive plug in the third opening, the surface of the fourth conductive plug being connected to the third conductive layer.

[0021] Optionally, the method for forming a first test structure in the first test area includes: forming a fourth conductive layer in the first test area, the first surface exposing the fourth conductive layer; and a first conductive plug between the fourth conductive layer and the first interconnect structure; the method for forming a second test structure in the second test area includes: forming a fifth conductive layer in the second test area, the first surface exposing the fifth conductive layer; and a second conductive plug between the fifth conductive layer and the second interconnect structure.

[0022] Optionally, after forming the shielding layer in the isolation structure, the method includes: forming a first insulating layer on a surface of the shielding layer, and forming a second insulating layer between the first insulating layer and the shielding layer.

[0023] Optionally, the method for forming the first opening in the first test area includes: forming a first insulating dielectric layer on a surface of the first opening; and the method for forming the second opening in the second test area includes: forming a second insulating dielectric layer on a surface of the second opening.

[0024] Optionally, the method for forming the photoelectric sensor test structure further includes: forming a passivation structure on the second surface, the first test structure surface, the charge collection area surface, the third interconnect structure surface and the second test structure surface.

[0025] The technical solution of the present invention also provides a test method for a photoelectric sensor test structure, comprising: applying a first frequency to a first test structure and a second test structure to obtain a first capacitance value Chf; applying a second frequency to the first test structure and the second test structure to obtain a second capacitance value Clf; obtaining an interface state density according to the first capacitance value and the second capacitance value. Wherein, A is the overlapping area of ​​the photoelectric doping region and the isolation structure, q is the charge amount, and Cox is the capacitance value corresponding to the first insulating layer and the second insulating layer.

[0026] Optionally, the first frequency is at least 100 times a preset threshold, and the second frequency is less than the preset threshold.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] The photoelectric sensor test structure provided in the technical solution of the present invention electrically connects the charge collection area with the first test structure through a first interconnection structure, electrically connects the photoelectric doping area with the second test structure through a second interconnection structure, and electrically connects the shielding layer with the charge collection area through a third interconnection structure, so that the interface state characterization data of the substrate overlapping with the isolation structure can be converted into the capacitance value of the photoelectric doping area and the isolation structure, and then measured; and the test structure in the technical solution of the present invention can match the existing photoelectric sensor, and will not cause damage to the photoelectric sensor during the test process, thereby ensuring the universality of the test structure and shortening the development cycle.

[0029] Furthermore, a first isolation structure and a second isolation structure are formed on both sides of the photoelectric doping region, so that the photoelectric doping region is isolated from other regions in the substrate during the test process, avoiding the influence of the potential of other regions of the substrate, ensuring the accuracy of the test results, and measuring multiple isolation structures further reduces the error of the test results.

[0030] The testing method of the photoelectric sensor testing structure provided in the technical solution of the present invention obtains the interface state density by testing different capacitance values ​​at different frequencies, thereby further ensuring the accuracy of the characterization data of the interface state. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the structure of a photoelectric sensor;

[0032] Figures 2 to 9 is a structural schematic diagram of a process of forming a photoelectric sensor test structure in an embodiment of the present invention;

[0033] Fig.10It is a flow chart of a method for testing a photoelectric sensor test structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0035] As can be seen from the background technology, the photoelectric sensors in the prior art lack effective interface state characterization equipment, so it is impossible to directly obtain interface state characterization data. The changing trend of the interface state can only be qualitatively inferred through changes in chip performance, and the credibility of the qualitative inference is low.

[0036] Figure 1 The present invention is a schematic structural diagram of an embodiment of a photoelectric sensor.

[0037] The photoelectric sensor comprises a substrate 100 , wherein the substrate 100 comprises an isolation structure and a photosensitive structure 104 , wherein the isolation structure comprises a shielding layer 103 , a first insulating layer 102 between the shielding layer 103 and the substrate, and a second insulating layer 101 between the substrate and the first insulating layer.

[0038] The interface state between the second insulating layer 101 and the surface of the substrate 100 is an important reference for characterizing the performance of the photoelectric sensor. However, there is currently no method or device that can reasonably test the characterization data of the interface state.

[0039] In order to solve the above technical problems, the technical solution of the present invention provides a photoelectric sensor test structure, a formation method and a test method, wherein the photoelectric doping region and the isolation structure are respectively connected to the test structure through an interconnection structure, and then the capacitance values ​​of the photoelectric doping region and the isolation structure are measured through the test structure, and the capacitance values ​​of the photoelectric doping region and the isolation structure can be converted into interface state characterization data, so that they can be measured in the interface state characterization data, and the test structure in the technical solution of the present invention can match existing photoelectric sensors, thereby ensuring the universality of the test structure.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 2 to 9 Schematic diagram of the structure of the photoelectric sensor forming process in an embodiment of the present invention.

[0042] Please refer to Figure 2 , providing a substrate 200, wherein the substrate 200 has a first test area I, a second test area II, and a device area III located between the first test area I and the second test area II, and the substrate 200 includes a first surface a and a second surface b opposite to each other.

[0043] The substrate is used to provide a holding space for a test structure, an isolation structure and a photoelectric doping region formed subsequently.

[0044] In this embodiment, the material of the substrate 200 includes silicon, and the doping type of the substrate 200 is P-type doping.

[0045] In other embodiments, the material of the substrate 200 includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0046] In this embodiment, a plurality of photoelectric doping regions 201 and charge collection regions are formed in the device region III, the plurality of photoelectric doping regions 201 and the charge collection regions and photoelectric doping regions 201 are separated from each other, and the first surface a exposes the photoelectric doping regions 201 .

[0047] The charge collection region is used to collect the charges generated by the isolation structure, and transmit the charges generated by the isolation structure to the first test structure through the first interconnection structure.

[0048] The photoelectric doping region 201 is controlled by the second test structure to test the capacitance value of the photoelectric doping region.

[0049] In this embodiment, the doping type of the photoelectric doping region 201 is N-type doping, and the ions implanted into the photoelectric doping region 201 include phosphorus ions or arsenic ions.

[0050] In this embodiment, the method for forming the photoelectric doping region 201 includes: forming a mask layer (not marked) on the surface of the first surface a, the mask layer exposing a portion of the surface of the first surface a; using the mask layer as a mask, ion implantation is performed on the exposed portion of the surface on the first surface a, and finally forming the photoelectric doping region 201.

[0051] Please refer to Figure 3 A first interconnect structure is formed on the surface of the first surface a, and the first interconnect structure is electrically connected to the charge collection area and the first test structure respectively; a second interconnect structure is formed on the surface of the first surface a, and the second interconnect structure is electrically connected to the photoelectric doping area 201 and the second test structure respectively.

[0052] In this embodiment, the further step includes: forming an interlayer dielectric structure 223 on the first surface, and the first interconnect structure is located in the interlayer dielectric structure 223 .

[0053] Specifically, the first interconnect structure includes: a plurality of first conductive plugs 202 and a first conductive layer 203 .

[0054] The interlayer dielectric structure 223 includes a first interlayer dielectric layer and a second interlayer dielectric layer.

[0055] The first interconnect structure includes: a plurality of first conductive plugs 202 and a first conductive layer 203 .

[0056] In this embodiment, the method for forming the first interconnect structure includes: forming a plurality of first conductive plugs 202 on the surface of the charge collection region of the first surface a respectively; and forming a first conductive layer 203 on the surface of the first conductive plugs 202 .

[0057] The second interconnect structure includes: a plurality of second conductive plugs 204 and a second conductive layer 205 .

[0058] The method for forming the second interconnect structure comprises: forming a plurality of second conductive plugs 204 on the surface of the photoelectric doping region 201 of the first surface a respectively; and forming a second conductive layer 205 on the surface of the second conductive plugs 204 .

[0059] In this embodiment, the number of the first conductive plug 202 and the second conductive plug 204 ranges from 1 to 5. Specifically, there are two first conductive plugs 202 and two second conductive plugs 204. The material of the first conductive layer 203 and the second conductive layer 205 is a conductive metal material, specifically aluminum.

[0060] The method for forming the first interlayer dielectric layer includes: forming a first interlayer dielectric layer on a first surface, and forming the first conductive plug 202 and the second conductive plug 204 in the first interlayer dielectric layer.

[0061] The method for forming the second interlayer dielectric layer includes: forming the second interlayer dielectric layer on the surface of the first interlayer dielectric layer, wherein the first conductive layer 203 and the second conductive layer 205 are located on the surface of the first interlayer dielectric layer, and the first conductive layer 203 and the second conductive layer 205 are located in the second interlayer dielectric layer.

[0062] Please refer to Figure 4 , a plurality of isolation structures are formed between the photoelectric doping regions 201 and between the charge collection region and the photoelectric doping region 201 .

[0063] The plurality of isolation structures are used to isolate the photoelectric doping region from other substrate regions.

[0064] In this embodiment, the isolation structure includes: a shielding layer 206 , a first insulating layer 207 located on a surface of the shielding layer 206 , and a second insulating layer 208 located between the first insulating layer 207 and the shielding layer 206 .

[0065] The material of the shielding layer 206 includes tungsten W, the material of the first insulating layer 207 includes a high-K material, and the second insulating layer 208 includes silicon nitride, silicon dioxide, or a combination of silicon nitride and silicon dioxide.

[0066] The thickness of the isolation structure is the same as the thickness of the substrate.

[0067] In this embodiment, any two isolation structures among the plurality of isolation structures are symmetrically distributed on two sides of the photoelectric doping region 201 .

[0068] In this embodiment, the method for forming the isolation structure includes: forming a mask layer (not marked) on the surface of the second surface b, the mask layer exposing a portion of the surface of the second surface; using the mask layer as a mask, etching the substrate to form a groove in the substrate 200; depositing a first initial insulating layer in the groove and on the surface of the substrate; depositing a second initial insulating layer on the surface of the first initial insulating layer; depositing an initial shielding layer on the surface of the second initial insulating layer; and flattening the initial shielding layer, the first initial insulating layer and the second initial insulating layer until the second surface is exposed, thereby forming the shielding layer 206, the first insulating layer 207 and the second insulating layer 208.

[0069] In other embodiments, before forming the first interconnect structure, the second interconnect structure and the interlayer dielectric structure, the method for forming the isolation structure includes: forming the shielding layer 206, the first insulating layer 207 and the second insulating layer 208 on the first surface, specifically: forming a mask layer (not marked) on the surface of the first surface a, the mask layer exposing a portion of the surface of the first surface a; etching the substrate using the mask layer as a mask to form a groove in the substrate 200; depositing a first initial insulating layer in the groove and on the surface of the substrate; depositing a second initial insulating layer on the surface of the first initial insulating layer; depositing an initial shielding layer on the surface of the second initial insulating layer; and flattening the initial shielding layer, the first initial insulating layer and the second initial insulating layer until the first surface is exposed, thereby forming the shielding layer 206, the first insulating layer 207 and the second insulating layer 208.

[0070] The process of etching the groove includes wet etching or dry etching. Wet etching is a technique of etching by immersing the etching material in an etching solution. It is a pure chemical etching with excellent selectivity. Wet etching is isotropic. Dry etching includes isotropic radial etching, reactive ion etching, sputtering etching, ion milling, ion beam assisted etching, reactive ion beam etching, etc. Dry etching is anisotropic.

[0071] The planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization treatment method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.

[0072] Please refer to Figure 5 , etching is performed on the second surface b of the first test area to form a first opening 209; etching is performed on the second surface b of the second test area to form a second opening 210; etching is performed on the second surface of the charge collection area to form a third opening 211, and part of the third interconnection structure is located in the third opening 211.

[0073] The first opening 209 is used to provide a receiving space for a first test structure formed subsequently, the second opening 210 is used to provide a receiving space for a second test structure formed subsequently, and the third opening 211 is used to provide a receiving space for a contact layer formed subsequently.

[0074] The method for forming the first opening 209 includes: forming a mask layer (not marked) on the surface of the second surface b, the mask layer exposing a portion of the surface of the second surface; using the mask layer as a mask, etching the substrate to form the first opening 209 in the substrate 200.

[0075] The method for forming the second opening 210 includes: forming a mask layer (not marked) on the surface of the second surface b, the mask layer exposing a portion of the surface of the second surface; using the mask layer as a mask, etching the substrate to form the second opening 210 in the substrate 200.

[0076] The method for forming the third opening 211 includes: forming a mask layer (not marked) on the surface of the second surface b, the mask layer exposing a portion of the surface of the second surface; using the mask layer as a mask, etching the substrate to form the third opening 211 in the substrate 200.

[0077] The depth of the first opening 209 is the same as that of the second opening 210 , the depth of the third opening 211 is less than that of the first opening 209 , and the top widths of the first opening 209 and the second opening 210 are greater than the bottom widths, that is, they are in an inverted trapezoidal shape.

[0078] Please refer to Figure 6 , a contact layer 212 is formed on the inner wall surface of the third opening 211 .

[0079] The method for forming the contact layer 212 includes: depositing an initial contact layer on the surface of the third opening 211 ; and planarizing the initial contact layer until the second surface is exposed, thereby forming the contact layer 212 .

[0080] The material of the contact layer 212 is the same as that of the shielding layer 206 . Specifically, the material of the contact layer 212 is tungsten.

[0081] The thickness of the contact layer 212 is smaller than the thickness of the isolation structure.

[0082] The contact layer 212 is used to receive the charges generated on the interface state and the isolation structure.

[0083] Please refer to Figure 7 A first insulating dielectric layer 218 is formed on the sidewalls and bottom surface of the first opening; and a second insulating dielectric layer 219 is formed on the sidewalls and bottom surface of the second opening.

[0084] The method for forming the first insulating dielectric layer 218 includes: depositing a first initial insulating dielectric layer on the surface of the first opening; and planarizing the first initial insulating dielectric layer until the second surface is exposed to form the first insulating dielectric layer 218 .

[0085] The method for forming the second insulating dielectric layer 219 includes: depositing a second initial insulating dielectric layer on the surface of the second opening; and planarizing the second initial insulating dielectric layer until the second surface is exposed to form the second insulating dielectric layer 219 .

[0086] The material of the first insulating dielectric layer 218 and the second insulating dielectric layer 219 includes silicon oxide.

[0087] Please refer to Figure 8 , a first test structure is formed in the first test area I; and a second test structure is formed in the second test area II.

[0088] In this embodiment, the first test structure includes a fourth conductive layer 216 and a first conductive plug 202 ; the second test structure includes a fifth conductive layer 217 and a second conductive plug 204 .

[0089] The method for forming the first test structure includes: etching the bottom surface of the first insulating dielectric layer 218 and the first interlayer dielectric layer to form a fourth opening exposing the surface of the first conductive layer 203; forming a first conductive plug 202 in the fourth opening, the first conductive plug 202 is located on the surface of the first conductive layer 203; forming a fourth conductive layer 216 in the fourth opening, the fourth conductive layer 216 is located on the surface of the first conductive plug 202, and a portion of the fourth conductive layer 216 is located in the fourth opening.

[0090] The method for forming the second test structure includes: etching the bottom surface of the second insulating dielectric layer and the first interlayer dielectric layer to form a fifth opening exposing the surface of the second conductive layer 205; forming a second conductive plug 204 in the fifth opening, and the second conductive plug 204 is located on the surface of the second conductive layer 205; forming a fifth conductive layer 217 in the fifth opening, and the fifth conductive layer 217 is located on the surface of the second conductive plug 204, and a portion of the fifth conductive layer 217 is located in the fifth opening.

[0091] The fourth conductive layer 216 and the fifth conductive layer 217 are made of silicon or germanium.

[0092] Please refer to Fig. 9 A passivation structure 220 and a third interconnection structure located within the passivation structure are formed on the second surface b, the sidewall surface of the first opening 209 and the sidewall surface of the second opening 210, and the third interconnection structure is electrically connected to the shielding layer 206 and the charge collection region, respectively.

[0093] The material of the passivation structure 220 includes silicon dioxide.

[0094] In this embodiment, the passivation structure includes a first passivation layer 221 and a second passivation layer 222. The third interconnection structure includes: a fourth conductive plug 215 located in the third opening, a third conductive plug 213 located on the surface of the shielding layer, and a third conductive layer 214 located on the surface of the third conductive plug 213 and the fourth conductive plug 215. The fourth conductive plug 215 and the third conductive plug 213 are located in the first passivation layer 221, and the third conductive layer 214 is located in the second passivation layer 222.

[0095] The material of the third conductive layer 214 is a conductive metal material, specifically aluminum.

[0096] The thickness of the second passivation layer 222 is greater than that of the third conductive layer 214 , and the first passivation layer is flush with the third conductive plug 213 and the fourth conductive plug 215 .

[0097] The method for forming the first passivation layer 221, the fourth conductive plug 215 and the third conductive plug 213 includes: depositing a first initial passivation layer on the surface of the second surface b, the side wall surface of the first opening 209 and the side wall surface of the second opening 210; etching the first initial passivation layer located on the surface of the shielding layer 206 to form a sixth opening (not marked in the figure) exposing the surface of the shielding layer 206, and forming a plurality of third conductive plugs 213 in the sixth opening; etching the first initial passivation layer located on the surface of the contact layer 212 to form a seventh opening (not marked in the figure) exposing the surface of the contact layer 212, and forming a plurality of fourth conductive plugs 215 in the seventh opening; and planarizing the first initial passivation layer until the surfaces of the third conductive plugs 213 and the fourth conductive plugs 215 are exposed to form the first passivation layer 221.

[0098] The method for forming the second passivation layer 222 and the third conductive layer 214 includes: depositing a second initial passivation layer on the surface of the second surface b; etching the second initial passivation layer located on the device area to form an eighth opening exposing the surface of the first passivation layer 221, the surface of the third conductive plug 213 and the surface of the fourth conductive plug 215; forming the third conductive layer 214 in the eighth opening; and planarizing the second initial passivation layer to form a second passivation layer 222.

[0099] In this embodiment, the number of the third conductive plugs 213 and the fourth conductive plugs 215 ranges from 1 to 5. Specifically, there are 2 third conductive plugs 213 and 1 fourth conductive plug. The number of the third conductive plugs 213 is the same as the number of the shielding layers 206 .

[0100] In other embodiments, the method for forming the fourth conductive layer 216 further includes: after forming the first passivation layer 221, etching the bottom surface of the first passivation layer 221 located on the side wall surface of the first opening to form a ninth opening exposing the first surface, and forming the fourth conductive layer 216 in the ninth opening.

[0101] In other embodiments, the method for forming the fifth conductive layer 217 further includes: after forming the first passivation layer 221, etching the bottom surface of the first passivation layer 221 located on the side wall surface of the second opening to form a tenth opening exposing the first surface, and forming the fifth conductive layer 217 in the tenth opening.

[0102] Please continue to refer to Fig. 9 The technical solution of the present invention also provides a photoelectric sensor test structure, including:

[0103] A substrate 200, wherein the substrate 200 comprises a first test area I, a second test area II, and a device area III located between the first test area I and the second test area II, and the substrate 200 comprises a first surface a and a second surface b opposite to each other;

[0104] A plurality of photoelectric doping regions 201 and charge collection regions located in the device region III, the plurality of photoelectric doping regions 201 and the charge collection regions and photoelectric doping regions 201 are separated from each other, and the first surface a exposes the photoelectric doping regions 201;

[0105] A first test structure located in a first test area I;

[0106] A second test structure located in a second test area II;

[0107] A plurality of isolation structures located between the photoelectric doping regions 201 and between the charge collection region and the photoelectric doping region 201, wherein the isolation structures include a shielding layer 206;

[0108] a first interconnection structure located on the surface of the first surface a, the first interconnection structure being electrically connected to the charge collection region and the first test structure respectively;

[0109] a second interconnect structure located on the surface of the first surface a, the second interconnect structure being electrically connected to the photoelectric doping region 201 and the second test structure respectively;

[0110] A third interconnection structure is located on the surface of the second surface b, and the third interconnection structure is electrically connected to the shielding layer 206 and the charge collection region respectively.

[0111] The following is a detailed description with reference to the accompanying drawings.

[0112] Please continue to refer to Fig. 9 The photoelectric sensor test structure also includes: a first opening 209 located in the first test area I, the first opening 209 is recessed relative to the second surface b, and the first opening 209 exposes the first test structure; a second opening 210 located in the second test area II, the second opening 210 is recessed relative to the second surface b, and the second opening 210 exposes the second test structure; a third opening located in the charge collection area, the third opening is recessed relative to the second surface b, and part of the third interconnection structure is located in the third opening.

[0113] In this embodiment, the photoelectric sensor test structure further includes: a contact layer 212 located on the inner wall surface of the third opening.

[0114] In this embodiment, the first interconnect structure includes: a plurality of first conductive plugs 202 respectively located on the surface of the charge collection region of the first surface a, and a first conductive layer 203 located on the surface of the first conductive plugs 202; the second interconnect structure includes: a plurality of second conductive plugs 204 respectively located on the surface of the photoelectric doping region 201 of the first surface a, and a second conductive layer 205 located on the surface of the second conductive plugs 204; the third interconnect structure includes: a plurality of third conductive plugs 213 located on the surface of each shielding layer 206, a fourth conductive plug 215 located in the third opening, and a third conductive layer 214 located on the surface of the third conductive plug 213 and the surface of the fourth conductive plug 215.

[0115] In this embodiment, the first test structure includes: a fourth conductive layer 216 located in the first test area I, the first side a exposing the fourth conductive layer 216; a first conductive plug 202 located between the fourth conductive layer 216 and the first interconnect structure; the second test structure includes: a fifth conductive layer 217 located in the second test area II, the first side a exposing the fifth conductive layer 217; and a second conductive plug 204 located between the fifth conductive layer 217 and the second interconnect structure.

[0116] In this embodiment, the isolation structure includes: a first isolation structure and a second isolation structure located on both sides of the photoelectric doping region 201 .

[0117] In this embodiment, the isolation structure further includes: an insulation structure located between the shielding layer 206 and the substrate 200 .

[0118] In this embodiment, the insulating structure includes: a first insulating layer 207 located on the surface of the shielding layer 206 and a second insulating layer 208 located between the first insulating layer 207 and the shielding layer 206. The shielding layer 206, the first insulating layer 207 and the second insulating layer 208 are made of different materials.

[0119] In this embodiment, the first test area I further includes: a first insulating dielectric layer 218 located on the surface of the first opening 209 ; the second test area II further includes: a second insulating dielectric layer 219 located on the surface of the second opening 210 .

[0120] In this embodiment, the photoelectric sensor test structure further includes: a passivation structure 220 located on the surface of the second surface b, the surface of the first test structure, the surface of the charge collection region, the surface of the third interconnection structure and the surface of the second test structure.

[0121] In other embodiments, the first test structure and the second test structure include a test socket kit (TSK), which consists of a base and a test needle and can be inserted into the photoelectric sensor to test the interface state density of the photoelectric sensor, wherein the test needle is connected to the fourth conductive layer and the fifth conductive layer in the photoelectric sensor to test the capacitance value and then test the interface state density.

[0122] On the one hand, the photoelectric sensor test structure in the above scheme can fit well into the existing manufacturing process of photoelectric sensors, and can realize simultaneous measurement during the manufacturing process or measurement outside the manufacturing process or after manufacturing is completed. Compared with some destructive characterization methods, the above photoelectric sensor test structure does not need to be separated from the production environment, will not introduce other pollution or affect chip performance, and is suitable for mass production environments.

[0123] On the other hand, existing optical characterization technologies need to consider the impact of the insulating layer structure above the characterization structure on the signal, and therefore need to be optimized separately for different structures, which greatly increases the development cycle and implementation difficulty. The photoelectric sensor test structure of the technical solution of the present invention will not be affected by the chip design or the thin film structure of the process itself, and has the advantage of universality. In addition, the photoelectric sensor test structure of the technical solution of the present invention is simple, is less affected by the external environment, the test is repeatable, and the result is highly reliable.

[0124] Accordingly, please refer to Fig.10 The technical solution of the present invention also provides a test method for a photoelectric sensor test structure, comprising:

[0125] S1: Apply a first frequency to the first test structure and the second test structure to obtain a first capacitance value Chf;

[0126] S2: applying a second frequency to the first test structure and the second test structure to obtain a second capacitance value Clf;

[0127] S3: Obtaining interface state density according to the first capacitance value and the second capacitance value Where A is the overlapping area between the photoelectric doping region and the isolation structure, q is the charge, and C ox is the capacitance value corresponding to the first insulating layer and the second insulating layer.

[0128] Combine the following Fig. 9 as well as Fig.10 The working principle of the test method of the photoelectric sensor test structure in the technical solution of the present invention is described as follows:

[0129] Since the description of interface state defects generally adopts the donor-like and acceptor-like theory, taking N-type semiconductors as an example, they can be divided into acceptor-like states and donor-like states according to the neutral energy level. When there is no external bias, the acceptor-like state is not occupied by electrons, and the donor-like state is occupied by electrons, and both are electrically neutral; when the external bias is positive, the Fermi level is higher than all interface states, and both the acceptor-like and donor-like states are occupied by electrons, which is reflected in the fact that the overall interface state is negatively charged.

[0130] When the external bias is negative, if the bias is small, the semiconductor is in the depletion zone, the acceptor-like state is partially occupied by electrons and is electrically neutral, and partially carries a negative charge, while the donor-like state is completely unoccupied by electrons and is electrically neutral, which is reflected in the fact that the total interface state carries a negative charge; when the external negative bias is large, the semiconductor is in the inversion zone, both the acceptor-like and donor states are not occupied by electrons, the donor-like state is electrically neutral, and the donor-like state carries a positive charge, which is reflected in the fact that the total interface state carries a positive charge.

[0131] It can be seen that the interface state will show different charge accumulation under different bias voltages. Therefore, the technical solution of the present invention uses this principle to characterize and calculate the interface state by measuring the capacitance value.

[0132] Please refer to Fig. 9 as well as Fig.10 , in S1: applying a first frequency to the first test structure and the second test structure to obtain a first capacitance value C corresponding to the photoelectric doping region, the first insulating layer and the second insulating layer hf .

[0133] In a specific embodiment, a first capacitance value is first measured at a high frequency (i.e., a first frequency), and the first capacitance value is characterized by a CV curve of the capacitance structure at the first frequency. Since the interface state defects at the high frequency (i.e., the first frequency) do not have time to respond to the change of the high frequency signal, the first capacitance value is mainly composed of the following formula: Among them, C s is the capacitance value of the photoelectric doping region, C ox is the capacitance value corresponding to the first insulating layer and the second insulating layer.

[0134] Please continue to refer to Fig. 9 as well as Fig.10 , in S2: applying a second frequency to the first test structure and the second test structure to obtain a second capacitance value C corresponding to the photoelectric doping region, the first insulating layer, the second insulating layer and the interface state lf .

[0135] Specifically, the second capacitance value is measured at a low frequency (ie, the second frequency), and the second capacitance value is characterized by a CV curve of the capacitance structure at the second frequency. Since the interface state defects at the low frequency (ie, the second frequency) will respond to the change of the high-frequency signal, the second capacitance value is mainly composed of the following formula: Among them, C it is the capacitance value corresponding to the interface state.

[0136] In this embodiment, the first frequency is at least 100 times a preset threshold, and the second frequency is less than the preset threshold.

[0137] Preferably, the first frequency is 100 to 1000 times a preset threshold, and the preset threshold is 100 to 1000 times a second frequency.

[0138] In a specific embodiment, the preset threshold is 10 KHz, the first frequency is 1 MHz, and the second frequency is 100 Hz.

[0139] In this embodiment, before testing the interface state density, the preset threshold is measured. Specifically, a high frequency is first applied to the photoelectric sensor to obtain a first CV curve corresponding to the high frequency frequency. Secondly, the high frequency frequency is continuously reduced, and during the reduction process, the CV curves corresponding to different frequencies are compared with the first CV curve. When the CV curve does not overlap with the first CV curve, it is determined that the frequency corresponding to the CV curve at this time is the preset threshold.

[0140] Please continue to refer to Fig. 9 as well as Fig.10 , in S3: according to the first capacitance value and the second capacitance value, obtain the interface state density Wherein, A is the overlapping area of ​​the photoelectric doping region and the isolation structure, q is the charge amount, and Cox is the capacitance value corresponding to the first insulating layer and the second insulating layer.

[0141] The interface state density is characterized by the interface state density of the substrate overlapping with the isolation structure.

[0142] Specifically, the interface state density In the formula, subtract C from the second capacitor value. ox Then the sum of the capacitance value of the photoelectric doping region and the capacitance value corresponding to the interface state is obtained. s +C it , subtract C from the first capacitance value ox Then the capacitance value C of the photoelectric doping region is obtained s , and finally C s +C it and C s The capacitance value C corresponding to the interface state is obtained by subtracting it , and then the interface state density can be calculated.

[0143] In other embodiments, when there are N isolation structures in the photoelectric sensor test structure, the capacitance value measured at the first frequency or the second frequency is the sum of the capacitance values ​​of the N isolation structures. Therefore, when calculating the interface state density, the measured capacitance value needs to be divided by N to obtain the average value. At this time, the interface state density is the interface state density of an isolation structure, and averaging the test results can reduce the impact of measurement error factors.

[0144] In addition, since the N isolation structures are symmetrically distributed in the substrate, the obtained interface state density can characterize the interface state density of any isolation structure.

[0145] In other embodiments, the testing method of the photoelectric sensor test structure also includes: measuring using a quasi-static method or a conductivity method. The technical solution of the present invention is not limited to this, and other calculation methods that can characterize the interface state density are within the protection scope of the technical solution of the present invention.

[0146] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A photoelectric sensor test structure, characterized in that: include: A substrate, the substrate comprising a first test area, a second test area, and a device area located between the first test area and the second test area, the substrate comprising a first surface and a second surface opposite to each other; A plurality of photoelectric doping regions and charge collection regions are located in the device region, the plurality of photoelectric doping regions and the charge collection regions and photoelectric doping regions are separated from each other, and the first surface exposes the photoelectric doping regions; a first test structure located in a first test area; a second test structure located in a second test area; a plurality of isolation structures located between the photoelectric doping regions and between the charge collection region and the photoelectric doping region, the isolation structures comprising a shielding layer; A first interconnect structure located on the surface of the first side, the first interconnect structure being electrically connected to the charge collection region and the first test structure respectively; A second interconnect structure located on the surface of the first surface, the second interconnect structure being electrically connected to the photoelectric doping region and the second test structure respectively; A third interconnection structure is located on the surface of the second side, and the third interconnection structure is electrically connected to the shielding layer and the charge collection region respectively.

2. The photoelectric sensor test structure according to claim 1, characterized in that: Also includes: a first opening located in the first test area, wherein the first opening is recessed relative to the second surface, and the first opening exposes the first test structure; a second opening located in the second test area, the second opening being recessed relative to the second surface, and the second opening exposing the second test structure; A third opening is located in the charge collection region, the third opening is recessed relative to the second surface, and a portion of the third interconnection structure is located in the third opening.

3. The photoelectric sensor test structure according to claim 2, characterized in that: Also includes: A contact layer is located on the inner wall surface of the third opening.

4. The photoelectric sensor test structure according to claim 2, characterized in that: The first interconnect structure comprises: a plurality of first conductive plugs respectively located on the surface of the charge collection region of the first surface, and a first conductive layer located on the surface of the first conductive plugs; The second interconnect structure comprises: a plurality of second conductive plugs respectively located on the surface of the photoelectric doping region of the first surface, and a second conductive layer located on the surface of the second conductive plugs; The third interconnection structure includes: a plurality of third conductive plugs located on the surface of each shielding layer, a fourth conductive plug located in the third opening, and a third conductive layer located on the surface of the third conductive plug and the surface of the fourth conductive plug.

5. The photoelectric sensor test structure according to claim 1, characterized in that: The first test structure comprises: a fourth conductive layer located in the first test area, the first surface exposing the fourth conductive layer; a first conductive plug located between the fourth conductive layer and the first interconnect structure; The second test structure includes: a fifth conductive layer located in the second test area, the fifth conductive layer being exposed by the first surface; and a second conductive plug located between the fifth conductive layer and the second interconnect structure.

6. The photoelectric sensor test structure according to claim 1, characterized in that: The isolation structure includes: a first isolation structure and a second isolation structure located at two sides of the photoelectric doping region.

7. The photoelectric sensor test structure according to claim 1, characterized in that: The isolation structure further includes: an insulating structure located between the shielding layer and the substrate.

8. The photoelectric sensor test structure according to claim 7, characterized in that: The insulating structure comprises: a first insulating layer located on the surface of the shielding layer and a second insulating layer located between the first insulating layer and the shielding layer. The shielding layer, the first insulating layer and the second insulating layer are made of different materials.

9. The photoelectric sensor test structure according to claim 2, characterized in that: The first test area further includes: a first insulating dielectric layer located on the surface of the first opening; The second test area further includes: a second insulating medium layer located on the surface of the second opening.

10. The photoelectric sensor test structure according to claim 1, characterized in that: The photoelectric sensor test structure further includes: a passivation structure located on the second surface, the first test structure surface, the charge collection area surface, the third interconnection structure surface and the second test structure surface.

11. A method for forming a photoelectric sensor test structure, characterized in that: include: Providing a substrate, the substrate having a first test area, a second test area, and a device area located between the first test area and the second test area, the substrate comprising a first surface and a second surface opposite to each other; A plurality of photoelectric doping regions and charge collection regions are formed in the device region, the plurality of photoelectric doping regions and the charge collection regions and photoelectric doping regions are separated from each other, and the first surface exposes the photoelectric doping regions; forming a first test structure in the first test area, wherein the first surface exposes the first test structure; forming a second test structure in the second test area, wherein the first surface exposes the first test structure; forming a first interconnection structure on the surface of the first surface, wherein the first interconnection structure is electrically connected to the charge collection area and the first test structure respectively; forming a second interconnect structure on the surface of the first surface, wherein the second interconnect structure is electrically connected to the photoelectric doping region and the second test structure respectively; forming a plurality of isolation structures between the photoelectric doping regions and between the charge collection region and the photoelectric doping region, and forming a shielding layer within the isolation structures; A third interconnection structure is formed on the surface of the second side, and the third interconnection structure is electrically connected to the shielding layer and the charge collection region respectively.

12. The method for forming a photoelectric sensor test structure according to claim 11, wherein: Also includes: Before or after forming the first test structure, etching is performed on the second surface of the first test area to form a first opening, wherein the first opening exposes the first test structure; Before or after forming the second test structure, etching is performed on the second surface of the second test area to form a second opening, and the second opening exposes the second test structure; etching is performed on the second surface of the charge collection area to form a third opening, and part of the third interconnection structure is located in the third opening.

13. The method for forming a photoelectric sensor test structure according to claim 12, wherein: Also includes: A contact layer is formed on the inner wall surface of the third opening.

14. The method for forming a photoelectric sensor test structure according to claim 11, wherein: The method for forming a first interconnection structure on the surface of the first surface comprises: forming a plurality of first conductive plugs on the surface of the charge collection region of the first surface respectively; forming a first conductive layer on the surface of the first conductive plugs; the method for forming a second interconnection structure on the surface of the first surface comprises: forming a plurality of second conductive plugs on the surface of the photoelectric doping region of the first surface respectively; forming a second conductive layer on the surface of the second conductive plugs; The method for forming a third interconnection structure on the second surface includes: forming a plurality of third conductive plugs on the surface of each shielding layer; forming a third conductive layer on the surface of the third conductive plugs; forming a fourth conductive plug in the third opening, wherein the surface of the fourth conductive plug is connected to the third conductive layer.

15. The method for forming a photoelectric sensor test structure according to claim 11, wherein: The method for forming a first test structure in a first test area includes: forming a fourth conductive layer in the first test area, the first surface exposing the fourth conductive layer; a first conductive plug between the fourth conductive layer and the first interconnect structure; The method for forming a second test structure in a second test area includes: forming a fifth conductive layer in the second test area, wherein the first surface exposes the fifth conductive layer; and forming a second conductive plug between the fifth conductive layer and the second interconnect structure.

16. The method for forming a photoelectric sensor test structure according to claim 11, wherein: After the shielding layer is formed in the isolation structure, the method includes: forming a first insulating layer on the surface of the shielding layer, and forming a second insulating layer between the first insulating layer and the shielding layer.

17. The method for forming a photoelectric sensor test structure according to claim 12, wherein: The method of forming a first opening in a first test area includes: forming a first insulating dielectric layer on a surface of the first opening; The method for forming the second opening in the second test area includes: forming a second insulating medium layer on the surface of the second opening.

18. The method for forming a photoelectric sensor test structure according to claim 11, wherein: Also includes: A passivation structure is formed on the surface of the second surface, the surface of the first test structure, the surface of the charge collection region, the surface of the third interconnection structure, and the surface of the second test structure.

19. A method for testing the photoelectric sensor test structure according to claim 1, characterized in that: include: Apply a first frequency to the first test structure and the second test structure to obtain a first capacitance value C hf ; Apply a second frequency to the first test structure and the second test structure to obtain a second capacitance value C lf ; According to the first capacitance value and the second capacitance value, the interface state density is obtained. Where A is the overlapping area between the photoelectric doping region and the isolation structure, q is the charge, and C ox is the capacitance value corresponding to the first insulating layer and the second insulating layer.

20. The testing method of the photoelectric sensor testing structure according to claim 19, characterized in that: The first frequency is at least 100 times a preset threshold, and the second frequency is less than the preset threshold.

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