A valley locking and valley switching circuit and method for a quasi-resonant switching power supply

Abstract

The present invention discloses a valley locking and valley switching circuit and method for a quasi-resonant switching power supply, which mainly solves the problems of discontinuous valley locking and difficulty in determining the timing time existing in the prior art. The control chip in the present invention includes a valley locking and switching module, a valley detection module connected to the valley locking and switching module, a VCO clock signal generating module and a trigger, a peak current limiting module connected to the reset terminal R pin of the trigger, and a driving module connected to the output terminal Q of the trigger. The continuous valley switching function in the present invention enables the system control loop to work continuously and reliably, avoiding the problem of large output voltage ripple caused by large frequency changes. Fast valley switching following allows the switching frequency to quickly follow the changes in load power, ensuring that the power output of the switching power supply is equal to the load power, and avoiding the problem of large output voltage fluctuations caused by large or small power output due to slow frequency following.

Description

Technical Field

[0001] The present invention belongs to the technical field of switching power supplies, and more specifically, relates to a valley locking and valley switching circuit and method for a quasi-resonant switching power supply. Background Art

[0002] As the power of the switching power supply increases, the switching loss increases. To reduce the switching loss of the switching transistor, the quasi-resonant switching technology of turning on the switching transistor when the drain voltage of the switching transistor oscillates to the valley is generally adopted, so as to achieve the purpose of reducing the turn-on loss of the switching transistor and improving the efficiency of the switching power supply. However, since it is limited to turn on the switching transistor at the valley of the oscillation, the switching frequency jumps when turning on at different valleys, and the switching frequency cannot change continuously. From the output power P of the switching power supply 0 =1 / 2*Lp*Ip 2 *f*η, where Lp is the primary inductance value, Ip is the peak current of the primary inductance, f is the switching frequency, and η is the conversion efficiency. It can be known that the output power is affected by the switching frequency. When the valley value at which the switch is turned on changes, the frequency will change significantly, resulting in a large change in the output power in a short time. The switching power supply loop control will adjust the peak current Ip of the primary inductance, which will cause the valley of the drain oscillation of the switching transistor to move, thereby affecting the valley value at which the switch is turned on again and affecting the switching frequency. In this way, the valley value at which the switch is turned on will be switched frequently, that is, the switching frequency will jump frequently. As Figure 1 shown in the waveform of the Drain terminal of the switching transistor N1 of the switching power supply, it can be known that the switching frequency of the quasi-resonant switching power supply is jointly determined by the turn-on time, the demagnetization time, and the number of valleys of the oscillation waveform. When turning on one valley in advance, the switching frequency will suddenly increase, resulting in an increase in the output power and an increase in the output voltage. Then the switching power supply loop control will reduce the FB voltage, thereby reducing the peak current Ip of the primary inductance and reducing the output power and the output voltage. This makes both the turn-on time and the demagnetization time smaller, and the valley of the drain oscillation of the switching transistor moves forward. On the contrary, it will cause the next switch to turn on one valley later, and the switching frequency will suddenly decrease again. Repeating like this, the frequency will change frequently.

[0003] To solve this problem, various valley locking techniques have been proposed in the prior art. The core principles can basically be divided into two categories. One is to judge valley locking and valley switching by outputting a feedback voltage signal FB, and the other is to judge valley locking and valley switching by the switching period and timing. The first method is relatively simple and widely used. The valley locking value is directly determined by voltage detection, and the voltage value corresponds one-to-one with the valley locking value, so the valley locking function is straightforward. However, the disadvantage is that the range of the FB feedback voltage is limited, resulting in a limited division of the valley locking interval, and it is only applicable to limited valley locking. Generally, a 6-valley locking scheme is adopted. Beyond 6 valleys, the valley locking and valley opening functions cannot be achieved, such as the control of the 7th valley locking switch cannot be realized. This will result in no valley locking function after 6 valleys, and the switching frequency will be discontinuous, increasing the difficulty of loop control adjustment. As shown in patents CN105071662B, CN112701924B, CN115065254B, and CN112332647B, patents CN114696626B and CN105262333B are essentially voltage-determined valley locking. Only in patent CN114696626B, a voltage signal CCsg related to the load is generated through the drive signal and the CS peak current. This voltage signal is actually similar to the FB voltage and can reflect the size of the output load. In patent CN105262333B, the feedback voltage FB is converted into a duty cycle time period to control valley locking. The second method has the problem of how to set the length of the timing. The oscillation period of resonance varies with the system, and the timing setting needs to adapt to the change of the oscillation period. As shown in patents CN111490681A and CN114900025B. In patent CN111490681A, a hysteresis time Tdv is introduced, and it can be seen that this time is not easy to determine and needs to be gradually adjusted. Patent CN114900025B does not specify what the resonance period is, so it is not clear how the time delay is generated and how long it is. The oscillation period of the oscillation waveform of valley detection is jointly affected by the transformer inductance, the parasitic capacitance at the drain end of the switching transistor, and the parasitic capacitance at the secondary transformer output end. Different system oscillation periods will be different, resulting in difficulty for the chip to follow this time change in setting the time delay. It is not clear in patent CN114900025B how valley locking reduces switching. However, it can be known that there is a problem with the time delay being difficult to accurately set, and the patent adopts various change treatments. Comparing with patent CN113992028B, which uses a dual-frequency clamping signal and a valley change signal to obtain the valley locking function, but its valley locking interval is only the rising edge difference of the dual-frequency clamping, with a small range, making it difficult to achieve an ideal valley locking function and resulting in frequent switching of the switching frequency. Summary of the Invention

[0004] The object of the present invention is to provide a valley locking and valley switching circuit and method for a quasi-resonant switching power supply, mainly solving the problems of discontinuous valley locking and difficult determination of timing in the prior art.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] A valley locking and valley switching circuit for a quasi-resonant switching power supply, comprising a rectifier bridge, a transformer TF1, a capacitor C1, a capacitor C2, voltage dividing resistors R1, R2, a switching transistor N1, a detection resistor Rcs, an absorption circuit and a control chip; both ends of the capacitor C1 are connected to two output terminals of the rectifier bridge, the non-corresponding terminal of the primary winding Lp of the transformer TF1 is connected to one end of the capacitor C1, the non-corresponding terminal of the auxiliary winding Laux of the transformer TF1 is connected to the other end of the capacitor C1, one end of the series-connected voltage dividing resistors R1 and R2 is connected to the corresponding terminal of the auxiliary winding Laux of the transformer TF1, the INV pin of the control chip is connected to the common terminal of the voltage dividing resistors R1 and R2, the drv pin of the control chip is connected to the gate of the switching transistor N1, one end of the detection resistor Rcs is connected to the source of the switching transistor N1 and the CS pin of the control chip, the other end of the detection resistor Rcs is connected to the FB pin of the control chip via the capacitor C2, and the other end of the series-connected voltage dividing resistors R1 and R2 is connected to the common terminal of the capacitor C2 and the detection resistor Rcs; the absorption circuit is connected between the corresponding terminal and the non-corresponding terminal of the primary winding Lp of the transformer TF1; the control chip includes a valley locking and switching module, a valley detection module, a VCO clock signal generation module and a flip-flop connected to the valley locking and switching module, a peak current limiting module connected to the reset terminal R pin of the flip-flop, and a driving module connected to the output terminal Q of the flip-flop; wherein, the valley detection module leads out the INV pin and is connected to the common terminal of the voltage dividing resistors R1 and R2, the peak current limiting module leads out the CS pin and is connected to the source of the switching transistor N1, the VCO clock signal generation module leads out the FB pin and is connected to the capacitor C2, and the driving module leads out the drv pin and is connected to the gate of the switching transistor N1.

[0007] Further, in the present invention, the valley locking and switching module includes a comparator, a valley pulse counter connected to the comparator, a valley count register connected to the valley pulse counter, a subtractor connected to the valley count register, a valley locking value module and a valley minus 1 judgment module connected to the subtractor, a valley plus 1 judgment module connected between the output terminal of the comparator and the valley locking value module, a first logic AND gate with one input terminal connected to the output terminal of the comparator, and a second logic AND gate connected to the output terminal of the first logic AND gate.

[0008] Based on the above circuit, the present invention further provides a valley lock and valley switching method for a quasi-resonant switching power supply, comprising the following steps:

[0009] S1. Rectify the AC input voltage into DC by using a rectifier bridge and store it on capacitor C1 to obtain the VIN DC input voltage, which serves as the main input power supply of the switching power supply;

[0010] S2. The main input power supply passes through transformer TF1, and then is divided by resistors R1 and R2 to obtain the INV detection signal for signal detection by the control chip;

[0011] S3. The control chip drives switch N1 to perform switching actions. Cooperating with transformer TF1, the output power is output to the output winding end of transformer TF1 cycle by cycle. The peak current of the primary winding of transformer TF1 is detected by detection resistor Rcs, and when the peak current is reached, the control chip turns off switch N1;

[0012] S4. The valley detection module of the control chip detects the INV detection signal divided and output by the auxiliary winding of the transformer and generates a valley pulse valley; the VCO clock signal generation module receives the FB voltage signal and generates a clock signal clk and a clock signal clkpre whose frequencies change with the voltage signal;

[0013] S5. The rising edge of the clock signal clk becomes high exactly at the valley number corresponding to the valley lock value, making the system in a stable equilibrium state, and outputting a switch N1 turn-on signal at the rising edge of the clock signal clk;

[0014] S6. When the load increases, the frequencies of the clock signal clk and the clock signal clkpre increase, and then the rising edges of the clock signal clk and the clock signal clkpre move forward. The rising edge of the clock signal clk maintains the valley corresponding to the valley lock value open within n valleys before the valley lock value, where n is a natural number. When the rising edge of the clock signal clk is at more than n valleys before the valley lock value, the valley switching speed is determined according to the valley difference between the rising edge of the clock signal clk and the valley lock value, realizing a stable valley lock function and a fast valley switching function; when the load decreases, the frequencies of the clock signal clk and the clock signal clkpre decrease, and then the rising edges of the clock signal clk and the clock signal clkpre move backward. When the rising edge of the clock signal clkpre is within the valley number corresponding to the valley lock value, the valley lock value remains unchanged for a certain period of time, that is, the valley lock state is maintained; thus, the valley lock interval of the valley lock function is realized through the dual clock signals; when the valley lock value deviates from the clock signal clk and the clock signal clkpre to a preset value, that is, when the valley number corresponding to the valley lock value arrives and the rising edge of the clock signal clkpre has not arrived yet, the valley lock value will be increased to realize the valley lock switching.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The present invention can achieve valley locking function, avoiding frequent switching due to inability to lock the valley during the switching process. At the same time, the method proposed by the present invention can achieve continuously adjustable valley locking, and can quickly follow the load change, making the loop control stable and reliable. Moreover, the valley locking and valley switching are not affected by the oscillation waveform period of the system, and have wide applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the quasi-resonant valley opening waveform in the prior art.

[0018] Figure 2 It is a system block diagram of the present invention.

[0019] Figure 3 It is a schematic diagram of valley locking of the present invention.

[0020] Figure 4 It is a diagram showing the relationship between the VCO clock signal generation - FB and the clk frequency in the embodiment of the present invention.

[0021] Figure 5 It is a diagram showing the relationship between the VCO dual clock signals in the embodiment of the present invention.

[0022] Figure 6 It is a block diagram of the valley locking and switching module in the present invention.

[0023] Figure 7 It is a flow chart of valley locking and valley switching in the embodiment of the present invention.

[0024] Figure 8 It is a schematic diagram of incrementing the valley locking by 1 in the embodiment of the present invention Figure 1 。

[0025] Figure 9 It is a schematic diagram of incrementing the valley locking by 1 in the embodiment of the present invention Figure 2 。

[0026] Figure 10 It is a schematic diagram of decrementing the valley locking by 1 in the embodiment of the present invention Figure 1 。

[0027] Figure 11 It is a schematic diagram of decrementing the valley locking by 1 in the embodiment of the present invention Figure 2 。

[0028] Figure 12 It is a schematic diagram of decrementing the valley locking by 1 in the embodiment of the present invention Figure 3 。 DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will be further described below in conjunction with the accompanying drawings and embodiments. The implementation manners of the present invention include but are not limited to the following embodiments.

[0030] A valley locking and valley switching circuit for a quasi-resonant switching power supply disclosed by the present invention includes a rectifier bridge, a transformer TF1, a capacitor C1, a capacitor C2, voltage dividing resistors R1, R2, a switching transistor N1, a detection resistor Rcs, an absorption circuit, and a control chip; both ends of the capacitor C1 are connected to two output ends of the rectifier bridge, the non - common end of the primary winding Lp of the transformer TF1 is connected to one end of the capacitor C1, the non - common end of the auxiliary winding Laux of the transformer TF1 is connected to the other end of the capacitor C1, one end of the series connection of the voltage dividing resistors R1 and R2 is connected to the common end of the auxiliary winding Laux of the transformer TF1, the INV pin of the control chip is connected to the common end of the voltage dividing resistors R1 and R2, the drv pin of the control chip is connected to the gate of the switching transistor N1, one end of the detection resistor Rcs is connected to the source of the switching transistor N1 and the CS pin of the control chip, the other end of the detection resistor Rcs is connected to the FB pin of the control chip through the capacitor C2, and the other end of the series connection of the voltage dividing resistors R1 and R2 is connected to the common end of the capacitor C2 and the detection resistor Rcs; the absorption circuit is connected between the common end and the non - common end of the primary winding Lp of the transformer TF1; the control chip includes a valley locking and switching module, a valley detection module, a VCO clock signal generation module, and a trigger connected to the valley locking and switching module, a peak current limiting module connected to the reset pin R of the trigger, and a driving module connected to the output pin Q of the trigger; wherein, the valley detection module leads out the INV pin and is connected to the common end of the voltage dividing resistors R1 and R2, the peak current limiting module leads out the CS pin and is connected to the source of the switching transistor N1, the VCO clock signal generation module leads out the FB pin and is connected to the capacitor C2, and the driving module leads out the drv pin and is connected to the gate of the switching transistor N1.

[0031] Among them, the valley locking and switching module includes a comparator, a valley pulse counter connected to the comparator, a valley count register connected to the valley pulse counter, a subtractor connected to the valley count register, a valley locking value module and a valley minus 1 judgment module connected to the subtractor, a valley plus 1 judgment module connected between the output end of the comparator and the valley locking value module, a first logic AND gate with one input end connected to the output end of the comparator, and a second logic AND gate connected to the output end of the first logic AND gate.

[0032] As Figure 2As shown, in this embodiment, diodes D1, D2, D3, and D4 form a rectifier bridge to rectify the AC input voltage into DC, which is stored on capacitor C1 to obtain the VIN DC input voltage, serving as the main input power supply of the switching power supply. Transformer TF1 usually has three windings, namely the primary winding Lp, the output winding Ls, and the auxiliary winding Laux. The VAUX terminal of the auxiliary winding and the Drain terminal of the primary winding are in the same phase. Therefore, the voltage at the VAUX terminal has a proportional relationship with the voltage waveform at the Drain of the switching transistor. The VAUX output from the auxiliary winding Laux is usually used to supply power to the chip and obtain the INV detection signal through voltage division by resistors R1 and R2 to provide signal detection for the control chip. The absorption circuit is used to absorb the spike voltage at the Drain terminal generated by the leakage inductance of the transformer.

[0033] The control chip drives the switching transistor N1 to perform switching actions. In cooperation with transformer TF1, it outputs power to the output winding terminal cycle by cycle. The detection resistor Rcs is used to detect the peak current of the primary winding of transformer TF1. When the peak current is reached, the control chip turns off the switching transistor N1. The FB pin of the control chip outputs an error signal obtained by comparing the output voltage fed back through the optocoupler with the reference voltage. The voltage of FB reflects the level of the output voltage. Since the output voltage is related to the load, the FB voltage also indirectly reflects the size of the output load. For example, when the output load increases, the output voltage drops, and the FB voltage will correspondingly become higher. Capacitor C2 is the loop compensation capacitor for FB. The valley detection module of the control chip detects the INV signal output by voltage division of the auxiliary winding of the transformer and generates a valley pulse valley.

[0034] As Figure 3 shown, the valley pulse valley generates a pulse signal for each valley of the oscillation waveform of the auxiliary winding Laux. The VCO clock signal generation module receives the FB voltage signal and generates a dual-clock signal clk and clkpre whose frequency changes with the voltage signal. When the frequency is appropriate, the rising edge of the clock signal clk becomes high exactly before the valley number corresponding to the valley lock value. As Figure 3 shown in, the clock signal clk becomes high exactly before the 3rd valley, so that the system is in a stable equilibrium state. When the load becomes larger, the frequency will increase, and then the rising edge of the clock signal will move forward. The rising edge of the clock signal clk will maintain the 3rd valley open within 2 valleys before the valley lock value, realizing the valley lock function. As Figure 3 shown, when the clock signal clk becomes high after the 1st valley, the 3rd valley will be locked open. When the load becomes smaller, the frequency will decrease, and then the rising edge of the clock signal will move backward. When the rising edge of the clock clkpre is within the valley number corresponding to the valley lock value, the valley lock value remains unchanged for a certain period of time, that is, the valley lock state is maintained. In this way, the valley lock interval for realizing the valley lock function is achieved through the dual-clock signal, avoiding frequent switching of valleys.

[0035] As Figure 4 shown, it is the frequency relationship between FB and the clock signal clk. The frequency of the clock signal clk increases with the increase of the FB voltage. However, the frequency of the clock signal clk is limited by the maximum switching frequency Fclk_max and the minimum switching frequency Fclk_min, which are used to limit the operating frequency range of the switching power supply. As Figure 5 shown, the frequencies of the two clock signals clk and clkpre are the same, and the rising edge of the clock signal clkpre arrives earlier than that of the clock signal clk.

[0036] In this embodiment, the working principle of the control chip is as follows: The valley locking and switching module receives the valley pulse signal valley and the clock signals clk and clkpre, generates a switch-on control signal to the set terminal S of the flip-flop, and outputs a high-level modulation pulse pwm to the drive module to output a drv signal to drive the external switch N1 to perform the turn-on operation. The peak current limiting module receives the FB voltage signal, performs an internal step-down operation, and is used to limit the peak voltage at the CS terminal, that is, to limit the peak current of the detection resistor Rcs and the primary side of the transformer, realizing the peak current limiting function. When the CS voltage reaches the divided voltage value of FB, a pulse signal is output to the reset terminal R of the flip-flop to reset the flip-flop, the pulse signal pwm becomes low, and after passing through the drive module, the drv signal becomes low, turning off the external switch N1. Among them, when the output load is large, the FB voltage is high, and the corresponding CS peak current is large, and vice versa. At the same switching frequency, there are also maximum and minimum limits for the peak value of CS.

[0037] Figure 6The valley locking and valley switching module of the present invention is shown. The valley pulse counting module is reset when the pulse signal pwm is at a high level, and then counts each valley pulse. The valley pulse count value is registered at the rising edge of the clock signal clk, and at the same time, the valley pulse counting continues. The valley locking value module compares with the valley pulse count in real time. When the valley pulse count value reaches the valley locking value, the comparator outputs a high level, and at the same time, the valley pulse counting stops. After the comparator outputs a high level, it indicates that the valley opening condition is reached. The valley opening control pulse valleyon is output through an AND logic operation with the valley pulse. When the clock signal clkpre is at a high level, the switch opening control signal pwmon is output, which acts on the set end S of the subsequent flip-flop to achieve switch opening control. At the same time, the high-level signal output by the comparator, the clock signal clk, and clkpre are jointly used to determine whether the valley locking value is incremented by 1 as the valley locking value. When the comparator outputs a high level and both the clock signals clk and clkpre are still at a low level, the valley locking value is immediately incremented by 1, and when the clock signal clkpre becomes high level and the valley pulse is satisfied at the same time, the switch opening control signal is output. When the comparator outputs a high level, the clock signal clkpre is at a high level but the clock signal clk is still at a low level, the switch opening control signal is output, and the valley locking value is incremented by 1 only after the condition is continuously satisfied for the set time T1. When the comparator outputs a high level and both the clock signals clk and clkpre are at a high level, the switch opening control signal is immediately output, and the valley locking value is not incremented. At the same time, after the valley count register registers the valley count value at the rising edge of clk, the valley locking value minus the valley count register value is sent to the valley minus 1 judgment module. When the valley difference < n, the valley locking value remains unchanged. When n <= valley difference < m, if this condition is continuously satisfied within the T2 time, the valley locking value is decremented by 1. When m <= valley difference < k, if this condition is satisfied in consecutive switching cycles within the T3 time, the valley locking value is decremented by 1. When the valley difference >= k, the valley locking value is immediately decremented by 1. Where n, m, and k are positive integers, and n < m < k. At the same time, when the valley difference is greater than 0, it indicates that the clock signal clkpre has become high before the valley count reaches the valley locking value, so the switch opening control signal is immediately output when the valley count reaches the valley locking value.

[0038] Figure 7The following is the flowchart of valley locking and valley switching of the present invention. First, set the valley locking value, including the initial setting of the valley locking value and the adjustment of adding 1 and subtracting 1 during the working process. Then, reset the valley count when each switching cycle starts, perform real-time counting on each valley pulse, and determine whether the count reaches the valley locking value. If it reaches, stop counting. Then, determine whether the rising edges of the clock signals clk and clkpre both arrive. If not, it means that the switching frequency needs to be reduced and the valley locking value needs to be increased. There are two cases. If the rising edge of the clock signal clkpre does not arrive, the valley locking value is immediately incremented by 1. If the rising edge of the clock signal clkpre arrives but the rising edge of the clock signal clk does not arrive, continuous judgment is required. If this condition is continuously satisfied within the time T1, the valley locking value is incremented by 1. And when the clock signal clkpre arrives, output the switch-on signal pwmon. The time T1 can be set to infinity, that is, no operation of incrementing the valley locking value is performed under this condition.

[0039] At the same time, during the valley counting, the counted value is latched at the rising edge of the clock signal clk to obtain the valley count latched value. Then, subtract the valley count latched value from the valley locking value to obtain the valley difference. Judge the valley difference. When the valley difference is greater than or equal to n, immediately output the switch-on signal pwmon, and at the same time, it means that the valley locking value is too large and needs to be reduced. Then, according to the deviation degree, set the adjustment rate. When n <= valley difference < m, if this condition is continuously satisfied within the time T2, the valley locking value is decremented by 1. When m <= valley difference < k, if this condition is satisfied in consecutive switching cycles within the time T3, the valley locking value is decremented by 1. When the valley difference >= k, the valley locking value is immediately decremented by 1. Where n, m, and k are positive integers, and n < m < k. The times T2 and T3 can also be clock count values, where T2 > T3, and T3 can also be set to 1 clock count value, that is, equal to one switching cycle, and the valley locking value is decremented by 1, which is the same as the processing when the valley difference >= k. At the same time, when the valley difference is greater than 0, it means that the clock signal clkpre has become high before the valley count reaches the valley locking value, so the switch-on control signal is immediately output when the valley count reaches the valley locking value.

[0040] Figures 8 - 12 This is the illustration of the embodiment of valley locking and switching of the present invention. Figure 8 This is the schematic diagram of incrementing the valley locking of the present invention Figure 1 . At the beginning, the valley locking value is 3, indicating that the switch will stably turn on at the third valley during normal operation. At this time, if the load becomes slightly smaller, the FB voltage becomes lower, the corresponding clock frequency becomes smaller, and the clock period becomes larger. Then the rising edges of both the clock clk and clkpre are delayed. At the same time, the peak current decreases, and the corresponding switch-on time and demagnetization time both decrease, and the vibration waveform moves forward, relatively reflecting the delay of the rising edges of the clock signals clk and clkpre. There appears Figure 8When the valley bottom pulse count reaches 3, clkpre has become high, but the clock signal clk has not become high. At this time, the control chip can still lock at the third valley bottom to control the switch tube to turn on and maintain the switching frequency unchanged. When the above lasts for T1 time, it indicates that the switching power supply system is stable and the valley bottom lock value is too small, then the valley bottom lock value is incremented by 1. In the subsequent switching cycle, the switch tube is controlled to turn on at the fourth valley bottom. At this time, the rising edge of the clock signal clk just corresponds to the fourth valley bottom pulse, and the system is in a balanced state. Among them, the T1 time can be set to infinity, that is, the operation of incrementing the valley bottom lock value is not performed under this condition.

[0041] Figure 9 Schematic diagram of incrementing the valley bottom lock of the present invention Figure 2 。At the beginning, the valley bottom lock value is 2. At the second valley bottom, the clock signal clkpre is already high, so the first switching cycle turns on the switch at the second valley bottom. However, as the load rapidly decreases, the FB voltage rapidly decreases, and the switching frequency significantly decreases. In the second switching cycle, when the valley bottom count reaches the valley bottom lock value of 2, the clock signal clkpre is still low, and the switch does not turn on at this time. After the rising edge of the clock signal clkpre arrives after the second valley bottom, after the valley bottom count reaches the valley bottom lock value, the valley bottom lock value is immediately incremented by 1, and the valley bottom lock value becomes 3. At the third valley bottom, the clock signal clkpre is already high, and the control switch turns on at this time. The subsequent switches are switched to turn on at valley bottom 3.

[0042] Figure 10 Schematic diagram of decrementing the valley bottom lock of the present invention Figure 1 。Another situation is that the output load increases, resulting in a higher FB voltage, a higher switching frequency, and the clock signals clk and clkpre becoming high before the valley bottom count reaches the valley bottom lock value. The valley bottom count value is reset to zero every time the switch turns on, and then the valley bottom pulses are counted in real time. During the counting process, the count value is stored at the rising edge of the clock signal clk. As shown in the figure, the valley bottom count storage value is 1. The valley bottom lock value is 4, so the valley bottom difference is 3. When the valley bottom difference of 3 lasts for T2 time, the valley bottom lock value is decremented by 1, and the valley bottom lock value becomes 3. In the subsequent switching cycle, the switch is controlled to turn on at the third valley bottom.

[0043] Figure 11 Schematic diagram of decrementing the valley bottom lock of the present invention Figure 2 。If the load changes greatly, the switching frequency also changes greatly, and a large valley bottom difference will occur. As Figure 11 shown, at the beginning, the valley bottom lock value is 4, and the clock rises to high before the first valley bottom, so the valley bottom difference is 4. After lasting for T3 time, the valley bottom lock value is decremented by 1. Compared with Figure 10 the situation, T3 is less than T2, and the valley bottom lock value switches faster.

[0044] Figure 12 Schematic of valley lock minus 1 for the present invention Figure 3 When the load switches from light load to heavy load, the original valley lock value is relatively large, but the clock frequency increases significantly, resulting in a large valley difference between the clock rising edge and valley lock. At this time, it is necessary to quickly adjust the valley lock value. As Figure 12 shown, the original valley lock value is 5. However, due to the frequency increase, the valley count value at the clk rising edge is 0. Therefore, the valley count register value is 0 and the valley difference is 5. At this time, the valley lock value is immediately decreased by 1, from 5 to 4. The next switching cycle will turn on at the 4th valley. At this time, the valley count register value may be 1 and the valley difference is 3, then it satisfies Figure 10 shown. After a duration of T2, the valley lock value is decreased by 1 again.

[0045] The present invention realizes a stable valley lock function and a fast and continuous valley switching following function. The stable valley lock function can avoid the noise problem caused by frequent switching of valley opening. The continuous valley switching function enables the system control loop to work continuously and reliably, avoiding the problem of large output voltage ripple caused by large frequency changes. The fast valley switching following can make the switching frequency quickly follow the change of load power, ensure that the power output of the switching power supply is equal to the load power, and avoid the problem of large output voltage fluctuations caused by too large or too small power output due to slow frequency following.

[0046] The above embodiments are only one of the preferred embodiments of the present invention and should not be used to limit the protection scope of the present invention. Any meaningless changes or polish made on the main design concept and spirit of the present invention, as long as the technical problems solved are still the same as those of the present invention, should be included in the protection scope of the present invention.

Claims

1. A valley locking and valley switching circuit for a quasi-resonant switching power supply, comprising a rectifier bridge, a transformer TF1, a capacitor C1, a capacitor C2, a voltage-dividing resistor R1, a voltage-dividing resistor R2, a switch tube N1, a detection resistor Rcs, an absorption circuit and a control chip; the two ends of the capacitor C1 are connected to the two output ends of the rectifier bridge, the opposite-name end of the primary winding Lp of the transformer TF1 is connected to one end of the capacitor C1, the opposite-name end of the auxiliary winding Laux of the transformer TF1 is connected to the other end of the capacitor C1, and the voltage-dividing resistor R1 and the voltage-dividing resistor R2 are connected in series at one end to the auxiliary winding Laux of the transformer TF1 The same-name end of the control chip is connected, the INV pin of the control chip is connected to the common end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2, the drv pin of the control chip is connected to the gate of the switch tube N1, one end of the detection resistor Rcs is connected to the source of the switch tube N1 and the CS pin of the control chip, the other end of the detection resistor Rcs is connected to the FB pin of the control chip via the capacitor C2, the other end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2 connected in series is connected to the common end of the capacitor C2 and the detection resistor Rcs, and the absorption circuit is connected between the same-name end and the opposite-name end of the primary winding Lp of the transformer TF1; it is characterized in that, The control chip includes a valley locking and switching module, a valley detection module connected to the valley locking and switching module, a VCO clock signal generating module and a trigger, a peak current limiting module connected to the reset end R pin of the trigger, and a driving module connected to the output end Q of the trigger; wherein, the valley detection module leads out an INV pin connected to the common end of the voltage-dividing resistor R1 and the voltage-dividing resistor R2, the peak current limiting module leads out a CS pin connected to the source of the switch tube N1, the VCO clock signal generating module leads out an FB pin connected to the capacitor C2, and the driving module leads out a drv pin connected to the gate of the switch tube N1.

2. A valley locking and valley switching circuit for a quasi-resonant switching power supply according to claim 1, characterized in that: The valley locking and switching module includes a comparator, a valley pulse counter connected to the comparator, a valley counting register connected to the valley pulse counter, a subtractor connected to the valley counting register, a valley locking value module and a valley minus 1 judgment module connected to the subtractor, a valley plus 1 judgment module connected between the output end of the comparator and the valley locking value module, an input end of a first logic AND gate connected to the output end of the comparator, and an input end of a second logic AND gate connected to the output end of the first logic AND gate.

3. A valley locking and valley switching method for a quasi-resonant switching power supply, characterized in that: A valley locking and valley switching circuit for a quasi-resonant switching power supply as claimed in claim 2 is adopted, comprising the following steps: S1, uses a rectifier bridge to rectify the AC input voltage into DC, and stores it on capacitor C1 to obtain the VIN DC input voltage, which serves as the main input power supply of the switching power supply; S2, the main input power passes through transformer TF1 and then through resistors R1 and R2 to obtain the INV detection signal to provide signal detection to the control chip; S3, the control chip drives the switch tube N1 to perform switching action, cooperates with the transformer TF1, outputs power to the output winding end of the transformer TF1 cycle by cycle, detects the peak current of the primary winding of the transformer TF1 through the detection resistor Rcs, and when the peak current is reached, the control chip turns off the switch tube N1; S4, the valley detection module of the control chip detects the INV detection signal output by the transformer auxiliary winding and generates a valley pulse valley; the VCO clock signal generation module receives the FB voltage signal and generates a clock signal clk and a clock signal clkpre whose frequency changes with the voltage signal; S5, the rising edge of the clock signal clk becomes high just at the valley number corresponding to the valley lock value, so that the system is in a stable equilibrium state, and the switch tube N1 is turned on at the rising edge of the clock signal clk; S6, when the load becomes larger, the frequencies of the clock signal clk and the clock signal clkpre become larger, and then the rising edges of the clock signal clk and the clock signal clkpre move forward, and the rising edge of the clock signal clk maintains the valley opening corresponding to the valley lock value within n valleys before the valley lock value, where n is a natural number, and when the rising edge of the clock signal clk is greater than n valleys before the valley lock value, the valley switching speed is determined according to the valley difference between the rising edge of the clock signal clk and the valley lock value, so as to realize a stable valley lock function and a fast valley switching function; when the load becomes smaller, the clock signal clk The frequencies of lk and clock signal clkpre become smaller, and then the rising edges of clock signal clk and clock signal clkpre move back. When the rising edge of clock signal clkpre is within the valley number corresponding to the valley lock value, the valley lock value remains unchanged for a certain period of time, that is, the valley lock state is maintained. In this way, the valley lock interval of the valley lock function is realized by dual clock signals. When the valley lock value deviates from the clock signals clk and clkpre to the preset value, that is, when the valley number corresponding to the valley lock value is arrived, the rising edge of clock signal clkpre has not arrived yet, the valley lock value will be increased to realize valley lock switching.

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