Gain adjusting method and gain adjusting circuit of filter amplifier

Abstract

The invention discloses a gain adjusting method and a gain adjusting circuit of a filter amplifier, and the gain adjusting method comprises the steps: according to a sequence from a most significant bit to a least significant bit, selecting an unselected significant bit from a control signal as a current significant bit, and setting the current significant bit as a first value; detecting a voltage output signal of the filter amplifier to obtain a detection voltage, and comparing the detection voltage with a reference voltage to generate a comparison signal; when the detection voltage is larger than the reference voltage, the value of the current effective bit is updated to be a second value, otherwise, the current effective bit is maintained to be the first value, and parameters of the filter amplifier are adjusted according to the obtained control signal so as to adjust the gain of the filter amplifier; and judging whether the current significant bit is the lowest significant bit, if so, ending gain adjustment, and otherwise, skipping to the first step. Therefore, the gain continuously approaches the expected gain through multiple times of stepping adjustment, the optimal signal-to-noise ratio is obtained, and signal saturation or dynamic range waste is avoided.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a gain adjustment method and a gain adjustment circuit for a filter amplifier. Background Art

[0002] With the development of communication technology, most modern wireless communication devices are equipped with a transceiver that can both send and receive data. Figure 1a shows a schematic structural diagram of a transceiver system, Figure 1b Shows Figure 1a The following is a comparison of the effects of excessive gain and too small gain on the circuit transmission signal of the transceiver system. Figure 1a As shown, the transceiver system includes a receiver 103 and a transmitter 104, which are coupled to an antenna 102 and an antenna 101, respectively. The receiver 103 includes a low noise amplifier 110 (LNA), a mixer 120, a transimpedance amplifier 130, and a programmable gain amplifier 140. The low noise amplifier 110 receives an input signal and converts it into a current signal. The mixer 120 mixes the current signal to generate an intermediate frequency signal. The intermediate frequency signal is processed by the transimpedance amplifier circuit 130, which converts the current signal into a voltage signal and filters out interference signals. The programmable gain amplifier then filters and amplifies the signal.

[0003] In actual applications, when using a radar system to receive signals, different energy levels will be received due to the size, material, and distance of the object. If only a fixed gain is used, it will have a great impact on the received signal. Figure 1b On the left, when the gain is very large, if a large self-interference signal (Self-Interference) 105 leaks from the transmitter 104 to the receiver 103, or receives signals reflected by multiple objects, or receives other signals with strong energy, the signal may be clamped by the amplifier during the amplification process, causing signal distortion and even generating high-order harmonics. Figure 1b On the right side, when the gain is small, the signal is amplified to a small extent, resulting in an excessively large signal-to-noise ratio and wasting the dynamic range of the analog-to-digital converter.

[0004] Therefore, due to the uncertainty of the environment, the current filter amplifier uses a small gain to avoid signal saturation, resulting in the inability to fully use the dynamic range most of the time and a large signal-to-noise ratio. Therefore, the gain of the current filter amplifier cannot be adjusted according to the environment, resulting in excessive or too small gain in some scenarios, causing signal saturation or dynamic range waste, and failing to obtain the most appropriate signal-to-noise ratio. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a gain adjustment method and a gain adjustment circuit for a filter amplifier.

[0006] According to one aspect of the present invention, a gain adjustment method for a filter amplifier is provided, wherein the filter amplifier is located on a receiving path of a transceiver to filter and amplify a signal received by an antenna to generate a voltage output signal, wherein the gain adjustment method comprises: selecting an unselected valid bit from a control signal in order from the most significant bit to the least significant bit as a current valid bit, and setting it to a first value; detecting the voltage output signal of the filter amplifier by a peak detector to obtain a detection voltage, and comparing the detection voltage with a reference voltage to generate a comparison signal; updating the control signal according to the comparison signal to update the value of the current valid bit to a second value when the detection voltage is greater than the reference voltage, otherwise the current valid bit is maintained at the first value, and then adjusting the parameters of the filter amplifier according to the obtained control signal to adjust the gain of the filter amplifier; and determining whether the current valid bit is the least significant bit, if so, ending the gain adjustment, otherwise jumping to the step of selecting an unselected valid bit from the control signal in order from the most significant bit to the least significant bit as the current valid bit, and setting it to the first value.

[0007] Optionally, when the current valid bit of the control signal is a first value, the gain of the filter amplifier is increased, and when the current valid bit of the control signal is a second value, the gain of the filter amplifier is decreased.

[0008] Optionally, the gain adjustment method of the filter amplifier further includes: setting the number of effective bits of the control signal according to the number of resistor and capacitor arrays of the filter amplifier.

[0009] Optionally, the gain adjustment method for the filter amplifier further includes: reading a reference voltage corresponding to the expected gain from a data table, wherein the data table pre-stores a mapping relationship between the gain and the reference voltage.

[0010] Optionally, the current valid bit is selected from the control signal by using a binary search or a linear search method.

[0011] Optionally, the first value is 1 and the second value is 0.

[0012] Optionally, the parameters are resistance values ​​and capacitance values ​​in a resistor and capacitor array of the filter amplifier.

[0013] According to another aspect of the present invention, a gain adjustment circuit of a filter amplifier is provided, wherein the filter amplifier is located on a receiving path of a transceiver to filter and amplify a signal received by an antenna to generate a voltage output signal, wherein the gain adjustment circuit comprises: a gain adjustment circuit, which provides a control signal, and selects one valid bit that has not been selected from the control signal in order from the most significant bit to the least significant bit as the current valid bit, and sets it to a first value each time; a peak detector, which detects the voltage output signal of the filter amplifier to obtain a detection voltage, and compares the detection voltage with a reference voltage to generate a comparison signal, wherein the gain adjustment circuit also updates the current valid bit according to the comparison signal, so as to update the value of the current valid bit to a second value when the detection voltage is greater than the reference voltage, otherwise, the current valid bit is maintained at the first value, and then the parameters of the filter amplifier are adjusted according to the obtained control signal to adjust the gain of the filter amplifier.

[0014] Optionally, the voltage output signal is an AC signal, the reference voltage is a DC signal, and the peak detector converts the AC signal into a DC signal.

[0015] Optionally, the filter amplifier includes a transimpedance amplifier and a programmable gain amplifier, and the output end of each filter amplifier is connected to one of the gain adjustment circuits.

[0016] The gain adjustment method and gain adjustment circuit of the filter amplifier provided by the present invention select a reference voltage according to the specific use scenario of the filter amplifier, and the voltage output signal output by the filter amplifier is converted into a DC detection voltage by a peak detector, and then compared with the reference voltage to obtain a comparison result. Then, the value of the current valid bit of the control signal is adjusted according to the comparison result, so as to adjust the parameters of the filter amplifier to adjust the gain. Each time, a current valid bit of the control signal is adjusted to achieve step adjustment of the gain, so that the gain of the filter amplifier is constantly close to the expected gain. The gain adjusted according to the final control signal is the gain that is most suitable for the use scenario, and the optimal signal-to-noise ratio can be obtained to avoid signal saturation or waste of dynamic range.

[0017] Furthermore, the mapping relationship between the expected gain and the reference voltage is stored in the data table in advance, and the reference voltage can be adjusted at any time according to the usage scenario and the working environment, so that the control signal changes with the usage scenario, and the gain that best matches the current working environment of the filter amplifier is obtained, ensuring the optimal signal-to-noise ratio. In addition, the number of effective bits can be set according to the number of resistor and capacitor arrays, and then the resistor and capacitor values ​​of the resistor and capacitor array are adjusted according to the adjusted control signal, and the cycle is repeated to continuously optimize the signal-to-noise ratio.

[0018] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1a A structural schematic diagram of a transceiver system is shown.

[0020] Figure 1b Shows Figure 1a A comparison chart of the impact of excessive gain and too small gain on the circuit transmission signal of the transceiver system.

[0021] Figure 2 A schematic structural block diagram of a gain adjustment circuit of a filter amplifier according to an embodiment of the present invention is shown.

[0022] Figure 3 A schematic flow chart of a gain adjustment method for a filter amplifier according to a first embodiment of the present invention is shown.

[0023] Figure 4 Shows Figure 2 Schematic circuit diagram of a mid-impedance amplifier, programmable gain amplifier, and peak detector.

[0024] Figure 5 The schematic flow chart of the gain adjustment method of the filter amplifier according to the second embodiment of the present invention is shown. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0026] Figure 2 A schematic structural block diagram of a gain adjustment circuit of a filter amplifier according to an embodiment of the present invention is shown.

[0027] like Figure 2As shown, the filter amplifier of the present invention is arranged on the receiving path of the transceiver, and performs operations such as filtering and amplifying the signal received by the antenna to generate a voltage output signal. The filter amplifier may include a transimpedance amplifier 310 TIA (Trans impedance Amplifier) ​​and a programmable gain amplifier 320 PGA (Programmable-Gain Amplifier), and the output end of each amplifier may be connected to a gain adjustment circuit 200. The transimpedance amplifier 310 is connected to the programmable gain amplifier 320, for example, so that the current input signal Iin can be converted into a voltage output signal Vout. The transimpedance amplifier 310 of this embodiment can filter out low-frequency interference signals in the current input signal Iin. The transimpedance amplifier 310 is used to receive the current input signal Iin for filtering and convert it into a voltage output signal Vout, and the programmable gain amplifier 320 performs gain adjustment on the signal output by the transimpedance amplifier 310.

[0028] Any gain adjustment circuit 200 of this embodiment may include a gain adjustment circuit 220 and a peak detector 210. The gain adjustment circuit 220 is used to provide a control signal Vctrl, and select an unselected valid bit from the control signal Vctrl in order from the most significant bit to the least significant bit as the current valid bit, and set it to the first value. Then the peak detector 210 detects the voltage output signal Vout of the filter amplifier to obtain the detection voltage Vo, and compares the detection voltage Vo with the reference voltage Vref to generate a comparison signal Vcom. The gain adjustment circuit 220 receives the comparison signal Vcom and updates the current valid bit according to the comparison signal Vcom. Specifically, when the detection voltage Vo is greater than the reference voltage Vref, it is considered that the current gain is large, so the value of the current valid bit is updated to the second value. Otherwise, it is considered that the current gain is too small, so that the current valid bit maintains the first value, and then the parameters of the filter amplifier are adjusted according to the control signal Vctrl obtained after adjustment to adjust the gain of the filter amplifier. When the current valid bit is the first value, the gain of the filter amplifier is increased, and when the current valid bit is the second value, the gain of the filter amplifier is reduced. The first value is, for example, a binary number 1, and the second value is, for example, a binary number 0.

[0029] The voltage output signal Vout is an AC signal, the reference voltage Vref is a DC signal, and the peak detector 210 is used to convert the voltage output signal Vout of the AC signal into a detection voltage Vo of the DC signal. As long as the circuit can convert the AC signal into a DC signal that can correspond to its amplitude, it can be used as the peak detector 210. Therefore, the circuit form of the peak detector 210 of this embodiment is diversified.

[0030] In this embodiment, the reference voltage Vref corresponds to the expected gain, for example, the mapping relationship between the gain and the reference voltage Vref is stored in a data table in advance, and then the peak detector 210 reads the reference voltage Vref corresponding to the required expected gain from the data table. The control signal Vctrl output by the gain adjustment circuit 220 is adjusted according to the comparison result, and the parameters of the filter amplifier can be adjusted according to the control signal Vctrl. The parameters here are, for example, the resistance value and the capacitance value in the resistor and capacitor array. The filter amplifier usually has a resistor and capacitor array, including a combination circuit of multiple resistors and capacitors, for example, a capacitor and a resistor are connected in parallel as a resistor and capacitor group, and multiple resistor and capacitor groups form a resistor and capacitor array. Correspondingly, the number of effective bits of the control signal Vctrl can also be set according to the number of resistor and capacitor arrays, for example, the number of effective bits is set according to the number of resistor and capacitor groups, and each resistor and capacitor group is adjusted according to one effective bit. Or other bit setting methods can also be adopted, which are not given examples one by one here.

[0031] Figure 3 A schematic flow chart of a gain adjustment method for a filter amplifier according to a first embodiment of the present invention is shown.

[0032] like Figure 3 As shown, the gain adjustment method of this embodiment can be applied to the above Figure 2 The gain adjustment circuit shown in FIG. 1 is used to gradually adjust the gain of the filter amplifier. Figure 2 The same circuit structure will not be described again in detail here. The gain adjustment method of the filter amplifier of this embodiment includes the following steps.

[0033] In step S101 , in order from the most significant bit to the least significant bit, an unselected significant bit is selected from the control signal as the current significant bit, and is set to a first value.

[0034] In this embodiment, a binary search or linear search method can be used to select the most significant bit or the current significant bit from the control signal Vctrl. One significant bit is selected from the control signal Vctrl in the order from the most significant bit to the least significant bit, and is set to the first value. The significant bit is subsequently adjusted according to the comparison result. The control signal Vctrl obtained is the final adjustment result until all significant bits are adjusted.

[0035] In step S102, the peak detector detects the voltage output signal of the filter amplifier to obtain a detection voltage, and compares the detection voltage with a reference voltage to generate a comparison signal.

[0036] In this step, the peak detector 210 converts the voltage output signal Vout of the AC signal output by the filter amplifier into a detection voltage Vo of a DC signal, and then compares the detection voltage Vo with a reference voltage Vref corresponding to the expected gain to obtain a comparison result.

[0037] In step S103, the control signal is updated according to the comparison signal to update the value of the current valid bit to the second value when the detection voltage is greater than the reference voltage, otherwise the current valid bit is maintained at the first value, and then the parameters of the filter amplifier are adjusted according to the obtained control signal to adjust the gain of the filter amplifier.

[0038] In this step, the current effective bit of the control signal Vctrl is adjusted according to the comparison result. When the comparison result indicates that the detection voltage Vo is greater than the reference voltage Vref, it is considered that the current gain exceeds the expected gain, so that the current effective bit of the control signal Vctrl maintains the first value, thereby increasing the gain of the filter amplifier by adjusting the parameters. Correspondingly, when the comparison result indicates that the detection voltage Vo is less than the reference voltage Vref, it is considered that the current gain does not reach the expected gain, so that the current effective bit of the control signal Vctrl is updated to the second value, thereby reducing the gain of the filter amplifier by adjusting the parameters. The first value is, for example, 1, and the second value is, for example, 0. Of course, the numerical values ​​of the first value and the second value can also be opposite, depending on the actual circuit setting. The parameters adjusted are, for example, the resistance value and the capacitance value in the resistor and capacitor array of the filter amplifier.

[0039] In step S104, it is determined whether the current valid bit is the least significant bit. If so, the gain adjustment is terminated. Otherwise, the process jumps to the step of selecting an unselected valid bit from the control signal as the current valid bit in order from the most significant bit to the least significant bit, and setting it to the first value.

[0040] In this step, it is determined whether the current valid bit is the least significant bit, and if so, the control signal Vctrl at this time is output as the final adjustment result. If not, step S101 is continued, and the next valid bit is selected to continue adjustment until all valid bits are adjusted.

[0041] Figure 4 Shows Figure 2 Schematic circuit diagram of a mid-impedance amplifier, programmable gain amplifier, and peak detector.

[0042] like Figure 4As shown, a possible circuit structure of a transimpedance amplifier 310, a programmable gain amplifier 320 and a peak detector 210 is provided. Other circuit forms may also be used in other embodiments. The transimpedance amplifier 310 receives a current input signal Iin for filtering and converts it into a voltage output signal Vout. The transimpedance amplifier 310 includes a feedback filter, which is located on the negative feedback path of the transimpedance amplifier 310 to filter out interference signals in the current input signal Iin. If the current input signal Iin is, for example, a differential signal, the transimpedance amplifier 310 conducts the differential signal into a first differential path 301 and a second differential path 302. The transimpedance amplifier 310 includes a first operational amplifier A1. The input end 311 of the first differential path 301 is, for example, the positive input end of the first operational amplifier A1, and the input end 312 of the second differential path 302 is, for example, the negative input end of the first operational amplifier A1. In this embodiment, the output end 313 of the first differential path 301 is connected to the input end 312 of the second differential path 302 via a feedback filter, and the output end 314 of the second differential path 302 is connected to the input end 311 of the first differential path 301 via a feedback filter. The transimpedance amplifier 310 also includes a first feedback resistor R1 and a first feedback capacitor C1 connected to the first operational amplifier and connected between the input end 311 and the output end 313 on the first differential path 301, and a second feedback resistor R2 and a second feedback capacitor C2 connected between the input end 312 and the output end 314 on the second differential path 302. The first feedback resistor R1 and the first feedback capacitor C1 are equivalent to a low-pass filter, and the second feedback resistor R2 and the second feedback capacitor C2 are equivalent to a second low-pass filter. Each low-pass filter can be regarded as a resistor and capacitor group, and multiple resistor and capacitor groups form a resistor and capacitor array.

[0043] Further, the feedback filter includes a second operational amplifier A2, a third feedback capacitor C3 and a fourth feedback capacitor C4, the positive input terminal and the negative input terminal of the second operational amplifier A2 are respectively connected to the output terminal 314 of the second differential path and the output terminal 313 of the first differential path, for example, the third feedback capacitor C3 is connected between the positive input terminal and the output terminal of the second operational amplifier A2, and the fourth feedback capacitor C4 is connected between the negative input terminal and the output terminal of the second operational amplifier A2. The feedback filter further includes a third feedback resistor R3, a fourth feedback resistor R4, a fifth feedback resistor R5 and a sixth feedback resistor R6. The third feedback resistor R3 is connected between the output terminal 313 of the first differential path and the negative input terminal of the second operational amplifier A2. The fourth feedback resistor R4 is connected between the input terminal 312 of the second differential path and the output terminal of the second operational amplifier A2. The fifth feedback resistor R5 is connected between the output terminal 314 of the second differential path and the positive input terminal of the second operational amplifier A2. And the sixth feedback resistor R6 is connected between the input terminal 311 of the first differential path and the output terminal of the second operational amplifier A2.

[0044] Further, the programmable gain amplifier 320 includes a third operational amplifier A3, a fifth feedback capacitor C5 and a seventh feedback resistor R7, as well as a sixth feedback capacitor C6 and an eighth feedback resistor R8. The programmable gain amplifier 320 also includes a feedback filter, and the circuit structure of the feedback filter is the same as described above. The seventh feedback resistor R7 and the fifth feedback capacitor C5 are equivalent to a low-pass filter, and the eighth feedback resistor R8 and the sixth feedback capacitor C6 are equivalent to a second low-pass filter. The circuit structure is the same as that of the transimpedance amplifier 310 and is not repeated here. The feedback filter includes a fourth operational amplifier A4, a capacitor C7, a capacitor C8, and resistors R11, R12, R13 and R14. The specific connection method between each circuit element is shown in the attached drawings, which are not described one by one here.

[0045] Further, the peak detector 210 includes a hysteresis comparator, whose positive input terminal and reverse input terminal receive the detection voltage Vo and the reference voltage Vref respectively, and the output terminal outputs the comparison signal Vcom. The peak detector 210 also includes a transistor M1 and a transistor M2, whose source terminals are connected and grounded through a resistor R3 and a current source A01, and whose drain terminals are connected to the power supply terminal. The control terminal of the transistor M1 and the control terminal of the transistor M2 are respectively connected to one end of the capacitor C02 and one end of the capacitor C01, and the other end of the capacitor C01 and the other end of the capacitor C02 receive the voltage output signal Vout. One end of the resistor R01 and one end of the resistor R02 receive the bias voltage Vb, and the other end of the resistor R01 and the other end of the resistor R02 are respectively connected to the control end of the transistor M1 and the control end of the transistor M2. The capacitor C03 is connected in parallel to the two ends of the current source A01. Thus, the AC voltage output signal Vout is converted into a DC detection voltage Vo through the above circuit structure. Then the detection voltage Vo is compared with the reference voltage Vref to obtain the comparison signal Vcom. The peak detector 210 may have many circuit forms, and only one example is given here, which is not intended to limit the present invention.

[0046] Figure 5 The schematic flow chart of the gain adjustment method of the filter amplifier according to the second embodiment of the present invention is shown.

[0047] like Figure 5 As shown, the gain adjustment method of this embodiment includes steps S210 to S208.

[0048] In step S210, the number of effective bits of the control signal is set according to the number of resistor and capacitor arrays of the filter amplifier. In this step, for example, the number of effective bits can be set to be the same as the number of resistor and capacitor groups, or other setting methods can be used.

[0049] In step S202, a reference voltage corresponding to the expected gain is read from a data table, in which a mapping relationship between the gain and the reference voltage is pre-stored. In this step, a mapping relationship between the gain and the reference voltage can be pre-set and stored in the data table. The reference voltage is selected according to the expected gain required by the actual working environment of the filter amplifier.

[0050] In step S203, the most significant bit of the control signal is retrieved as the current significant bit, and is set to be the first value. In this step, the most significant bit is found by binary search or linear search, and is set to be the first value.

[0051] In step S204, the peak detector detects the voltage output signal of the filter amplifier to obtain a detection voltage, and compares the detection voltage with a reference voltage to generate a comparison signal.

[0052] In step S205, if the detection voltage is greater than the reference voltage, the value of the current valid bit is updated to the second value, otherwise the current valid bit is maintained at the first value, and the parameters of the filter amplifier are adjusted according to the obtained control signal.

[0053] In step S206, it is determined whether the current more significant bit of the control signal is the least significant bit. If the current more significant bit is the least significant bit, step S208 is executed, otherwise step S207 is executed.

[0054] In step S207, the next valid bit of the control signal is used as the current valid bit and is set to the first value. After executing this step, the process returns to step S204.

[0055] In step S208, the gain calibration of the filter amplifier is completed, and the current control signal is the final calibration value.

[0056] In summary, the gain adjustment method and gain adjustment circuit of the filter amplifier provided by the present invention will select a reference voltage according to the specific use scenario of the filter amplifier, and the peak detector will convert the voltage output signal output by the filter amplifier into a DC detection voltage, and then compare it with the reference voltage to obtain a comparison result. Then, the value of the current valid bit of the control signal is adjusted according to the comparison result, so as to adjust the parameters of the filter amplifier to adjust the gain. Each time, a current valid bit of the control signal is adjusted to achieve step adjustment of the gain, so that the gain of the filter amplifier is constantly approaching the expected gain. The gain adjusted according to the final control signal is the gain that is most suitable for the use scenario, and the optimal signal-to-noise ratio can be obtained to avoid signal saturation or waste of dynamic range.

[0057] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.

[0058] It should also be understood that the terms and expressions used herein are for descriptive purposes only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. A gain adjustment method for a filter amplifier, wherein the filter amplifier is located on a receiving path of a transceiver to filter and amplify a signal received by an antenna to generate a voltage output signal, wherein: The gain adjustment method comprises: In order from the most significant bit to the least significant bit, select an unselected significant bit from the control signal as the current significant bit, and set it to the first value; The peak detector detects the voltage output signal of the filter amplifier to obtain a detection voltage, and compares the detection voltage with a reference voltage to generate a comparison signal; updating the control signal according to the comparison signal, so as to update the value of the current valid bit to the second value when the detection voltage is greater than the reference voltage, otherwise, the current valid bit is maintained at the first value, and then adjusting the parameters of the filter amplifier according to the obtained control signal to adjust the gain of the filter amplifier; and Determine whether the current valid bit is the least significant bit. If so, end the gain adjustment. Otherwise, jump to the step of selecting an unselected valid bit from the control signal as the current valid bit in order from the most significant bit to the least significant bit, and set it to the first value.

2. The gain adjustment method according to claim 1, wherein: When the current valid bit of the control signal is a first value, the gain of the filter amplifier is increased; when the current valid bit of the control signal is a second value, the gain of the filter amplifier is reduced.

3. The gain adjustment method according to claim 1, further comprising: The number of effective bits of the control signal is set according to the number of resistor and capacitor arrays of the filter amplifier.

4. The gain adjustment method according to claim 1, further comprising: A reference voltage corresponding to the expected gain is read from a data table, wherein a mapping relationship between the gain and the reference voltage is pre-stored in the data table.

5. The gain adjustment method according to claim 1, wherein: The current valid bit is selected from the control signal by using a binary search or a linear search method.

6. The gain adjustment method according to claim 2, wherein: The first value is 1, and the second value is 0.

7. The gain adjustment method according to claim 1, wherein: The parameters are resistance values ​​and capacitance values ​​in the resistor and capacitor array of the filter amplifier.

8. A gain adjustment circuit for a filter amplifier, wherein the filter amplifier is located on a receiving path of a transceiver to filter and amplify a signal received by an antenna to generate a voltage output signal, wherein: The gain adjustment circuit comprises: The gain adjustment circuit provides a control signal, selects one valid bit that has not been selected from the control signal in order from the most significant bit to the least significant bit as the current valid bit, and sets it to a first value; The peak detector detects the voltage output signal of the filter amplifier to obtain a detection voltage, and compares the detection voltage with a reference voltage to generate a comparison signal. Among them, the gain adjustment circuit also updates the current valid bit according to the comparison signal, so that when the detection voltage is greater than the reference voltage, the value of the current valid bit is updated to the second value, otherwise the current valid bit is maintained at the first value, and then the parameters of the filter amplifier are adjusted according to the obtained control signal to adjust the gain of the filter amplifier.

9. The gain adjustment circuit according to claim 8, wherein: The voltage output signal is an AC signal, the reference voltage is a DC signal, and the peak detector converts the AC signal into a DC signal.

10. The gain adjustment circuit according to claim 8, wherein: The filter amplifier comprises a transimpedance amplifier and a programmable gain amplifier, and the output end of each filter amplifier is connected to one of the gain adjustment circuits.

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