Semiconductor device and manufacturing method thereof
By forming a high density sacrificial layer and removing the insulating layer at the bottom of the opening during the production of non-planar semiconductor devices, structural defects and reliability problems are solved, and higher product reliability and lower process difficulty are achieved.
Patent Information
- Application Number
- CN202410679629.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-28
- Publication Date
- 2025-02-07
AI Technical Summary
During the production of non-planar semiconductor devices, structural defects are prone to occur, resulting in poor product reliability.
By forming a stacked structure on the substrate, and forming a second insulating layer on the side wall and bottom of the opening, then forming a sacrificial layer with a density greater than 2.2 g/cm3 on its surface, finally removing the sacrificial layer and the second insulating layer at the bottom of the opening. The layer and the first insulating layer to form a trench.
It reduces the occurrence of structural defects, improves product reliability, and reduces the probability of plasma penetration through a high density sacrificial layer, reducing the difficulty of subsequent processes.
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Figure CN119403149A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art
[0002] Non-planar semiconductor devices are widely used in mobile devices such as mobile phones and tablet computers due to their advantages of small size, large capacity, high integration and fast transmission speed. However, structural defects are prone to occur during the manufacturing process of non-planar semiconductor devices, and product reliability is poor.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0004] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, which can reduce structural defects and improve product reliability.
[0005] According to one aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:
[0006] A stacking structure is formed on a substrate, wherein the stacking structure comprises a first conductive layer, a first insulating layer and a second conductive layer which are stacked and distributed in sequence along a vertical direction; an opening is formed in the stacking structure, and in a thickness direction of the stacking structure, the opening penetrates the second conductive layer and extends into the first insulating layer;
[0007] forming a second insulating layer on the sidewalls and bottom of the opening;
[0008] A sacrificial layer is formed on the surface of the second insulating layer, and the density of the sacrificial layer is greater than 2.2 g / cm 3 ;
[0009] The sacrificial layer at the bottom of the opening, the second insulating layer at the bottom of the opening, and the first insulating layer at the bottom of the opening are removed to form a trench exposing at least a portion of the surface of the first conductive layer.
[0010] In an exemplary embodiment of the present disclosure, the material of the sacrificial layer is silicon nitride or carbon.
[0011] In an exemplary embodiment of the present disclosure, the thickness of the sacrificial layer is less than 5 nm.
[0012] In an exemplary embodiment of the present disclosure, removing the sacrificial layer located at the bottom of the opening, the second insulating layer located at the bottom of the opening, and the first insulating layer located at the bottom of the opening comprises the following steps:
[0013] S1, forming a protective layer on the sidewall and bottom of the opening, wherein the thickness of the protective layer at the bottom of the opening is less than the thickness of the protective layer on the sidewall of the opening;
[0014] S2, etching the protective layer located at the bottom of the opening and the film layer adjacent to the protective layer;
[0015] S3, cleaning the opening to remove residues from the etching process;
[0016] Steps S1 to S3 are repeated until the first insulating layer does not exist on the surface of the region of the first conductive layer directly facing the bottom of the opening.
[0017] In an exemplary embodiment of the present disclosure, the ratio of the time required to form the protection layer to the time required to etch is 1:1 to 1:3.
[0018] In an exemplary embodiment of the present disclosure, the material of the protection layer is carbon.
[0019] In an exemplary embodiment of the present disclosure, when the material of the sacrificial layer is silicon nitride, cleaning the opening to remove residues in the etching process includes:
[0020] The opening after the etching is flushed with oxygen.
[0021] In an exemplary embodiment of the present disclosure, when the material of the sacrificial layer is carbon, cleaning the opening to remove residues in the etching process includes:
[0022] The opening after the etching is flushed with argon gas.
[0023] In an exemplary embodiment of the present disclosure, the method for manufacturing the semiconductor device further includes:
[0024] After forming the trench, the sacrificial layer is removed.
[0025] In an exemplary embodiment of the present disclosure, removing the sacrificial layer includes:
[0026] The sacrificial layer is removed by a wet etching process, and an etching selectivity ratio of the sacrificial layer to the second insulating layer, the first insulating layer, and the first conductive layer is greater than 50.
[0027] In an exemplary embodiment of the present disclosure, when the material of the sacrificial layer is silicon nitride, the etching solution of the wet etching is a phosphoric acid solution; when the material of the sacrificial layer is carbon, the etching solution of the wet etching is hydrofluoric acid.
[0028] In an exemplary embodiment of the present disclosure, the stacked structure further includes a third insulating layer, the third insulating layer is located on a side of the second conductive layer away from the substrate, the opening penetrates the third insulating layer and the second conductive layer at the same time, the second insulating layer is also formed on a surface of a sidewall of the opening surrounded by the third insulating layer, and the method for manufacturing the semiconductor device further includes:
[0029] forming a channel layer on a surface of the second insulating layer located on a sidewall of the trench;
[0030] Filling the trench having the channel layer with an insulating material to form an insulating dielectric layer;
[0031] A third conductive layer is formed on a side of the channel layer away from the substrate.
[0032] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device is manufactured using any one of the semiconductor device manufacturing methods described above.
[0033] The semiconductor device and its manufacturing method disclosed in the present invention, due to the high density of the sacrificial layer located on the side wall of the opening, in the process of removing the sacrificial layer, the second insulating layer and the first insulating layer at the bottom of the opening, the sacrificial layer is not easily penetrated by plasma, and the probability of pinholes appearing inside it is low, which can reduce the probability of plasma passing through the sacrificial layer and then damaging the second insulating layer on the side wall of the opening, that is, the probability of structural damage to the second insulating layer can be reduced, which helps to ensure the insulation effect, and then reduce the probability of coupling or short circuit between the subsequently formed channel layer and the second conductive layer, thereby improving product reliability. At the same time, due to the high density of the sacrificial layer, under the same protection effect, the thickness of the sacrificial layer in the present invention can be thinner, that is, the thickness of the sacrificial layer attached to the side wall of the opening is thinner, leaving a larger process space for etching the film layer at the bottom of the opening (for example, the sacrificial layer, the second insulating layer and the first insulating layer), which helps to reduce the difficulty of subsequent processes.
[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0036] Figure 1The flowchart is a method for manufacturing a semiconductor device in an embodiment of the present disclosure.
[0037] Figure 2 It is a schematic diagram of the structure after completing step S110 in the embodiment of the present disclosure.
[0038] Figure 3 It is a schematic diagram of the structure after completing step S120 in the embodiment of the present disclosure.
[0039] Figure 4 It is a schematic diagram of the structure after completing step S130 in the embodiment of the present disclosure.
[0040] Figure 5 It is a schematic diagram of the structure after completing step S140 in the embodiment of the present disclosure.
[0041] Figure 6 It is a schematic diagram of the structure after completing step S150 in the embodiment of the present disclosure.
[0042] Figure 7 It is a schematic diagram of the structure after completing step S230 in the embodiment of the present disclosure.
[0043] Description of reference numerals:
[0044] 1. Substrate; 2. Stacked structure; 201. Opening; 202. Groove; 21. First conductive layer; 211. First barrier layer; 212. First metal layer; 213. Second barrier layer; 22. First insulating layer; 23. Second conductive layer; 231. Third barrier layer; 232. Second metal layer; 24. Third insulating layer; 25. Insulating material layer; 3. Second insulating layer; 31. First sub-film layer; 32. Second sub-film layer; 4. Sacrificial layer; 5. Channel layer; 6. Insulating dielectric layer; 7. Third conductive layer. DETAILED DESCRIPTION
[0045] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.
[0046] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
[0047] The terms "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the term "having" is used to indicate an open-ended inclusive meaning and means that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.
[0048] In the process of manufacturing Junction Field-Effect Transistor (JFET), during the etching process of the bottom opening of the channel, a sacrificial layer is usually required to protect the insulating layer in the opening to prevent the insulating layer on the sidewall of the opening from being damaged during the etching process of the bottom opening. The material of the sacrificial layer currently used is polycrystalline silicon (density is about 2.2g / cm 3 ), due to the existence of crystal orientation in polysilicon, when the thickness of the sacrificial layer composed of polysilicon is relatively thin, there are more grain boundaries inside it and the arrangement is chaotic, so that pinholes are easily formed in the sacrificial layer under the bombardment of high bias voltage during etching. At this time, the plasma generated during the high bias voltage process is easy to damage the insulating layer through the pinholes in the sacrificial layer, causing structural defects in the insulating layer. When the thickness of the sacrificial layer is relatively thick (for example, the thickness of the sacrificial layer is greater than or equal to 5nm), the sacrificial layer occupies more space in the opening, so that the area of the area to be etched at the bottom of the opening is smaller, the process space size of the opening is smaller, and the subsequent process is more difficult. In addition, due to the thick sacrificial layer, the size of the corner at the bottom of the groove formed after removing the sacrificial layer is larger, and the charge is easily concentrated there to cause leakage.
[0049] Based on this, the present disclosure provides a method for manufacturing a semiconductor device. Figure 1 A flowchart showing a method for manufacturing a semiconductor device disclosed in the present invention is shown in FIG. Figure 1 As shown, the method for manufacturing a semiconductor device disclosed in the present invention may include steps S110 to S140, wherein:
[0050] Step S110, forming a stacked structure on a substrate, the stacked structure comprising a first conductive layer, a first insulating layer, and a second conductive layer stacked and distributed in sequence along a vertical direction; an opening is formed in the stacked structure, and in a thickness direction of the stacked structure, the opening penetrates the second conductive layer and extends into the first insulating layer;
[0051] Step S120, forming a second insulating layer on the sidewalls and bottom of the opening;
[0052] Step S130, forming a sacrificial layer on the surface of the second insulating layer, wherein the density of the sacrificial layer is greater than 2.2 g / cm 3 ;
[0053] Step S140, removing the sacrificial layer at the bottom of the opening, the second insulating layer at the bottom of the opening, and the first insulating layer at the bottom of the opening to form a groove exposing at least a portion of the surface of the first conductive layer.
[0054] The manufacturing method of the semiconductor device disclosed in the present invention has a high density of the sacrificial layer located on the side wall of the opening. In the process of removing the sacrificial layer, the second insulating layer and the first insulating layer at the bottom of the opening, the sacrificial layer is not easily penetrated by plasma, and the probability of pinholes appearing inside is low, which can reduce the probability of plasma passing through the sacrificial layer and then damaging the second insulating layer on the side wall of the opening, that is, the probability of structural damage to the second insulating layer can be reduced, which helps to ensure the insulation effect, thereby reducing the probability of coupling or short circuit between the subsequently formed channel layer and the second conductive layer, and improving product reliability. At the same time, due to the high density of the sacrificial layer, under the same protection effect, the thickness of the sacrificial layer in the present invention can be thinner, that is, the thickness of the sacrificial layer attached to the side wall of the opening is thinner, leaving a larger process space for etching the film layer (e.g., the sacrificial layer, the second insulating layer and the first insulating layer) at the bottom of the opening, which helps to reduce the difficulty of subsequent processes.
[0055] The following is a detailed description of the steps and specific details of the method for manufacturing a semiconductor device disclosed in the present invention:
[0056] like Figure 1 As shown, in step S110, a stacking structure is formed on a substrate, the stacking structure comprising a first conductive layer, a first insulating layer and a second conductive layer stacked and distributed in sequence along a vertical direction; an opening is formed in the stacking structure, and in the thickness direction of the stacking structure, the opening penetrates the second conductive layer and extends into the first insulating layer.
[0057] like Figure 2As shown, the substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, germanium or germanium silicon, etc. The shape and material of the substrate 1 are not particularly limited here.
[0058] A stacking structure 2 may be formed on the substrate 1 , and the stacking structure 2 may include a first conductive layer 21 , a first insulating layer 22 , and a second conductive layer 23 stacked and distributed in sequence along a vertical direction; wherein the vertical direction may be a direction perpendicular to an extension direction of the substrate 1 .
[0059] The first conductive layer 21 can be formed on the surface of the substrate 1. The first conductive layer 21 can be a single film layer or a composite film layer structure composed of multiple film layers, which is not specifically limited here. In some embodiments of the present disclosure, the first conductive layer 21 may include a first barrier layer 211, a first metal layer 212, and a second barrier layer 213 stacked and distributed in sequence along the vertical direction; wherein the first barrier layer 211 can be formed on the surface of the substrate 1, and its material can be a material with ion blocking function, for example, its material can be titanium nitride; the thickness of the first barrier layer 211 can be 4nm to 6nm, for example, its thickness can be 4nm, 5nm or 6nm. The first metal layer 212 can be formed on the surface of the first barrier layer 211, and its material can be a metal material with strong conductive properties, for example, tungsten; the thickness of the first metal layer 212 can be 25nm to 35nm, for example, its thickness can be 25nm, 30nm or 35nm. The first barrier layer 211 is located between the first metal layer 212 and the substrate 1. The first barrier layer 211 can prevent the metal ions (for example, tungsten) in the first metal layer 212 from diffusing into the substrate 1, and can also improve the adhesion between the substrate 1 and the first metal layer 212 through the first barrier layer 211, which helps to improve the reliability of the device. The second barrier layer 213 can be formed on the surface of the first metal layer 212, and its material can be a material with ion blocking function. The second barrier layer 213 can prevent the metal ions (for example, tungsten) in the first metal layer 212 from diffusing into the first insulating layer 22 formed subsequently, and can also improve the adhesion between the first insulating layer 22 formed subsequently and the first metal layer 212 through the second barrier layer 213, which helps to further improve the reliability of the device.
[0060] It should be noted that the material of the second barrier layer 213 can be the same as that of the first barrier layer 211. For example, the material of the second barrier layer 213 can also be titanium nitride. Of course, the material of the second barrier layer 213 can also be different from that of the first barrier layer 211, which is not particularly limited here. The thickness of the second barrier layer 213 can be 8nm to 12nm. For example, its thickness can be 8nm, 9nm, 10nm, 11nm or 12nm. In some embodiments of the present disclosure, the first conductive layer 21 can be used as a source or drain of a junction field effect transistor (JFET).
[0061] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 As shown, the stacked structure 2 of the present disclosure may further include an insulating material layer 25, which may be formed on the surface of the substrate 1, and the insulating material layer 25 may be adjacent to the first conductive layer 21 and surround the periphery of the first conductive layer 21. The surface of the insulating material layer 25 away from the substrate 1 may be flush with the surface of the first conductive layer 21 away from the substrate 1, so as to provide a flat process reference for subsequent processes, which helps to reduce the difficulty of the process. The material of the insulating material layer 25 may be silicon oxide or silicon nitride, etc.
[0062] Please continue to see Figure 2 As shown, the first insulating layer 22 can cover the surface of the first conductive layer 21 away from the substrate 1. When an insulating material layer 25 is also formed on the substrate 1, the first insulating layer 22 can also cover the insulating material layer 25 at the same time. The material of the first insulating layer 22 can be silicon oxide or tetraethoxysilane (Tetraethoxysilane, abbreviated as TEOS). The thickness of the first insulating layer 22 can be 8nm to 12nm, for example, its thickness can be 8nm, 9nm, 10nm, 11nm or 12nm. Of course, the first insulating layer 22 can also be other thicknesses, which are not listed here one by one.
[0063] Please continue to see Figure 2As shown, the second conductive layer 23 can be formed on the surface of the first insulating layer 22. At this time, the second conductive layer 23 and the first conductive layer 21 can be insulated and isolated by the first insulating layer 22 to prevent coupling or short circuit between the second conductive layer 23 and the first conductive layer 21. The second conductive layer 23 can be a single-layer film structure or a composite film structure composed of multiple film layers, which is not specifically limited here. In some embodiments of the present disclosure, the second conductive layer 23 may include a third barrier layer 231 and a second metal layer 232, wherein the third barrier layer 231 can be formed on the surface of the first insulating layer 22, and the material of the third barrier layer 231 can be a material with ion blocking function, for example, the material can be titanium nitride. The thickness of the third barrier layer 231 can be 8nm to 12nm, for example, the thickness can be 8nm, 9nm, 10nm, 11nm or 12nm. The second metal layer 232 can be formed on the surface of the third barrier layer 231, and the material of the second metal layer 232 can be a metal material with good conductivity, for example, it can be tungsten. That is, the third barrier layer 231 is located between the second metal layer 232 and the first insulating layer 22, and the third barrier layer 231 can prevent the metal ions (for example, tungsten) in the second metal layer 232 from diffusing into the first insulating layer 22, thereby improving the reliability of the device, and the third barrier layer 231 can also improve the adhesion between the second metal layer 232 and the first insulating layer 22, which helps to reduce the risk of peeling of the second metal layer 232 or the first insulating layer 22. The thickness of the second metal layer 232 can be 50nm to 60nm, for example, its thickness can be 50nm, 52nm, 54nm, 56nm, 58nm or 60nm, etc.
[0064] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 As shown, the stacked structure 2 may further include a third insulating layer 24, which may be formed on a side of the second conductive layer 23 away from the substrate 1, and the second conductive layer 23 may be insulated and protected by the third insulating layer 24 to reduce the risk of coupling or short circuit between the second conductive layer 23 and other conductive structures formed subsequently. The thickness of the third insulating layer 24 may be 25nm to 35nm, for example, it may be 25nm, 30nm or 35nm, and of course, the third insulating layer 24 may also be of other thicknesses as long as the insulation effect on the second conductive layer 23 is guaranteed.
[0065] In some embodiments of the present disclosure, the first conductive layer 21, the first insulating layer 22, the second conductive layer 23 and the third insulating layer 24 can be sequentially formed on the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the first conductive layer 21, the first insulating layer 22, the second conductive layer 23 or the third insulating layer 24 can also be formed by other methods. The formation method of the first conductive layer 21, the first insulating layer 22, the second conductive layer 23 and the third insulating layer 24 is not particularly limited. It should be noted that when the stacked structure 2 also includes an insulating material layer 25, before forming the first insulating layer 22, the insulating material layer 25 can also be formed on the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition or other methods.
[0066] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 2 As shown, an opening 201 is formed in the stacked structure 2. In the thickness direction (i.e., vertical direction) of the stacked structure 2, the opening 201 can penetrate the second conductive layer 23 and extend into the first insulating layer 22, and the orthographic projection of the bottom surface of the opening 201 on the substrate 1 is located within the orthographic projection of the first conductive layer 21 on the substrate 1. The opening 201 can divide the second conductive layer 23 into a plurality of conductive portions distributed at intervals. In some embodiments of the present disclosure, the conductive portion can serve as a gate of a junction field effect transistor (JFET). It should be noted that when the stacked structure 2 also includes a third insulating layer 24, the opening 201 can penetrate the third insulating layer 24 and the second conductive layer 23 at the same time, that is, the third insulating layer 24 is also formed on the top of each conductive portion separated by the opening 201.
[0067] In some embodiments of the present disclosure, the width of the bottom of the opening 201 (i.e., the minimum spacing between adjacent conductive portions) may be 40nm to 50nm. For example, it may be 40nm, 42nm, 44nm, 46nm, 48nm or 50nm. Of course, the bottom of the opening 201 may also be other widths, which are not listed here one by one.
[0068] like Figure 1 As shown, in step S120 , a second insulating layer 3 is formed on the sidewall and bottom of the opening 201 .
[0069] The second insulating layer 3 may be a single-layer film structure, for example, it may be a silicon oxide layer or a silicon nitride layer; the second insulating layer 3 may also be a composite film structure composed of multiple film layers, such as Figure 3As shown, it may include a first sub-film layer 31 and a second sub-film layer 32, wherein the material of the first sub-film layer 31 may be silicon nitride, and the first sub-film layer 31 may conformally cover the bottom and sidewalls of the opening 201, and the first sub-film layer 31 may be formed on the sidewalls and bottom of the opening 201 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. It should be noted that in the process of forming the first sub-film layer 31, for the convenience of the process, the first sub-film layer 31 may simultaneously cover the bottom, sidewalls of the opening 201 and the top surface of the second conductive layer 23 (at this time, the surface of the second conductive layer 23 is not formed with the third insulating layer 24); when the surface of the second conductive layer 23 is formed with the third insulating layer 24, the second insulating layer 3 is also formed on the surface of the sidewalls surrounded by the third insulating layer 24 in the opening 201, and for the convenience of the process, the first sub-film layer 31 may simultaneously cover the bottom, sidewalls of the opening 201 and the top surface of the third insulating layer 24. The second sub-layer 32 may conformally cover the surface of the first sub-layer 31 , and the material of the second sub-layer 32 may be silicon oxide.
[0070] The thickness of the second insulating layer 3 may be 4 nm to 8 nm, for example, 4 nm, 5 nm, 6 nm, 7 nm or 8 nm, etc. In an exemplary embodiment of the present disclosure, when the second insulating layer 3 includes a first sub-film layer 31 and a second sub-film layer 32, the thickness of the first sub-film layer 31 may be 2 nm, and the thickness of the second sub-film layer 32 may be 3 nm.
[0071] like Figure 1 As shown, in step S130, a sacrificial layer 4 is formed on the surface of the second insulating layer 3, and the density of the sacrificial layer 4 is greater than 2.2 g / cm 3 .
[0072] like Figure 4 As shown, the sacrificial layer 4 can be conformally covered on the surface of the second insulating layer 3. The material of the sacrificial layer 4 can be a material with relatively high density. For example, the material of the sacrificial layer 4 can be silicon nitride or carbon. Silicon nitride itself has a high density, and there is no crystal orientation inside it, so it is not easy to have pinholes under plasma bombardment. Carbon has a high hardness and there are carbon-carbon bonds inside it. On this basis, it is not easy to have pinholes under plasma bombardment. In some embodiments of the present disclosure, carbon can be amorphous carbon. Since amorphous carbon has a high density itself and has a strong resistance to plasma, using it as the material of the sacrificial layer 4 can reduce the probability of pinholes appearing in the sacrificial layer 4.
[0073] The sacrificial layer 4 can be formed by an atomic layer deposition process to improve the density of the sacrificial layer 4. In an exemplary embodiment of the present disclosure, the thickness of the sacrificial layer 4 can be less than 5nm, for example, it can be 4.5nm, 4nm, 3.5nm, 3nm or 2.5nm. Of course, the thickness of the sacrificial layer 4 can also be other values, as long as it will not be broken down by plasma and pinholes will appear during the subsequent etching process. Optionally, the thickness of the sacrificial layer 4 in the present disclosure is 3nm. Compared with the thickness of the sacrificial layer 4 in the related art being greater than or equal to 5nm, when the bottom size of the opening 201 is 45nm and the thickness of the second insulating layer 3 is 5nm, if the thickness of the sacrificial layer 4 is greater than or equal to 5nm, then the process space when the bottom film layer of the opening 201 is subsequently removed is less than or equal to 25nm; if the thickness of the sacrificial layer 4 is 3nm, then the process space when the bottom film layer of the opening 201 is subsequently removed is 29nm. Compared with the prior art, the thinner thickness of the sacrificial layer 4 in the present application can help increase the process space when the bottom film layer of the opening 201 is subsequently removed, thereby reducing the process difficulty.
[0074] like Figure 1 As shown, in step S140, the sacrificial layer 4 located at the bottom of the opening 201, the second insulating layer 3 located at the bottom of the opening 201, and the first insulating layer 22 located at the bottom of the opening 201 are removed to form a groove 202 exposing at least a portion of the surface of the first conductive layer 21.
[0075] In the process of removing the sacrificial layer 4, the second insulating layer 3 and the first insulating layer 22 located at the bottom of the opening 201, due to the high density of the sacrificial layer 4, the sacrificial layer 4 is not easily penetrated by the plasma, and the probability of pinholes appearing inside it is low, which can reduce the probability of plasma passing through the sacrificial layer 4 and damaging the second insulating layer 3 on the side wall of the opening, that is, the probability of structural damage to the second insulating layer 3 can be reduced, thereby reducing structural defects. At the same time, due to the high density of the sacrificial layer 4, under the same protective effect, the thickness of the sacrificial layer 4 in the present disclosure can be thinner, that is, the thickness of the sacrificial layer 4 attached to the side wall of the opening 201 is thinner, leaving a larger process space for etching the film layer at the bottom of the opening 201 (for example, the sacrificial layer 4, the second insulating layer 3 and the first insulating layer 22), which helps to reduce the difficulty of subsequent processes. In the embodiment of the present disclosure, the structure after completing step S140 is as follows: Figure 5 shown.
[0076] In an exemplary embodiment of the present disclosure, removing the sacrificial layer 4 at the bottom of the opening 201, the second insulating layer 3 at the bottom of the opening 201, and the first insulating layer 22 at the bottom of the opening 201 (ie, step S140) may include steps S1-S3, wherein:
[0077] Step S1 , forming a protective layer (not shown) on the sidewalls and bottom of the opening 201 , wherein the thickness of the protective layer at the bottom of the opening 201 is smaller than the thickness of the protective layer on the sidewalls of the opening 201 .
[0078] For example, a protective layer may be formed on the surface of the sacrificial layer 4 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Due to the limitations of the opening 201 and the thin film deposition process, the thickness of the deposited protective layer at the bottom of the opening 201 is relatively small, while the thickness of the protective layer at the sidewall of the opening 201 and the top surface of the opening 201 is relatively large. For example, fluoromethane (CH 3 F) and perfluorobutadiene (C 4 F 6 ) as a gas source to form a protective layer, that is, the material of the formed protective layer can be carbon. In the above deposition process, the opening 201 area can be placed at the center of the thin film deposition machine. In order to increase the difference between the thickness of the protective layer at the bottom of the opening 201 and the thickness of the protective layer on the sidewall, the gas flow rate at the center of the machine can be controlled to be smaller than the gas flow rate at its edge. For example, the ratio of the gas flow rate at the center of the machine to the gas flow rate at its edge can be 1:3.
[0079] Step S2, etching the protection layer at the bottom of the opening 201 and the film layer adjacent to the protection layer.
[0080] After the protective layer is deposited, the protective layer at the bottom of the opening 201 and the film layer adjacent to the protective layer can be etched by dry etching. In this process, the protective layer on the side wall of the opening 201 will also be etched (that is, the protective layer on the side wall of the opening 201 can prevent the sacrificial layer 4 on the side wall of the opening 201 from being consumed during the dry etching process, and the protective layer is used to protect the sacrificial layer 4 on the side wall of the opening 201, and the second insulating layer 3 on the side wall of the opening 201 can be doubly protected by the sacrificial layer 4 and the protective layer), but because the thickness of the protective layer at the bottom of the opening 201 is relatively thin, the protective layer at the bottom of the opening 201 will be etched first, and in the subsequent etching process, the film layer consumed at the bottom of the opening 201 is the film layer adjacent to the protective layer (for example, the sacrificial layer 4).
[0081] In some embodiments of the present disclosure, trifluoromethane (CHF 3 ), fluoromethane (CH 3 F), silicon tetrachloride (SiCl 4 ), perfluorobutadiene (C 4 F 6) is used as an etching gas to etch the protective layer and the film layer adjacent to the protective layer. It should be noted that inert gases, such as argon and helium, can also be input during this process.
[0082] Step S3, cleaning the opening 201 to remove residues from the etching process.
[0083] After the partial area of the protective layer located on the side wall of the opening 201 is completely etched, the protective effect of the protective layer on the sacrificial layer 4 is weakened, and the residues in the etching process can be removed, and then step S1 is repeated to form a protective layer with a stronger protective effect on the surface of the sacrificial layer 4 again, and then the above steps S2 and S3 are repeated. That is, the above steps S1-step S3 can be repeated until the first insulating layer 22 does not exist on the surface of the area of the first conductive layer 21 directly opposite to the bottom of the opening 201. It should be noted that after repeating the above steps S1-step S3 for many times, the sacrificial layer 4 located at the bottom of the opening 201 will be completely etched, and the film layer adjacent to the protective layer in the subsequent repetition of steps S1-step S3 will become the second insulating layer 3; when the second insulating layer 3 located at the bottom of the opening 201 is completely etched, the film layer adjacent to the protective layer in the subsequent repetition of steps S1-step S3 will become the first insulating layer 22.
[0084] In some embodiments of the present disclosure, in order to ensure that the finally formed groove 202 can completely expose the first conductive layer 21, and thus ensure the electrical contact performance between the first conductive layer 21 and the channel layer 5 subsequently formed in the groove 202, the finally formed groove 202 can be extended to the inside of the first conductive layer 21 during the process of repeating the above steps S1 to S3, that is, the first conductive layer 21 can be slightly overetched. In the process of etching the first conductive layer 21, the film layer adjacent to the protective layer is the first conductive layer 21.
[0085] In some embodiments of the present disclosure, when the material of the sacrificial layer 4 is silicon nitride, oxygen can be used to flush the opening 201 after etching to remove residues in the etching process; when the material of the sacrificial layer 4 is carbon, in order to avoid damaging the sacrificial layer 4, oxygen is no longer used to flush it, and argon can be used to flush the opening 201 after etching to remove residues in the etching process.
[0086] In some embodiments of the present disclosure, the "L" shape formed between the bottom and the sidewall of the final trench 202 can be controlled by optimizing the time required to form the protective layer and the time required for the dry etching, so as to appropriately shorten the length of the "L"-shaped bottom lateral region, thereby increasing the size of the bottom of the trench 202. For example, the ratio of the time required to form the protective layer to the etching time can be 1:1 to 1:3, for example, the ratio of the time required to form the protective layer to the dry etching time can be 1:1, 1:2 or 1:3.
[0087] In an exemplary embodiment of the present disclosure, the method for manufacturing a semiconductor device of the present disclosure may further include:
[0088] Step S150 , after forming the groove 202 , removing the sacrificial layer 4 .
[0089] After the groove 202 is formed, the groove 202 can be cleaned to remove the impurities remaining in the groove 202; after cleaning, the sacrificial layer 4 on the side wall of the groove 202 can be removed by a wet etching process to expose the remaining second insulating layer 3. Since the thickness of the sacrificial layer 4 attached to the side wall of the opening 201 is relatively thin, after removing the sacrificial layer 4, the size of the laterally distributed part of the "L" shape formed at the bottom corner of the groove 202 is smaller, the area where the charge is concentrated at the corner is reduced, and the leakage phenomenon is weakened. In some embodiments of the present disclosure, the remaining second insulating layer 3 can be used as a gate oxide layer in a junction field effect transistor (JFET). In the embodiment of the present disclosure, the structure after completing step S150 is as follows Figure 6 shown.
[0090] In an exemplary embodiment of the present disclosure, during the wet etching process, the etching selectivity ratios of the sacrificial layer 4 and the second insulating layer 3, the first insulating layer 22, and the first conductive layer 21 exposed at the bottom of the groove 202 are all greater than 50, so as to reduce damage to the second insulating layer 3, the first insulating layer 22, and the first conductive layer 21 during the wet etching process.
[0091] For example, when the material of the sacrificial layer 4 is silicon nitride, the material of the first insulating layer 22 is tetraethoxysilane (TEOS) or silicon oxide, the material of the second insulating layer 3 includes silicon oxide and / or silicon nitride, and the material of the film layer exposed in the first conductive layer 21 is titanium nitride, the etching solution for wet etching may be phosphoric acid (H 3 PO 4 ) solution; when the material of the sacrificial layer 4 is carbon, the material of the first insulating layer 22 is tetraethoxysilane (TEOS) or silicon oxide, the material of the second insulating layer 3 includes silicon oxide and / or silicon nitride, and the material of the film layer exposed in the first conductive layer 21 is titanium nitride, the etching solution for wet etching can be a diluted hydrofluoric acid (HF) solution.
[0092] In an exemplary embodiment of the present disclosure, the method for manufacturing a semiconductor device of the present disclosure may further include steps S210 to S230, wherein:
[0093] Step S210 , forming a channel layer 5 on the surface of the second insulating layer 3 located on the sidewall of the trench 202 .
[0094] like Figure 7 As shown, the material of the channel layer 5 may be polysilicon, and a polysilicon layer may be formed on the surface of the second insulating layer 3 on two side walls relatively distributed in the groove 202 by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD), and the polysilicon layer may be doped by an ion implantation process to form the channel layer 5. It should be noted that the polysilicon layer may be n-type doped or p-type doped according to actual needs, and the doping type of the channel layer 5 formed after doping is not specifically limited here.
[0095] Step S220 , filling the trench 202 having the channel layer 5 with an insulating material to form an insulating dielectric layer 6 .
[0096] For example, the insulating material may be silicon oxide, and the insulating material may be filled in the trench 202 where the channel layer 5 is formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, thereby forming an insulating dielectric layer 6. The insulating dielectric layer 6 may fill the trench 202, and its surface away from the substrate 1 may be flush with the surface of the channel layer 5 away from the substrate 1. The channel layer 5 on two oppositely distributed side walls in the trench 202 may be insulated and isolated by the insulating dielectric layer 6.
[0097] Step S230 , forming a third conductive layer 7 on a side of the channel layer 5 away from the substrate 1 .
[0098] For example, the material of the third conductive layer 7 may be a material with strong conductivity, and the third conductive layer 7 may be formed on the surface of the channel layer 5 away from the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The third conductive layer 7 may constitute a junction field effect transistor (JFET) together with the first conductive layer 21, the second conductive layer 23, the second insulating layer 3 and the channel layer 5, wherein the first conductive layer 21 may serve as the source (or drain) of the JFET, the second conductive layer 23 may serve as the gate of the JFET, the second insulating layer may serve as the gate oxide layer of the JFET, the third conductive layer 7 may serve as the drain (or source) of the JFET, and the channel layer 5 may serve as the channel region of the JFET. In the embodiment of the present disclosure, the structure after completing step S230 is as follows: Figure 7 shown.
[0099] In some embodiments of the present disclosure, in the process of forming the third conductive layer 7, for the convenience of the process, the third conductive layer 7 can simultaneously cover the ends of the two channel layers 5 away from the substrate 1 and the surface of the insulating dielectric layer 6 away from the substrate 1, that is, the third conductive layer 7 can be connected between the channel layers 5 of the two JFETs, that is, the two adjacently distributed JFETs can share the same drain (or source). At the same time, in the embodiments of the present disclosure, the first conductive layer 21 is also connected between the channel layers 5 of the two JFETs, that is, the two adjacently distributed JFETs can also share the same source (or drain).
[0100] It should be noted that, although the steps of the method for manufacturing a semiconductor device in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.
[0101] The embodiments of the present disclosure also provide a semiconductor device, which can be manufactured using the manufacturing method of the semiconductor device in any of the above embodiments. The specific details, formation process and beneficial effects have been described in detail in the embodiments of the corresponding semiconductor device manufacturing method, and will not be repeated here.
[0102] For example, the semiconductor device may be a Junction Field-Effect Transistor (JFET), a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM), etc. Of course, it may also be other storage devices, which are not listed here one by one.
[0103] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: Forming a stacking structure on a substrate, the stacking structure comprising a first conductive layer, a first insulating layer, and a second conductive layer stacked and distributed in sequence along a vertical direction; An opening is formed in the stacked structure, and in the thickness direction of the stacked structure, the opening penetrates the second conductive layer and extends into the first insulating layer; forming a second insulating layer on the sidewalls and bottom of the opening; A sacrificial layer is formed on the surface of the second insulating layer, and the density of the sacrificial layer is greater than 2.2 g / cm 3 ; The sacrificial layer at the bottom of the opening, the second insulating layer at the bottom of the opening, and the first insulating layer at the bottom of the opening are removed to form a trench exposing at least a portion of the surface of the first conductive layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the sacrificial layer is silicon nitride or carbon.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the sacrificial layer is less than 5 nm.
4. The method for manufacturing a semiconductor device according to claim 2, wherein: Removing the sacrificial layer located at the bottom of the opening, the second insulating layer located at the bottom of the opening, and the first insulating layer located at the bottom of the opening comprises the following steps: S1, forming a protective layer on the sidewall and bottom of the opening, wherein the thickness of the protective layer at the bottom of the opening is less than the thickness of the protective layer on the sidewall of the opening; S2, etching the protective layer located at the bottom of the opening and the film layer adjacent to the protective layer; S3, cleaning the opening to remove residues from the etching process; Steps S1 to S3 are repeated until the first insulating layer does not exist on the surface of the region of the first conductive layer directly facing the bottom of the opening.
5. The method for manufacturing a semiconductor device according to claim 4, characterized in that: The ratio of the time required to form the protective layer to the time required for etching is 1:1 to 1:
3.
6. The method for manufacturing a semiconductor device according to claim 4, characterized in that: The material of the protective layer is carbon.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: When the material of the sacrificial layer is silicon nitride, cleaning the opening to remove residues in the etching process includes: The opening after the etching is flushed with oxygen.
8. The method for manufacturing a semiconductor device according to claim 6, wherein: When the material of the sacrificial layer is carbon, cleaning the opening to remove residues in the etching process includes: The opening after the etching is flushed with argon gas.
9. The method for manufacturing a semiconductor device according to claim 2, wherein: The method for manufacturing the semiconductor device further includes: After forming the trench, the sacrificial layer is removed.
10. The method for manufacturing a semiconductor device according to claim 9, characterized in that: Removing the sacrificial layer comprises: The sacrificial layer is removed by a wet etching process, and an etching selectivity ratio of the sacrificial layer to the second insulating layer, the first insulating layer, and the first conductive layer is greater than 50.
11. The method for manufacturing a semiconductor device according to claim 10, characterized in that: When the material of the sacrificial layer is silicon nitride, the etching solution of the wet etching is a phosphoric acid solution; when the material of the sacrificial layer is carbon, the etching solution of the wet etching is hydrofluoric acid.
12. The method for manufacturing a semiconductor device according to any one of claims 1 to 11, characterized in that: The stacked structure further includes a third insulating layer, the third insulating layer is located on a side of the second conductive layer away from the substrate, the opening penetrates the third insulating layer and the second conductive layer at the same time, the second insulating layer is also formed on a surface of a side wall of the opening surrounded by the third insulating layer, and the method for manufacturing the semiconductor device further includes: forming a channel layer on a surface of the second insulating layer located on a sidewall of the trench; Filling the trench having the channel layer with an insulating material to form an insulating dielectric layer; A third conductive layer is formed on a side of the channel layer away from the substrate.
13. A semiconductor device, characterized in that: The semiconductor device is manufactured by using the method for manufacturing a semiconductor device according to any one of claims 1 to 12.