Shield gate groove type power device and preparation method thereof
By forming grooves and sub-gate structures in the SGT power device and performing fine etching processing, the problem of difficult reduction of gate source capacitance Cgs in the SGT power device is solved, and lower switching power consumption and higher switching speed are achieved .
Patent Information
- Application Number
- CN202411513760.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-02-07
AI Technical Summary
In the prior art, the switch power consumption of shielded gate trench type (SGT) power devices is relatively high and the parasitic capacitance is high, especially the gate-source capacitance Cgs, which is difficult to effectively reduce.
Two sub-gate are formed by forming grooves on the semiconductor wafer and forming two sub-gate trenches between the two sub-gatees. Then, the intergate trench is laterally etched by an isotropic etching process, and the overlap area is adjusted to reduce the gate source capacitance Cgs.
The gate-source capacitance Cgs of the SGT power device is effectively reduced, thereby reducing switching losses and improving the switching speed and efficiency of the device.
Smart Images
Figure CN119403153A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and more specifically, to a shielded gate trench power device and a preparation method thereof. Background Art
[0002] Shielded gate trench (SGT) MOSFET is an advanced field effect transistor that combines the advantages of trench MOSFET and shielded gate. It has been widely used in electric vehicles, renewable energy conversion and high-efficiency motor drives, demonstrating its importance in modern electronic devices.
[0003] Compared with traditional trench MOSFET, shielded gate trench (SGT) MOSFET achieves lower on-resistance and switching loss by introducing shielded gate technology. In order to further reduce the switching loss of SGT power devices, the structure of the gate and shielded gate can be optimized to reduce the influence of various parasitic capacitances.
[0004] In SGT power devices, parasitic capacitance mainly consists of three parts: gate-source capacitance Cgs, gate-drain capacitance Cgd and drain-source capacitance Cds. The existence of these parasitic capacitances will directly affect the switching loss, speed and efficiency of the device. Therefore, how to effectively reduce these parasitic capacitances has become an important issue in SGT device design.
[0005] In the prior art, although certain progress has been made in reducing parasitic capacitance in SGT power devices, no effective solution strategy has been found that can be flexibly adjusted according to design requirements for reducing parasitic capacitance, especially gate-source capacitance Cgs, in shielded gate trench (SGT) devices. Summary of the invention
[0006] The object of the present invention is to provide a shielded gate trench power device and a preparation method thereof, so as to solve the problem of high switch power consumption of SGT power devices in the prior art.
[0007] Another object of the present invention is to provide a shielded gate trench power device and a preparation method thereof, so as to solve the problem of high parasitic capacitance of SGT power devices in the prior art.
[0008] Another object of the present invention is to provide a shielded gate trench power device and a preparation method thereof, so as to solve the problem of high gate-source capacitance Cgs of SGT power devices in the prior art.
[0009] In order to achieve the above object, the present invention provides a method for preparing a shielded gate trench power device, comprising the following steps:
[0010] Prepare a semiconductor wafer to be processed, the semiconductor wafer at least comprising a substrate layer, an epitaxial layer and a trench structure, wherein the epitaxial layer is on the upper surface of the substrate layer, the trench structure is in the epitaxial layer, the trench structure is filled with source polysilicon, and the trench structure is covered with an oxide layer above and around the source polysilicon and on the upper surface of the epitaxial layer;
[0011] Depositing gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure so that a groove is formed above the trench structure;
[0012] Etching the gate polysilicon in the groove until reaching the oxide layer above the source polysilicon to form two sub-gates, with an inter-gate trench formed between the two sub-gates;
[0013] Planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed;
[0014] Forming an oxide film dielectric layer covering the oxide layer covering the upper surface of the epitaxial layer and the gate polysilicon;
[0015] The oxide film dielectric layer is planarized to obtain a flat surface of the oxide film dielectric layer.
[0016] In some embodiments, the step of etching the gate polysilicon in the groove until reaching the oxide layer above the source polysilicon to form two sub-gates further includes:
[0017] The gate polysilicon in the groove is etched by dry anisotropic etching process until the oxide layer above the source polysilicon is reached to form two sub-gates, and / or
[0018] The gate polysilicon in the inter-gate trench is laterally etched by adopting an isotropic etching process to adjust the lateral structure of the inter-gate trench.
[0019] In some embodiments, the polysilicon etch selectivity is in a range of 50:1 to 100:1, and / or
[0020] The isotropic selection ratio is 1:1.
[0021] In some embodiments, the step of preparing the semiconductor wafer to be processed further comprises:
[0022] Providing a substrate layer of a semiconductor wafer and an epitaxial layer on the surface of the substrate layer;
[0023] etching a trench structure in the epitaxial layer;
[0024] forming an oxide layer at the edge of the trench structure;
[0025] Filling source polysilicon in the middle of the trench structure;
[0026] An oxide layer is formed to cover the source polysilicon and its surroundings and the upper surface of the epitaxial layer.
[0027] In some embodiments, in the step of preparing the semiconductor wafer to be processed, a high-density plasma deposition process for the inter-gate oxide layer or a thermal oxidation growth process for forming the inter-gate oxide layer is used to form the oxide layer.
[0028] In some embodiments, after the step of depositing gate polysilicon on the upper surface of the epitaxial layer and the trench structure of the semiconductor wafer to form a groove above the trench structure, it also includes: forming a sacrificial layer above the gate polysilicon; etching the sacrificial layer until the gate polysilicon in the groove is exposed.
[0029] After the step of etching the gate polysilicon in the groove until reaching the oxide layer above the source polysilicon, the method further includes: removing the sacrificial layer.
[0030] In some embodiments, the step of etching the sacrificial layer until the gate polysilicon in the groove is exposed further comprises:
[0031] The sacrificial layer is etched by using a dry anisotropic etching process until the gate polysilicon in the groove is exposed.
[0032] In some embodiments, the sacrificial layer is a deposited film generated by chemical vapor deposition, and the sacrificial layer is removed by dry etching or wet etching.
[0033] In some embodiments, the sacrificial layer includes a nitride film and an oxide film;
[0034] When the sacrificial layer is a nitride film, hot phosphoric acid is used to perform wet etching to remove the sacrificial layer;
[0035] When the sacrificial layer is an oxide film, hydrofluoric acid is used to perform wet etching to remove the sacrificial layer.
[0036] In some embodiments, after the step of planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed, the method further includes:
[0037] An inter-gate oxide layer is formed on the surface of the gate polysilicon, and the inter-gate oxide layer is not higher than the oxide layer on the surface of the epitaxial layer.
[0038] In some embodiments, a chemical mechanical polishing process is used for planarization.
[0039] In some embodiments, the oxide film dielectric layer is formed by a chemical vapor deposition process.
[0040] In some embodiments, a sub-atmospheric pressure vapor deposition process is used to form an oxide film dielectric layer, so that a cavity is formed in the middle of the inter-gate trench.
[0041] In some embodiments, after the step of planarizing the oxide film dielectric layer to obtain a flat surface of the oxide film dielectric layer, the method further includes:
[0042] A double contact hole is formed at the sub-gate position, and the double contact hole connects the electrode to lead out the external circuit of the power device.
[0043] In order to achieve the above object, the present invention provides a shielded gate trench power device, which is prepared by using the above-mentioned method for preparing a shielded gate trench power device.
[0044] The present invention proposes a shielded gate trench power device and a preparation method. After the gate polysilicon is deposited, a groove formed above the trench structure is used as a self-aligned etching window to perform anisotropic etching on the gate polysilicon to form two sub-gates, and an isotropic etching process is used to laterally etch the inter-gate trench. According to different design requirements, the isotropic etching amount is selectively adjusted to change the overlapping area between the gate and the source and the shielding gate, so that an SGT power device with low gate-source capacitance Cgs can be obtained in an adjustable manner. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] The above and other features, properties and advantages of the present invention will become more apparent through the following description in conjunction with the accompanying drawings and embodiments, in which the same reference numerals always represent the same features, wherein:
[0046] Figure 1 A step diagram of a method for preparing a shielded gate trench power device according to an embodiment of the present invention is disclosed;
[0047] Figure 2a Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S1 is completed in the embodiment shown;
[0048] Figure 2b Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S2 is completed in the illustrated embodiment;
[0049] Figure 2c Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S3 is completed in the illustrated embodiment;
[0050] Figure 2d Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S4 is completed in the embodiment shown;
[0051] Figure 2e Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S5 is completed in the illustrated embodiment;
[0052] Figure 2f Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S6 is completed in the illustrated embodiment;
[0053] Figure 2g Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S7 is completed in the illustrated embodiment;
[0054] Figure 2h Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S8 is completed in the illustrated embodiment;
[0055] Figure 2i Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S9 is completed in the illustrated embodiment;
[0056] Figure 2j Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S10 is completed in the illustrated embodiment;
[0057] Figure 2k Revealed Figure 1 A schematic diagram of a cross-sectional structure of a device after step S11 is completed in the illustrated embodiment;
[0058] Figure 2l Revealed Figure 1 The illustrated embodiment is a schematic diagram of a cross-sectional structure of a device after step S12 is completed.
[0059] The meanings of the reference numerals in the figures are as follows:
[0060] 11 epitaxial layer;
[0061] 12 substrate layer;
[0062] 13 Groove structure;
[0063] 14 source polysilicon;
[0064] 15 oxide layer;
[0065] 21 gate polysilicon;
[0066] 211 grooves;
[0067] 212 sub-grid;
[0068] 213 inter-gate trench;
[0069] 22 sacrificial layer;
[0070] 23 inter-gate oxide layer;
[0071] 24 oxide film dielectric layer;
[0072] 25 cavity;
[0073] 26 double contact holes;
[0074] 31 Source metal layer. DETAILED DESCRIPTION
[0075] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the invention and are not used to limit the invention.
[0076] In the prior art, a shield gate without etching that can reduce the gate-source capacitance Cgs has been proposed. The preparation method thereof is to completely oxidize the exposed shield gate during a wet etching process and then fill it with gate polysilicon. However, this technical solution is only applicable to a molding process in which a thermal IPO is grown to form an inter-gate oxide layer. In addition, the width of the polysilicon in this technical solution is limited and difficult to adjust flexibly, and the inter-gate oxide layer may be too thin, resulting in an increase in the gate-source leakage current.
[0077] SGT parasitic capacitance can also be subdivided into input capacitance Ciss and output capacitance Coss. Among them, the gate-source capacitance Cgs is an important component of the input capacitance Ciss (the input capacitance Ciss is equal to the gate-source capacitance Cgs plus the gate-drain capacitance Cgd), which affects the turn-on speed of the SGT power device.
[0078] The gate-source capacitance Cgs can be subdivided into four parts, including the capacitance Cgs1 between the gate and the source electrode, the capacitance Cgs2 between the gate and the N+ source region, the capacitance Cgs3 between the gate and the P-type body region, and the capacitance Cgs4 between the gate and the shielding gate (common with the source).
[0079] The present invention proposes a method for preparing a shielded gate trench power device, which adjusts the device structure, etches the gate polysilicon to form two sub-gates, and forms an inter-gate trench between the two sub-gates to reduce the overlapping area between the gate and the source and the shielding gate, thereby reducing the gate-source capacitance Cgs, thereby preparing an SGT power device with low gate-source capacitance Cgs while keeping other parasitic capacitances unchanged.
[0080] The present invention provides a method for preparing a shielded gate trench power device, comprising the following steps:
[0081] Prepare a semiconductor wafer to be processed, the semiconductor wafer at least comprising a substrate layer, an epitaxial layer and a trench structure, wherein the epitaxial layer is on the upper surface of the substrate layer, the trench structure is in the epitaxial layer, the trench structure is filled with source polysilicon, and the trench structure is covered with an oxide layer above and around the source polysilicon and on the upper surface of the epitaxial layer;
[0082] Depositing gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure so that a groove is formed above the trench structure;
[0083] Etching the gate polysilicon in the groove until reaching the oxide layer above the source polysilicon to form two sub-gates, with an inter-gate trench formed between the two sub-gates;
[0084] Planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed;
[0085] Forming an oxide film dielectric layer covering the oxide layer covering the upper surface of the epitaxial layer and the gate polysilicon;
[0086] The oxide film dielectric layer is planarized to obtain a flat surface of the oxide film dielectric layer.
[0087] The present invention proposes a method for preparing a shielded gate trench power device. After gate polysilicon is deposited, a groove formed above the trench structure is used as a self-aligned etching window to perform anisotropic etching on the gate polysilicon to form two sub-gates, and an isotropic etching process is used to laterally etch the inter-gate trench. According to different design requirements, the isotropic etching amount is selectively adjusted to change the overlapping area between the gate and the source and the shielding gate, so that an SGT power device with low gate-source capacitance Cgs can be obtained in an adjustable manner.
[0088] Figure 1 A step diagram of a method for preparing a shielded gate trench power device according to an embodiment of the present invention is disclosed, such as Figure 1 As shown, a method for preparing a shielded gate trench power device proposed by the present invention comprises the following steps:
[0089] Step S1, preparing a semiconductor wafer to be processed;
[0090] Step S2, depositing gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure, so that a groove is formed above the trench structure;
[0091] Step S3, forming a sacrificial layer on the gate polysilicon;
[0092] Step S4, etching the sacrificial layer until the gate polysilicon in the groove is exposed;
[0093] Step S5, etching the gate polysilicon in the groove by dry anisotropic etching process until reaching the oxide layer above the source polysilicon to form two sub-gates, and forming an inter-gate trench between the two sub-gates;
[0094] Step S6, performing side etching on the gate polysilicon in the inter-gate trenches by using an isotropic etching process to adjust the lateral structure of the inter-gate trenches;
[0095] Step S7, removing the sacrificial layer;
[0096] Step S8, planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed;
[0097] Step S9, forming an inter-gate oxide layer on the surface of the gate polysilicon, wherein the inter-gate oxide layer is not higher than the oxide layer on the surface of the epitaxial layer;
[0098] Step S10, forming an oxide film dielectric layer, covering the oxide layer covering the upper surface of the epitaxial layer and the gate polysilicon;
[0099] Step S11, performing a planarization process on the oxide film dielectric layer to obtain a flat surface of the oxide film dielectric layer.
[0100] Among them, step S6 is an optional and preferred step.
[0101] Furthermore, after step S11, the following steps are further included:
[0102] Step S12, completing the remaining process steps according to the standard process flow.
[0103] Figure 2a to Figure 2l Revealed Figure 1 In the embodiment shown, the schematic diagram of the device cross-sectional structure after each step is completed is shown below in conjunction with Figure 2a to Figure 2l Each step of the method for preparing the shielded gate trench power device provided in this embodiment is described in detail.
[0104] Step S1, preparing a semiconductor wafer to be processed;
[0105] Please refer to Figure 2a In step S1, the semiconductor wafer to be processed at least includes an epitaxial layer 11, a substrate layer 12 and a trench structure 13:
[0106] The epitaxial layer 11 is located in the area above the device structure, on the upper surface of the substrate layer 12. The epitaxial layer 11 is usually a high-quality silicon material, which is used to support the current transmission of the device and ensure the electrical characteristics of the channel region. It usually has a low defect density and high conductivity;
[0107] The substrate layer 12 is located at the bottom of the device structure and plays a role in supporting the entire device. The substrate layer 12 is usually doped silicon, which determines the overall mechanical strength and conductivity of the device. According to the design requirements of the power device, the doping concentration of the substrate layer is relatively high to enhance its current carrying capacity.
[0108] The trench structure 13 is a plurality of vertical trenches etched in the epitaxial layer 11. These trenches are prepared for subsequent filling of gate and shield gate materials, so that the gate can be deeply embedded in the substrate, improving the control capability of the electric field and reducing parasitic capacitance.
[0109] In this embodiment, the trench structure 13 is filled with source polysilicon 14 , and the trench structure 13 is covered with an oxide layer 15 above and around the source polysilicon 14 and on the upper surface of the epitaxial layer 11 .
[0110] Through the above characteristics, the semiconductor wafer to be processed provides a good foundation to ensure that efficient current control and low-loss switching performance can be achieved in subsequent process steps.
[0111] More specifically, preparing the semiconductor wafer to be processed comprises the following steps:
[0112] Providing a substrate layer 12 of a semiconductor wafer and an epitaxial layer 11 on the surface of the substrate layer 12;
[0113] Etching a trench structure 13 in the epitaxial layer 11;
[0114] forming an oxide layer 15 at the edge of the trench structure 13;
[0115] Filling the source polysilicon 14 in the middle of the trench structure 13;
[0116] An oxide layer 15 is formed to cover the source polysilicon 14 and its surroundings as well as the upper surface of the epitaxial layer 11 .
[0117] In this embodiment, the oxide layer 15 is formed by adopting a high density plasma deposition inter-gate oxide layer (HDP IPO) forming process or a thermal oxidation growth inter-gate oxide layer (Thermal IPO) forming process.
[0118] HDP IPO is a forming method that uses high-density plasma to deposit the inter-gate oxide layer. The inter-gate oxide layer has high quality and high process freedom.
[0119] Thermal IPO is an inter-gate oxide layer formed by thermal oxidation growth, and is usually used as an oxide film for isolating SGT gate polysilicon and source polysilicon.
[0120] Step S2, depositing gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure, so that a groove is formed above the trench structure;
[0121] Please refer to Figure 2b In step S2, gate polysilicon 21 is deposited on the upper surface of the epitaxial layer 11 and the trench structure 13 of the semiconductor wafer. During the deposition process, a groove 211 is formed above the trench structure 13. The groove 211 is a structural feature naturally formed when depositing polysilicon.
[0122] Generally, gate polysilicon deposition can be performed by chemical vapor deposition (CVD) deposition, direct thermal oxygen growth, a combination of the two (thermal oxygen followed by CVD), or furnace deposition.
[0123] Step S3, forming a sacrificial layer on the gate polysilicon;
[0124] Please refer to Figure 2c In step S3 , the sacrificial layer 22 refers to a material layer that is temporarily provided during the manufacturing process and needs to be removed eventually, and is formed on the gate polysilicon 21 .
[0125] In this embodiment, the sacrificial layer 22 is a deposited film generated by a chemical vapor deposition (CVD) process; the deposited film may be a nitride film, an oxide film or other material layer that can be used as a sacrificial layer to block deposition.
[0126] The thickness of the deposited film is related to the structure itself. Usually, the thickness of the deposited film ranges from 500A to 2000A.
[0127] By adjusting the thickness of the deposited film, the size of the etching window can be adjusted. The etching window refers to the opening part used for subsequent etching. The thickness of the deposited film when filling the groove is often thin, and the thickness of the bottom of the groove is only about 50% to 70% of the top.
[0128] In step S3 , the thickness of the sacrificial layer 22 at the bottom, sidewall and top of the groove is inconsistent. The thickness of the sacrificial layer 22 at the bottom is thinner than that at the top, which is about 50% to 70% of the thickness at the top.
[0129] Step S4, etching the sacrificial layer until the gate polysilicon in the groove is exposed;
[0130] Please refer to Figure 2d Through the dry anisotropic etching process, the thinner sacrificial layer 22 at the bottom of the groove 211 can be completely etched away, while the sacrificial layer 22 on the sidewall and top of the groove 211 still has a certain thickness, thereby forming a specific self-aligned etching window.
[0131] The formation of this etching window is based on the shape and position of the groove itself, without the use of a photolithography mask for positioning. This natural formation method is called "self-alignment". Since no additional photolithography steps are required, it can improve production efficiency and reduce costs.
[0132] Anisotropic etching means that the material removal rate in different directions during the etching process is different. In dry anisotropic etching, by selecting appropriate gases and controlling reaction conditions, preferential etching in a specific direction can be achieved, thereby forming a vertical sidewall structure.
[0133] In this embodiment, the polysilicon etching selectivity is between 50:1 and 100:1, which means that in this step, polysilicon is etched much faster than other materials. This ensures that the etching process has high selectivity, that is, only the target material is effectively etched, while other materials are little affected.
[0134] Step S5, etching the gate polysilicon in the groove until reaching the oxide layer above the source polysilicon to form two sub-gates, with an inter-gate trench formed between the two sub-gates;
[0135] Please refer to Figure 2e In step S5, an anisotropic etching process is used to etch the gate polysilicon 21 in the vertical direction to form two sub-gates 212, and a gate trench 213 of a specific depth is formed between the two sub-gates 212. The present invention reduces the overlapping area of the gate, the shielding gate, and the source through the structure of the two sub-gates and the gate trench between the sub-gates, thereby reducing the gate-source capacitance Cgs.
[0136] In this embodiment, the polysilicon etching selectivity ratio is 50:1 to 100:1.
[0137] Step S6, performing side etching on the gate polysilicon in the inter-gate trenches by using an isotropic etching process to adjust the lateral structure of the inter-gate trenches;
[0138] Please refer to Figure 2f In step S6, an isotropic etching process is used to laterally etch the gate polysilicon 21 on both sides of the inter-gate trench 213, and the etching amount of the lateral etching can be selected according to the structural design requirements, so as to further adjust the overlapping area between the gate and the shield gate and the source.
[0139] This step mainly controls the geometric structure of the inter-gate trench by accurately controlling the isotropic etching process to etch the gate polysilicon. By selectively controlling the etching amount of the isotropic etching, the shape of the sub-gate 212 and the width of the inter-gate trench 213 are further adjusted to optimize the overlapping area of the electrodes.
[0140] Furthermore, in step S6, the isotropic selectivity is 1:1, and the polysilicon etching selectivity is 50:1 to 100:1.
[0141] Isotropic etching means that the etching rate is the same in all directions. This etching method does not distinguish between materials, so the selectivity is 1:1, which means that the etching rate of all materials is the same.
[0142] Step S5 and step S6 include operations related to the trench etching process. Figure 2e , 2f and Figure 2l It is analyzed that if the etching amount of the inter-gate trench 213 in the horizontal direction increases, the corresponding facing area of the upper gate polysilicon (sub-gate 212) and the lower source polysilicon 214 and the subsequent upper source metal plate will be reduced accordingly, resulting in a reduction in the overlapping area.
[0143] like Figure 2e As shown, in step S5, the inter-gate trench 213 has been etched, thereby forming a smaller overlap area. If step S6 is not performed, the overlap area formed after step S5 is fixed and cannot be adjusted.
[0144] In step S6, if Figure 2f As shown, the overlapping area between the two sub-gates 212 and the source polysilicon 14 can be further reduced by etching. The shield gate refers to the source polysilicon 14 below.
[0145] like Figure 2l As shown, the area facing the source (the source metal layer 31 above and the source polysilicon 14 below) and the two sub-gates 212 is greatly reduced.
[0146] Therefore, step S6 is an optional but preferred step because it provides the possibility to further optimize the overlap area, thereby having a positive impact on the final semiconductor device performance.
[0147] Step S7, removing the sacrificial layer;
[0148] Please refer to Figure 2g In step S7, the sacrificial layer is removed by dry etching or wet etching to expose the gate polysilicon 21. Both dry etching and wet etching are techniques for removing materials in the semiconductor manufacturing process.
[0149] When the sacrificial layer is a nitride film, the sacrificial layer may be removed by wet etching using hot phosphoric acid;
[0150] When the sacrificial layer is an oxide film, hydrofluoric acid is used to perform wet etching to remove the sacrificial layer.
[0151] Step S8, planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed;
[0152] Please refer to Figure 2h In step S8, a chemical mechanical polishing process is used to perform a planarization process.
[0153] In this step, the gate polysilicon is surface ground and etched back to remove excess polysilicon, ensure the flatness of the gate area, and prepare for subsequent processes.
[0154] In this embodiment, the chemical mechanical polishing process stops on the oxide layer 15 on the surface of the epitaxial layer 11. The gate polysilicon on the surface of the epitaxial layer 11 is completely removed, and the gate polysilicon (two sub-gates 212) in the trench structure 13 is retained.
[0155] The etching depth generally ranges from 500A to 1000A. The etching depth refers to the depth reached during the etching process. This depth needs to be precisely controlled to meet the requirements of chip design.
[0156] The depth of back engraving is determined according to the design requirements, which means that the grinding depth needs to be precisely controlled according to the actual chip design and manufacturing standards.
[0157] Step S9, forming an inter-gate oxide layer on the surface of the gate polysilicon, wherein the inter-gate oxide layer is not higher than the oxide layer on the surface of the epitaxial layer;
[0158] Please refer to Figure 2i In step S9, the gate polysilicon (two sub-gates 212) in the trench structure 13 is oxidized by a high temperature oxidation process to form an oxide film protection layer on the surface of the gate polysilicon to ensure electrical isolation in subsequent processes.
[0159] In this embodiment, the oxide film protection layer is the inter-gate oxide layer 23, and the thickness is 200 Å to 500 Å.
[0160] Step S10, forming an oxide film dielectric layer, covering the oxide layer covering the upper surface of the epitaxial layer and the gate polysilicon;
[0161] Please refer to Figure 2j In step S10, a subatmospheric pressure chemical vapor deposition is used to form an oxide film dielectric layer 24, so that a cavity 25 is formed in the middle of the inter-gate trench 213;
[0162] In this embodiment, a sub-atmospheric pressure vapor deposition technique is used to cover the entire structure surface with a uniform oxide film dielectric layer as a protective layer for the next step of mechanical grinding. In other embodiments, other vapor deposition processes can also be used to form the oxide film dielectric layer 24.
[0163] Subatmospheric pressure chemical vapor deposition is a chemical vapor deposition technology performed under relatively low pressure, which can produce uniform and high-quality oxide films.
[0164] Since the depth-to-width ratio of this oxide film is high, that is, the thickness of the film is large relative to its width, a cavity (airgap) structure can be formed in the middle of the gate polysilicon, that is, between the two sub-gates. This cavity structure helps to release and buffer the stress generated inside the structure, thereby improving the stability and reliability of the material.
[0165] Step S11, performing a planarization process on the oxide film dielectric layer to obtain a flat surface of the oxide film dielectric layer.
[0166] Please refer to Figure 2k In step S11, chemical mechanical polishing is performed on the oxide film dielectric layer 24;
[0167] The purpose of this step is to make the surface of the oxide film dielectric layer 24 flat, especially the groove portion, to facilitate the subsequent preparation of contact holes.
[0168] By precisely controlling the grinding time, it is possible to ensure that the oxide film dielectric layer maintains a certain thickness after grinding. The remaining thickness range is set between 500A and 800A.
[0169] Step S12, completing the remaining process steps according to the standard process flow.
[0170] Please refer to Figure 2l In step S12, the subsequent process is carried out according to the normal process flow to complete the access of the entire SGT power device structure.
[0171] Furthermore, a double contact hole 26 is formed on the gate bus region, and the position of the double contact hole corresponds to the position of the two sub-gates 212. The double contact hole 26 connects the electrode to connect other external circuits of the power device to ensure that the device can work normally.
[0172] The method for preparing the shielded gate trench power device proposed in the present invention adjusts the overlapping area between the gate and the source electrode and the shielding gate through fine anisotropic and isotropic etching processes, effectively reduces the gate-source capacitance Cgs, and thus improves the performance of the device.
[0173] Based on the above-mentioned method for preparing the shielded gate trench power device, the present invention also proposes a shielded gate trench power device obtained by the preparation method.
[0174] Since the specific structure of the shielded gate trench power device has been described in detail in the preparation method, it will not be repeated here.
[0175] The shielded gate trench power device proposed in the present invention reduces the overlapping area between the gate and the source through the shielded gate trench design, thereby reducing Cgs in the parasitic capacitance. This optimization is critical to improving switching speed and reducing power consumption, because the smaller the gate-source capacitance, the faster the switching speed of the device, making it perform better in high-frequency applications.
[0176] In addition, it is worth emphasizing that the shielded gate trench power device, which may include shielded gate trench MOSFET, demonstrates the wide application potential of this technology.
[0177] The shielded gate trench power device and the preparation method thereof provided by the present invention have the following beneficial effects:
[0178] 1) This method does not require the use of additional masks and is suitable for two different process routes of medium and high voltage SGT HDP IPO and thermal IPO with larger pitch;
[0179] 2) By adjusting the isotropic etching amount within a certain range, the gate-source overlap area can be adjusted, thereby increasing the degree of freedom in device preparation;
[0180] 3) It will not affect other parasitic capacitances and maintain the performance of the device;
[0181] 4) A certain cavity is formed in the middle of the device, which helps to buffer and reduce the stress inside the device.
[0182] Although the above methods are illustrated and described as a series of actions for simplicity of explanation, it should be understood and appreciated that these methods are not limited by the order of the actions, because according to one or more embodiments, some actions may occur in a different order and / or concurrently with other actions from those illustrated and described herein or not illustrated and described herein but understandable to those skilled in the art.
[0183] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.
[0184] The above embodiments are provided for persons familiar with the art to implement or use the present invention. Personnel familiar with the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the protection scope of the present invention is not limited to the above embodiments, but should be the maximum scope of the innovative features mentioned in the claims.
Claims
1. A method for preparing a shielded gate trench power device, characterized in that: The following steps are involved: Prepare a semiconductor wafer to be processed, the semiconductor wafer at least comprising a substrate layer, an epitaxial layer and a trench structure, wherein the epitaxial layer is on the upper surface of the substrate layer, the trench structure is in the epitaxial layer, the trench structure is filled with source polysilicon, and the trench structure is covered with an oxide layer above and around the source polysilicon and on the upper surface of the epitaxial layer; Depositing gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure so that a groove is formed above the trench structure; Etching the gate polysilicon in the groove until reaching the oxide layer above the source polysilicon to form two sub-gates, with an inter-gate trench formed between the two sub-gates; Planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed; Forming an oxide film dielectric layer covering the oxide layer covering the upper surface of the epitaxial layer and the gate polysilicon; The oxide film dielectric layer is planarized to obtain a flat surface of the oxide film dielectric layer.
2. The method for preparing a shielded gate trench power device according to claim 1, characterized in that: The step of etching the gate polysilicon in the groove until reaching the oxide layer above the source polysilicon to form two sub-gates further includes: The gate polysilicon in the groove is etched by dry anisotropic etching process until the oxide layer above the source polysilicon is reached to form two sub-gates, and / or The gate polysilicon in the inter-gate trench is laterally etched by adopting an isotropic etching process to adjust the lateral structure of the inter-gate trench.
3. The method for preparing a shielded gate trench power device according to claim 2, characterized in that: The polysilicon etch selectivity is in the range of 50:1 to 100:1, and / or The isotropic selection ratio is 1:
1.
4. The method for preparing a shielded gate trench power device according to claim 1, characterized in that: The semiconductor wafer to be processed is further prepared, comprising: Providing a substrate layer of a semiconductor wafer and an epitaxial layer on the surface of the substrate layer; etching a trench structure in the epitaxial layer; forming an oxide layer at the edge of the trench structure; Filling source polysilicon in the middle of the trench structure; An oxide layer is formed to cover the source polysilicon and its surroundings and the upper surface of the epitaxial layer.
5. The method for preparing a shielded gate trench power device according to claim 4, characterized in that: In the step of preparing the semiconductor wafer to be processed, the oxide layer is formed by adopting a high-density plasma deposition process for the inter-gate oxide layer or a thermal oxidation growth process for forming the inter-gate oxide layer.
6. The method for preparing a shielded gate trench power device according to claim 1, characterized in that: After the step of depositing gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure to form a groove above the trench structure, the method further includes: forming a sacrificial layer above the gate polysilicon; etching the sacrificial layer until the gate polysilicon in the groove is exposed; After the step of etching the gate polysilicon in the groove until reaching the oxide layer above the source polysilicon, the method further includes: removing the sacrificial layer.
7. The method for preparing a shielded gate trench power device according to claim 6, characterized in that: The step of etching the sacrificial layer until the gate polysilicon in the groove is exposed further comprises: The sacrificial layer is etched by using a dry anisotropic etching process until the gate polysilicon in the groove is exposed.
8. The method for preparing a shielded gate trench power device according to claim 6, characterized in that: The sacrificial layer is a deposited film generated by a chemical vapor deposition process, and the sacrificial layer is removed by a dry etching process or a wet etching process.
9. The method for preparing a shielded gate trench power device according to claim 6, characterized in that: The sacrificial layer includes a nitride film and an oxide film; When the sacrificial layer is a nitride film, hot phosphoric acid is used to perform wet etching to remove the sacrificial layer; When the sacrificial layer is an oxide film, hydrofluoric acid is used to perform wet etching to remove the sacrificial layer.
10. The method for preparing a shielded gate trench power device according to claim 1, characterized in that: After the step of planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed, the method further includes: An inter-gate oxide layer is formed on the surface of the gate polysilicon, and the inter-gate oxide layer is not higher than the oxide layer on the surface of the epitaxial layer.
11. The method for preparing a shielded gate trench power device according to claim 1, characterized in that: The planarization process is performed using a chemical mechanical polishing process.
12. The method for preparing a shielded gate trench power device according to claim 1, characterized in that: The oxide film dielectric layer is formed by chemical vapor deposition process.
13. The method for preparing a shielded gate trench power device according to claim 12, characterized in that: The oxide film dielectric layer is formed by a sub-atmospheric pressure vapor deposition process, so that a cavity is formed in the middle of the inter-gate trench.
14. The method for preparing a shielded gate trench power device according to claim 1, characterized in that: After the step of flattening the oxide film dielectric layer to obtain a flat surface of the oxide film dielectric layer, the method further comprises: A double contact hole is formed at the sub-gate position, and the double contact hole connects the electrode to lead out the external circuit of the power device.
15. A shielded gate trench power device, characterized in that: The shielded gate trench power device is prepared by the method for preparing the shielded gate trench power device according to any one of claims 1 to 14.
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