Semiconductor device

Abstract

The semiconductor device includes a lower pattern. The channel isolation structure and the field insulating layer contact the lower pattern. A gate structure is on the lower pattern in contact with the channel isolation structure. A channel pattern is on the lower pattern and includes sheet patterns, each of which is in contact with a channel isolation structure. The source / drain pattern contacts the channel pattern and the channel isolation structure. The channel isolation structure includes a first region contacting the gate structure and a second region contacting the source / drain pattern. The second region of the channel isolation structure includes a portion whose width increases as a distance from the bottom surface of the field insulating layer increases. A width of an uppermost portion of the channel isolation structure is greater than a width of a lowermost portion of the channel isolation structure.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0096984 filed in the Korean Intellectual Property Office on July 25, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to semiconductors, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0003] Multi-gate transistors have been proposed as a method for increasing the density of circuits within semiconductor devices. In a multi-gate transistor, a fin-shaped multi-channel active pattern (or silicon body) or a nanowire-shaped multi-channel active pattern (or silicon body) is formed on a substrate, and a gate is formed on a surface of the multi-channel active pattern.

[0004] Since the multi-gate transistor uses a three-dimensional (3D) channel, the scaling of the multi-gate transistor can be more easily achieved. In addition, the current control capability can be increased without increasing the gate length of the multi-gate transistor. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

[0005] As the pitch (size) of semiconductor devices decreases, it may be desirable to reduce capacitance between contacts in the semiconductor devices and ensure electrical stability between contacts in the semiconductor devices. Summary of the invention

[0006] A semiconductor device includes: a lower pattern, which mainly extends in a first direction and has a first side wall and a second side wall facing each other in a second direction. A channel isolation structure mainly extends in the first direction and contacts the first side wall of the lower pattern. A field insulation layer contacts the second side wall of the lower pattern. A gate structure is arranged on the lower pattern, contacts the channel isolation structure, and mainly extends in the second direction. The channel pattern is arranged on the lower pattern and includes a plurality of sheet patterns spaced apart from each other in a third direction. Each of the plurality of sheet patterns contacts the channel isolation structure. And, a source / drain pattern contacts the channel pattern and the channel isolation structure. The channel isolation structure includes a first region contacting the gate structure and a second region contacting the source / drain pattern. The second region of the channel isolation structure includes a first portion and a second portion, and the widths of the first portion and the second portion increase in the second direction as the distance from the bottom surface of the field insulation layer increases. The second portion of the second region of the channel isolation structure is arranged on the first portion of the second region of the channel isolation structure. A width of an uppermost portion of the trench isolation structure in the first portion of the second region of the trench isolation structure is greater than a width of a lowermost portion of the trench isolation structure in the second portion of the second region of the trench isolation structure.

[0007] A semiconductor device includes: a first gate structure having a first gate electrode and a first gate insulating layer. A second gate structure includes a second gate electrode and a second gate insulating layer, and is spaced apart from the first gate structure in a first direction. A first source / drain pattern is disposed adjacent to the first gate structure in a second direction, and a second source / drain pattern is disposed adjacent to the second gate structure in the second direction, and is spaced apart from the first source / drain pattern in the first direction. A channel isolation structure is disposed between the first gate structure and the second gate structure and between the first source / drain pattern and the second source / drain pattern, and mainly extends in the second direction. The first channel pattern includes a plurality of first sheet patterns, each of which is in contact with the channel isolation structure and the first source / drain pattern. The second channel pattern includes a plurality of second sheet patterns, each of which is in contact with the channel isolation structure and the second source / drain pattern. The width of the channel isolation structure between the first gate structure and the second gate structure in the first direction is different from the width of the channel isolation structure between the first source / drain pattern and the second source / drain pattern in the first direction.

[0008] A semiconductor device includes: a lower pattern, which mainly extends in a first direction and has a first sidewall and a second sidewall opposite to the first sidewall in a second direction. A channel isolation structure mainly extends in the first direction and contacts the first sidewall of the lower pattern. A field insulation layer contacts the second sidewall of the lower pattern. A gate isolation structure is arranged on the field insulation layer and mainly extends in the first direction. The gate structure is arranged between the channel isolation structure and the gate isolation structure and contacts the channel isolation structure and the gate isolation structure. The channel pattern is arranged on the lower pattern and includes a plurality of sheet patterns spaced apart from each other in a third direction. Each of the plurality of sheet patterns contacts the channel isolation structure. A source / drain pattern is arranged between the channel isolation structure and the gate isolation structure and contacts the channel pattern and the channel isolation structure. A portion of the source / drain pattern overlaps the channel isolation structure in the third direction and is arranged across the channel isolation structure.

[0009] A method for manufacturing a semiconductor device includes: forming a first molded fin pattern and a second molded fin pattern, the second molded fin pattern being spaced apart from the first molded fin pattern in a second direction by a trench isolation trench extending mainly in a first direction. The first molded fin pattern includes a first lower pattern and a first upper pattern structure. The second molded fin pattern includes a second lower pattern and a second upper pattern structure. The first upper pattern structure and the second upper pattern structure each include an active pattern and a sacrificial pattern stacked alternately. A lower trench isolation structure is formed to fill the trench isolation trench. After removing a portion of the lower trench isolation structure exposed between adjacent dummy gate electrodes, a plurality of dummy gate electrodes intersecting the first molded fin pattern and the second molded fin pattern and extending mainly in a second direction are formed on the first molded fin pattern, the second molded fin pattern, and the lower trench isolation structure. After forming a first source / drain groove and a second source / drain groove, a first source / drain groove is formed in the first molded fin pattern, and a second source / drain groove is formed in the second molded fin pattern. An upper channel isolation structure is formed on the lower channel isolation structure. A first source / drain pattern in contact with the lower channel isolation structure and the upper channel isolation structure is formed in the first source / drain groove. A second source / drain pattern in contact with the lower channel isolation structure and the upper channel isolation structure is formed in the second source / drain groove. The dummy gate electrode is removed to form a gate groove exposing the first upper pattern structure and the second upper pattern structure. The sacrificial pattern of the exposed first upper pattern structure is removed to form a first sheet pattern in contact with the first source / drain pattern. The sacrificial pattern of the exposed second upper pattern structure is removed to form a second sheet pattern in contact with the second source / drain pattern. A pre-gate electrode is formed to intersect with the first sheet pattern and the second sheet pattern in the gate groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0011] Figure 1 is a layout diagram showing a semiconductor device according to an embodiment of the present disclosure;

[0012] Figures 2 to 5 It is along Figure 1 sectional views taken along lines AA, BB, CC and DD;

[0013] Figure 6 It is shown Figure 2 a diagram of the shape of the first pattern;

[0014] Figure 7 yes Figure 1 A schematic plan view of a portion P of;

[0015] Figure 8 yes Figure 4 An enlarged view of part Q;

[0016] Fig. 9 yes Figure 5 An enlarged view of part S;

[0017] Fig.10 and Fig.11 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure;

[0018] Fig.12 and Fig.13 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure;

[0019] Fig.14 and Fig.15 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure;

[0020] Figures 16 to 19 are diagrams each showing a semiconductor device according to an embodiment of the present disclosure;

[0021] Fig. 20 and Fig.21 are diagrams each showing a semiconductor device according to an embodiment of the present disclosure;

[0022] Figure 22 to Figure 24 are diagrams each showing a semiconductor device according to an embodiment of the present disclosure;

[0023] Fig.25 and Fig.26 are diagrams each showing a semiconductor device according to an embodiment of the present disclosure;

[0024] Fig. 27 and Fig.28 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure;

[0025] Fig.29 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure; and

[0026] Figures 30 to 59 2 is a diagram illustrating an intermediate step of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Although the terms first, second, etc. can be used to describe various elements or components herein, these elements or components should not necessarily be limited by these terms. These terms are used to distinguish an element or component from another element or component. Therefore, without departing from the teaching of the present disclosure, the first element or first component discussed below may be referred to as the second element or second component.

[0028] In the drawings of the semiconductor device according to the embodiments of the present disclosure, a transistor including a nanowire or a nanosheet is shown as an example, but the present disclosure is not necessarily limited thereto. The technical concept of the present disclosure can be applied to a transistor based on a two-dimensional material (a field effect transistor (FET) based on a 2D material) and a heterostructure thereof.

[0029] In addition, the semiconductor device according to the embodiment of the present disclosure may include a fin transistor (FinFET), a tunneling transistor (tunneling FET), or a three-dimensional (3D) transistor, and the fin transistor includes a channel region having a fin pattern shape. The semiconductor device according to the embodiment of the present disclosure may include a bipolar junction transistor, a lateral double diffused MOS (LDMOS) transistor, etc.

[0030] Will refer to Figures 1 to 9 A semiconductor device according to an embodiment of the present disclosure is described.

[0031] Figure 1 is a layout diagram showing a semiconductor device according to an embodiment of the present disclosure. Figures 2 to 5 It is along Figure 1 Cross-sectional views taken along lines AA, BB, CC and DD. Figure 6 It is shown Figure 2 An illustration of the shape of the first pattern. Figure 7 yes Figure 1 Schematic plan view of part P of FIG. Figure 8 yes Figure 4 A magnified view of part Q. Fig. 9 yes Figure 5 An enlarged view of part S.

[0032] For reference, in Figure 1 In the figure, the source / drain contacts 180, 280, 380, 480, etc. are omitted. Figure 7 It may be obtained between the source / drain contacts 180 and 280 and the sheet patterns NS1 and NS2 disposed at the uppermost portion.

[0033] Reference Figures 1 to 9 According to an embodiment of the present disclosure, the semiconductor device may include a first lower pattern BP1, a second lower pattern BP2, a third lower pattern BP3, a fourth lower pattern BP4, a first channel pattern CH1, a second channel pattern CH2, a third channel pattern CH3, a fourth channel pattern CH4, a first channel isolation structure CCW1, a second channel isolation structure CCW2, a first gate electrode 120, a second gate electrode 220, a third gate electrode 320, a fourth gate electrode 420, a first source / drain pattern 150, a second source / drain pattern 250, a third source / drain pattern 350, a fourth source / drain pattern 450 and a gate isolation structure GCS.

[0034] The first substrate 100 may include a first surface 100US and a second surface 100BS facing each other in the third direction D3. The gate electrodes 120, 220, 320 and 420, the source / drain patterns 150, 250, 350 and 450, and the channel patterns CH1, CH2, CH3 and CH4 may be disposed on the first surface 100US of the first substrate, so that the first surface 100US of the first substrate may be the upper surface of the first substrate 100. The second surface 100BS of the first substrate facing away from the first surface 100US of the first substrate may be the bottom surface of the first substrate 100.

[0035] The first substrate 100 may be made of a semiconductor material, or may include a semiconductor material. The first substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the first substrate 100 may include, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not necessarily limited thereto.

[0036] The first lower pattern BP1 and the second lower pattern BP2 may each protrude from the first substrate 100 in the third direction D3. The first lower pattern BP1 and the second lower pattern BP2 may protrude from the first surface 100US of the first substrate. The first lower pattern BP1 and the second lower pattern BP2 may each extend mainly in the first direction D1. The first lower pattern BP1 and the second lower pattern BP2 may be spaced apart from each other in the second direction D2.

[0037] The third lower pattern BP3 and the fourth lower pattern BP4 may each protrude from the first substrate 100 in the third direction D3. The third lower pattern BP3 and the fourth lower pattern BP4 may protrude from the first surface 100US of the first substrate. Each of the third lower pattern BP3 and the fourth lower pattern BP4 may be elongated in the first direction D1. The third lower pattern BP3 and the fourth lower pattern BP4 may be spaced apart from each other in the second direction D2.

[0038] For example, the third direction D3 may be a thickness direction of the first substrate 100. Each of the first direction D1 and the second direction D2 intersects the third direction D3. The first direction D1 intersects the second direction D2.

[0039] The first lower pattern BP1 and the third lower pattern BP3 may be disposed between the second lower pattern BP2 and the fourth lower pattern BP4. The first lower pattern BP1 may be disposed between the second lower pattern BP2 and the third lower pattern BP3.

[0040] The first lower pattern BP1 and the third lower pattern BP3 may be isolated by the fin trench FT extending mainly in the first direction D1. For example, the first surface 100US of the first substrate may be a bottom surface of the fin trench FT.

[0041] As used herein, the phrase "extending primarily in one direction" means that the structure has the greatest extent in that direction, even though the structure may extend to a lesser extent in other directions.

[0042] In the case of the first lower pattern BP1, for example, the first lower pattern BP1 may include a first side wall BP1_SW1 and a second side wall BP1_SW2 facing away from each other in the second direction D2. The first side wall BP1_SW1 of the first lower pattern and the second side wall BP1_SW2 of the first lower pattern may extend mainly in the first direction D1. The second side wall BP1_SW2 of the first lower pattern may be defined by the fin trench FT. The first side wall BP1_SW1 of the first lower pattern is not defined by the fin trench FT.

[0043] Similar to the first lower pattern BP1, the second to fourth lower patterns BP2, BP3, and BP4 may include first and second sidewalls facing away from each other in the second direction D2. For example, since the second sidewall BP1_SW2 of the first lower pattern and the second sidewall of the third lower pattern BP3 are defined by the fin trench FT, the second sidewall BP1_SW2 of the first lower pattern may face the second sidewall of the third lower pattern BP3.

[0044] The first lower pattern BP1 and the second lower pattern BP2 may be disposed in a region where transistors of the same conductivity type are formed. The third lower pattern BP3 and the fourth lower pattern BP4 may be disposed in a region where transistors of the same conductivity type are formed. For example, the first lower pattern BP1 may be disposed in a PMOS formation region, and the third lower pattern BP3 may be disposed in an NMOS formation region. For example, the first lower pattern BP1 and the third lower pattern BP3 may be disposed in a PMOS formation region. For example, the first lower pattern BP1 and the third lower pattern BP3 may be disposed in an NMOS formation region.

[0045] Each of the first to fourth lower patterns BP1, BP2, BP3, and BP4 may be formed by etching a portion of the first substrate 100, or may include an epitaxial layer grown from the first substrate 100. Each of the first to fourth lower patterns BP1, BP2, BP3, and BP4 may include silicon or germanium as an elemental semiconductor material. In addition, each of the lower patterns BP1, BP2, BP3, and BP4 may include a compound semiconductor (e.g., a group IV-IV compound semiconductor or a group III-V compound semiconductor).

[0046] The Group IV-IV compound semiconductor may be a binary or ternary compound including at least two elements of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or the above-mentioned compounds doped with a Group IV element.

[0047] The III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining aluminum (Al), gallium (Ga), and / or indium (In) as Group III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as Group V elements.

[0048] The first lower pattern BP1 and the second lower pattern BP2 include the same material. The third lower pattern BP3 and the fourth lower pattern BP4 include the same material.

[0049] The field insulating layer 105 is disposed on the first substrate 100. For example, the field insulating layer 105 may be disposed on the first surface 100US of the first substrate. The field insulating layer 105 may fill at least a portion of the fin trench FT isolating the first lower pattern BP1 and the third lower pattern BP3.

[0050] In a cross-sectional view, the first and second lower patterns BP1 and BP2 may be disposed between the field insulation layers 105 adjacent in the second direction D2. The third and fourth lower patterns BP3 and BP4 may be disposed between the field insulation layers 105 adjacent in the second direction D2.

[0051] The field insulating layer 105 is not disposed on the upper surface BP1_US of the first lower pattern, the upper surface BP2_US of the second lower pattern, the upper surface BP3_US of the third lower pattern, and the upper surface BP4_US of the fourth lower pattern.

[0052] The field insulating layer 105 may contact the second side wall BP1_SW2 of the first lower pattern and the second side wall of the third lower pattern BP3. For example, the field insulating layer 105 may completely cover the second side wall BP1_SW2 of the first lower pattern and the second side wall of the third lower pattern BP3. For example, the field insulating layer 105 may cover a portion of the second side wall BP1_SW2 of the first lower pattern and / or a portion of the second side wall of the third lower pattern BP3.

[0053] The field insulating layer 105 may include an upper surface 105US and a bottom surface 105BS facing each other in the third direction D3. The bottom surface 105BS of the field insulating layer may face the first substrate 100. For example, the bottom surface 105BS of the field insulating layer may contact the first substrate 100.

[0054] Although the upper surface 105US of the field insulation layer is shown to have a flat shape, this is to simplify the description, and the present disclosure is not necessarily limited thereto. The field insulation layer 105 may include, for example, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof. Although the field insulation layer 105 is shown as a single layer, this is to simplify the description, and the present disclosure is not necessarily limited thereto.

[0055] A plurality of first channel patterns CH1 may be disposed on the first lower pattern BP1. Each of the plurality of first channel patterns CH1 may overlap the first lower pattern BP1 in the third direction D3. The plurality of first channel patterns CH1 may be aligned in the first direction D1. As used herein, the phrase "aligned in one direction" may mean that the listed elements each have the same longest axis as each other.

[0056] A plurality of second channel patterns CH2 may be disposed on the second lower pattern BP2. Each of the plurality of second channel patterns CH2 may overlap the second lower pattern BP2 in the third direction D3. The plurality of second channel patterns CH2 may be aligned in the first direction D1. The second channel pattern CH2 may correspond to the first channel pattern CH1. The first channel pattern CH1 and the second channel pattern CH2 corresponding to each other may be spaced apart from each other in the second direction D2.

[0057] The plurality of third channel patterns CH3 may be disposed on the third lower pattern BP3. Each of the plurality of third channel patterns CH3 may overlap the third lower pattern BP3 in the third direction D3. The plurality of third channel patterns CH3 may be aligned in the first direction D1.

[0058] A plurality of fourth channel patterns CH4 may be disposed on the fourth lower pattern BP4. Each of the plurality of fourth channel patterns CH4 may overlap the fourth lower pattern BP4 in the third direction D3. The plurality of fourth channel patterns CH4 may be aligned in the first direction D1. The fourth channel pattern CH4 may correspond to the third channel pattern CH3. The third channel pattern CH3 and the fourth channel pattern CH4 corresponding to each other may be spaced apart from each other in the second direction D2.

[0059] Each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 may include a plurality of sheet patterns spaced apart from each other in the third direction D3. Although it is shown that each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 includes three sheet patterns, this is to simplify the description, and the present disclosure is not necessarily limited thereto.

[0060] The first channel pattern CH1 may include a plurality of first sheet patterns NS1. The plurality of first sheet patterns NS1 may be disposed on an upper surface BP1-US of the first lower pattern. The plurality of first sheet patterns NS1 are arranged on the first lower pattern BP1 along a third direction D3. The plurality of first sheet patterns NS1 are spaced apart from each other in the third direction D3. Each of the plurality of first sheet patterns NS1 includes an upper surface NS1_US and a bottom surface NS1_BS facing away from each other in the third direction D3. For example, the upper surface NS1_US of the first sheet pattern disposed at the uppermost portion may be the upper surface of the first channel pattern CH1.

[0061] The third channel pattern CH3 may include a plurality of third sheet patterns NS3. The plurality of third sheet patterns NS3 may be disposed on the upper surface BP3_US of the third lower pattern. The plurality of third sheet patterns NS3 are arranged on the third lower pattern BP3 along the third direction D3. The plurality of third sheet patterns NS3 are spaced apart from each other in the third direction D3. Each of the plurality of third sheet patterns NS3 includes an upper surface NS3_US and a bottom surface NS3_BS facing away from each other in the third direction D3.

[0062] The second channel pattern CH2 may include a plurality of second sheet patterns NS2. The plurality of second sheet patterns NS2 may be disposed on the upper surface BP2-US of the second lower pattern. The plurality of second sheet patterns NS2 are spaced apart from each other in the third direction D3. The fourth channel pattern CH4 may include a plurality of fourth sheet patterns NS4. The plurality of fourth sheet patterns NS4 may be disposed on the upper surface BP4_US of the fourth lower pattern. The plurality of fourth sheet patterns NS4 are spaced apart from each other in the third direction D3.

[0063] In the case of the first sheet pattern NS1, for example, the first sheet pattern NS1 may include first side walls NS1_SW1 facing away from each other in the first direction D1 and second side walls NS1_SW2 facing away from each other in the second direction D2. An upper surface NS1_US of the first sheet pattern and a bottom surface NS1_BS of the first sheet pattern may be connected by the first side wall NS1_SW1 of the first sheet pattern and the second side wall NS1_SW2 of the first sheet pattern. The first side wall NS1_SW1 of the first sheet pattern is connected to and contacts the first source / drain pattern 150 to be described later. The description of the first sheet pattern NS1 may also be applied to the second to fourth sheet patterns NS2, NS3, and NS4.

[0064] Each of the sheet patterns NS1, NS2, NS3, and NS4 may include any one of silicon or germanium as an elemental semiconductor material, a group IV-IV compound semiconductor, and a group III-V compound semiconductor. The first sheet pattern NS1 and the second sheet pattern NS2 may include the same material as the first lower pattern BP1, or may include a different material from the first lower pattern BP1. The third sheet pattern NS3 and the fourth sheet pattern NS4 may include the same material as the third lower pattern BP3, or include a material different from that of the third lower pattern BP3.

[0065] In the semiconductor device according to the embodiment of the present disclosure, each of the first to fourth lower patterns BP1, BP2, BP3, and BP4 may be a silicon lower pattern including silicon. Each of the first to fourth sheet patterns NS1, NS2, NS3, and NS4 may be a silicon sheet pattern including silicon.

[0066] The first trench isolation structure CCW1 may be disposed on the first surface 100US of the first substrate. The first trench isolation structure CCW1 may be disposed between the first lower pattern BP1 and the second lower pattern BP2. The first trench isolation structure CCW1 may extend mainly in the first direction D1.

[0067] The first trench isolation structure CCW1 may isolate the first lower pattern BP1 from the second lower pattern BP2. The first trench isolation structure CCW1 isolates the first channel pattern CH1 from the second channel pattern CH2. The first lower pattern BP1 and the second lower pattern BP2 cover a portion of a sidewall of the first trench isolation structure CCW1. The sidewall of the first trench isolation structure CCW1 may extend mainly in the first direction D1.

[0068] The first trench isolation structure CCW1 may contact the first and second lower patterns BP1 and BP2. The first trench isolation structure CCW1 may contact the first sidewall BP1_SW1 of the first and second lower patterns BP2. The first sidewall BP1_SW1 of the first lower pattern faces the first sidewall of the second lower pattern BP2.

[0069] The first channel pattern CH1 and the second channel pattern CH2 are in contact with the first channel isolation structure CCW1. A plurality of first sheet patterns NS1 and a plurality of second sheet patterns NS2 are in contact with the first channel isolation structure CCW1. The first sheet pattern NS1 and the second sheet pattern NS2 may protrude from the sidewall of the first channel isolation structure CCW1 in the second direction D2. In the case of the first sheet pattern NS1, for example, one of the second sidewalls NS1_SW2 of the first sheet pattern is in contact with the first channel isolation structure CCW1. One of the second sidewalls of the second sheet pattern NS2 is in contact with the first channel isolation structure CCW1.

[0070] The second trench isolation structure CCW2 may be disposed on the first surface 100US of the first substrate. The second trench isolation structure CCW2 may be disposed between the third lower pattern BP3 and the fourth lower pattern BP4. The second trench isolation structure CCW2 may extend mainly in the first direction D1. The second trench isolation structure CCW2 is spaced apart from the first trench isolation structure CCW1 in the second direction D2.

[0071] The second trench isolation structure CCW2 may isolate the third lower pattern BP3 from the fourth lower pattern BP4. The second trench isolation structure CCW2 isolates the third channel pattern CH3 from the fourth channel pattern CH4. The third lower pattern BP3 and the fourth lower pattern BP4 cover a portion of a sidewall of the second trench isolation structure CCW2. The sidewall of the second trench isolation structure CCW2 may extend mainly in the first direction D1.

[0072] The second trench isolation structure CCW2 may contact the third and fourth lower patterns BP3 and BP4. The second trench isolation structure CCW2 may contact the first sidewalls of the third and fourth lower patterns BP3 and BP4. The first sidewall of the third lower pattern BP3 faces the first sidewall of the fourth lower pattern BP4.

[0073] The third channel pattern CH3 and the fourth channel pattern CH4 are in contact with the second channel isolation structure CCW2. A plurality of third sheet patterns NS3 and a plurality of fourth sheet patterns NS4 are in contact with the second channel isolation structure CCW2. The third sheet pattern NS3 and the fourth sheet pattern NS4 may protrude from the sidewall of the second channel isolation structure CCW2 in the second direction D2. One of the second sidewalls of the third sheet pattern NS3 is in contact with the second channel isolation structure CCW2. One of the second sidewalls of the fourth sheet pattern NS4 is in contact with the second channel isolation structure CCW2.

[0074] Each of the first channel isolation structure CCW1 and the second channel isolation structure CCW2 includes an electrically insulating material. Each of the first channel isolation structure CCW1 and the second channel isolation structure CCW2 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO) or a combination thereof. Although each of the first channel isolation structure CCW1 and the second channel isolation structure CCW2 may be a single layer, this is merely to simplify the description, and the present disclosure is not necessarily limited to this. Since the first channel isolation structure CCW1 and the second channel isolation structure CCW2 are formed simultaneously, the first channel isolation structure CCW1 and the second channel isolation structure CCW2 include the same material.

[0075] Since the description of the second trench isolation structure CCW2 may be substantially the same as that of the first trench isolation structure CCW1, the description of the first trench isolation structure CCW1 may be applied to the second trench isolation structure CCW2. The shape of the first trench isolation structure CCW1 will be described in detail later.

[0076] In the semiconductor device according to an embodiment of the present disclosure, a depth H11 from the upper surface BP1_US of the first lower pattern to the lowermost portion of the first trench isolation structure CCW1 may be less than a depth H12 from the upper surface BP1_US of the first lower pattern to the bottom surface 105BS of the field insulation layer.

[0077] The gate isolation structure GCS may be disposed on the first surface 100US of the first substrate. The gate isolation structure GCS may extend mainly in the first direction D1. The gate isolation structure GCS may be disposed on the field insulating layer 105. A portion of the gate isolation structure GCS may be disposed in the upper interlayer insulating layer 190.

[0078] The gate isolation structure GCS may contact the field insulation layer 105 . The gate isolation structure GCS may protrude further than the upper surface 105US of the field insulation layer in the third direction D3 . For example, a portion of the gate isolation structure GCS may be inserted into the field insulation layer 105 .

[0079] The gate isolation structure GCS is disposed between the first and second channel isolation structures CCW1 and CCW2. Channel patterns CH1, CH2, CH3, and CH4 are disposed between the channel isolation structures CCW1 and CCW2 and the gate isolation structure GCS.

[0080] For example, a depth H11 from the upper surface BP1_US of the first lower pattern to the lowermost portion of the first trench isolation structure CCW1 may be greater than a depth H13 from the upper surface BP1_US of the first lower pattern to the lowermost portion of the gate isolation structure GCS.

[0081] The gate isolation structure GCS includes an electrically insulating material. The gate isolation structure GCS may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), or a combination thereof. Although the gate isolation structure GCS may be a single layer, this is only to simplify the description, and the present disclosure is not necessarily limited thereto.

[0082] The first to fourth gate structures GS1, GS2, GS3, and GS4 may be disposed on the first surface 100US of the first substrate. The first to fourth gate structures GS1, GS2, GS3, and GS4 may be in contact with the upper surface 105US of the field insulating layer.

[0083] The plurality of first gate structures GS1 may be disposed between the first channel isolation structure CCW1 and the gate isolation structure GCS. The plurality of first gate structures GS1 may contact the first channel isolation structure CCW1 and the gate isolation structure GCS. The plurality of first gate structures GS1 may be adjacent to each other in the first direction D1.

[0084] The first gate structure GS1 may be disposed on the first lower pattern BP1. For example, the first gate structure GS1 may be in contact with the upper surface BP1_US of the first lower pattern. The first channel pattern CH1 may be disposed between the first gate structure GS1 and the first channel isolation structure CCW1. Each of the plurality of first sheet patterns NS1 may be disposed between the first gate structure GS1 and the first channel isolation structure CCW1. Since each of the plurality of first sheet patterns NS1 is in contact with the first channel isolation structure CCW1, in a cross-sectional view, the first gate structure GS1 does not surround each of the plurality of first sheet patterns NS1.

[0085] The first gate structure GS1 may include a first gate electrode 120 and a first gate insulating layer 130. The first gate electrode 120 may be disposed on the first lower pattern BP1. The first gate insulating layer 130 may be disposed between the first gate electrode 120 and the first channel pattern CH1. For example, the first gate insulating layer 130 may be disposed between the first gate electrode 120 and the first sheet pattern NS1.

[0086] The first gate insulating layer 130 may extend mainly along the upper surface 105US of the field insulating layer and the upper surface BP1_US of the first lower pattern. The first gate insulating layer 130 may be in contact with the upper surface 105US of the field insulating layer and the upper surface BP1_US of the first lower pattern. Figure 4 In the cross-sectional view of , the first gate insulating layer 130 may extend mainly along the sidewalls of the first trench isolation structure CCW1. The first gate electrode 120 does not contact the sidewalls of the first trench isolation structure CCW1. The first gate insulating layer 130 does not extend along the sidewalls of the gate isolation structure GCS. The first gate electrode 120 may contact the sidewalls of the gate isolation structure GCS. The first gate insulating layer 130 may be disposed along a portion of the circumference of the first sheet pattern NS1.

[0087] The first gate structure GS1 may include a first inner gate structure INT_GS1. The first inner gate structure INT_GS1 may be disposed between the first lower pattern BP1 and the first sheet pattern NS1 and between first sheet patterns NS1 adjacent along the third direction D3. The first inner gate structure INT_GS1 contacts an upper surface BP1_US of the first lower pattern, an upper surface NS1_US of the first sheet pattern, and a bottom surface NS1_BS of the first sheet pattern. The first gate insulating layer 130 included in the first inner gate structure INT_GS1 may contact a first source / drain pattern 150 to be described later.

[0088] Since the description of the second to fourth gate structures GS2 , GS3 , and GS4 may be substantially the same as the description of the first gate structure GS1 described above, the second to fourth gate structures GS2 , GS3 , and GS4 will be briefly described.

[0089] A plurality of second gate structures GS2 may be disposed between the first channel isolation structure CCW1 and the gate isolation structure GCS. A plurality of second gate structures GS2 may be in contact with the first channel isolation structure CCW1 and the gate isolation structure GCS. The first channel isolation structure CCW1 may be disposed between the first gate structure GS1 and the second gate structure GS2. A plurality of second gate structures GS2 may be adjacent to each other in the first direction D1. The second gate structure GS2 may be spaced apart from the first gate structure GS1 in the second direction D2.

[0090] The second gate structure GS2 may be disposed on the second lower pattern BP2. For example, the second gate structure GS2 may be in contact with the upper surface BP2_US of the second lower pattern. The second channel pattern CH2 may be disposed between the second gate structure GS2 and the first channel isolation structure CCW1. Each of the plurality of second sheet patterns NS2 may be disposed between the second gate structure GS2 and the first channel isolation structure CCW1. The second gate structure GS2 may include a second gate electrode 220 and a second gate insulating layer 230. The second gate structure GS2 may include a second inner gate structure, which is disposed between the second lower pattern BP2 and the second sheet pattern NS2 and between the second sheet patterns NS2 adjacent along the third direction D3.

[0091] A plurality of third gate structures GS3 may be disposed between the second channel isolation structure CCW2 and the gate isolation structure GCS. The plurality of third gate structures GS3 may contact the second channel isolation structure CCW2 and the gate isolation structure GCS. The plurality of third gate structures GS3 may be adjacent to each other in the first direction D1. The third gate structure GS3 may be spaced apart from the first gate structure GS1 in the second direction D2.

[0092] The third gate structure GS3 may be disposed on the third lower pattern BP3. For example, the third gate structure GS3 may be in contact with the upper surface BP3_US of the third lower pattern. The third channel pattern CH3 may be disposed between the third gate structure GS3 and the second channel isolation structure CCW2. Each of the plurality of third sheet patterns NS3 may be disposed between the third gate structure GS3 and the second channel isolation structure CCW2. The third gate structure GS3 may include a third gate electrode 320 and a third gate insulating layer 330. The third gate structure GS3 may include a third inner gate structure INT_GS3, and the third inner gate structure INT_GS3 is disposed between the third lower pattern BP3 and the third sheet pattern NS3 and between the third sheet patterns NS3 adjacent to each other along the third direction D3. The third gate insulating layer 330 included in the third inner gate structure INT_GS3 may be in contact with the third source / drain pattern 350 to be described later.

[0093] A plurality of fourth gate structures GS4 may be disposed between the second channel isolation structure CCW2 and the gate isolation structure GCS. A plurality of fourth gate structures GS4 may be in contact with the second channel isolation structure CCW2 and the gate isolation structure GCS. The second channel isolation structure CCW2 may be disposed between the third gate structure GS3 and the fourth gate structure GS4. A plurality of fourth gate structures GS4 may be adjacent to each other in the first direction D1. The fourth gate structure GS4 may be spaced apart from the third gate structure GS3 in the second direction D2.

[0094] The fourth gate structure GS4 may be disposed on the fourth lower pattern BP4. For example, the fourth gate structure GS4 may be in contact with the upper surface BP4_US of the fourth lower pattern. The fourth channel pattern CH4 may be disposed between the fourth gate structure GS4 and the second channel isolation structure CCW2. Each of the plurality of fourth sheet patterns NS4 may be disposed between the fourth gate structure GS4 and the second channel isolation structure CCW2. The fourth gate structure GS4 may include a fourth gate electrode 420 and a fourth gate insulating layer 430. The fourth gate structure GS4 may include a fourth inner gate structure, and the fourth inner gate structure is disposed between the fourth lower pattern BP4 and the fourth sheet pattern NS4 and between the fourth sheet patterns NS4 adjacent to each other along the third direction D3.

[0095] Although in Figure 2 and Figure 3 The cross-sectional view of FIG. 1 shows that the upper surface 120US of the first gate electrode and the upper surface 320US of the third gate electrode are concave surfaces, but the present disclosure is not necessarily limited thereto. The upper surface 120US of the first gate electrode and the upper surface 320US of the third gate electrode may be flat surfaces.

[0096] exist Figure 4 In the cross-sectional view of FIG. 1 , the upper surface of the first gate electrode 120 and the upper surface of the second gate electrode 220 may be flat surfaces. The upper surface of the third gate electrode 320 and the upper surface of the fourth gate electrode 420 may be flat surfaces.

[0097] The first to fourth gate electrodes 120, 220, 320, and 420 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and / or a conductive metal oxynitride. The first to fourth gate electrodes 120, 220, 320, and 420 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TiC), (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof, but are not necessarily limited thereto. The conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the above-mentioned materials, but are not necessarily limited thereto.

[0098] The first to fourth gate insulating layers 130, 230, 330, and 430 may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. As used herein, the term "high-k" may be understood to mean a material having a dielectric constant at least as high as that of silicon oxide. The high-k material may include, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0099] Although each of the first to fourth gate insulating layers 130, 230, 330, and 430 is shown as a single layer, this is to simplify the description, and the present disclosure is not necessarily limited thereto. Each of the first to fourth gate insulating layers 130, 230, 330, and 430 may include a plurality of layers. In the case of the first gate insulating layer 130, for example, the first gate insulating layer 130 may include a high-k insulating layer, and an interface layer disposed between the first channel pattern CH1 and the first gate electrode 120. For example, the interface layer may not be formed along the contour of the upper surface 105US of the field insulating layer.

[0100] The semiconductor device according to an embodiment of the present disclosure may include a negative capacitor (NC) FET using a negative capacitor (NC). For example, each of the first to fourth gate insulating layers 130, 230, 330, and 430 may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0101] The ferroelectric material layer may have a negative capacitance, and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance becomes smaller than the capacitance of each capacitor. When at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and may be greater than the absolute value of each capacitance.

[0102] When a ferroelectric material layer having negative capacitance and a paraelectric material layer having positive capacitance are connected in series, the total capacitance value of the ferroelectric material layer and the paraelectric material layer connected in series can be increased. By using the principle of increasing the total capacitance value, a transistor including a ferroelectric material layer can have a subthreshold swing (SS) lower than or equal to a threshold voltage lower than 60 mV / decade at room temperature.

[0103] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. In this case, as an example, the hafnium zirconium oxide may be a material containing hafnium oxide doped with zirconium (Zr). As an example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0104] The ferroelectric material layer may also include a dopant doped therein. For example, the dopant may include aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and / or tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on which ferroelectric material is included in the ferroelectric material layer.

[0105] When the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0106] When the dopant is aluminum (Al), the ferroelectric material layer may include 3 to 8 atomic percent (at%) of aluminum. In this case, the ratio of the dopant may be a ratio of "aluminum" to "the sum of hafnium and aluminum".

[0107] When the dopant is silicon (Si), the ferroelectric material layer may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material layer may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material layer may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material layer may include 50at% to 80at% zirconium.

[0108] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, silicon oxide and / or a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material layer may include, for example, hafnium oxide, zirconium oxide, and / or aluminum oxide, but is not necessarily limited thereto.

[0109] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0110] The ferroelectric material layer may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, in the range of 0.5 nm to 10 nm, but is not necessarily limited thereto. Since the critical thickness at which each ferroelectric material exhibits ferroelectric properties may be different, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0111] In one example, each of the first to fourth gate insulating layers 130, 230, 330, and 430 may include one ferroelectric material layer. In one example, each of the first to fourth gate insulating layers 130, 230, 330, and 430 may include a plurality of ferroelectric material layers spaced apart from each other. Each of the first to fourth gate insulating layers 130, 230, 330, and 430 may have a stacked structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0112] The first gate spacer 140 may be disposed on the sidewall of the first gate structure GS1. The third gate spacer 340 may be disposed on the sidewall of the third gate structure GS3. The second gate spacer 240 and the fourth gate spacer may be disposed on the sidewall of the second gate structure GS2 and the sidewall of the fourth gate structure GS4, respectively.

[0113] For example, the first gate spacer 140 may not be disposed between the first lower pattern BP1 and the first sheet pattern NS1, and may not be disposed between first sheet patterns NS1 adjacent along the third direction D3. The third gate spacer 340 may not be disposed between the third lower pattern BP3 and the third sheet pattern NS3, and may not be disposed between third sheet patterns NS3 adjacent along the third direction D3.

[0114] The first gate spacer 140 and the third gate spacer 340 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or a combination thereof. Although the first gate spacer 140 and the third gate spacer 340 are shown as a single layer, this is to simplify the description, and the present disclosure is not necessarily limited thereto.

[0115] The first gate covering pattern 145 may be disposed on the first gate structure GS1 and the second gate structure GS2. The first gate covering pattern 145 is disposed on the upper surface 120US of the first gate electrode and the upper surface of the second gate electrode 220. The upper surface 145US of the first gate covering pattern may be on the same plane as the upper surface GCS_US of the gate isolation structure.

[0116] The second gate covering pattern 345 may be disposed on the third gate structure GS3 and the fourth gate structure GS4. The second gate covering pattern 345 is disposed on the upper surface 320US of the third gate electrode and the upper surface of the fourth gate electrode 420. The upper surface 345US of the second gate covering pattern may be on the same plane as the upper surface GCS_US of the gate isolation structure.

[0117] exist Figure 4 In the cross-sectional view, the first gate covering pattern 145 may be disposed on the first channel isolation structure CCW1. The first gate covering pattern 145 may be disposed on the upper surface CCW1_US of the first channel isolation structure. The second gate covering pattern 345 may be disposed on the second channel isolation structure CCW2. The second gate covering pattern 345 may be disposed on the upper surface CCW2_US of the second channel isolation structure. Relative to the bottom surface 105BS of the field insulation layer, the upper surface CCW1_US of the first channel isolation structure may be lower than the upper surface GCS_US of the gate isolation structure. Relative to the bottom surface 105BS of the field insulation layer, the upper surface CCW2_US of the second channel isolation structure may be lower than the upper surface GCS_US of the gate isolation structure.

[0118] The first gate capping pattern 145 and the second gate capping pattern 345 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or a combination thereof.

[0119] The first source / drain pattern 150 may be disposed on the first lower pattern BP1. The first source / drain pattern 150 is disposed adjacent to the first gate structure GS1 in the first direction D1. The first source / drain pattern 150 may be disposed between the first channel isolation structure CCW1 and the gate isolation structure GCS. The first source / drain pattern 150 is connected to the first channel pattern CH1. The first source / drain pattern 150 may contact the first channel pattern CH1. The first source / drain pattern 150 may contact each of the plurality of first sheet patterns NS1. For example, the first source / drain pattern 150 may contact the first inner gate structure INT_GS1.

[0120] The second source / drain pattern 250 may be disposed on the second lower pattern BP2. The second source / drain pattern 250 may be disposed adjacent to the second gate structure GS2 in the first direction D1. The second source / drain pattern 250 may be disposed between the first channel isolation structure CCW1 and the gate isolation structure GCS. The second source / drain pattern 250 is connected to the second channel pattern CH2. The second source / drain pattern 250 may be in contact with the second channel pattern CH2.

[0121] The third source / drain pattern 350 may be disposed on the third lower pattern BP3. The third source / drain pattern 350 is disposed adjacent to the third gate structure GS3 in the first direction D1. The third source / drain pattern 350 may be disposed between the second channel isolation structure CCW2 and the gate isolation structure GCS. The third source / drain pattern 350 is connected to the third channel pattern CH3. The third source / drain pattern 350 may contact the third channel pattern CH3. The third source / drain pattern 350 may contact each of the plurality of third sheet patterns NS3. For example, the third source / drain pattern 350 may contact the third inner gate structure INT_GS3.

[0122] The fourth source / drain pattern 450 may be disposed on the fourth lower pattern BP4. The fourth source / drain pattern 450 may be disposed adjacent to the fourth gate structure GS4 in the first direction D1. The fourth source / drain pattern 450 may be disposed between the second channel isolation structure CCW2 and the gate isolation structure GCS. The fourth source / drain pattern 450 is connected to the fourth channel pattern CH4. The fourth source / drain pattern 450 may be in contact with the fourth channel pattern CH4.

[0123] The first channel isolation structure CCW1 may be disposed between the first source / drain pattern 150 and the second source / drain pattern 250. The first source / drain pattern 150 and the second source / drain pattern 250 are spaced apart from each other in the second direction D2.

[0124] The first source / drain pattern 150 and the second source / drain pattern 250 may contact the first trench isolation structure CCW1. For example, the first source / drain pattern 150 and the second source / drain pattern 250 may contact the sidewall of the first trench isolation structure CCW1.

[0125] For example, a portion of the first source / drain pattern 150 may overlap with the first channel isolation structure CCW1 in the third direction D3. The first source / drain pattern 150 may include an overlapping portion 150_OVR overlapping with the first channel isolation structure CCW1 in the third direction D3. A portion of the first source / drain pattern 150 may be disposed across the first channel isolation structure CCW1. A portion of the second source / drain pattern 250 may overlap with the first channel isolation structure CCW1 in the third direction D3. A portion of the second source / drain pattern 250 may be disposed across the first channel isolation structure CCW1.

[0126] The second channel isolation structure CCW2 may be disposed between the third source / drain pattern 350 and the fourth source / drain pattern 450. The third source / drain pattern 350 and the fourth source / drain pattern 450 are spaced apart from each other in the second direction D2.

[0127] The third source / drain pattern 350 and the fourth source / drain pattern 450 may contact the second channel isolation structure CCW2. For example, the third source / drain pattern 350 and the fourth source / drain pattern 450 may contact the sidewall of the second channel isolation structure CCW2.

[0128] For example, a portion of the third source / drain pattern 350 and a portion of the fourth source / drain pattern 450 may overlap the second channel isolation structure CCW2 in the third direction D3. A portion of the third source / drain pattern 350 and a portion of the fourth source / drain pattern 450 may be disposed across the second channel isolation structure CCW2.

[0129] In the semiconductor device according to the embodiment of the present disclosure, the first source / drain pattern 150 may contact the first sheet pattern NS1 and the first lower pattern BP1. The third source / drain pattern 350 may contact the third sheet pattern NS3 and the third lower pattern BP3.

[0130] Source / drain patterns 150, 250, 350, and 450 may be disposed on the first surface 100US of the substrate. The first source / drain pattern 150 may be included in the source / drain of a transistor using the first sheet pattern NS1 as a channel region. The second source / drain pattern 250 may be included in the source / drain of a transistor using the second sheet pattern NS2 as a channel region. The third source / drain pattern 350 may be included in the source / drain of a transistor using the third sheet pattern NS3 as a channel region. The fourth source / drain pattern 450 may be included in the source / drain of a transistor using the fourth sheet pattern NS4 as a channel region.

[0131] Each of the first to fourth source / drain patterns 150, 250, 350, and 450 may include an epitaxial pattern. Each of the first to fourth source / drain patterns 150, 250, 350, and 450 may include a semiconductor material.

[0132] The first source / drain pattern 150 and the second source / drain pattern 250 may include dopants of the same conductivity type. The first source / drain pattern 150 and the second source / drain pattern 250 may include p-type dopants or n-type dopants. The third source / drain pattern 350 and the fourth source / drain pattern 450 may include dopants of the same conductivity type. The third source / drain pattern 350 and the fourth source / drain pattern 450 may include p-type dopants or n-type dopants. The p-type dopant may include boron (B) and / or gallium (Ga), but the present disclosure is not necessarily limited thereto. The n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb) and / or bismuth (Bi), but the present disclosure is not necessarily limited thereto.

[0133] A height H14 from the bottom surface 105BS of the field insulating layer to the upper surface of the first channel pattern CH1 is less than a height H16 from the bottom surface 105BS of the field insulating layer to the uppermost portion of the first source / drain pattern 150. Here, the uppermost portion of the first source / drain pattern 150 may be included in the structure including the first source / drain pattern 150 and the first contact silicide layer 155. The uppermost portion of the first source / drain pattern 150 may be a portion of the first source / drain pattern 150 farthest from the bottom surface 105BS of the field insulating layer.

[0134] The following description will focus on the first trench isolation structure CCW1. For example, the description of the first trench isolation structure CCW1 can be applied to the second trench isolation structure CCW2.

[0135] exist Figure 1 , Figure 4 , Figure 5 and Figures 7 to 9In the embodiment, the first channel isolation structure CCW1 may include a first region CCW1_R1 and a second region CCW1_R2. The first region CCW1_R1 of the first channel isolation structure may be a region in contact with the first gate structure GS1 and the second gate structure GS2 in the first channel isolation structure CCW1. The first region CCW1_R1 of the first channel isolation structure may be a region overlapping with the first gate structure GS1 and the second gate structure GS2 in the second direction D2. The second region CCW1_R2 of the first channel isolation structure may be a region in contact with the first source / drain pattern 150 and the second source / drain pattern 250 in the first channel isolation structure CCW1. The second region CCW1_R2 of the first channel isolation structure may be a region overlapping with the first source / drain pattern 150 and the second source / drain pattern 250 in the second direction D2.

[0136] For example, Figure 8 is a diagram showing the shape of the first region CCW1_R1 of the first trench isolation structure, and Fig. 9 is a diagram illustrating the shape of the second region CCW1_R2 of the first trench isolation structure.

[0137] exist Figure 4 and Figure 8 In the embodiment, the width of the first trench isolation structure CCW1 in the second direction D2 may continuously increase as the distance from the bottom surface 105BS of the field insulation layer increases.

[0138] exist Figure 5 and Fig. 9 In the first region CCW1_R2 of the first trench isolation structure, the second region CCW1_R2 may include a first portion CCW1_R21 and a second portion CCW1_R22, and the widths of the first portion CCW1_R21 and the second portion CCW1_R22 increase as the distance from the bottom surface 105BS of the field insulation layer increases. In the first portion CCW1_R21 of the second region of the first trench isolation structure and the second portion CCW1_R22 of the second region of the first trench isolation structure, the width of the first trench isolation structure CCW1 in the second direction D2 may continuously increase as the distance from the bottom surface 105BS of the field insulation layer increases.

[0139] The second portion CCW1_R22 of the second region of the first trench isolation structure may be disposed on the first portion CCW1_R21 of the second region of the first trench isolation structure. In the semiconductor device according to an embodiment of the present disclosure, the second portion CCW1_R22 of the second region of the first trench isolation structure may be directly connected to the first portion CCW1_R21 of the second region of the first trench isolation structure.

[0140] There may be a step portion disposed between the first portion CCW1_R21 of the second region of the first trench isolation structure and the second portion CCW1_R22 of the second region of the first trench isolation structure CCW1. For example, a width W21 of an uppermost portion of the first trench isolation structure CCW1 in the first portion CCW1_R21 of the second region of the first trench isolation structure CCW1 is greater than a width W22 of a lowermost portion of the first trench isolation structure CCW1 in the second portion CCW1_R22 of the second region of the first trench isolation structure CCW1.

[0141] The first portion CCW1_R21 of the second region of the first trench isolation structure may include a first width center line WCL1 extending mainly in the third direction D3. The second portion CCW1_R22 of the second region of the first trench isolation structure may include a second width center line WCL2 extending mainly in the third direction D3. In the semiconductor device according to an embodiment of the present disclosure, the first width center line WCL1 may be aligned with the second width center line WCL2 in the third direction D3. For example, an extension line of the first width center line WCL1 may coincide with the second width center line WCL2.

[0142] For example, the first width center line WCL1 may be an imaginary line dividing the width W21 of the uppermost portion of the first portion CCW1_R21 of the second region of the first trench isolation structure in half. The second width center line WCL2 may be an imaginary line dividing the width W22 of the lowermost portion of the second portion CCW1_R22 of the second region of the first trench isolation structure in half.

[0143] A height H15 from the bottom surface 105BS of the field insulation layer to the uppermost portion of the first portion CCW1_R21 of the second region of the first trench isolation structure is smaller than a height H16 from the bottom surface 105BS of the field insulation layer to the uppermost portion of the first source / drain pattern 150 .

[0144] A portion of the first source / drain pattern 150 may overlap the first portion CCW1_R21 of the second region of the first trench isolation structure in the third direction D3. An overlapping portion 150_OVR of the first source / drain pattern may overlap the first portion CCW1_R21 of the second region of the first trench isolation structure in the third direction D3. An overlapping portion 150_OVR of the first source / drain pattern may be disposed across the first portion CCW1_R21 of the second region of the first trench isolation structure.

[0145] A portion of the second source / drain pattern 250 may overlap the first portion CCW1_R21 of the second region of the first trench isolation structure in the third direction D3. A portion of the second source / drain pattern 250 may be disposed across the first portion CCW1_R21 of the second region of the first trench isolation structure.

[0146] Although there is no boundary surface between the first portion CCW1_R21 of the second region of the first trench isolation structure and the second portion CCW1_R22 of the second region of the first trench isolation structure, the present disclosure is not necessarily limited thereto. For example, the first portion CCW1_R21 of the second region of the first trench isolation structure may be distinguished from the second portion CCW1_R22 of the second region of the first trench isolation structure by a boundary surface.

[0147] exist Figure 4 and Figure 5 , a height H15 from the bottom surface 105BS of the field insulation layer to the uppermost portion of the first portion CCW1_R21 of the second region of the first trench isolation structure is smaller than a height H14 from the bottom surface 105BS of the field insulation layer to the upper surface of the first channel pattern CH1 .

[0148] exist Figure 5 In the cross-sectional view, the upper surface CCW1_US of the first trench isolation structure may be on the same plane as the upper surface GCS_US of the gate isolation structure.

[0149] An upper surface CCW1_US of the first trench isolation structure in the first region CCW1_R1 of the first trench isolation structure may be lower than an upper surface CCW1_US of the first trench isolation structure in the second region CCW1_R2 of the first trench isolation structure. A height from a bottom surface 105BS of the field insulation layer to an upper surface CCW1_US of the first trench isolation structure in the first region CCW1_R1 of the first trench isolation structure may be lower than a height from a bottom surface 105BS of the field insulation layer to an upper surface CCW1_US of the first trench isolation structure in the second region CCW1_R2 of the first trench isolation structure.

[0150] For example, Figure 7 is a plan view that may be taken at a height level of the second portion CCW1_R22 of the second region of the first trench isolation structure.

[0151] exist Figure 7 In the embodiment, a width W11 of the first channel isolation structure CCW1 between the first gate structure GS1 and the second gate structure GS2 in the second direction D2 is different from a width W12 of the first channel isolation structure CCW1 between the first source / drain pattern 150 and the second source / drain pattern 250 in the second direction D2. For example, a width W11 of the first channel isolation structure CCW1 between the first gate structure GS1 and the second gate structure GS2 in the second direction D2 is greater than a width I2 of the first channel isolation structure CCW1 between the first source / drain pattern 150 and the second source / drain pattern 250 in the second direction D2.

[0152] The first source / drain pattern 150 may overlap the first trench isolation structure CCW1 in the first direction D1 by a first overlap width W13. The second source / drain pattern 250 may overlap the first trench isolation structure CCW1 in the first direction D1 by a second overlap width W14. For example, the first overlap width W13 may be the same as the second overlap width W14.

[0153] The source / drain etch stop layer 185 may extend mainly along the outer walls of the first gate spacer 140 and the third gate spacer 340 and the sidewalls of the source / drain patterns 150, 250, 350, and 450. The source / drain etch stop layer 185 may extend mainly along the upper surface 105US of the field insulating layer. For example, the source / drain etch stop layer 185 may contact the sidewalls of the first to fourth source / drain patterns 150, 250, 350, and 450.

[0154] A portion of the source / drain etch stop layer 185 may extend mainly along the sidewalls of the first trench isolation structure CCW1 and the second trench isolation structure CCW2. The source / drain etch stop layer 185 on the sidewalls of the first trench isolation structure CCW1 and the second trench isolation structure CCW2 may be a portion that is not removed and remains in the process of manufacturing the source / drain contacts 180, 280, 380, and 480.

[0155] The source / drain etch stop layer 185 may not extend mainly along the sidewalls of the first gate capping pattern 145 and the second gate capping pattern 345. Unlike the illustrated example, the source / drain etch stop layer 185 may extend mainly along the sidewalls of the first gate capping pattern 145 and the second gate capping pattern 345.

[0156] The source / drain etch stop layer 185 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), or combinations thereof.

[0157] When the source / drain etch stop layer 185 includes the same material as the first trench isolation structure CCW1, the boundary between the source / drain etch stop layer 185 and the first trench isolation structure CCW1 may not be distinguished (i.e., there may be no perceptible boundary). When the source / drain etch stop layer 185 includes the same material as the second trench isolation structure CCW2, the boundary between the source / drain etch stop layer 185 and the second trench isolation structure CCW2 may not be distinguished (i.e., there may be no perceptible boundary). In this case, the source / drain etch stop layer 185 disposed on the source / drain patterns 150, 250, 350 and 450 and in contact with the source / drain contacts 180, 280, 380 and 480 may be identified as a portion of the first trench isolation structure CCW1 and / or the second trench isolation structure CCW2.

[0158] Unlike the illustrated example, the source / drain etch stop layer 185 may not be formed.

[0159] The upper interlayer insulating layer 190 is disposed on the first surface 100US of the substrate. The upper interlayer insulating layer 190 may be disposed on the source / drain etch stop layer 185. The upper interlayer insulating layer 190 may be disposed on the first to fourth source / drain patterns 150, 250, 350, and 450.

[0160] The upper interlayer insulating layer 190 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material. The dielectric constant of the low dielectric constant material may have a value less than 3.9, which is the dielectric constant of silicon oxide.

[0161] The first source / drain contact 180 may be disposed on the first source / drain pattern 150. The first source / drain contact 180 is electrically connected to the first source / drain pattern 150. The first source / drain contact 180 is disposed between the first trench isolation structure CCW1 and the gate isolation structure GCS. The first source / drain contact 180 may be disposed on the upper interlayer insulating layer 190. A portion of the source / drain etch stop layer 185 may be disposed between the first source / drain contact 180 and the first trench isolation structure CCW1.

[0162] The second source / drain contact 280 may be disposed on the second source / drain pattern 250. The second source / drain contact 280 is electrically connected to the second source / drain pattern 250. The second source / drain contact 280 is disposed between the first trench isolation structure CCW1 and the gate isolation structure GCS. The second source / drain contact 280 may be disposed on the upper interlayer insulating layer 190. A portion of the source / drain etch stop layer 185 may be disposed between the second source / drain contact 280 and the first trench isolation structure CCW1.

[0163] A third source / drain contact 380 may be disposed on the third source / drain pattern 350. The third source / drain contact 380 is electrically connected to the third source / drain pattern 350. A fourth source / drain contact 480 may be disposed on the fourth source / drain pattern 450. The fourth source / drain contact 480 is electrically connected to the fourth source / drain pattern 450.

[0164] The first contact silicide layer 155 may be disposed between the first source / drain contact 180 and the first source / drain pattern 150. The second contact silicide layer 255 may be disposed between the second source / drain contact 280 and the second source / drain pattern 250. The third contact silicide layer 355 may be disposed between the third source / drain contact 380 and the third source / drain pattern 350. The fourth contact silicide layer 455 may be disposed between the fourth source / drain contact 480 and the fourth source / drain pattern 450.

[0165] Although the source / drain contacts 180, 280, 380, and 480 are shown to have a single conductive layer structure, the present disclosure is not necessarily limited thereto. Unlike the illustrated example, the source / drain contacts 180, 280, 380, and 480 may have a multi-conductive layer structure including a barrier layer and a plug layer. The source / drain contacts 180, 280, 380, and 480 may include, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and / or a two-dimensional (2D) material. The contact silicide layers 155, 255, 355, and 455 may include a metal silicide material.

[0166] The 2D material may include a 2D allotrope or a 2D compound, and may include, for example, graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and / or tantalum sulfide, but the present disclosure is not necessarily limited thereto. For example, since the 2D materials mentioned above are only examples, the 2D materials that may be included in the semiconductor device of the present disclosure are not necessarily limited thereto.

[0167] Fig.10 and Fig.11 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Fig.12 and Fig.13 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Fig.14 and Fig.15 is a diagram showing a semiconductor device according to an embodiment of the present disclosure. Figures 1 to 9 The difference in description.

[0168] Fig.10 yes Figure 1 Schematic plan view of part P of FIG. Fig.11 yes Figure 5 An enlarged view of part S. Fig.13 and Fig.15 yes Fig.12 and Fig.14 An enlarged view of part S.

[0169] Reference Fig.10 and Fig.11 , in the semiconductor device according to the embodiment of the present disclosure, the first stacking width W13 may be different from the second stacking width W14.

[0170] For example, a first overlapping width W13 of the first source / drain pattern 150 overlapping the first trench isolation structure CCW1 in the first direction D1 may be greater than a second overlapping width W14 of the second source / drain pattern 250 overlapping the first trench isolation structure CCW1 in the first direction D1.

[0171] The first width centerline WCL1 may be spaced apart from the second width centerline WCL2 in the second direction D2. The first width centerline WCL1 may not be aligned with the second width centerline WCL2 in the third direction D3. An extension line of the first width centerline WCL1 may not intersect the second width centerline WCL2.

[0172] Although a portion of the second source / drain pattern 250 is shown overlapping the first portion CCW1_R21 of the second region of the first trench isolation structure in the third direction D3, the present disclosure is not necessarily limited thereto. For example, the second source / drain pattern 250 may not include a portion disposed across the first portion CCW1_R21 of the second region of the first trench isolation structure.

[0173] Reference Fig.12 and Fig.13 In the semiconductor device according to the embodiment of the present disclosure, the second region CCW1_R2 of the first trench isolation structure may further include a third portion CCW1_R23 disposed between the first portion CCW1_R21 of the second region of the first trench isolation structure and the second portion CCW1_R22 of the second region of the first trench isolation structure.

[0174] In the third portion CCW1_R23 of the second region of the first trench isolation structure, the width of the first trench isolation structure CCW1 in the second direction D2 may decrease as the distance from the bottom surface 105BS of the field insulation layer increases.

[0175] Although there is no boundary surface between the first portion CCW1_R21 of the second region of the first trench isolation structure and the third portion CCW1_R23 of the second region of the first trench isolation structure, the present disclosure is not necessarily limited thereto. For example, the first portion CCW1_R21 of the second region of the first trench isolation structure may be distinguished from the third portion CCW1_R23 of the second region of the first trench isolation structure by a boundary surface.

[0176] Reference Fig.14 and Fig.15 In the semiconductor device according to the embodiment of the present disclosure, the second region CCW1_R2 of the first trench isolation structure may further include a fourth portion CCW1_R24 whose width increases as the distance from the bottom surface 105BS of the field insulation layer increases.

[0177] In the fourth portion CCW1_R24 of the second region of the first trench isolation structure, the width of the first trench isolation structure CCW1 in the second direction D2 may increase as the distance from the bottom surface 105BS of the field insulation layer increases.

[0178] For example, the second portion CCW1_R22 of the second region of the first trench isolation structure may be directly connected to the fourth portion CCW1_R24 of the second region of the first trench isolation structure. The fourth portion CCW1_R24 of the second region of the first trench isolation structure may overlap the first source / drain contact 180 and the second source / drain contact 280 in the second direction D2.

[0179] There may be a step portion between the fourth portion CCW1_R24 of the second region of the first trench isolation structure and the second portion CCW1_R22 of the second region of the first trench isolation structure. A width W23 of the uppermost portion of the first trench isolation structure CCW1 at the second portion CCW1_R22 of the second region of the first trench isolation structure is greater than a width W24 of the lowermost portion of the first trench isolation structure CCW1 at the fourth portion CCW1_R24 of the second region of the first trench isolation structure.

[0180] Figures 16 to 19 are diagrams each showing a semiconductor device according to an embodiment of the present disclosure. Figures 1 to 9 The difference in description.

[0181] Reference Fig.16In the semiconductor device according to an embodiment of the present disclosure, a depth H11 from the upper surface BP1_US of the first lower pattern to the lowermost portion of the first trench isolation structure CCW1 may be the same as a depth H12 from the upper surface BP1_US of the first lower pattern to the bottom surface 105BS of the field insulation layer.

[0182] Reference Fig.17 , the semiconductor device according to the embodiment of the present disclosure may further include a field insulation line pattern 105DP.

[0183] The field insulation line pattern 105DP may be disposed at a boundary portion between a bottom surface of the fin trench FT and a sidewall of the fin trench FT. The field insulation line pattern 105DP may extend mainly along the fin trench FT in the first direction D1. The field insulation layer 105 is disposed on the field insulation line pattern 105DP.

[0184] The field insulation line pattern 105DP includes the same material as that of the first and second trench isolation structures CCW1 and CCW2. In the manufacturing process, the field insulation line pattern 105DP may be formed during the formation of the first and second trench isolation structures CCW1 and CCW2.

[0185] Reference Fig.18 In the semiconductor device according to an embodiment of the present disclosure, the first gate capping pattern 145 may cover a portion of a sidewall of the first trench isolation structure CCW1 .

[0186] A portion of the first gate capping pattern 145 may overlap a portion of the sidewall of the first trench isolation structure CCW1 in the second direction D2. In a cross-sectional view, a portion of the first gate capping pattern 145 may protrude further toward the first substrate 100 than an upper surface CCW1_US of the first trench isolation structure.

[0187] The second gate capping pattern 345 may cover a portion of a sidewall of the second trench isolation structure CCW2 .

[0188] Reference Fig.19 , the semiconductor device according to the embodiment of the present disclosure may further include a gate contact 170 and a gate bridge contact 171 .

[0189] The gate contact 170 may be disposed in the second gate capping pattern 345. The gate contact 170 may be connected to the third gate electrode 320 and the fourth gate electrode 420. For example, one gate contact 170 may be connected to one gate electrode 320 or 420.

[0190] The gate bridge contact 171 may be disposed in the first gate capping pattern 145. The gate bridge contact 171 is connected to the first gate electrode 120 and the second gate electrode 220. The gate bridge contact 171 connects the first gate electrode 120 and the second gate electrode 220 spaced apart from each other in the second direction D2. The gate bridge contact 171 is used to connect the spaced apart gate electrodes and also performs the function of the gate contact 170.

[0191] Although the gate contact 170 and the gate bridge contact 171 are shown to have a single conductive layer structure, the present disclosure is not necessarily limited thereto. Unlike the illustrated example, the gate contact 170 and the gate bridge contact 171 may have a multi-conductive layer structure including a barrier layer and a plug layer. The gate contact 170 and the gate bridge contact 171 may include, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and / or a two-dimensional (2D) material.

[0192] Fig. 20 and Fig.21 are diagrams each showing a semiconductor device according to an embodiment of the present disclosure. Figures 1 to 9 The difference in description.

[0193] Reference Fig. 20 , the semiconductor device according to the embodiment of the present disclosure may further include first to fourth inserted source / drain oxide layers 151 , 251 , 351 , and 451 contacting the first to fourth source / drain patterns 150 , 250 , 350 , and 450 .

[0194] The first inserted source / drain oxide layer 151 may be disposed between the first source / drain pattern 150 and the source / drain etch stop layer 185. The second inserted source / drain oxide layer 251 may be disposed between the second source / drain pattern 250 and the source / drain etch stop layer 185. The third inserted source / drain oxide layer 351 may be disposed between the third source / drain pattern 350 and the source / drain etch stop layer 185. The fourth inserted source / drain oxide layer 451 may be disposed between the fourth source / drain pattern 450 and the source / drain etch stop layer 185.

[0195] The first to fourth inserted source / drain oxide layers 151 , 251 , 351 , and 451 include an oxide of the semiconductor material included in the first to fourth source / drain patterns 150 , 250 , 350 , and 450 .

[0196] Reference Fig.21, the semiconductor device according to the embodiment of the present disclosure may further include first to fourth source / drain fences 150SP, 250SP, 350SP, and 450SP disposed on the upper surface 105US of the field insulating layer.

[0197] Each of the first to fourth source / drain fences 150SP, 250SP, 350SP, and 450SP may protrude from the upper surface 105US of the field insulating layer in the third direction D3. The first to fourth source / drain fences 150SP, 250SP, 350SP, and 450SP may contact the first to fourth source / drain patterns 150, 250, 350, and 450, respectively.

[0198] The first source / drain fence 150SP may be disposed on a portion of the sidewall of the first source / drain pattern 150. The second source / drain fence 250SP may be disposed on a portion of the sidewall of the second source / drain pattern 250. The third source / drain fence 350SP may be disposed on a portion of the sidewall of the third source / drain pattern 350. The fourth source / drain fence 450SP may be disposed on a portion of the sidewall of the fourth source / drain pattern 450.

[0199] The first to fourth source / drain gates 150SP, 250SP, 350SP, and 450SP may include materials included in the first gate spacer 140 and the third gate spacer 340. For example, the first to fourth source / drain gates 150SP, 250SP, 350SP, and 450SP may be formed together with the first gate spacer 140 and the third gate spacer 340 in the manufacturing process.

[0200] Reference Figure 22 to Figure 24 , Figure 22 to Figure 24 is a diagram showing a semiconductor device according to an embodiment of the present disclosure. Figures 1 to 9 The difference in description.

[0201] Figure 22 to Figure 24 are diagrams each illustrating a semiconductor device according to an embodiment of the present disclosure.

[0202] Reference Figure 22 to Figure 24 , the semiconductor device according to the embodiment of the present disclosure may further include first to fourth lower insulating patterns BDI1 , BDI2 , BDI3 , and BDI4 .

[0203] The first lower insulating pattern BDI1 may be disposed between the first lower pattern BP1 and the first channel pattern CH1. The first lower insulating pattern BDI1 may contact the upper surface BP1_US of the first lower pattern. The first lower insulating pattern BDI1 may extend mainly in the first direction D1 along the upper surface BP1_US of the first lower pattern.

[0204] The second lower insulating pattern BDI2 may be disposed between the second lower pattern BP2 and the second channel pattern CH2. The second lower insulating pattern BDI2 may contact the upper surface BP2-US of the second lower pattern. The second lower insulating pattern BDI2 may extend mainly in the first direction D1 along the upper surface BP2_US of the second lower pattern.

[0205] The third lower insulating pattern BDI3 may be disposed between the third lower pattern BP3 and the third channel pattern CH3. The third lower insulating pattern BDI3 may contact the upper surface BP3_US of the third lower pattern. The third lower insulating pattern BDI3 may extend mainly in the first direction D1 along the upper surface BP3_US of the third lower pattern.

[0206] The fourth lower insulating pattern BDI4 may be disposed between the fourth lower pattern BP4 and the fourth channel pattern CH4. The fourth lower insulating pattern BDI4 may contact the upper surface BP4_US of the fourth lower pattern. The fourth lower insulating pattern BDI4 may extend mainly in the first direction D1 along the upper surface BP4_US of the fourth lower pattern.

[0207] The first lower insulating pattern BDI1 may be spaced apart from the second lower insulating pattern BDI2 in the second direction D2. The first trench isolation structure CCW1 may isolate the first lower insulating pattern BDI1 from the second lower insulating pattern BDI2.

[0208] The third lower insulating pattern BDI3 may be spaced apart from the fourth lower insulating pattern BDI4 in the second direction D2. The second trench isolation structure CCW2 may isolate the third lower insulating pattern BDI3 from the fourth lower insulating pattern BDI4.

[0209] The first to fourth lower insulating patterns BDI1, BDI2, BDI3, and BDI4 may not extend along the upper surface 105US of the field insulating layer. The first to fourth lower insulating patterns BDI1, BDI2, BDI3, and BDI4 may not cover the upper surface 105US of the field insulating layer.

[0210] The first to fourth lower insulating patterns BDI1, BDI2, BDI3, and BDI4 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), and / or silicon oxycarbon nitride (SiOCN). Alternatively, the first to fourth lower insulating patterns BDI1, BDI2, BDI3, and BDI4 may include silicon oxide.

[0211] The first channel pattern CH1 may further include a first dummy sheet pattern NSD1 disposed between the first sheet pattern NS1 and the first lower insulating pattern BDI1. The first dummy sheet pattern NSD1 may be in contact with the first lower insulating pattern BDI1.

[0212] The second channel pattern CH2 may further include a second dummy sheet pattern NSD2 disposed between the second sheet pattern NS2 and the second lower insulating pattern BDI2. The second dummy sheet pattern NSD2 may be in contact with the second lower insulating pattern BDI2.

[0213] The third channel pattern CH3 may further include a third dummy sheet pattern NSD3 disposed between the third sheet pattern NS3 and the third lower insulating pattern BDI3. The third dummy sheet pattern NSD3 may be in contact with the third lower insulating pattern BDI3.

[0214] The fourth channel pattern CH4 may further include a fourth dummy sheet pattern NSD4 disposed between the fourth sheet pattern NS4 and the fourth lower insulating pattern BDI4. The fourth dummy sheet pattern NSD4 may be in contact with the fourth lower insulating pattern BDI4.

[0215] The thickness of the dummy sheet patterns NSD1, NSD2, NSD3, and NSD4 in the third direction D3 is smaller than the thickness of the sheet patterns NS1, NS2, NS3, and NS4 in the third direction D3. The dummy sheet patterns NSD1, NSD2, NSD3, and NSD4 may include the same material as the sheet patterns NS1, NS2, NS3, and NS4.

[0216] Taking the first lower insulating pattern BDI1 as an example, the first lower insulating pattern BDI1 may include an upper surface and a bottom surface facing away from each other in the third direction D3. The bottom surface of the first lower insulating pattern BDI1 may be in contact with the upper surface BP1_US of the first lower pattern. The upper surface of the first lower insulating pattern BDI1 may be higher than the upper surface 105US of the field insulating layer relative to the bottom surface 105BS of the field insulating layer. The upper surface of the first lower insulating pattern BDI1 may protrude beyond the upper surface 105US of the field insulating layer. Since the first dummy sheet pattern NSD1 is in contact with the upper surface of the first lower insulating pattern BDI1, the first gate insulating layer 130 may not be in contact with the upper surface of the first lower insulating pattern BDI1.

[0217] The first source / drain pattern 150 may contact the first dummy sheet pattern NSD1 and the first sheet pattern NS1. The first source / drain pattern 150 may contact the first lower insulating pattern BDI1. The first source / drain pattern 150 may not contact the first lower pattern BP1.

[0218] The second source / drain pattern 250 may contact the second dummy sheet pattern NSD2 and the second sheet pattern NS2. The second source / drain pattern 250 may contact the second lower insulating pattern BDI2. The second source / drain pattern 250 may not contact the second lower pattern BP2.

[0219] The third source / drain pattern 350 may contact the third dummy sheet pattern NSD3 and the third sheet pattern NS3. The third source / drain pattern 350 may contact the third lower insulating pattern BDI3. The third source / drain pattern 350 may not contact the third lower pattern BP3.

[0220] The fourth source / drain pattern 450 may contact the fourth dummy sheet pattern NSD4 and the fourth sheet pattern NS4. The fourth source / drain pattern 450 may contact the fourth lower insulating pattern BDI4. The fourth source / drain pattern 450 may not contact the fourth lower pattern BP4.

[0221] Fig.25 and Fig.26 are diagrams each showing a semiconductor device according to an embodiment of the present disclosure. Figure 22 to Figure 24 The difference in description.

[0222] Reference Fig.25 , in the semiconductor device according to an embodiment of the present disclosure, the first source / drain pattern 150 may penetrate the first lower insulating pattern BDI1 .

[0223] The first source / drain pattern 150 may be in contact with the first lower insulating pattern BDI1 and the first lower pattern BP1.

[0224] Since the first lower insulating pattern BDI1 is isolated by the first source / drain pattern 150, a plurality of first lower insulating patterns BDI1 may be disposed on the upper surface BP1_US of the first lower pattern. The plurality of first lower insulating patterns BDI1 may be arranged in the first direction D1. Each of the plurality of first lower insulating patterns BDI1 may be disposed at a position overlapping the first gate structure GS1 along the third direction D3.

[0225] For example, information about the first source / drain pattern 150 and the first lower insulating pattern BDI1 may be applied to the second to fourth source / drain patterns 250, 350, and 450 and the second to fourth lower insulating patterns BDI2, BDI3, and BDI4. For example, information about the first source / drain pattern 150 and the first lower insulating pattern BDI1 may be applied to the second source / drain pattern 250 and the second lower insulating pattern BDI2. Information about the first source / drain pattern 150 and the first lower insulating pattern BDI1 may not be applied to the third and fourth source / drain patterns 350 and 450 and the third and fourth lower insulating patterns BDI3 and BDI4.

[0226] Reference Fig.26 , in the semiconductor device according to the embodiment of the present disclosure, the first channel pattern CH1 does not include a dummy sheet pattern disposed between the first sheet pattern NS1 and the first lower insulating pattern BDI1.

[0227] Since the first dummy piece pattern NSD1 (see Fig. 22 and Fig.23 ) is not disposed between the first lower insulating pattern BDI1 and the first sheet pattern NS1, and thus the first gate insulating layer 130 may contact an upper surface of the first lower insulating pattern BDI1.

[0228] The second to fourth channel patterns CH2 , CH3 , and CH4 do not include a dummy sheet pattern.

[0229] Fig. 27 and Fig.28 is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Fig.29 is a diagram showing a semiconductor device according to an embodiment of the present disclosure. Figures 1 to 9 The difference in description.

[0230] Reference Fig. 27 and Fig.28 , the semiconductor device according to the embodiment of the present disclosure may further include a sacrificial semiconductor pattern 160SC, a sacrificial pattern capping layer 160IP, back source / drain contacts 175 , and back wiring lines 290 .

[0231] The first to fourth lower patterns BP1, BP2, BP3, and BP4 may be disposed on the second substrate 200. The second substrate 200 may include a first surface 200US and a second surface 200BS facing each other in the third direction D3. The first to fourth lower patterns BP1, BP2, BP3, and BP4 are disposed on the first surface 200US of the second substrate.

[0232] The second substrate 200 may include an electrically insulating material, and may include silicon oxide, silicon nitride, and / or a combination thereof. The second substrate 200 may be removed during the manufacturing process. Figures 2 to 5 The first substrate 100 is then formed by a deposition process or the like.

[0233] The field insulating layer 105 may contact the second substrate 200. A bottom surface 105BS of the field insulating layer faces the second substrate 200.

[0234] The sacrificial semiconductor pattern 160SC may be disposed in the first to fourth lower patterns BP1, BP2, BP3, and BP4. The sacrificial semiconductor pattern 160SC may be disposed between the first to fourth source / drain patterns 150, 250, 350, and 450 and the second substrate 200. The sacrificial semiconductor pattern 160SC may overlap the first to fourth source / drain patterns 150, 250, 350, and 450 in the third direction D3.

[0235] The sacrificial pattern capping layer 160IP may be disposed between the first source / drain pattern 150 and the sacrificial semiconductor pattern 160SC and between the second source / drain pattern 250 and the sacrificial semiconductor pattern 160SC. The sacrificial pattern capping layer 160IP may be disposed between the third source / drain pattern 350 and the sacrificial semiconductor pattern 160SC and between the fourth source / drain pattern 450 and the sacrificial semiconductor pattern 160SC.

[0236] The sacrificial semiconductor pattern 160SC may include a material having an etching selectivity with respect to the first to fourth lower patterns BP1, BP2, BP3, and BP4. When the first to fourth lower patterns BP1, BP2, BP3, and BP4 are silicon patterns, the sacrificial semiconductor pattern 160SC may include silicon germanium. The sacrificial pattern capping layer 160IP may include an electrically insulating material.

[0237] The back wiring line 290 may be disposed in the second substrate 200. The back wiring line 290 may include a line portion and a via portion. Although the line portion of the back wiring line 290 is shown as extending mainly in the first direction D1, this is to simplify the description and is not necessarily limited thereto. The via portion of the back wiring line 290 may protrude from the line portion of the back wiring line 290 in the third direction D3. Unlike the illustrated example, the back wiring line 290 may not include a via portion.

[0238] The back source / drain contact 175 may be disposed between the first source / drain pattern 150 and the back wiring line 290. The back source / drain contact 175 electrically connects the first source / drain pattern 150 to the back wiring line 290.

[0239] The back source / drain contact 175 is shown as being connected to a portion of the first source / drain pattern 150, but this is to simplify the description and is not necessarily limited thereto. Unlike the illustrated example, the back source / drain contact 175 may be connected to the second to fourth source / drain patterns 250, 350, and 450.

[0240] A back contact silicide layer 156 may be disposed between the back source / drain contacts 175 and the first source / drain pattern 150 .

[0241] Each of the back source / drain contact 175 and the back wiring line 290 is shown as a single conductive layer, but is not necessarily limited thereto. Unlike the illustrated example, the back source / drain contact 175 and / or the back wiring line 290 may have a conductive multilayer structure including a barrier layer and a filling layer. Each of the back source / drain contact 175 and the back wiring line 290 may include, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and / or a two-dimensional material.

[0242] Reference Fig.29 , the semiconductor device according to the embodiment of the present disclosure may further include an inner spacer 340IN disposed between the third source / drain pattern 350 and the third inner gate structure INT_GS3 .

[0243] The inner spacer 340IN may be disposed between the third lower pattern BP3 and the third sheet pattern NS3 and between the third sheet patterns NS3 adjacent in the third direction D3 The third inner gate structure INT_GS3 may not contact the third source / drain pattern 350 .

[0244] The inner spacer 340IN may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC) and / or combinations thereof.

[0245] The inner spacer may be disposed in the third lower pattern BP3 (see Figure 3 ) and the third pattern NS3 and between the third pattern NS3 adjacent to the third direction D3.

[0246] Figures 30 to 59 2 is a diagram illustrating an intermediate step of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0247] Reference Figure 30 to Figure 32 , first to fourth mold fin patterns FMS1 , FMS2 , FMS3 , and FMS4 may be formed on the first substrate 100 .

[0248] Each of the first to fourth mold fin patterns FMS1 , FMS2 , FMS3 , and FMS4 may extend mainly in the first direction D1 . The first to fourth mold fin patterns FMS1 , FMS2 , FMS3 , and FMS4 may be spaced apart from each other in the second direction D2 .

[0249] The first molded fin pattern FMS1 and the second molded fin pattern FMS2 may be isolated by a channel trench CH_T extending mainly in the first direction D1. The third molded fin pattern FMS3 and the fourth molded fin pattern FMS4 may be isolated by a channel trench CH_T extending mainly in the first direction D1. The first molded fin pattern FMS1 and the third molded fin pattern FMS3 may be isolated by a fin trench FT extending mainly in the first direction D1.

[0250] Two molded fin patterns may be formed between adjacent fin trenches FT in the second direction D2. The two molded fin patterns formed between the fin trenches FT may be isolated by the channel trench CH_T. The bottom surface of the channel trench CH_T is shown as being higher than the bottom surface of the fin trench FT, but is not necessarily limited thereto. Unlike the example shown, the bottom surface of the channel trench CH_T may be at the same height level as the bottom surface of the fin trench FT.

[0251] The first molded fin pattern FMS1 may include a first lower pattern BP1 and a first upper pattern structure UP1. The second molded fin pattern FMS2 may include a second lower pattern BP2 and a second upper pattern structure UP2. The third molded fin pattern FMS3 may include a third lower pattern BP3 and a third upper pattern structure UP3. The fourth molded fin pattern FMS4 may include a fourth lower pattern BP4 and a fourth upper pattern structure UP4. The first to fourth upper pattern structures UP1, UP2, UP3, and UP4 are formed on the first to fourth lower patterns BP1, BP2, BP3, and BP4.

[0252] Each of the first to fourth upper pattern structures UP1, UP2, UP3, and UP4 may include a plurality of sacrificial patterns SC_L and a plurality of active patterns ACT_L alternately stacked. For example, the active pattern ACT_L may include a silicon layer. The sacrificial pattern SC_L may include a silicon germanium layer.

[0253] In the first to fourth upper pattern structures UP1, UP2, UP3, and UP4, a sacrificial pattern SC_L may be disposed on the uppermost portion. For example, the sacrificial pattern SC_L disposed on the uppermost portion may be the uppermost sacrificial pattern. The thickness of the uppermost sacrificial pattern SC_L is greater than that of other sacrificial patterns SC_L.

[0254] A mold hard mask pattern F_HM may be disposed on each of the first to fourth mold fin patterns FMS1, FMS2, FMS3, and FMS4. The mold hard mask pattern F_HM may be used as a mask for forming the first to fourth mold fin patterns FMS1, FMS2, FMS3, and FMS4. For example, the mold hard mask pattern F_HM may include silicon nitride, but is not necessarily limited thereto.

[0255] Reference Figure 33 to Figure 35 , a lower trench isolation structure CCW_L is formed on the first substrate 100 .

[0256] A lower trench isolation structure CCW_L is formed in the trench CH_T. The lower trench isolation structure CCW_L may fill the trench CH_T.

[0257] While forming the lower trench isolation structure CCW_L, the mold hard mask pattern F_HM may be removed. The upper surfaces of the first to fourth upper pattern structures UP1, UP2, UP3, and UP4 may be exposed. For example, the upper surface of the lower trench isolation structure CCW_L may be on the same plane as the upper surfaces of the first to fourth mold fin patterns FMS1, FMS2, FMS3, and FMS4.

[0258] Since the lower channel isolation structure CCW_L is formed in the channel trench CH_T, variations in widths of the first to fourth sheet patterns NS1 , NS2 , NS3 , and NS4 formed by the first to fourth upper pattern structures UP1 , UP2 , UP3 , and UP4 may be minimized.

[0259] In addition, since the lower channel isolation structure CCW_L does not protrude more than the first to fourth molded fin patterns FMS1, FMS2, FMS3, and FMS4, the constraints of subsequent manufacturing processes can be reduced. Figures 38 to 41 ), a skirt structure, etc. may not be formed by the dummy gate electrode 120P. For example, process defects that may occur due to the skirt structure, etc. may be reduced or eliminated.

[0260] The lower trench isolation structure CCW_L can be formed at the same time Fig.17 The field insulation line pattern 105DP. Figure 4 The first region CCW1_R1 of the first trench isolation structure and Fig. 9 The first portion CCW1_R21 of the second region of the first trench isolation structure may be formed of the lower trench isolation structure CCW_L.

[0261] Reference Fig.36 and Fig.37, a field insulating layer 105 may be formed on the first substrate 100 .

[0262] The field insulation layer 105 may fill a portion of the fin trench FT.

[0263] Reference Figures 38 to 41 , a plurality of dummy gate electrodes 120P may be formed on the first to fourth mold fin patterns FMS1 , FMS2 , FMS3 , and FMS4 .

[0264] A plurality of dummy gate electrodes 120P may be formed on the lower channel isolation structure CCW_L.

[0265] Each of the plurality of dummy gate electrodes 120P may extend mainly in the second direction D2. The respective dummy gate electrodes 120P may be spaced apart in the first direction D1.

[0266] Each of the plurality of dummy gate electrodes 120P may intersect the first to fourth mold fin patterns FMS1 , FMS2 , FMS3 , and FMS4 . Each of the plurality of dummy gate electrodes 120P may intersect the lower channel isolation structure CCW_L.

[0267] For example, the pre-dummy gate insulating layer 130PP may be formed on the first to fourth mold fin patterns FMS1 , FMS2 , FMS3 , and FMS4 , and may be formed along contours of the first to fourth mold fin patterns FMS1 , FMS2 , FMS3 , and FMS4 that protrude more than the field insulating layer 105 .

[0268] For example, the pre-dummy gate insulating layer 130PP may be formed using an oxidation process for oxidizing a semiconductor material. The pre-dummy gate insulating layer 130PP is not formed on the lower channel isolation structure CCW_L.

[0269] Subsequently, a plurality of dummy gate electrodes 120P may be formed on the pre-dummy gate insulating layer 130PP. The dummy gate electrodes 120P may be formed using the dummy gate capping layer 120HM as a mask. When forming the dummy gate electrodes 120P, the pre-dummy gate insulating layer 130PP may not be removed.

[0270] The dummy gate electrode 120P may include, for example, polysilicon, but the present disclosure is not necessarily limited thereto. The dummy gate capping layer 120_HM may include, for example, silicon nitride, but the present disclosure is not necessarily limited thereto.

[0271] Reference Fig.42 and Fig.43 , a portion of the pre-dummy gate insulating layer 130PP may be removed to form a dummy gate insulating layer 130P.

[0272] The dummy gate insulating layer 130P is formed between the dummy gate electrode 120P and the first to fourth mold fin patterns FMS1, FMS2, FMS3, and FMS4. The dummy gate insulating layer 130P may be formed by removing the pre-dummy gate insulating layer 130PP exposed between adjacent dummy gate electrodes 120P in the first direction D1.

[0273] While forming the dummy gate insulating layer 130P, a first lower channel isolation structure CCW_L1 may be formed. The first lower channel isolation structure CCW_L1 may be formed by removing a portion of the lower channel isolation structure CCW_L exposed between adjacent dummy gate electrodes 120P. A portion of the lower channel isolation structure CCW_L overlapping the dummy gate electrode 120P in the third direction D3 may not be etched.

[0274] Reference Fig.44 and Fig.45 , after forming the first lower channel isolation structure CCW_L1 , the uppermost sacrificial pattern SC_L exposed between the dummy gate electrodes 120P may be removed.

[0275] The uppermost sacrificial pattern SC_L included in the first to fourth mold fin patterns FMS1 , FMS2 , FMS3 , and FMS4 may be patterned using the dummy gate electrode 120P as a mask.

[0276] Reference Figure 46 to Figure 48 , a dummy gate spacer 140P may be formed on a sidewall of the dummy gate electrode 120P.

[0277] While the dummy gate spacers 140P are formed, first to fourth source / drain recesses 150R, 250R, 350R, and 450R may be formed between the dummy gate electrodes 120P by using the dummy gate electrodes 120P as masks.

[0278] A first source / drain groove 150R may be formed in the first mold fin pattern FMS1. A second source / drain groove 250R may be formed in the second mold fin pattern FMS2. A third source / drain groove 350R may be formed in the third mold fin pattern FMS3. A fourth source / drain groove 450R may be formed in the fourth mold fin pattern FMS4.

[0279] The dummy gate spacer 140P may cover at least a portion of a sidewall of the patterned uppermost sacrificial pattern SC_L.

[0280] After removing a portion of the lower trench isolation structure CCW_L exposed between adjacent dummy gate electrodes 120P, the first to fourth source / drain recesses 150R, 250R, 350R, and 450R may be formed. For example, after forming the first lower trench isolation structure CCW_L1, the first to fourth source / drain recesses 150R, 250R, 350R, and 450R may be formed.

[0281] While forming the first to fourth source / drain recesses 150R, 250R, 350R, and 450R, a second lower channel isolation structure CCW_L2 may be formed. The second lower channel isolation structure CCW_L2 may be formed by removing a portion of the first lower channel isolation structure CCW_L1 exposed between adjacent dummy gate electrodes 120P. The portion of the first lower channel isolation structure CCW_L1 overlapping the dummy gate electrode 120P in the third direction D3 may not be etched. For example, in Fig.48 In the cross-sectional view of FIG. 1 , an upper surface of the second lower trench isolation structure CCW_L2 is lower than an upper surface of the active pattern ACT_L disposed on the uppermost portion.

[0282] along Fig.46 The cross-sectional view taken along line CC can be compared with Fig.40 The cross-sectional views are the same.

[0283] Reference Fig.49 and Fig.50 , a sacrificial insulating layer 50 may be formed on the first substrate 100 .

[0284] The sacrificial insulating layer 50 may fill the first to fourth source / drain recesses 150R, 250R, 350R, and 450R. The sacrificial insulating layer 50 may fill the space between the dummy gate electrodes 120P. The sacrificial insulating layer 50 may be formed to reach the upper surface of the dummy gate capping layer 120HM.

[0285] Subsequently, an upper channel isolation structure CCW_U is formed on the second lower channel isolation structure CCW_L2. The upper channel isolation structure CCW_U may be formed between adjacent dummy gate electrodes 120P along the first direction D1. After forming the first to fourth source / drain grooves 150R, 250R, 350R, and 450R, the upper channel isolation structure CCW_U is formed.

[0286] Fig. 9 The second portion CCW1_R22 of the second region of the first trench isolation structure may be formed by the upper trench isolation structure CCW_U.

[0287] Reference Figure 51 to Figure 53 , remove the sacrificial insulating layer 50.

[0288] Thus, the first to fourth source / drain recesses 150R, 250R, 350R, and 450R may be exposed. For example, the first to fourth upper pattern structures UP1, UP2, UP3, and UP4 may be exposed.

[0289] A first source / drain pattern 150 may be formed in the first source / drain groove 150R. The first source / drain pattern 150 may be formed on the first lower pattern BP1. A second source / drain pattern 250 may be formed in the second source / drain groove 250R. The second source / drain pattern 250 may be formed on the second lower pattern BP2. A third source / drain pattern 350 may be formed in the third source / drain groove 350R. The third source / drain pattern 350 may be formed on the third lower pattern BP3. A fourth source / drain pattern 450 may be formed in the fourth source / drain groove 450R. The fourth source / drain pattern 450 may be formed on the fourth lower pattern BP4.

[0290] Each of the first to fourth source / drain patterns 150 , 250 , 350 , and 450 may be in contact with the upper channel isolation structure CCW_U and the second lower channel isolation structure CCW_L2 .

[0291] Subsequently, a source / drain etch stop layer 185 and an upper interlayer insulating layer 190 may be formed on the source / drain patterns 150, 250, 350, and 450. While forming the source / drain etch stop layer 185 and the upper interlayer insulating layer 190, the dummy gate capping layer 120HM may be removed. The dummy gate electrode 120P may be exposed.

[0292] Reference Fig.54 and Fig.55 , the gate trench 120t may be formed by removing the dummy gate electrode 120P and the dummy gate insulating layer 130P.

[0293] The gate trench 120t may expose the first to fourth upper pattern structures UP1, UP2, UP3, and UP4. The gate trench 120t may extend mainly in the second direction D2.

[0294] Reference Fig.56 and Fig.57 , a first sheet pattern NS1 contacting the second lower channel isolation structure CCW_L2 and the first source / drain pattern 150 may be formed by removing the sacrificial pattern SC_L of the first upper pattern structure UP1 exposed by the gate trench 120 t .

[0295] The second sheet pattern NS2 contacting the second lower channel isolation structure CCW_L2 and the second source / drain pattern 250 may be formed by removing the sacrificial pattern SC_L of the second upper pattern structure UP2 exposed by the gate trench 120 t .

[0296] The third and fourth sheet patterns NS3 and NS4 may be formed by removing the sacrificial patterns SC_L of the third and fourth upper pattern structures UP3 and UP4 exposed by the gate trenches 120t. The third and fourth sheet patterns NS3 and NS4 may contact the second lower channel isolation structure CCW_L2.

[0297] Reference Fig.58 and Fig.59 , a pre-gate electrode 120PR and a pre-gate insulating layer 130PR may be formed in the gate trench 120t.

[0298] The pre-gate electrode 120PR may intersect the first to fourth patterns NS1, NS2, NS3, and NS4. The pre-gate electrode 120PR may cover the upper surface of the second lower trench isolation structure CCW_L2. The upper surface of the pre-gate electrode 120PR may be on the same plane as the upper surface of the upper trench isolation structure CCW_U (see Fig.53 ).

[0299] exist Figures 2 to 5 In the embodiment, the first to fourth gate structures GS1, GS2, GS3 and GS4 can be formed by removing a portion of the pre-gate electrode 120PR and the pre-gate insulating layer 130PR. The pre-gate electrode 120PR and the pre-gate insulating layer 130PR can be etched until the upper surface of the second lower channel isolation structure CCW_L2 is exposed. Therefore, the first to fourth gate structures GS1, GS2, GS3 and GS4 can be formed. The first gate covering pattern 145 and the second gate covering pattern 345 can be formed on the first to fourth gate structures GS1, GS2, GS3 and GS4.

[0300] and Fig.31 and Fig.32 Different from those shown in FIG. 1 , each of the first to fourth mold fin patterns FMS1, FMS2, FMS3, and FMS4 may further include a lower buffer pattern formed between the first to fourth lower patterns BP1, BP2, BP3, and BP4 and the first to fourth upper pattern structures UP1, UP2, UP3, and UP4.

[0301] The lower buffer pattern may include a material having an etching selectivity relative to the active pattern ACT_L and the sacrificial pattern SC_L. For example, the sacrificial pattern SC_L may include a silicon germanium layer doped with carbon, and the lower buffer pattern may include a silicon germanium layer. For example, the sacrificial pattern SC_L may include a silicon germanium layer, and the lower buffer pattern may include a silicon germanium layer doped with carbon. Depending on whether carbon is doped, the etching rate of the silicon germanium layer may vary. For example, the sacrificial pattern SC_L may have an etching selectivity relative to the lower buffer pattern.

[0302] In this case, the reference Figure 46 to Figure 48 The lower buffer pattern is removed before the dummy gate spacer 140P is formed. Subsequently, while forming the dummy gate spacer 140P, a reference retardant may be formed in the space where the lower buffer pattern is removed. Figure 22 to Figure 26 The first to fourth lower insulating patterns BDI1, BDI2, BDI3, and BDI4 are described.

[0303] At the conclusion of the detailed description, it will be appreciated by those skilled in the art that many variations and modifications may be made to the described embodiments without substantially departing from the principles of the inventive concept.

Claims

1. A semiconductor device comprising: a lower pattern extending mainly in the first direction and comprising a first side wall and a second side wall opposite to the first side wall in the second direction; a trench isolation structure extending mainly in a first direction and contacting a first sidewall of the lower pattern; a field insulating layer in contact with the second side wall of the lower pattern; A gate structure, disposed on the lower pattern, the gate structure contacts the trench isolation structure and mainly extends in the second direction; a channel pattern disposed on the lower pattern and including a plurality of sheet patterns spaced apart from each other in a third direction, each of the plurality of sheet patterns being in contact with the trench isolation structure; as well as A source / drain pattern in contact with both the channel pattern and the channel isolation structure, The trench isolation structure includes a first region in contact with the gate structure and a second region in contact with the source / drain pattern. The second region of the trench isolation structure includes a first portion and a second portion, and widths of the first portion and the second portion increase in the second direction as the distance from the bottom surface of the field insulation layer increases. wherein the second portion of the second region of the trench isolation structure is disposed on the first portion of the second region of the trench isolation structure, and The width of the uppermost portion of the trench isolation structure in the first portion of the second region of the trench isolation structure is greater than the width of the lowermost portion of the trench isolation structure in the second portion of the second region of the trench isolation structure.

2. The semiconductor device according to claim 1, wherein The second region of the trench isolation structure further includes: a third portion disposed between the first portion of the second region of the trench isolation structure and the second portion of the second region of the trench isolation structure, and In the third portion of the second region of the trench isolation structure, the width of the trench isolation structure in the second direction decreases as the distance from the bottom surface of the field insulation layer increases.

3. The semiconductor device according to claim 1, wherein In the first region of the trench isolation structure, a width of the trench isolation structure in the second direction continuously increases as a distance from a bottom surface of the field insulation layer increases.

4. The semiconductor device according to claim 1, wherein A height from a bottom surface of the field insulation layer to an uppermost portion of the first portion of the second region of the trench isolation structure is smaller than a height from the bottom surface of the field insulation layer to an uppermost portion of the source / drain pattern.

5. The semiconductor device according to claim 4, wherein: A portion of the source / drain pattern overlaps the first portion of the second region of the trench isolation structure in the third direction.

6. The semiconductor device according to claim 1, wherein A height from a bottom surface of the field insulation layer to an uppermost portion of the first portion of the second region of the trench isolation structure is smaller than a height from the bottom surface of the field insulation layer to an upper surface of the channel pattern.

7. The semiconductor device according to claim 1, wherein Each of the first portion of the second region of the trench isolation structure and the second portion of the second region of the trench isolation structure includes a width centerline extending primarily in the third direction, and The width center line of the first portion of the second region of the trench isolation structure is aligned with the width center line of the second portion of the second region of the trench isolation structure in the third direction.

8. The semiconductor device according to claim 1, wherein Each of the first portion of the second region of the trench isolation structure and the second portion of the second region of the trench isolation structure includes a width centerline extending primarily in the third direction, and Wherein, a width center line of the first portion of the second region of the trench isolation structure is spaced apart from a width center line of the second portion of the second region of the trench isolation structure in the second direction.

9. The semiconductor device according to claim 1, further comprising: The lower insulating pattern is disposed between the lower pattern and the channel pattern and contacts an upper surface of the lower pattern.

10. The semiconductor device according to claim 1, wherein A depth from an upper surface of the lower pattern to a lowermost portion of the trench isolation structure is less than or equal to a depth from an upper surface of the lower pattern to a bottom surface of the field insulation layer.

11. The semiconductor device according to claim 1, further comprising: a sacrificial semiconductor pattern and a sacrificial pattern cover layer, wherein the sacrificial semiconductor pattern overlaps the source / drain pattern in the third direction, and The sacrificial pattern covering layer is disposed between the sacrificial semiconductor pattern and the source / drain pattern.

12. The semiconductor device according to claim 1, further comprising: A source / drain etch stop layer, disposed on the source / drain pattern; as well as A source / drain oxide layer is inserted, disposed between the source / drain etch stop layer and the source / drain pattern, and contacts the source / drain pattern.

13. The semiconductor device according to claim 1, further comprising: A source / drain gate is disposed on the field insulating layer and protrudes in a third direction, The source / drain fence is in contact with the source / drain pattern.

14. The semiconductor device according to claim 1, further comprising: a gate isolation structure, disposed on the field insulation layer and mainly extending in a first direction, The gate structure and the source / drain pattern are respectively arranged between the channel isolation structure and the gate isolation structure.

15. A semiconductor device comprising: A first gate structure comprising a first gate electrode and a first gate insulating layer; a second gate structure including a second gate electrode and a second gate insulating layer and spaced apart from the first gate structure in the first direction; a first source / drain pattern disposed adjacent to the first gate structure in the second direction; a second source / drain pattern disposed adjacent to the second gate structure in the second direction and spaced apart from the first source / drain pattern in the first direction; A channel isolation structure is disposed between the first gate structure and the second gate structure and between the first source / drain pattern and the second source / drain pattern, and the channel isolation structure mainly extends in the second direction; a first channel pattern including a plurality of first sheet patterns, each of the plurality of first sheet patterns being in contact with the channel isolation structure and the first source / drain pattern; as well as a second channel pattern, comprising a plurality of second sheet patterns, each of the plurality of second sheet patterns being in contact with the channel isolation structure and the second source / drain pattern, The width of the channel isolation structure between the first gate structure and the second gate structure in the first direction is different from the width of the channel isolation structure between the first source / drain pattern and the second source / drain pattern in the first direction.

16. The semiconductor device according to claim 15, wherein: A width of the trench isolation structure between the first gate structure and the second gate structure in the first direction is greater than a width of the trench isolation structure between the first source / drain pattern and the second source / drain pattern in the first direction.

17. The semiconductor device according to claim 15, wherein: Each of the first gate insulating layer, the second gate insulating layer, the first source / drain pattern, and the second source / drain pattern contacts the channel isolation structure.

18. The semiconductor device according to claim 15, wherein The first source / drain pattern overlaps the trench isolation structure by a first width in the second direction, and The second source / drain pattern overlaps the channel isolation structure in the second direction by a second width, and the second width is different from the first width.

19. A semiconductor device comprising: a lower pattern extending mainly in the first direction and comprising a first side wall and a second side wall opposite to the first side wall in the second direction; a trench isolation structure extending mainly in a first direction and contacting a first sidewall of the lower pattern; a field insulating layer in contact with the second side wall of the lower pattern; A gate isolation structure is disposed on the field insulation layer and mainly extends in a first direction; a gate structure disposed between the trench isolation structure and the gate isolation structure and in contact with each of the trench isolation structure and the gate isolation structure; a channel pattern disposed on the lower pattern and including a plurality of sheet patterns spaced apart from each other in a third direction, each of the plurality of sheet patterns being in contact with the trench isolation structure; as well as a source / drain pattern disposed between the channel isolation structure and the gate isolation structure and contacting each of the channel pattern and the channel isolation structure, Part of the source / drain pattern overlaps the channel isolation structure in the third direction.

20. The semiconductor device according to claim 19, wherein The trench isolation structure includes a first region contacting the gate structure and a second region contacting the source / drain pattern, The second region of the trench isolation structure includes a first portion and a second portion, and widths of the first portion and the second portion increase in the second direction as the distance from the bottom surface of the field insulation layer increases. wherein the second portion of the second region of the trench isolation structure is disposed on the first portion of the second region of the trench isolation structure, and The width of the uppermost portion of the trench isolation structure in the first portion of the second region of the trench isolation structure is greater than the width of the lowermost portion of the trench isolation structure in the second portion of the second region of the trench isolation structure.

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