Semiconductor device

Abstract

A semiconductor device includes: a substrate; an active region extending along a first horizontal direction on the substrate and including a first active pattern at a first height along a vertical direction above a bottom surface of the substrate and having a first width in a second horizontal direction, a second active pattern at a second height along a vertical direction above the bottom surface of the substrate and having a second width in a second horizontal direction; a second active pattern having a second width different from the first width in the second direction, the transition active pattern connecting the first active pattern to the second active pattern; gate structures crossing the active region, each gate structure extending across the substrate in a second direction; and a source / drain region disposed on a side surface of the gate structure and including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a transition source / drain region disposed on the transition active pattern.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0098170 filed in the Korean Intellectual Property Office on July 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the present disclosure relate to a semiconductor device. Background Art

[0003] As the demand for high performance, speed and / or versatility of semiconductor devices increases, the integration of semiconductor devices has also increased. In response to the trend of high integration of semiconductor devices, when manufacturing semiconductor devices with fine patterns, it may be necessary to implement patterns with fine widths or fine intervals. In addition, in order to overcome the limitations of operating characteristics according to the size reduction of planar MOSFETs (metal oxide semiconductor FETs), efforts have been made to develop semiconductor devices including FinFETs with three-dimensional channels. Summary of the invention

[0004] Example embodiments of the present disclosure provide a semiconductor device having improved reliability.

[0005] According to an exemplary embodiment of the present disclosure, a semiconductor device includes: a substrate; an active region, including a first active pattern, a second active pattern, and a transition active pattern, the first active pattern extending along a first horizontal direction on the substrate and having a first width in a second direction horizontally perpendicular to the first direction at a first height along a third vertical direction above a bottom surface of the substrate, the second active pattern extending in the first direction and having a second width along the second direction less than the first width at a first height, the transition active pattern extending in the first direction and connecting the first active pattern to the second active pattern; a gate structure intersecting the active region and extending along the second direction on the substrate; a plurality of groups of channel layers, each group including a channel layer extending in the first direction, the channel layers being arranged in a continuous order from the active region and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, and each group being surrounded by a corresponding gate structure on the active region; and a source / drain region arranged on a side of the gate structure and including a first source / drain region arranged on the first active pattern, a second source / drain region arranged on the second active pattern, and a transition source / drain arranged on the transition active pattern. The active region is symmetrical in a second direction with respect to a central axis of the active region extending in the first direction, each of the source / drain regions is disposed on the active region and includes a first epitaxial layer disposed on a first group of the plurality of channel layers and a second group of the plurality of channel layers and a second epitaxial layer disposed on the first epitaxial layer, at a second height above a bottom surface of the substrate along a third direction, a first sidewall thickness of the first epitaxial layer of the first source / drain region in the first direction is greater than a second sidewall thickness of the first epitaxial layer of the second source / drain region in the first direction, and at the second height, the first epitaxial layer of the transition source / drain region has a first transition sidewall and a second transition sidewall, the first transition sidewall having a first transition sidewall thickness in the first direction, and the second transition sidewall having a second sidewall thickness in the first direction that is less than the first transition sidewall thickness. According to an exemplary embodiment of the present disclosure, a semiconductor device includes: a substrate; an active region extending along a first horizontal direction on the substrate and including a first active pattern, a second active pattern and a transition active pattern, the first active pattern having a first width at a first height in a vertical direction above a bottom surface of the substrate and in a second horizontal direction, the second active pattern having a second width different from the first width in the second direction, and the transition active pattern connecting the first active pattern to the second active pattern; a gate structure intersecting the active region, each gate structure extending across the substrate in the second direction; and a source / drain region arranged on a side of the gate structure and including a first source / drain region arranged on the first active pattern, a second source / drain region arranged on the second active pattern, and a transition source / drain region arranged on the transition active pattern. Each of the source / drain regions is arranged on the active region and includes a first epitaxial layer having a recessed upper surface and a second epitaxial layer arranged on the first epitaxial layer, at a second height in the vertical direction above the bottom surface of the substrate, a first sidewall thickness of the first epitaxial layer of the first source / drain region in the first direction is different from a second sidewall thickness of the first epitaxial layer of the second source / drain region in the first direction, at the second height, relative sidewall thicknesses of the first epitaxial layer of the transition source / drain region in the first direction are different, and a vertical level of a lowermost end of the second epitaxial layer of the first source / drain region, a vertical level of a lowermost end of the second epitaxial layer of the second source / drain region, and a vertical level of a lowermost end of the second epitaxial layer of the transition source / drain region are different from each other.

[0006] According to an exemplary embodiment of the present disclosure, a semiconductor device includes: a substrate; an active region extending along a first direction on the substrate and including a first active pattern, a second active pattern and a transition active pattern, the first active pattern having a first width in a second direction intersecting the first direction, the second active pattern having a second width smaller than the first width in the second direction, and the transition active pattern connecting the first active pattern to the second active pattern; a gate structure intersecting the active region on the substrate and extending in the second direction; a plurality of channel layer groups, each group including channel layers extending in the first direction, the channel layers being arranged in a continuous order from the active region and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, and each group being surrounded by a corresponding gate structure on the active region, the plurality of channel layer groups being arranged spaced apart from each other in the first direction; and a source / drain region disposed between gate structures adjacent to each other in the first direction and including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a transition source / drain region disposed on the transition active pattern. Each of the source / drain regions is arranged on the active region and includes a first epitaxial layer arranged between adjacent groups of the plurality of channel layers and a second epitaxial layer arranged on the first epitaxial layer, and at a first vertical height above the bottom surface of the substrate, the transition source / drain region has a first transition sidewall thickness of the first epitaxial layer of the transition source / drain region in the first direction and a second transition sidewall thickness in the first direction that is smaller than the first transition sidewall thickness, and a vertical level of a lowermost end of the second epitaxial layer of the transition source / drain region is higher than a vertical level of a lowermost end of the second epitaxial layer of the first source / drain region and lower than a vertical level of a lowermost end of the second epitaxial layer of the second source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure; FIG. 2A to FIG. 2C is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure; Figure 3 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure; Figure 4 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure; Figure 5 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure; Fig. 6Ais a plan view showing a semiconductor device according to an example embodiment of the present disclosure; Figure 6B is a plan view showing a semiconductor device according to an example embodiment of the present disclosure; Fig. 7A is a plan view showing a semiconductor device according to an example embodiment of the present disclosure; Figure 7B is a plan view showing a semiconductor device according to an example embodiment of the present disclosure; Figure 8 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure; and 9A to 9C , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B , FIG. 14A to FIG. 14B , FIG. 15A to FIG. 15C as well as Fig.16 is a diagram illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0008] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0009] Figure 1 is a plan view showing a semiconductor device according to an example embodiment. As used herein, a semiconductor device may refer to, for example, a device such as a semiconductor chip (e.g., a memory chip and / or a logic chip formed on a die), a semiconductor chip stack, a semiconductor package including one or more semiconductor chips stacked on a packaging substrate, or a stacked package including multiple packages. These devices may be formed using a ball grid array, wire bonding, through-substrate vias, or other electrical connection elements, and may include a memory device (such as a volatile memory device or a non-volatile memory device). The semiconductor package may include a packaging substrate, one or more semiconductor chips, and an encapsulation formed on the packaging substrate and covering the semiconductor chip. The semiconductor device disclosed in various embodiments herein includes a gate-all-around type transistor, also described as a nanosheet transistor, which includes a channel region fully surrounded by a gate or a channel region of a nanosheet.

[0010] FIG. 2A to FIG. 2C is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 2A Shows a view taken along line II' Figure 1 Cross-sectional surface of a semiconductor device in FIG. Figure 2B The diagrams taken along lines II1-II1', II2-II2' and II3-II3' are shown. Figure 1A cross section of a semiconductor device shown in FIG. Figure 2C The diagrams taken along lines III1-III1', III2-III2' and III3-III3' are shown. Figure 1 For ease of description, Figure 1 Only a portion of the components of the semiconductor device are shown.

[0011] Reference Figures 1 to 2C , the semiconductor device 100 may include: a substrate 101; an active region 105 including a first active pattern 105A, a second active pattern 105B, and a transition active pattern 105T; gate structures 160 extending by crossing the active region 105 and each including a gate electrode 165; a channel structure 140 including first to fourth channel layers 141, 142, 143, and 144 vertically disposed on the active region 105 and spaced apart from each other; a source / drain region 150 contacting the channel structure 140; and a contact plug 180 connected to the source / drain region 150. The semiconductor device 100 may also include a device isolation layer 110, a gate dielectric layer 162, a gate spacer layer 164, a gate capping layer 166, and an interlayer insulating layer 190.

[0012] In the semiconductor device 100, the active region 105 may have a fin structure, and the gate electrode 165 may be disposed between the active region 105 and the channel structure 140, between the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140, and on the channel structure 140. Therefore, the semiconductor device 100 may include a multi-bridge channel FET structure (MBCFET) as a gate-all-around field effect transistor. TM ) transistor.

[0013] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material (such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor), or be formed of a semiconductor material (such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor). For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0014] The substrate 101 may include an active region 105 disposed in an upper portion of the substrate 101. The active region 105 may be defined by a device isolation layer 110 in the substrate 101 and may be disposed to extend longitudinally in a first direction (e.g., an X direction). An object, layer, or portion of an object or layer described as extending "longitudinally" in a particular direction has a length in the particular direction and a width perpendicular to the particular direction, wherein the length is greater than the width. In some examples, the active region 105 may be described as a component separate from the substrate 101.

[0015] The active region 105 may include a first active pattern 105A extending in a first direction (e.g., X direction) on the substrate 101 and having a first width Wa in a second direction (e.g., Y direction), a second active pattern 105B having a second width Wb different from the first width Wa in the second direction, and a transition active pattern 105T connecting the first active pattern 105A to the second active pattern 105B. The first width Wa and the second width Wb may refer to the width of each active pattern at a specific vertical level (e.g., at a specific height above the bottom surface of the substrate), FIG. 2A to FIG. 2C , but the embodiment is not limited thereto. In an example embodiment, at a specific vertical level, the second width Wb may be less than the first width Wa. The transition active pattern 105T may provide non-parallel opposite side surfaces, and the width along the second direction (e.g., the Y direction) at a specific vertical level may change along the first direction (e.g., the X direction) according to different portions of the non-parallel opposite side surfaces. Each of the first active pattern 105A and the second active pattern 105B may have a constant width at a specific vertical level, while the width Wt of the transition active pattern 105T in the second direction (e.g., the Y direction) at a specific vertical level may gradually decrease or increase along the first direction (e.g., the X direction).

[0016] The active region 105 may partially protrude from the device isolation layer 110, and the upper surface of the active region 105 may be disposed at a level higher than that of the upper surface of the device isolation layer 110. The upper surface of the active region 105 may have a downwardly curved shape. In example embodiments, the upper surface of each of the first active pattern 105A, the second active pattern 105B, and the transition active pattern 105T may have a downwardly curved shape (e.g., a concave shape). The active region 105 may include a portion of the substrate 101 (e.g., formed by etching other portions of the substrate), or may include an epitaxial layer grown from the substrate 101. In either case, the active region 105 is disposed with the substrate 101. The active region 105 may be partially recessed into both sides of the gate structure 160, and a recessed region may be formed, and the source / drain region 150 may be disposed in the recessed region. The source / drain regions 150 may extend from a lower surface of the interlayer insulating layer 190 disposed between the gate structures 160 , and may be disposed within the active region 105 .

[0017] In example embodiments, the active region 105 may or may not include a well region including impurities. For example, in the case of a P-type transistor (PFET), the well region may include N-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb), and in the case of an N-type transistor (nFET), the well region may include P-type impurities such as boron (B), gallium (Ga), or indium (In). For example, the well region may be disposed at a predetermined depth from an upper surface of the active region 105.

[0018] In example embodiments, the active region 105 may be symmetrical in a second direction (eg, Y direction) with respect to a central axis CL extending in a first direction (eg, X direction) of the active region 105. This structure has an effect of preventing contact between the second epitaxial layer 152 and the gate structure 160, so that a semiconductor device having improved electrical characteristics and reliability may be provided.

[0019] The device isolation layer 110 may define the active region 105 in the substrate 101. The device isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. The device isolation layer 110 may expose the upper surface of the active region 105 and may partially expose the upper portion of the active region 105. Although not shown, in some example embodiments, the device isolation layer 110 may have a wavy upper surface so that its level may increase toward the active region 105. The device isolation layer 110 may be formed of an insulating material. The device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0020] The gate structure 160 may be disposed to intersect the active region 105 and the channel structure 140, and extend in a second direction (e.g., Y direction) on the active region 105 and the channel structure 140. A functional channel region of the transistor may be formed in the active region 105 and / or the channel structure 140 intersecting the gate electrode 165 of the gate structure 160. Each of the gate structures 160 may include a gate electrode 165, a gate dielectric layer 162 between the gate electrode 165 and the first to fourth channel layers 141, 142, 143, and 144, and a gate spacer layer 164 on a side surface of the gate electrode 165. In example embodiments, each of the gate structures 160 may further include a gate capping layer 166 on an upper surface of the gate electrode 165.

[0021] The gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165 and between the channel structure 140 and the gate electrode 165, and may be disposed to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may be disposed to surround the entire surface of the gate electrode 165 except for the upper surface. The gate dielectric layer 162 may extend to a region between the gate electrode 165 and the gate spacer layer 164, but example embodiments thereof are not limited thereto. The gate dielectric layer 162 may include or be formed of an oxide, a nitride, or a high-κ material. The high-κ material may refer to a material having a higher κ than silicon oxide (SiO 2 ) of dielectric materials with a high dielectric constant. The high κ material can be, for example, aluminum oxide (Al 2 O 3 )、Tantalum oxide(Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 )、ZrO2 silicon(ZrSi x O y )、HfO 2 )、HfSiO x O y )、Lanthanum oxide(La 2 O 3 )、Lanthanum Aluminum Oxide(LaAl x O y ), lanthanum hafnium oxide (LaHf x O y )、HfAl x O y ) and praseodymium oxide (Pr 2 O 3 ). In example embodiments, the gate dielectric layer 162 may be formed of a multi-layer film.

[0022] The gate electrode 165 may fill the space between the first to fourth channel layers 141, 142, 143, and 144 on the active region 105, and may extend to the active region 105. The gate electrode 165 may be spaced apart from the first to fourth channel layers 141, 142, 143, and 144 by the gate dielectric layer 162. The gate electrode 165 may include, for example, a metal nitride (such as a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film) and / or a metal material (such as aluminum (Al), tungsten (W), or molybdenum (Mo)) or a conductive material or a semiconductor material (such as doped polysilicon) or be formed of, for example, a metal nitride (such as a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film) and / or a metal material (such as aluminum (Al), tungsten (W), or molybdenum (Mo)) or a conductive material or a semiconductor material (such as doped polysilicon). In example embodiments, the gate electrode 165 may include two or more multilayers.

[0023] The gate spacer layer 164 may be disposed on both side surfaces (e.g., opposite side surfaces) of the gate electrode 165 on the channel structure 140. The gate spacer layer 164 may insulate the source / drain region 150 from the gate electrode 165. In example embodiments, the gate spacer layer 164 may have a multi-layer structure. The gate spacer layer 164 may be formed of oxide, nitride, and oxynitride, and may be formed of a low-κ film in some embodiments.

[0024] The gate capping layer 166 may be disposed on the gate electrode 165 , and a bottom surface thereof may be surrounded (eg, covered) by the gate electrode 165 and the gate spacer layer 164 .

[0025] The channel structure 140 may be disposed on the active region 105 in a region where the active region 105 intersects the gate structure 160. Each of the channel structures 140 may include first to fourth channel layers 141, 142, 143, and 144, which are a plurality of channel layers spaced apart from each other in a third direction (e.g., Z direction or vertical direction) perpendicular to the upper surface of the substrate 101. The first to fourth channel layers 141, 142, 143, and 144 may be disposed in sequence from the active region 105. For example, a plurality of groups of channel layers, each group including a channel layer extending in a first direction (e.g., a first channel layer 141, a second channel layer 142, a third channel layer 143, and a fourth channel layer 144) may be disposed in a continuous order from the active region 105 and spaced apart from each other in a third direction (e.g., Z direction). Each group of channel layers may be surrounded by a corresponding gate structure 160 on the active region 105. The channel structure 140 may be connected to the source / drain region 150. The channel structure 140 may have a width in the X direction that is equal to or similar to that of the gate structure 160, and may have a width in the Y direction that is equal to or less than that of the active region 105. On a cross-sectional surface along the Y direction, a width of a channel layer disposed in a lower portion among the first to fourth channel layers 141, 142, 143, and 144 may be equal to or greater than a width of a channel layer disposed in an upper portion.

[0026] In example embodiments, the plurality of channel layers 141, 142, 143, and 144 disposed on the first active pattern 105A may have a first channel width (or, referred to as “a width of the first group”) CHa in the second direction (e.g., the Y direction), the plurality of channel layers 141, 142, 143, and 144 disposed on the second active pattern 105B may have a second channel width (or, referred to as “a width of the second group”) CHb in the second direction (e.g., the Y direction) that is smaller than the first channel width CHa, and the plurality of channel layers 141, 142, 143, and 144 disposed on the transition active pattern 105T may have a transition channel width (or, referred to as “a width of the third group”) CHt in the second direction (e.g., the Y direction) that is smaller than the first channel width CHa and larger than the second channel width CHb. For example, for any given vertical level (e.g., height above the bottom surface of the substrate 101), the width of the channel layer disposed on the first active pattern 105A in the second direction (e.g., Y direction) may be greater than the width of the channel layer disposed on the second active pattern 105B in the second direction (e.g., Y direction), and the width of the channel layer disposed on the transition active pattern 105T in the second direction (e.g., Y direction) may be greater than the width of the channel layer disposed on the second active pattern 105B in the second direction (e.g., Y direction) and less than the width of the channel layer disposed on the first active pattern 105A in the second direction (e.g., Y direction). In other words, each group of channel layers disposed on the first active pattern 105A may include a continuously ordered sequence of channel layers having a first group of widths, each group of channel layers disposed on the second active pattern 105B may include a continuously ordered sequence of channel layers having a second group of widths in the second direction, and each width of the second group of widths is less than a corresponding width in the first group of widths. In a plan view, each of the width CHa of the first channel and the width CHb of the second channel may have a constant width, while the width CHt of the transition channel may gradually increase or decrease along the first direction (eg, the X direction). In one embodiment, each group of channel layers disposed on the transition active pattern 105T may include channel layers sequentially ordered with a third group of widths in the second direction, each width of the third group of widths being smaller than a corresponding width in the first group of widths and larger than a corresponding width in the second group of widths.

[0027] In example embodiments, the number of channel layers included in the channel structure 140 and the shapes thereof may vary. Figure 2A As shown in FIG. 1 , the side surfaces of the first to third channel layers 141, 142, and 143 in the X direction may have an outwardly curved shape, and the uppermost fourth channel layer 144 may have an inclined side surface so that its width may decrease toward the active region 105. Figure 2BAs shown in , the channel structure 140 may have a shape in which the width of the channel layer close to the active region 105 in the X direction may be increased (e.g., compared to the width of the adjacent channel layer far from the active region 105 in the X direction). At least one of the first to fourth channel layers 141, 142, 143, and 144 may have a reduced width so that its side surface may be disposed below the gate structure 160 in the X direction (e.g., to vertically overlap with at least one of the gate structures 160). However, in example embodiments, the shapes and relative widths of the side surfaces of the first to fourth channel layers 141, 142, 143, and 144 may vary and are not limited to FIG. 2A to FIG. 2C For example, in some example embodiments, the first to fourth channel layers 141 , 142 , 143 , and 144 may have side surfaces vertically extending in a third direction (eg, Z direction).

[0028] The channel structure 140 may be formed of a semiconductor material, and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). For example, the channel structure 140 may be formed of the same material as that of the active region 105. In some example embodiments, the channel structure 140 may include an impurity region disposed in a region adjacent to the source / drain region 150.

[0029] The source / drain region 150 may be disposed in a recessed region partially recessed into an upper portion of the active region 105 on opposite sides of the gate structure 160 in the X direction. The source / drain region 150 may be disposed to cover the side surface of each of the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140 in the X direction. The uppermost surface of the source / drain region 150 may be disposed at the same level or a similar level to the lower surface of the gate electrode 165 on the channel structure 140, and the level may vary in example embodiments. The source / drain region 150 may include or be formed of at least one semiconductor material (e.g., silicon (Si) and / or germanium (Ge)), and may further include impurities.

[0030] In example embodiments, the source / drain region 150 may include a first source / drain region 150A disposed on the first active pattern 105A, a second source / drain region 150B disposed on the second active pattern 105B, and a transitional source / drain region 150T disposed on the transitional active pattern 105T.

[0031] Each of the source / drain regions 150 may include a first epitaxial layer 151 and a second epitaxial layer 152 disposed on the first epitaxial layer 151. According to another example embodiment, the source / drain regions 150 may further include a plurality of epitaxial layers in addition to the first and second epitaxial layers 151 and 152.

[0032] For each set of the first to fourth channel layers 141, 142, 143, and 144, the first epitaxial layer 151 may cover the side surfaces of the first to fourth channel layers 141, 142, 143, and 144 in the X direction, and may cover the side surface of the gate structure 160 formed below and around the channel structure 140 in the X direction. The first epitaxial layer 151 may cover the inner side surface and the bottom surface of the recessed region in which the source / drain region 150 is provided, and may extend as an integral layer in the source / drain region 150. The first epitaxial layer 151 may have a side surface protruding curvedly toward the gate structure 160 below each channel layer 141, 142, 143, and 144, and thus, the side surface of the first epitaxial layer 151 may have a curve. The entire surface of the first epitaxial layer 151 contacting the side of the stack of the alternating channel structure 140 may have a wavy shape (also described as a concave-convex shape). During the manufacturing process, due to the gate spacer layer 164 of the gate structure 160, the first epitaxial layer 151 can be grown to a relatively small thickness on the side surface of the fourth channel layer 144. In a plan view, the outer side surface of at least a portion of the first epitaxial layer 151 and the second epitaxial layer 152 can be a facet (or end face, facet) along the crystal plane, but its example embodiment is not limited to this. The source / drain region 150 is not limited to the shape shown. Depending on whether the source / drain region 150 is an N-type transistor or a P-type transistor, the source / drain region 150 can be formed of different materials or can have different shapes. The cross-sectional surface of the source / drain region 150 in the second direction (e.g., the Y direction) can have a pentagonal shape, a hexagonal shape, or a polygonal shape with a gentle angle, but its example embodiment is not limited to this.

[0033] Since the first epitaxial layer 151 is formed by epitaxial growth from the sidewalls of the plurality of channel layers 141, 142, 143, and 144, the thickness of the sidewalls of the first epitaxial layer 151 may be determined by the widths of the plurality of channel layers 141, 142, 143, and 144 in the second direction (eg, the Y direction). Figure 2AAs shown in , at a specific vertical level, a thickness Ta of a first sidewall of the first epitaxial layer 151 of the first source / drain region 150A in a first direction (e.g., X direction) may be different from a thickness Tb of a second sidewall of the first epitaxial layer 151 of the second source / drain region 150B in the first direction (e.g., X direction). In example embodiments, since a width CHa of the first channel may be greater than a width CHb of the second channel, at the specific vertical level, a thickness Ta of a first sidewall of the first epitaxial layer 151 of the first source / drain region 150A along the first direction (e.g., X direction) may be greater than a thickness Tb of a second sidewall of the first epitaxial layer 151 of the second source / drain region 150B along the first direction (e.g., X direction).

[0034] like Figure 1 As shown in FIG. 1 , since the widths of the plurality of channel layers 141, 142, 143, and 144 contacting both side surfaces of the transition source / drain region 150T in the second direction (eg, the Y direction) may be different, as shown in FIG. Figure 2A As shown in , the thicknesses of the opposite sidewalls of the first epitaxial layer 151 of the transitional source / drain region 150T in the first direction (e.g., the X direction) may be different at any particular vertical level. In example embodiments, at a particular vertical level, the transitional source / drain region 150T may have a thickness Tt1 of the first transitional sidewall along the first epitaxial layer 151 of the transitional source / drain region 150T in the first direction (e.g., the X direction) and a thickness Tt2 of the second transitional sidewall that is less than the thickness Tt1 of the first transitional sidewall. In one embodiment, this is because the width CHa of the first channel may be greater than the width CHb of the second channel. In example embodiments, the thickness Ta of the first sidewall may be substantially equal to the thickness Tt1 of the first transitional sidewall, and the thickness Tb of the second sidewall may be substantially equal to the thickness Tt2 of the second transitional sidewall, but example embodiments thereof are not limited thereto.

[0035] The second epitaxial layer 152 may cover the first epitaxial layer 151 and may fill the recessed region. The second epitaxial layer 152 may be surrounded by the first epitaxial layer 151 except for the upper surface of the second epitaxial layer 152. At certain heights, the widths Pa, Pb, Pt of the second epitaxial layer 152 between adjacent first epitaxial layers 151 along the X direction may be greater than the corresponding thicknesses Ta, Tb, Tt1, Tt2 of each of the first epitaxial layers 151 at the sidewalls. In example embodiments, at a certain height, the width Pt of the second epitaxial layer 152 of the transition source / drain region 150T along the first direction (e.g., X direction) may be greater than the width Pa of the second epitaxial layer 152 of the first source / drain region 150A along the first direction (e.g., X direction), and may be less than the width Pb of the second epitaxial layer 152 of the second source / drain region 150B along the first direction (e.g., X direction).

[0036] The second epitaxial layer 152 may include or be formed of the same material as the first epitaxial layer 151, but the composition and / or doping concentration of the second epitaxial layer 152 may be different from the composition and / or doping concentration of the first epitaxial layer 151. When the semiconductor device 100 is a pFET, the source / drain region 150 may include silicon germanium (SiGe), and the concentration of germanium (Ge) of the second epitaxial layer 152 may be higher than the concentration of germanium (Ge) of the first epitaxial layer 151. For example, the concentration of germanium (Ge) of the first epitaxial layer 151 may be in the range of about 1 at% to about 15 at%, and the concentration of germanium (Ge) of the second epitaxial layer 152 may be in the range of about 20 at% to about 100 at%. In addition, the second epitaxial layer 152 may have an impurity doping concentration higher than that of the first epitaxial layer 151. When the semiconductor device 100 is a pFET, the impurity may be at least one of boron (B), gallium (Ga), and indium (In), and when the semiconductor device 100 is an nFET, the impurity may be phosphorus (P), arsenic (As), and antimony (Sb). Therefore, according to these various embodiments, the first epitaxial layer 151 has a different material composition from the second epitaxial layer 152.

[0037] In example embodiments, on a cross-sectional surface viewed along a first direction (e.g., X direction), a level La (e.g., vertical height) of a lowermost end of the second epitaxial layer 152 of the first source / drain region 150A, a level Lb (e.g., vertical height) of a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B, and a level Lt (e.g., vertical height) of a lowermost end of the second epitaxial layer 152 of the transitional source / drain region 150T may be different. For example, on a cross-sectional surface in the first direction (e.g., X direction), a level Lt of a lowermost end of the second epitaxial layer 152 of the transitional source / drain region 150T may be higher than a level La of a lowermost end of the second epitaxial layer 152 of the first source / drain region 150A, and may be lower than a level Lb of a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B.

[0038] In example embodiments, on a cross-sectional surface viewed along a first direction (e.g., the X direction), a thickness Dt from a lowermost end of the first epitaxial layer 151 of the transitional source / drain region 150T to a lowermost end of the second epitaxial layer 152 of the transitional source / drain region 150T may be greater than a thickness Da from a lowermost end of the first epitaxial layer 151 of the first source / drain region 150A to a lowermost end of the second epitaxial layer 152 of the first source / drain region 150A, and may be less than a thickness Db from a lowermost end of the first epitaxial layer 151 of the second source / drain region 150B to a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B. This may be because the first width Wa of the first active pattern 105A in the second direction (e.g., the Y direction) may be greater than the second width Wb of the second active pattern 105B in the second direction (e.g., the Y direction), and the width Wt of the transition active pattern 105T in the second direction (e.g., the Y direction) may be smaller than the first width Wa and greater than the second width Wb.

[0039] Due to the above structure, the second epitaxial layer 152 of the transition source / drain region 150T can be spaced apart from the gate structure 160 (e.g., the gate dielectric layer 162 and the gate electrode 165 of the gate structure 160), so that leakage current can be prevented from occurring when the second epitaxial layer 152 and the gate structure 160 are in contact with each other. Therefore, a semiconductor device with improved electrical characteristics and reliability can be provided.

[0040] The interlayer insulating layer 190 may cover the source / drain region 150 and the gate structure 160, and may be disposed to cover the device isolation layer 110. The interlayer insulating layer 190 may include or be formed of at least one of an oxide, a nitride, and an oxynitride, and may include, for example, a low-κ material, or may be, for example, a low-κ material. In example embodiments, the interlayer insulating layer 190 may include a plurality of insulating layers.

[0041] The contact plug 180 may penetrate the interlayer insulating layer 190, may be connected to the source / drain region 150, and may apply an electrical signal to the source / drain region 150. The contact plug 180 may have an inclined side surface in which the width of the lower portion is further reduced than the width of the upper portion according to the aspect ratio, but example embodiments thereof are not limited thereto. The contact plug 180 may extend downward to, for example, an area below the lower surface of the fourth channel layer 144 on the channel structure 140, but example embodiments thereof are not limited thereto. The contact plug 180 may contact the second epitaxial layer 152 of the source / drain region 150. In another example embodiment, the contact plug 180 may not be provided to be recessed into the source / drain region 150, but may be provided to contact the upper surface of the source / drain region 150.

[0042] Each of the contact plugs 180 may include a metal silicide layer disposed on a lower end including the lower surface, or be formed of a metal silicide layer disposed on a lower end including the lower surface, and may also include a barrier layer forming a side surface of the contact plug 180 and extending to an upper surface of the metal silicide layer. The barrier layer may include or may be, for example, a metal nitride (such as a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film). The contact plug 180 may include or be a metal material (such as aluminum (Al), tungsten (W), or molybdenum (Mo)). In example embodiments, the number of conductive layers included in the contact plug 180 and their arrangement may vary.

[0043] An interconnection structure such as a contact plug may be further disposed on the gate electrode 165 , and an interconnection structure connected to the contact plug 180 may be further disposed on the contact plug 180 .

[0044] In the description of the following exemplary embodiments, the above referenced Figures 1 to 2C Descriptions of descriptions overlap descriptions.

[0045] Figure 3 is a plan view illustrating a semiconductor device according to example embodiments.

[0046] Reference Figure 3 In the semiconductor device 100a, each of the outer side surfaces of the first epitaxial layer 151 and the second epitaxial layer 152 may have a circular shape. In example embodiments, in a plan view, the outer side surface of the first epitaxial layer 151 may have a circular shape toward the second epitaxial layer 152. For example, in a plan view, the surface where the first epitaxial layer 151 and the second epitaxial layer 152 contact each other may have a circular shape. Since the outer side surface of the second epitaxial layer 152 may not be formed along a crystal plane, the outer side surface may not have a facet but may have a circular shape.

[0047] Figure 4 is a plan view illustrating a semiconductor device according to example embodiments.

[0048] Reference Figure 4 In the semiconductor device 100b, the first active pattern 105A may be symmetrical in a second direction (e.g., Y direction) with respect to a central axis CLa of the first active pattern 105A extending in a first direction (e.g., X direction), and the second active pattern 105B may be symmetrical in a second direction (e.g., Y direction) with respect to a central axis CLb of the second active pattern 105B extending in the first direction (e.g., X direction). In example embodiments, the central axis CLa of the first active pattern 105A and the central axis CLb of the second active pattern 105B may be offset from each other. However, in a plan view, the second active pattern 105B may be disposed inside an extension line of the first active pattern 105A (e.g., may be completely overlapped in the X direction from a plan view).

[0049] Figure 5 is a plan view illustrating a semiconductor device according to example embodiments.

[0050] Reference Figure 5 In the semiconductor device 100c, the transition active pattern 105T may extend in a first direction (e.g., an X direction) and may vertically overlap two or more gate structures 160. In example embodiments, the channel structure 140 contacting both sidewalls of the transition source / drain region 150T may have transition channel widths CHt and CHt'. In example embodiments, the width CHt of the transition channel of the channel structure 140 disposed adjacent to the channel structure 140 having the first channel width CHa may be greater than the width CHt' of the transition channel of the channel structure 140 disposed adjacent to the channel structure 140 having the second channel width CHb. The widths CHt and CHt' of the transition channels of the channel structure 140 may gradually increase or decrease in the first direction (e.g., the X direction).

[0051] Fig. 6A is a plan view illustrating a semiconductor device according to example embodiments.

[0052] Figure 6B It shows that along Fig. 6A FIG. 1 is a plan view of a semiconductor device according to example embodiments taken along line I1 - I1 ′ in FIG.

[0053] Reference Fig. 6A and Figure 6BIn the semiconductor device 100d, the active region 105 may further include a third active pattern 105C having a third width Wc different from the first width Wa and the second width Wb. In example embodiments, the first width Wa may be greater than the second width Wb and the third width Wc, and the third width Wc may be greater than the second width Wb. A transition active pattern 105T connecting the first active pattern 105A to the second active pattern 105B may be disposed between the first active pattern 105A and the second active pattern 105B, and a transition active pattern (or, referred to as an "additional transition active pattern") 105T' connecting the second active pattern 105B to the third active pattern 105C may be disposed between the second active pattern 105B and the third active pattern 105C. The transition active patterns 105T and 105T' may provide an inclined side surface, and the widths of the transition active patterns 105T and 105T' in the second direction (e.g., the Y direction) vary according to different portions of the inclined side surface. In the region where the first active pattern 105A and the gate structure 160 vertically overlap each other, the region where the second active pattern 105B and the gate structure 160 vertically overlap each other, and the region where the third active pattern 105C and the gate structure 160 vertically overlap each other, the width CHa of the first channel, the width CHb of the second channel, and the width CHc of the third channel of the channel structure 140 may be constant. In the region where the transition active patterns 105T and 105T' and the gate structure 160 vertically overlap each other, the channel structure 140 may have widths CHt and CHt' of the transition channel. The widths CHt and CHt' of the transition channel of the channel structure 140 may gradually increase or decrease along the first direction (e.g., the X direction).

[0054] The source / drain region 150 may further include a third source / drain region 150C on the third active pattern 105C. The first width Wa of the first active pattern 105A, the second width Wb of the second active pattern 105B, and the third width Wc of the third active pattern 105C may be different, and the width CHa of the first channel, the width CHb of the second channel, and the width CHc of the third channel are different, and the thickness Tc of the third sidewall of the first epitaxial layer 151 of the third source / drain region 150C along the first direction (e.g., the X direction) may be different from the thickness Ta of the first sidewall and the thickness Tb of the second sidewall. In example embodiments, the thickness Ta of the first sidewall may be greater than the thickness Tb of the second sidewall and the thickness Tc of the third sidewall, and the thickness Tc of the third sidewall may be greater than the thickness Tb of the second sidewall.

[0055] The transitional source / drain region 150T may be disposed on the transitional active pattern 105T connecting the first active pattern 105A to the second active pattern 105B, and the transitional source / drain region 150T′ may be disposed on the transitional active pattern 105T′ connecting the second active pattern 105B to the third active pattern 105C.

[0056] In example embodiments, at a specific vertical level, the transition source / drain region 150T between the first source / drain region 150A and the second source / drain region 150B may have a thickness Tt1 of a first transition sidewall of the first epitaxial layer 151 of the transition source / drain region 150T along a first direction (e.g., X direction) and a thickness Tt2 of a second transition sidewall that is less than the thickness Tt1 of the first transition sidewall, which may be because the width CHa of the first channel may be greater than the width CHb of the second channel. In example embodiments, the thickness Ta of the first sidewall may be substantially equal to the thickness Tt1 of the first transition sidewall, and the thickness Tb of the second sidewall may be substantially equal to the thickness Tt2 of the second transition sidewall, but example embodiments thereof are not limited thereto.

[0057] In example embodiments, at a specific vertical level, the transition source / drain region 150T' between the second source / drain region 150B and the third source / drain region 150C may have a thickness Tt1' of a first transition sidewall of the first epitaxial layer 151 of the transition source / drain region 150T' along a first direction (e.g., X direction) and a thickness Tt2' of a second transition sidewall greater than the thickness Tt1' of the first transition sidewall, which may be because the width CHc of the third channel may be greater than the width CHb of the second channel. In example embodiments, the thickness Tb of the second sidewall may be substantially the same as the thickness Tt1' of the first transition sidewall, and the thickness Tc of the third sidewall may be substantially the same as the thickness Tt2' of the second transition sidewall, but example embodiments thereof are not limited thereto.

[0058] In example embodiments, at a specific vertical level, a width Pt of the second epitaxial layer 152 of the transition source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B in the first direction (e.g., the X direction) may be greater than a width Pa of the second epitaxial layer 152 of the first source / drain region 150A along the first direction (e.g., the X direction), and may be less than a width Pb of the second epitaxial layer 152 of the second source / drain region 150B along the first direction (e.g., the X direction).

[0059] In example embodiments, at a specific vertical level, a width Pt′ of the second epitaxial layer 152 of the transition source / drain region 150T′ disposed between the second source / drain region 150B and the third source / drain region 150C in the first direction (e.g., the X direction) may be smaller than a width Pb of the second epitaxial layer 152 of the second source / drain region 150B in the first direction (e.g., the X direction), and may be greater than a width Pc of the second epitaxial layer 152 of the third source / drain region 150C along the first direction (e.g., the X direction).

[0060] In example embodiments, on a cross-sectional surface along a first direction (e.g., X direction, when viewed from the Y direction), a level Lt of a lowermost end of the second epitaxial layer 152 of the transition source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B may be higher than a level La of a lowermost end of the second epitaxial layer 152 of the first source / drain region 150A and lower than a level Lb of a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B.

[0061] In example embodiments, on a cross-sectional surface in a first direction (e.g., X direction), a level Lt′ of a lowermost end of the second epitaxial layer 152 of the transition source / drain region 150T′ disposed between the second source / drain region 150B and the third source / drain region 150C may be higher than a level Lc of a lowermost end of the second epitaxial layer 152 of the third source / drain region 150C and lower than a level Lb of a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B.

[0062] exist Figure 6B In the embodiment, the level Lc of the lowermost end of the second epitaxial layer 152 of the third source / drain region 150C and the level Lt of the lowermost end of the second epitaxial layer 152 of the transition source / drain region 150T arranged between the first source / drain region 150A and the second source / drain region 150B may be the same, but example embodiments thereof are not limited thereto.

[0063] In example embodiments, on a cross-sectional surface along a first direction (e.g., the X direction when viewed from the Y direction), a thickness Dt from a lowermost end of a first epitaxial layer 151 of a transitional source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B to a lowermost end of a second epitaxial layer 152 of the transitional source / drain region 150T may be greater than a thickness Da from a lowermost end of the first epitaxial layer 151 of the first source / drain region 150A to a lowermost end of the second epitaxial layer 152 of the first source / drain region 150A, and may be less than a thickness Db from a lowermost end of the first epitaxial layer 151 of the second source / drain region 150B to a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B.

[0064] In example embodiments, on a cross-sectional surface along a first direction (e.g., X direction, when viewed from the Y direction), a thickness Dt′ from a lowermost end of the first epitaxial layer 151 of a transitional source / drain region 150T′ disposed between the second source / drain region 150B and the third source / drain region 150C to a lowermost end of the second epitaxial layer 152 of the transitional source / drain region 150T′ may be greater than a thickness Dc from a lowermost end of the first epitaxial layer 151 of the third source / drain region 150C to a lowermost end of the second epitaxial layer 152 of the third source / drain region 150C, and may be less than a thickness Db from a lowermost end of the first epitaxial layer 151 of the second source / drain region 150B to a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B.

[0065] exist Figure 6B In the embodiment, the thickness Dt from the lowermost end of the first epitaxial layer 151 of the transition source / drain region 150T arranged between the first source / drain region 150A and the second source / drain region 150B to the lowermost end of the second epitaxial layer 152 of the transition source / drain region 150T can be the same as the thickness Dc from the lowermost end of the first epitaxial layer 151 of the third source / drain region 150C to the lowermost end of the second epitaxial layer 152 of the third source / drain region 150C.

[0066] In the description of the following exemplary embodiments, the above referenced Fig. 6A and Figure 6B Descriptions of descriptions overlap descriptions.

[0067] Fig. 7A is a plan view illustrating a semiconductor device according to example embodiments.

[0068] Figure 7B It shows that along Fig. 7A FIG. 1 is a plan view of a semiconductor device according to example embodiments taken along line I2 - I2 ′ in FIG.

[0069] Reference Fig. 7A and Figure 7B In the semiconductor device 100e, the active region 105 may further include a third active pattern 105C having a third width Wc different from the first width Wa and the second width Wb. In example embodiments, the first width Wa may be greater than the second width Wb, and the second width Wb may be greater than the third width Wc. A transition active pattern 105T connecting the first active pattern 105A to the second active pattern 105B may be disposed between the first active pattern 105A and the second active pattern 105B, and a transition active pattern 105T' connecting the second active pattern 105B to the third active pattern 105C may be disposed between the second active pattern 105B and the third active pattern 105C.

[0070] The source / drain region 150 may further include a third source / drain region 150C on the third active pattern 105C. A thickness Tc of a third sidewall of the first epitaxial layer 151 of the third source / drain region 150C along a first direction (e.g., X direction) may be different from a thickness Ta of the first sidewall and a thickness Tb of the second sidewall. In example embodiments, the thickness Ta of the first sidewall may be greater than the thickness Tb of the second sidewall and the thickness Tc of the third sidewall, and the thickness Tb of the second sidewall may be greater than the thickness Tc of the third sidewall.

[0071] In example embodiments, at a specific vertical level, the transition source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B may have a thickness Tt1 of a first transition sidewall of the first epitaxial layer 151 of the transition source / drain region 150T along a first direction (e.g., X direction) and a thickness Tt2 of a second transition sidewall that is less than the thickness Tt1 of the first transition sidewall, which may be because the width CHa of the first channel may be greater than the width CHb of the second channel. In example embodiments, the thickness Ta of the first sidewall may be substantially equal to the thickness Tt1 of the first transition sidewall, and the thickness Tb of the second sidewall may be substantially equal to the thickness Tt2 of the second transition sidewall, but example embodiments thereof are not limited thereto.

[0072] In example embodiments, at a specific vertical level, the transition source / drain region 150T' between the second source / drain region 150B and the third source / drain region 150C may have a thickness Tt1' of a first transition sidewall of the first epitaxial layer 151 of the transition source / drain region 150T' along a first direction (e.g., X direction) and a thickness Tt2' of a second transition sidewall that is less than the thickness Tt1' of the first transition sidewall. In example embodiments, the thickness Tb of the second sidewall may be substantially the same as the thickness Tt1' of the first transition sidewall, and the thickness Tc of the third sidewall may be substantially the same as the thickness Tt2' of the second transition sidewall, but example embodiments are not limited thereto.

[0073] In example embodiments, at a specific vertical level, a width Pt of the second epitaxial layer 152 of the transition source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B in the first direction (e.g., the X direction) may be greater than a width Pa of the second epitaxial layer 152 of the first source / drain region 150A along the first direction (e.g., the X direction), and may be less than a width Pb of the second epitaxial layer 152 of the second source / drain region 150B along the first direction (e.g., the X direction).

[0074] In example embodiments, at a specific vertical level, a width Pt′ of the second epitaxial layer 152 of the transition source / drain region 150T′ disposed between the second source / drain region 150B and the third source / drain region 150C in the first direction (e.g., the X direction) may be greater than a width Pb of the second epitaxial layer 152 of the second source / drain region 150B in the first direction (e.g., the X direction), and may be less than a width Pc of the second epitaxial layer 152 of the third source / drain region 150C in the first direction (e.g., the X direction).

[0075] In example embodiments, on a cross-sectional surface along a first direction (e.g., X direction, when viewed from the Y direction), a level Lt of a lowermost end of the second epitaxial layer 152 of the transition source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B may be higher than a level La of a lowermost end of the second epitaxial layer 152 of the first source / drain region 150A, and may be lower than a level Lb of a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B.

[0076] In example embodiments, on a cross-sectional surface along a first direction (e.g., X direction, when viewed from the Y direction), a level Lt′ of a lowermost end of the second epitaxial layer 152 of the transition source / drain region 150T′ disposed between the second source / drain region 150B and the third source / drain region 150C may be higher than a level Lb of a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B, and may be lower than a level Lc of a lowermost end of the second epitaxial layer 152 of the third source / drain region 150C.

[0077] In example embodiments, on a cross-sectional surface along a first direction (e.g., the X direction when viewed from the Y direction), a thickness Dt from a lowermost end of a first epitaxial layer 151 of a transitional source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B to a lowermost end of a second epitaxial layer 152 of the transitional source / drain region 150T may be greater than a thickness Da from a lowermost end of the first epitaxial layer 151 of the first source / drain region 150A to a lowermost end of the second epitaxial layer 152 of the first source / drain region 150A, and may be less than a thickness Db from a lowermost end of the first epitaxial layer 151 of the second source / drain region 150B to a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B.

[0078] In example embodiments, on a cross-sectional surface along a first direction (e.g., X direction, when viewed from the Y direction), a thickness Dt′ from a lowermost end of the first epitaxial layer 151 of a transitional source / drain region 150T′ disposed between the second source / drain region 150B and the third source / drain region 150C to a lowermost end of the second epitaxial layer 152 of the transitional source / drain region 150T′ may be greater than a thickness Db from a lowermost end of the first epitaxial layer 151 of the second source / drain region 150B to a lowermost end of the second epitaxial layer 152 of the second source / drain region 150B, and may be less than a thickness Dc from a lowermost end of the first epitaxial layer 151 of the third source / drain region 150C to a lowermost end of the second epitaxial layer 152 of the third source / drain region 150C.

[0079] Figure 8 is a plan view illustrating a semiconductor device according to example embodiments.

[0080] Reference Figure 8 The semiconductor device 100 c may further include an inner spacer layer 130 disposed on both side surfaces of the gate structure 160 in the X direction under the fourth channel layer 144 .

[0081] The inner spacer layer 130 may be disposed between the first to fourth channel layers 141, 142, 143, and 144 in parallel with the gate electrode 165 and the gate dielectric layer 162 in a third direction (e.g., Z direction). A side surface of the inner spacer layer 130 may be in contact with the source / drain region 150. The gate electrode 165 may be stably spaced apart from the source / drain region 150 by the inner spacer layer 130 and may be electrically isolated from the source / drain region 150. The inner spacer layer 130 may have a shape in which a side surface opposite to the gate electrode 165 may have a smooth shape that is rounded inwardly toward the gate electrode 165 (e.g., to have a convex surface facing the gate electrode 165), but example embodiments thereof are not limited thereto. The inner spacer layer 130 may be formed of oxide, nitride, and oxynitride, and may be formed of, for example, a low-κ film.

[0082] In some example embodiments, the inner spacer layer 130 may be applied to only a portion of the devices of the semiconductor device 100 f. For example, in nFET, the inner spacer layer 130 may be applied, while in pFET, the inner spacer layer 130 may not be provided to improve the crystallinity of silicon germanium (SiGe) in the source / drain region 150 .

[0083] FIG. 9A to FIG. 16 is a diagram illustrating a method of manufacturing a semiconductor device according to an example embodiment, FIG. 2A to FIG. 2C An example embodiment of a method for a semiconductor device in FIG. Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A and Fig.16 Shows the corresponding Figure 2A The cross section, Fig. 9B , Fig. 10B , Fig. 11B and Fig. 15B Shows the corresponding Figure 2B The cross section, Fig. 9C , Fig. 10C , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15C Shows the corresponding Figure 2C cross section.

[0084] Reference 9A to 9C , the sacrificial layers 120 and the first to fourth channel layers 141 , 142 , 143 , and 144 may be alternately stacked on the substrate 101 .

[0085] It can be processed by subsequent processes such as Figure 2AThe gate dielectric layer 162 and the gate electrode 165 shown in the figure are disposed under the fourth channel layer 144 to replace the sacrificial layer 120. The sacrificial layer 120 may be formed of a material having an etching selectivity with respect to the first to fourth channel layers 141, 142, 143, and 144, respectively. The first to fourth channel layers 141, 142, 143, and 144 may include a material different from that of the sacrificial layer 120 or be formed of a material different from that of the sacrificial layer 120. The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 may include, for example, a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge) or be formed of a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial layer 120 may be silicon germanium (SiGe), and the first to fourth channel layers 141 , 142 , 143 , and 144 may be silicon (Si).

[0086] The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 may be formed by performing an epitaxial growth process from a stacked structure. Each of the sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 may have a thickness in a range of about 1 nm to about 20 nm. In example embodiments, the number of alternately stacked sacrificial layers 120 and the number of channel layers may vary.

[0087] Reference FIG. 10A to FIG. 10C An active structure including the active region 105 may be formed by partially removing the sacrificial layer 120 , the first to fourth channel layers 141 , 142 , 143 , and 144 , and the substrate 101 , and the device isolation layer 110 may be formed.

[0088] The active structure may include an active region 105, a sacrificial layer 120, and first to fourth channel layers 141, 142, 143, and 144. The active structure may be formed in the form of a line extending in one direction (e.g., X direction), and may be spaced apart from adjacent active structures in the Y direction. The active region 105, the sacrificial layer 120, and the first to fourth channel layers 141, 144 may be stacked sequentially in the vertical direction (Z direction). The width of the active structure in the second direction (Y direction) may gradually narrow along the vertical direction (Z direction).

[0089] An insulating material may be filled in the region from which a portion of each of the active region 105, the sacrificial layer 120, and the first to fourth channel layers 141, 142, 143, and 144 is removed, and a device isolation layer 110 may be formed by removing a portion of the insulating material so that the active region 105 may protrude. An upper surface of the device isolation layer 110 may be formed at a level lower than that of an upper surface of the active region 105.

[0090] When forming the active structure, the widths of the active patterns 105A, 105B, and 105T in the second direction (e.g., the Y direction) may be formed differently for each region. The active region 105 may include a first active pattern 105A having a first width Wa at a first vertical level, a second active pattern 105B having a second width Wb different from the first width Wa at the first vertical level, and a transition active pattern 105T connecting the first active pattern 105A to the second active pattern 105B. Since the transition active pattern 105T connects the first active pattern 105A and the second active pattern 105B having different widths, the width Wt of the transition active pattern 105T in the second direction (e.g., the Y direction) at the first vertical level may be gradually reduced or increased along the first direction (e.g., the X direction).

[0091] Reference Fig.11A and Fig. 11B , a sacrificial gate structure 170 and a gate spacer layer 164 may be formed on the active structure.

[0092] The sacrificial gate structure 170 may be constructed as follows Figure 2A The gate dielectric layer 162 and the gate electrode 165 shown in the figure are arranged in the dielectric structure formed by the subsequent process in the region on the first channel layer to the fourth channel layer 141, 142, 143 and 144. The sacrificial gate structure 170 may include a first sacrificial gate layer 172 and a second sacrificial gate layer 175 and a mask pattern layer 176 which may be stacked in sequence. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be patterned using the mask pattern layer 176. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be an insulating layer and a conductive layer, respectively. For example, the first sacrificial gate layer 172 may include silicon oxide or silicon oxide, and the second sacrificial gate layer 175 may include polysilicon or polysilicon. The mask pattern layer 176 may include silicon nitride or may be silicon nitride. The sacrificial gate structure 170 may have a line shape extending in one direction and intersecting with the active structure. For example, the sacrificial gate structure 170 may extend in the Y direction and may be spaced apart from each other in the X direction.

[0093] A gate spacer layer 164 may be formed on both (e.g., opposite) sidewalls of the sacrificial gate structure 170. The gate spacer layer 164 may be formed by forming a film having a uniform thickness along the upper and side surfaces of the sacrificial gate structure 170 and the active structure and performing anisotropic etching. The gate spacer layer 164 may be formed of a low-κ material and, for example, may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0094] Reference Fig. 12A and Fig. 12B , the recess region RC may be formed by removing the sacrificial layer 120 and portions of the first to fourth channel layers 141 , 142 , 143 , and 144 exposed from the sacrificial gate structure 170 , and the sacrificial layer 120 may be partially removed.

[0095] The recessed region RC may be formed by removing the exposed portion of the sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 using the sacrificial gate structure 170 and the gate spacer layer 164 as a mask. Therefore, the first to fourth channel layers 141, 142, 143, and 144 may form a channel structure 140 having a limited length in the X direction.

[0096] The sacrificial layer 120 may be selectively etched relative to the channel structure 140 by, for example, a wet etching process, and a predetermined depth may be removed from the side surface in the X direction. By etching the side surface as described above, the sacrificial layer 120 may have a side surface that is curved inward. However, the specific shape of the side surface of the sacrificial layer 120 is not limited to Fig. 12A and Fig. 12B The example shown in .

[0097] Reference Fig.13A and Fig. 13B , a first epitaxial layer 151 may be formed in the recessed region RC.

[0098] The first epitaxial layer 151 may extend in the recessed region RC to contact the first to fourth channel layers 141, 142, 143, and 144 and the sacrificial layer 120. Therefore, the upper surface of the first epitaxial layer 151 may be formed in a recessed shape and may be formed to have an almost U-shape. The surface of the first epitaxial layer 151 contacting the first to fourth channel layers 141, 142, 143, and 144 and the sacrificial layer 120 may have a wavy shape. The inner surface of the first epitaxial layer 151 may have a smooth non-wavy shape.

[0099] The first epitaxial layer 151 may include or be formed of silicon germanium (SiGe) doped with a Group 3 element. In example embodiments, the first epitaxial layer 151 may include one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). The first epitaxial layer 151 may be formed by supplying silicon (Si) and germanium (Ge) source gases along with supplying a carrier gas. In example embodiments, the carrier gas may be hydrogen (H 2 ) gas, and the silicon (Si) source gas may be, for example, silane (SiH 4 ), dichlorosilane (SiH 2 Cl 2 , DCS) or chlorosilane (SiH 3 Cl, MCS), and the germanium (Ge) source gas may be, for example, germanium tetrahydride (GeH 4 The second epitaxial layer 152 (see FIG. 1 ) which will be described later may also be formed in a similar manner. Fig.14A and Fig. 14B ).

[0100] Since the first epitaxial layer 151 is formed by epitaxial growth from the sidewalls of the active region 105 and the plurality of channel layers 141 , 142 , 143 , and 144 , the thicknesses Ta, Tb, Tt1 , Tt2 of the sidewalls of the first epitaxial layer 151 may be different from the thicknesses Da, Db, and Dt of the lower portions.

[0101] The thicknesses Ta, Tb, Tt1, and Tt2 of the sidewalls of the first epitaxial layer 151 may be determined by the widths of the plurality of channel layers 141, 142, 143, and 144 in the second direction (eg, the Y direction). Fig. 11B As shown in , at one level, since the width of the plurality of channel layers 141, 142, 143, and 144 on the first active pattern 105A in the second direction (e.g., the Y direction) may be greater than the width of the plurality of channel layers 141, 142, 143, and 144 on the second active pattern 105B in the second direction (e.g., the Y direction), the thickness Ta of the first sidewall of the first epitaxial layer 151 of the first source / drain region 150A to be formed below along the first direction (e.g., the X direction) may be greater than the thickness Tb of the second sidewall of the first epitaxial layer 151 of the second source / drain region 150B to be formed below along the first direction (e.g., the X direction). A thickness Tt1 of a first transition sidewall of the first epitaxial layer 151 of the transition source / drain region 150T to be formed below and disposed close to the first source / drain region 150A along the first direction (e.g., the X direction) may be greater than a thickness Tt2 of a second transition sidewall of the first epitaxial layer 151 of the transition source / drain region 150T and disposed close to the second source / drain region 150B along the first direction (e.g., the X direction).

[0102] The thicknesses Da, Db, and Dt of the lower portion of the first epitaxial layer 151 may be affected by the first width Wa of the first active pattern 105A, the second width Wb of the second active pattern 105B, and the width Wt of the transitional active pattern 105T in the second direction (e.g., the Y direction). In example embodiments, on a cross-sectional surface along the first direction (e.g., the X direction, when viewed from the Y direction), the thickness Dt of the lower portion of the first epitaxial layer 151 of the transitional source / drain region 150T in the vertical direction may be greater than the thickness Da of the lower portion of the first epitaxial layer 151 of the first source / drain region 150A in the vertical direction, and may be less than the thickness Db of the lower portion of the first epitaxial layer 151 of the second source / drain region 150B in the vertical direction.

[0103] Figure 8 The example embodiment in the embodiment may be manufactured in the process by forming the inner spacer layer 130 before forming the first epitaxial layer 151. The inner spacer layer 130 may be formed by filling the region where the sacrificial layer 120 has been removed with an insulating material and removing the insulating material deposited on the outer side of the channel structure 140.

[0104] Reference Fig.14A and Fig. 14B , the source / drain regions 150 may be formed by forming a second epitaxial layer 152 on the first epitaxial layer 151 .

[0105] The second epitaxial layer 152 may include silicon (Si) doped with a group III element or be formed of silicon (Si) doped with a group III element. For example, the second epitaxial layer 152 may include one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). The second epitaxial layer 152 may be formed to a level higher than that of the upper surface of the fourth channel layer 144, but example embodiments thereof are not limited thereto. In example embodiments, a plurality of epitaxial layers may be further formed on the second epitaxial layer 152. The width Pt of the second epitaxial layer 152 of the transition source / drain region 150T in the first direction (e.g., X direction) may be greater than the width Pa of the second epitaxial layer 152 of the first source / drain region 150A in the first direction (e.g., X direction), and may be less than the width Pb of the second epitaxial layer 152 of the second source / drain region 150B in the first direction (e.g., X direction).

[0106] Reference FIG. 15A to FIG. 15C , an interlayer insulating layer 190 may be formed between adjacent sacrificial gate structures 170 on the second epitaxial layer 152 , and the sacrificial layer 120 and the sacrificial gate structures 170 may be removed.

[0107] The interlayer insulating layer 190 may be formed by forming an insulating film covering the sacrificial gate structure 170 and the source / drain regions 150 and performing a planarization process.

[0108] The sacrificial layer 120 and the sacrificial gate structure 170 may be selectively removed relative to the gate spacer layer 164, the interlayer insulating layer 190, and the first to fourth channel layers 141, 142, 143, and 144. First, the upper gap region UR may be formed by removing the sacrificial gate structure 170, and the lower gap region LR may be formed by removing the sacrificial layer 120 exposed by the upper gap region UR. For example, when the sacrificial layer 120 includes silicon germanium (SiGe) and the first to fourth channel layers 141, 142, 143, and 144 include silicon (Si), the sacrificial layer 120 may be selectively removed relative to the first to fourth channel layers 141, 142, 143, and 144 by performing a wet etching process using peracetic acid as an etchant.

[0109] Reference Fig.16 , a gate structure 160 may be formed in the upper gap region UR and the lower gap region LR.

[0110] The gate dielectric layer 162 may be formed to conformally cover the inner surface of the upper gap region UR and the inner surface of the lower gap region LR. The gate electrode 165 may be formed to completely fill the upper gap region UR and the lower gap region LR. The gate electrode 165 and the gate spacer layer 164 may be removed downward from the upper gap region UR to a predetermined depth. In the upper gap region UR, a gate capping layer 166 may be formed in the region from which the gate electrode 165 and the gate spacer layer 164 are removed. Thus, a gate structure 160 including the gate dielectric layer 162, the gate electrode 165, the gate spacer layer 164, and the gate capping layer 166 may be formed.

[0111] Afterwards, refer to FIG. 2A to FIG. 2C , a contact plug 180 may be formed.

[0112] A contact hole exposing the source / drain region 150 may be formed by patterning the interlayer insulating layer 190. Thereafter, a contact plug 180 may be formed by filling the contact hole with a conductive material.

[0113] Specifically, after depositing a material forming a barrier layer in the contact hole, a metal-semiconductor compound layer as a silicide layer may be formed on the lower end by performing a silicide process. Thereafter, a contact plug 180 may be formed by depositing a conductive material to fill the contact hole. Thus, the Figures 1 to 2C A semiconductor device 100 in FIG.

[0114] According to the aforementioned example embodiments, by disposing a transition source / drain region on a transition active pattern that connects a first active pattern and a second active pattern of different widths, and using a structure in which the sidewall of the first epitaxial layer of the transition source / drain region has different thicknesses and a symmetrical structure of the active region, contact between the second epitaxial layer and the gate structure can be prevented, so that a semiconductor device with improved electrical characteristics and reliability can be provided.

[0115] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

[0116] It will be understood that when an element is referred to as being "connected" or "coupled" to or "on" another element, the element may be directly connected or coupled to or directly on another element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as being "contacting" or "in contact with" another element (or any form of the word "contacting"), there are no intervening elements at the point of contact.

[0117] When referring to an orientation, layout, position, shape, size, composition, amount or other measurement, terms such as "same", "equal", "planar" or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, composition, amount or other measurement, but are intended to cover nearly the same orientation, layout, position, shape, size, composition, amount or other measurement within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, items described as "substantially the same", "substantially equal" or "substantially planar" may be exactly the same, equal or planar, or may be the same, equal or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0118] Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for specific elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, a term referenced with a specific ordinal number (e.g., "first" in a specific claim) may be described with a different ordinal number elsewhere (e.g., "second" in the specification or another claim).

[0119] The embodiments described herein will be described with reference to plan views and / or cross-sectional views by way of ideal schematic diagrams. Therefore, the exemplary views may be modified according to manufacturing techniques and / or tolerances. Therefore, the disclosed embodiments are not limited to the embodiments shown in the views, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the figures may have schematic properties, and the shapes of the regions shown in the figures may illustrate specific shapes of regions of elements to which aspects of the invention are not limited.

[0120] For ease of description, spatially relative terms such as "under," "below," "below," "above," "on," "top," "bottom," may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the drawings is turned over, elements described as "under" or "beneath" other elements or features will be oriented as "above" the other elements or features. Thus, the term "under" can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

Claims

1. A semiconductor device, comprising: substrate; an active region, comprising a first active pattern, a second active pattern, and a transition active pattern, the first active pattern extending along a horizontal first direction on the substrate and having a first width in a horizontal second direction perpendicular to the first direction at a first height along a third direction above a bottom surface of the substrate, the second active pattern extending in the first direction and having a second width along the second direction smaller than the first width at a first height, the transition active pattern extending in the first direction and connecting the first active pattern to the second active pattern; a gate structure intersecting the active region and extending along a second direction on the substrate; a plurality of groups of channel layers, each group including channel layers extending in a first direction, the channel layers being arranged in a continuous order from the active region and spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, and each group being surrounded by a corresponding gate structure on the active region; as well as a source / drain region disposed on a side of the gate structure and including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a transition source / drain region disposed on the transition active pattern, The active region is symmetrical in the second direction relative to a central axis of the active region extending in the first direction. wherein each of the source / drain regions is disposed on the active region and includes a first epitaxial layer disposed on the first group of the plurality of channel layers and the second group of the plurality of channel layers and a second epitaxial layer disposed on the first epitaxial layer, wherein, at a second height along the third direction above the bottom surface of the substrate, a first sidewall thickness of the first epitaxial layer of the first source / drain region in the first direction is greater than a second sidewall thickness of the first epitaxial layer of the second source / drain region in the first direction, and Wherein, at the second height, the first epitaxial layer of the transition source / drain region has a first transition sidewall and a second transition sidewall, the first transition sidewall has a first transition sidewall thickness in the first direction, and the second transition sidewall has a second transition sidewall thickness in the first direction that is less than the first transition sidewall thickness.

2. The semiconductor device according to claim 1, in, At the second height, the first sidewall thickness is the same as the first transition sidewall thickness, and Wherein, at the second height, the second sidewall thickness is the same as the second transition sidewall thickness.

3. The semiconductor device according to claim 1, wherein The thickness in the third direction from the lowest end of the first epitaxial layer in the transition source / drain region to the lowest end of the second epitaxial layer in the transition source / drain region is greater than the thickness in the third direction from the lowest end of the first epitaxial layer in the first source / drain region to the lowest end of the second epitaxial layer in the first source / drain region, and is less than the thickness in the third direction from the lowest end of the first epitaxial layer in the second source / drain region to the lowest end of the second epitaxial layer in the second source / drain region.

4. The semiconductor device according to claim 1, wherein A vertical level of a lowermost end of the second epitaxial layer of the transition source / drain region is higher than a vertical level of a lowermost end of the second epitaxial layer of the first source / drain region and lower than a vertical level of a lowermost end of the second epitaxial layer of the second source / drain region.

5. The semiconductor device according to claim 1, wherein The second epitaxial layer of the transitional source / drain region is spaced apart from the gate electrode and the gate dielectric layer of the gate structure.

6. The semiconductor device according to claim 1, in, At the first height, each of the first active pattern and the second active pattern has a constant width in the second direction, and Wherein, at the first height, the width of the transition active pattern in the second direction gradually increases or decreases along the first direction.

7. The semiconductor device according to claim 1, wherein At the second height, a width of the second epitaxial layer of the transitional source / drain region in the first direction is greater than a width of the second epitaxial layer of the first source / drain region in the first direction and less than a width of the second epitaxial layer of the second source / drain region in the first direction.

8. The semiconductor device according to claim 1, wherein In a plan view, outer side surfaces of at least a portion of the first epitaxial layer and the second epitaxial layer are facets along a crystal plane.

9. The semiconductor device according to claim 1, further comprising: A contact plug is provided for each source / drain region, the contact plug being recessed into the source / drain region and connected to the source / drain region.

10. The semiconductor device according to claim 1, further comprising: An inner spacer layer is disposed on opposite sides of each of the gate structures along the first direction.

11. The semiconductor device according to claim 1, in, Each group of the plurality of channel layers disposed on the first active pattern includes channel layers sequentially ordered in the second direction having a width of the first group, wherein each group of the plurality of channel layers disposed on the second active pattern comprises channel layers sequentially ordered in the second direction having a width of the second group, each width of the second group being smaller than a corresponding width of the first group, and Wherein, each group of the plurality of channel layers disposed on the transition active pattern includes channel layers continuously ordered in the second direction having a third group of widths, each of the widths of the third group being smaller than a corresponding width of the first group and larger than a corresponding width of the second group.

12. The semiconductor device according to claim 11, in, At the first height, each of the first active pattern and the second active pattern has a constant width in the second direction, and Wherein, at the first height, the width of the transition active pattern in the second direction gradually increases or decreases along the first direction.

13. A semiconductor device, comprising: substrate; an active region extending along a first horizontal direction on the substrate and comprising a first active pattern, a second active pattern and a transition active pattern, the first active pattern being at a first height along a vertical direction above a bottom surface of the substrate and having a first width in a second horizontal direction, the second active pattern having a second width different from the first width in the second direction, and the transition active pattern connecting the first active pattern to the second active pattern; gate structures intersecting the active region, each gate structure extending across the substrate in a second direction; as well as a source / drain region disposed on a side of the gate structure and including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a transition source / drain region disposed on the transition active pattern, wherein each of the source / drain regions is disposed on the active region and includes a first epitaxial layer having a recessed upper surface and a second epitaxial layer disposed on the first epitaxial layer, wherein, at a second height in the vertical direction above the bottom surface of the substrate, a first sidewall thickness of the first epitaxial layer of the first source / drain region in the first direction is different from a second sidewall thickness of the first epitaxial layer of the second source / drain region in the first direction, wherein at the second height, the relative sidewall thicknesses of the first epitaxial layer of the transition source / drain region in the first direction are different, and The vertical level of the lowermost end of the second epitaxial layer of the first source / drain region, the vertical level of the lowermost end of the second epitaxial layer of the second source / drain region, and the vertical level of the lowermost end of the second epitaxial layer of the transition source / drain region are different from each other.

14. The semiconductor device according to claim 13, wherein: At the first height, the width of the transition active pattern in the second direction gradually decreases or increases along the first direction.

15. The semiconductor device according to claim 13, in, The active area further includes a third active pattern having a third width different from the first width and the second width, The source / drain region further includes a third source / drain region on the third active pattern. wherein the additional transition active pattern connects the second active pattern to the third active pattern, and Wherein, at the second height, a third sidewall thickness of the first epitaxial layer of the third source / drain region in the first direction is different from the first sidewall thickness and the second sidewall thickness.

16. The semiconductor device according to claim 15, in, The first width is greater than the second width, wherein the second width is greater than the third width, wherein the first sidewall thickness is greater than the second sidewall thickness, and The thickness of the second side wall is greater than the thickness of the third side wall.

17. The semiconductor device according to claim 15, in, The first width is greater than the second width and the third width, wherein the third width is greater than the second width, wherein the first sidewall thickness is greater than the second sidewall thickness and the third sidewall thickness, and The thickness of the third side wall is greater than the thickness of the second side wall.

18. The semiconductor device according to claim 13, in, The first active pattern is symmetrical in the second direction with respect to a central axis of the first active pattern extending in the first direction, wherein the second active pattern is symmetrical in the second direction with respect to a central axis of the second active pattern extending in the first direction, and Wherein, a central axis of the first active pattern and a central axis of the second active pattern are offset from each other.

19. A semiconductor device, comprising: substrate; The active area extends along a first direction on the substrate and includes a first active pattern, a second active pattern and a transition active pattern, wherein the first active pattern has a first width in a second direction intersecting the first direction, the second active pattern has a second width smaller than the first width in the second direction, and the transition active pattern connects the first active pattern to the second active pattern. a gate structure intersecting the active region on the substrate and extending in a second direction; a plurality of groups of channel layers, each group including channel layers extending in a first direction, the channel layers being arranged in a continuous order from the active region and spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, and each group being surrounded by a corresponding gate structure on the active region, the plurality of groups of channel layers being arranged spaced apart from each other in the first direction; as well as a source / drain region disposed between gate structures adjacent to each other along a first direction and including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a transition source / drain region disposed on the transition active pattern, wherein each of the source / drain regions is disposed on the active region and includes a first epitaxial layer disposed between adjacent groups of the plurality of channel layers and a second epitaxial layer disposed on the first epitaxial layer, wherein, at a first vertical height above the bottom surface of the substrate, the transitional source / drain region has a first transitional sidewall thickness of a first epitaxial layer of the transitional source / drain region in the first direction and a second transitional sidewall thickness in the first direction that is less than the first transitional sidewall thickness, and The vertical level of the lowermost end of the second epitaxial layer in the transition source / drain region is higher than that of the lowermost end of the second epitaxial layer in the first source / drain region, and lower than that of the lowermost end of the second epitaxial layer in the second source / drain region.

20. The semiconductor device according to claim 19, in, At a second vertical height above the bottom surface of the substrate, the width of the transition active pattern in the second direction gradually decreases or increases along the first direction, wherein each group of the plurality of channel layers disposed on the transition active pattern comprises channel layers sequentially ordered in the second direction having a width of one group, and Each of the first active pattern and the second active pattern has a constant width in the second direction.

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