Semiconductor device and manufacturing method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor device having a backside source / drain contact formed using a buried source / drain feature and a semiconductor cap layer formed between the buried source / drain feature and a source / drain region. Buried source / drain features and semiconductor cap layers enable self-aligned backside source / drain contacts and backside isolation. The semiconductor cap layer functions as an etch stop layer during backside contact formation while enabling source / drain region growth without manufacturing loss, such as voids in the source / drain region. The embodiment of the invention also relates to a semiconductor device and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor industry has experienced continued rapid growth due to the continuous improvement in the integration density of various electronic components. In most cases, this improvement in integration density comes from the repeated reduction in the minimum component size, thereby allowing more components to be integrated into a given chip area. As the minimum component size decreases, the metal layer routing in the metal-to-metal connection layer also becomes more complex. Therefore, there is a need to solve the above problems. Summary of the invention

[0003] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a semiconductor fin on a front side of a substrate; forming a sacrificial gate structure above the semiconductor fin; etching the semiconductor fin and the substrate to form a first source / drain groove and a second source / drain groove on both sides of the sacrificial gate structure; depositing a first buried source / drain component and a second buried source / drain component in the first source / drain groove and the second source / drain groove; forming a first semiconductor cap layer and a second semiconductor cap layer above the first buried source / drain component and the second buried source / drain component; forming a first source / drain region and a second source / drain region above the first semiconductor cap layer and the second semiconductor cap layer; forming a replacement gate structure; thinning the back side of the substrate to expose the first buried source / drain component and the second buried source / drain component; removing the first buried source / drain component and the first semiconductor cap layer to expose the first source / drain region; and forming a first back side source / drain contact on the first source / drain region.

[0004] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a semiconductor fin on a front side of a substrate, wherein the semiconductor fin comprises two or more first semiconductor layers sandwiched between two or more second semiconductor layers; forming isolation on the substrate and around a lower portion of the semiconductor fin; forming a sacrificial gate structure above the semiconductor fin; depositing a sidewall spacer layer; etching the semiconductor fin to a first depth; forming an internal spacer on an exposed end of the second semiconductor layer; etching the semiconductor fin to a second depth, wherein the second depth is greater than the first depth; forming buried source / drain components on both sides of the semiconductor fin; and forming a source / drain region above the buried source / drain components.

[0005] Some other embodiments of the present application provide a semiconductor device, including: a first source / drain region; a second source / drain region; a semiconductor channel, arranged between the first source / drain region and the second source / drain region, wherein the semiconductor channel includes two or more semiconductor layers; a gate dielectric layer, formed around the two or more semiconductor layers; a gate electrode layer, arranged on the gate dielectric layer; a first front side source / drain contact, arranged on the front side of the first source / drain region; a first back side source / drain contact, arranged on the back side of the first source / drain region; and a second front side source / drain contact, arranged on the front side of the second source / drain region, wherein the back side of the second source / drain region has a convex shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0008] Figures 2 to 4 , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6B , Figures 7 to 20 and FIG. 21A to FIG. 21B Various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically illustrated.

[0009] Figures 22 to 31 Various semiconductor devices according to embodiments of the present disclosure are schematically illustrated. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "over," "top," "upper," and the like may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] The above is a general overview of some aspects of the embodiments described in the present disclosure. Although some of the embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the embodiments of the present disclosure may be used in other processes and / or other devices, such as planar FETs, Fin-FETs, horizontal all-around gate (HGAA) FETs, vertical all-around gate (VGAA) FETs, and other suitable devices. Those of ordinary skill in the art will readily appreciate that other modifications that may be made are considered within the scope of the embodiments of the present disclosure. In addition, although the method embodiments may be described in a particular order, various other method embodiments may be implemented in any logical order and may include fewer or more steps than those described herein. In the embodiments of the present disclosure, the source / drain region refers to the source and / or drain. The source and drain may be used interchangeably.

[0013] The fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0014] An integrated circuit (IC) typically includes multiple semiconductor devices, such as field effect transistors and metal interconnect layers formed on a semiconductor substrate. The interconnect layers designed to connect the semiconductor devices to a power supply, input / output signals, and to each other may include signal lines and power rails. As semiconductor devices shrink in size, the spacing for metal power rails and signal lines decreases.

[0015] Embodiments of the present disclosure provide semiconductor devices having contact features (such as source / drain contacts) formed on the back side of a substrate and methods for manufacturing such semiconductor devices. In particular, embodiments of the present disclosure provide semiconductor devices having backside source / drain contacts formed using buried source / drain features and a semiconductor capping layer formed between the buried source / drain features and the source / drain region. The buried source / drain features and the semiconductor capping layer enable self-aligned backside source / drain contacts and backside isolation. The semiconductor capping layer serves as an etch stop layer during the formation of the backside contacts, while enabling the growth of the source / drain region without manufacturing losses, such as voids in the source / drain region.

[0016] Figure 1 is a flow chart of a method 100 for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. Figures 2 to 4 , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6B , Figures 7 to 20 and FIG. 21A to FIG. 21B Schematically illustrated are various stages of manufacturing a semiconductor device 200 according to method 100. Additional operations may be provided before, during, and after the operations / processes in method 100, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchangeable.

[0017] The method 100 begins at operation 102, where a plurality of semiconductor fins 220 are formed over a substrate 210, and an isolation layer 222 is formed in trenches between the plurality of semiconductor fins 220, such as Figure 2 as shown in . Figure 2 is a schematic perspective view of semiconductor device 200 after operation 102 .

[0018] A substrate 210 is provided to form the semiconductor device 200 thereon. The substrate 210 may include a single crystalline semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate 210 may include various doping configurations depending on the circuit design. For example, different doping profiles, e.g., n-well, p-well, may be formed in the substrate 210 in regions designed for different device types, such as n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs). In some embodiments, the substrate 210 may be a silicon-on-insulator (SOI) substrate including an insulator structure 211 for enhancement.

[0019] The substrate 210 has a top surface 210f and a back surface 210b. A semiconductor stack 218 is then formed over the top surface 210f of the substrate 210. The semiconductor stack 218 includes alternating semiconductor layers made of different materials to facilitate the formation of nanosheet channels in multi-gate devices, such as nanosheet channel FETs. In some embodiments, the semiconductor stack 218 includes a first semiconductor layer 214 sandwiched between a second semiconductor layer 216. The first semiconductor layer 214 and the second semiconductor layer 216 have different oxidation rates and / or etching selectivities.

[0020] In a later manufacturing stage, a portion of the second semiconductor layer 216 forms a nanosheet channel in a multi-gate device. As an example, three first semiconductor layers 214 and three second semiconductor layers 216 are arranged alternately, such as Figure 2 As shown in . More or fewer semiconductor layers 214 and 216 may be included in the semiconductor stack 218 , depending on the desired number of channels in the semiconductor device to be formed. In some embodiments, the number of semiconductor layers 216 is between 1 and 10.

[0021] The semiconductor layers 214 and 216 may be formed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the semiconductor layer 216 comprises the same material as the substrate 210. In some embodiments, the semiconductor layers 214 and 216 comprise materials different from the substrate 210. In some embodiments, the semiconductor layers 214 and 216 are made of materials having different lattice constants. In some embodiments, the first semiconductor layer 214 comprises an epitaxially grown silicon germanium (SiGe) layer, and the second semiconductor layer 216 comprises an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, any one of the semiconductor layers 214 and 216 may comprise: other materials, such as Ge; compound semiconductors, such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof.

[0022] The first semiconductor layer 214 in the channel region can be eventually removed and used to define the vertical distance between adjacent channels of the multi-gate device formed subsequently. In some embodiments, the thickness of the first semiconductor layer 214 is equal to or greater than the thickness of the second semiconductor layer 216. In some embodiments, each first semiconductor layer 214 has a thickness in the range between about 5nm and about 50nm. In other embodiments, each first semiconductor layer 214 has a thickness in the range between about 10nm and about 30nm. In some embodiments, each second semiconductor layer 216 has a thickness in the range between about 5nm and about 30nm. In other embodiments, each second semiconductor layer 216 has a thickness in the range between about 10nm and about 20nm. In some embodiments, each second semiconductor layer 216 has a thickness in the range between about 6nm and about 12nm. In some embodiments, the second semiconductor layer 216 in the semiconductor stack 218 is uniform in thickness.

[0023] The semiconductor fins 220 are formed by portions of the semiconductor stack 218 and the substrate 210. The semiconductor fins 220 may be formed by patterning a hard mask (not shown) formed on the semiconductor stack 218 and one or more etching processes. Each semiconductor fin 220 has a semiconductor stack 218 formed by semiconductor layers 214, 216 and a well portion 212 formed by the substrate 210. Figure 2 In the embodiment, the semiconductor fins 220 are formed along the X direction.

[0024] The isolation layer 222 is formed in the trenches between the semiconductor fins 220, such as Figure 2 As shown in . An isolation layer 222 is formed over the substrate 210 to cover the well portion 212 of the semiconductor fin 220. The isolation layer 222 may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 222 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, or combinations thereof. In some embodiments, the isolation layer 222 is formed by a suitable deposition process such as atomic layer deposition (ALD) to cover the semiconductor fin 220, and then recessedly etched using a suitable anisotropic etching process to expose the semiconductor stack 218 of the semiconductor fin 220.

[0025] In operation 104, a sacrificial gate structure 228 and spacers are then formed over the semiconductor fins 220, such as Figure 2. A sacrificial gate dielectric layer 224 is deposited over the exposed surface of the semiconductor device 200. The sacrificial gate dielectric layer 224 may be conformally formed over the semiconductor fins 220 and the isolation layer 222. In some embodiments, the sacrificial gate dielectric layer 224 may be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable processes. The sacrificial gate dielectric layer 224 may include one or more dielectric material layers, such as SiO2, SiN, a high-K dielectric material, and / or other suitable dielectric materials.

[0026] A sacrificial gate electrode layer 226 is deposited over the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 may be blanket deposited over the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 includes silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range between about 42 nm and about 200 nm. In some embodiments, the sacrificial gate electrode layer 226 is subjected to a planarization operation. The sacrificial gate electrode layer 226 may be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. In some embodiments, a pad layer 227 and a mask layer 229 may be sequentially deposited over the sacrificial gate electrode layer 226. A patterning operation is performed over the mask layer 229 to form a sacrificial gate structure 228, which covers a portion of the semiconductor fin 220 designed to be a channel region.

[0027] A gate sidewall spacer layer 230 is then deposited over the semiconductor device 200. The gate sidewall spacer layer 230 may be formed by blanket deposition of an insulating material and subsequent anisotropic etching to remove the insulating material from the horizontal surface. The gate sidewall spacer layer 230 may have a thickness in a range between about 2 nm and about 10 nm. In some embodiments, the insulating material of the gate sidewall spacer layer 230 is a silicon nitride-based material such as SiN, SiON, SiOCN or SiCN and combinations thereof. In other embodiments, the gate sidewall spacer layer 230 may be formed by two or more dielectric material layers.

[0028] In operation 106, a protection layer 223 is formed around the well portion 212 of the semiconductor fin 220. Figure 3 As shown in Figure 3 2 is a schematic perspective view of a semiconductor device 200. In some embodiments, a protective layer 223 is deposited over the gate sidewall spacer layer 230. After deposition, the fin structure 220 and the sacrificial gate structure 228 are immersed in the protective layer 223. An etch-back process is performed on the protective layer 223 so that the top surface 223t is substantially at the same level as the fin top portion 230ft of the gate sidewall spacer layer 230, as shown in FIG. Figure 3 as shown in .

[0029] The protection layer 223 may be selected from a material having an etch selectivity to materials in the gate sidewall spacer layer 230 and the semiconductor fin 220 , so that the protection layer 223 may be used to protect underlying structures during subsequent removal of the gate sidewall spacer layer 230 and the semiconductor fin 220 .

[0030] In some embodiments, the protective layer 223 may include one or more dielectric materials. The protective layer 223 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof. The protective layer 223 may be formed by a suitable deposition process, for example, by FCVD, HDP-CVD, PVD, ALD, CVD. In some embodiments, the protective layer 223 may include silicon oxide deposited by FCVD.

[0031] The protective layer 223 may include other materials, such as metals or metal oxides. In some embodiments, the protective layer 223 may include aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, ruthenium, alloys thereof, or combinations thereof, which are formed by CVD, ALD, electroplating, or other suitable methods. In other embodiments, the protective layer 223 may include one or more metal oxides, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, lanthanum oxide, yttrium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, and / or combinations thereof, which may be formed by CVD, ALD, or any suitable method.

[0032] The etch-back process may be an isotropic etching process such as dry chemical etching or wet etching or an anisotropic etching process such as dry plasma etching. In some embodiments, the desired thickness of the remaining protection layer 223 may be obtained by adjusting the etching time.

[0033] After operation 106, the trenches between the semiconductor fins 220 remain substantially filled with the protective layer 223. The protective layer 223 protects the isolation layer 222 from the processing environment during subsequent processing.

[0034] In operation 108, source / drain recesses 234 are formed by etching back the semiconductor fins 220, as shown in FIG. Figure 4 As shown in Figure 42 is a schematic perspective view of a semiconductor device 200. The semiconductor fins 220 on opposite sides of the sacrificial gate structures 228 are recessed etched to form source / drain recesses 234 between adjacent sacrificial gate structures 228. The first semiconductor layer 214 and the second semiconductor layer 216 in the semiconductor fin 220 are etched down on both sides of the sacrificial gate structure 228 using an etching operation. In some embodiments, all layers in the semiconductor stack 218 of the semiconductor fin 220 and a portion of the well portion 212 of the semiconductor fin 220 are etched. In some embodiments, the first semiconductor layer 214, the second semiconductor layer 216, and the substrate 210 may be removed using a suitable dry etch and / or wet etch. As shown in FIG. Figure 4 As shown in , source / drain recesses 234 are formed on opposite sides of the sacrificial gate structure 228 .

[0035] In some embodiments, the source / drain recesses 234 are shallow recesses compared to the prior art. As discussed below, the shallow recesses avoid residual dielectric material during the formation of the internal spacers. In some embodiments, the source / drain recesses 234 are formed to a depth that exposes all of the sacrificial semiconductor layers 214 in the semiconductor stack 218. For example, the bottom surface 234b of the source / drain recesses 234 is below the top surface 210f of the substrate 210. Figure 4 As shown in FIG. 1 , the bottom surface 234 b of the source / drain recess 234 is located below the top surface 210 f of the substrate 210 by a distance H. 234 In some embodiments, the distance H 234 In some embodiments, the distance H is between about 2 nm and about 40 nm. 234 In the range between 1 and 2.0 times the thickness of the semiconductor layer 216 .

[0036] In operation 110, an inner spacer 232 is formed on the exposed end of the first semiconductor layer 214 below the sacrificial gate structure 228, such as FIG. 5A to FIG. 5C as shown in . Figure 5A is a schematic perspective view of semiconductor device 200 after operation 110 . Figure 5B is a schematic cross-sectional view of the semiconductor device 200 during an intermediate stage of forming the inner spacers 232 . Figure 5C is a schematic cross-sectional view of the semiconductor device 200 after formation of the inner spacers 232 .

[0037] First, the first semiconductor layer 214 exposed to the source / drain recess 234 is horizontally etched along the X direction to form a spacer cavity. In some embodiments, the first semiconductor layer 214 can be selectively etched by using a wet etchant, such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP) or potassium hydroxide (KOH) solution. In some embodiments, the etching amount of the first semiconductor layer 214 is in the range between about 3 nm and about 15 nm along the X direction.

[0038] After forming the spacer cavity at the opposite ends of the first semiconductor layer 214, the inner spacer 232 may be formed in the spacer cavity by conformally depositing an insulating layer, such as Figure 5B and then partially removing the insulating layer, as shown in Figure 5C As shown in . The insulating layer can be formed by ALD or any other suitable method. A subsequent etching process removes most of the insulating layer except for the interior of the cavity, resulting in an internal spacer 232. The internal spacer 232 includes two or more segments alternately stacked with the second semiconductor layer 216.

[0039] The inner spacer 232 may be formed by a single dielectric material layer or a plurality of dielectric material layers. In some embodiments, the inner spacer 232 may include one of silicon nitride (SiN) and silicon oxide (SiO2), SiONC, or a combination thereof. The inner spacer 232 may have a thickness in the range of from about 3 nm to about 15 nm along the X direction. Because the source / drain recess 234 is relatively shallow compared to the prior art, after forming the inner spacer 232, there is no residue of the inner spacer material on the bottom surface 234b.

[0040] In operation 112, a second fin recessing process is performed to form a deep recess 235 in the substrate 210, such as Fig. 6A and Figure 6B as shown in . Fig. 6A is a schematic perspective view of a semiconductor device 200 . Figure 6B is a schematic cross-sectional view of a semiconductor device 200 .

[0041] In some embodiments, the well portion 212 of the semiconductor fin 220 is further etched to form a deep recess 235. In some embodiments, the substrate 210 may be removed using a suitable dry etch and / or wet etch. FIG. 6A to FIG. 6B As shown in FIG. 2 , a deep recess 235 is formed from a bottom surface 234 b of the source / drain recess 234 .

[0042] Due to the two different etching processes, a step 233 may be formed between the source / drain recess 234 and the corresponding deep recess 235 (i.e., at the bottom surface 234b of the source / drain recess 234 and the entrance of the deep recess 235). In some embodiments, the deep recess 235 is formed to a depth H. 235 In some embodiments, the depth H 235 In some embodiments, an upper step 233u may be formed between the topmost semiconductor layer 216 and the topmost inner spacer 232, such as Figure 6B as shown in .

[0043] In operation 114, buried source / drain features 236 are formed in lower portions of source / drain recesses 234, such as Figure 7 As shown in Figure 7 2 is a schematic perspective view of semiconductor device 200. The buried source / drain feature 236 fills the deep recess 235 and the lower portion of the source / drain recess 234. In some embodiments, the buried source / drain feature 236 is formed to a higher level and then recessed to a level below the bottommost semiconductor layer 216L or the bottommost channel region. In some embodiments, the buried source / drain feature 236 fills the source / drain recess 234 to a level below the bottommost inner spacer 232L. Figure 7 As shown in , front face 236t may be located at a level below bottommost interior spacer 232L.

[0044] The buried source / drain features 236 may be formed of a material having an etch selectivity relative to the material of the substrate 210, such as the material in the well portion 212 of the semiconductor fin 220. In some embodiments, the buried source / drain features 236 may also have an etch selectivity relative to the insulating material in the isolation layer 222. In some embodiments, the buried source / drain features 236 are formed of an undoped semiconductor material. In some embodiments, the buried source / drain features 236 are formed of a semiconductor material having a high etch selectivity relative to Si. For example, the buried source / drain features 236 are formed of SiGe or SiGeB. In some embodiments, the buried source / drain features 236 are formed of undoped SiGe. In some embodiments, the buried source / drain features 236 are formed of undoped SiGe or SiGeB including a Ge atomic concentration in a range between about 10% and about 50%. Alternatively, the buried source / drain features 236 may include other materials having etching selectivity to the substrate 210, such as Ge; compound semiconductors such as SiC, GeAs, GaP, InP, InAs and / or InSb; alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP; or combinations thereof. In some embodiments, the buried source / drain features 236 may be formed of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, metal oxides (such as aluminum oxide, hafnium oxide), or combinations thereof.

[0045] The buried source / drain features 236 may be formed by any suitable method, such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique.

[0046] like Figure 7 As shown in , the sidewalls of the buried source / drain feature 236 have a step that reflects the step 233 between the source / drain recess 234 and the deep recess 235 .

[0047] During the backside process, the buried source / drain features 236 are used as self-aligned features for forming contact holes to connect with the source / drain regions. The material of the buried source / drain features 236 allows for selective removal of portions of the semiconductor fins 220 located in the channel region and the opposing source / drain regions. In addition, the buried source / drain features 236 can be selectively removed without etching the dielectric material in the isolation layer 222.

[0048] exist Figure 7In the embodiment of the present invention, buried source / drain features 236 are formed in all source / drain recesses 234. Alternatively, a patterning process may be performed to selectively deepen the source / drain recesses 234 and form deep recesses 235, and then form buried source / drain features 236 in the selectively deepened source / drain recesses 234. For example, only source / drain regions having backside contacts will include buried source / drain features 236.

[0049] In operation 116, an optional semiconductor capping layer 238 is formed on the buried source / drain features 236, such as Figure 8 As shown in Figure 8 2 is a perspective view of the semiconductor device 200. Figure 8 As shown in FIG. 2 , a semiconductor capping layer 238 is formed on the front side 236 t of the buried source / drain features 236 .

[0050] In some embodiments, the semiconductor cap layer 238 may include a semiconductor material having an etch selectivity relative to the buried source / drain features 236, such that the semiconductor cap layer 238 may serve as an etch stop layer when removing the buried source / drain features 236 during backside processing. The semiconductor material in the semiconductor cap layer 238 also allows epitaxial growth of the source / drain regions during subsequent processing, thereby reducing defects such as voids in or around the source / drain regions.

[0051] The semiconductor cap layer 238 may be formed by any suitable method, such as by ALD, CVD, or any suitable deposition technique. In some embodiments, the semiconductor cap layer 238 is formed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth process. In some embodiments, the semiconductor cap layer 238 may include the same material as the substrate 210. In some embodiments, the semiconductor cap layer 238 includes an epitaxially grown silicon (Si) layer. Alternatively, the semiconductor cap layer 238 may include other materials having etching selectivity to the buried source / drain features 236, such as Si:B, SiN, SiCN, SiOCN, SiOC. The semiconductor cap layer 238 may include: other materials; compound semiconductors such as SiC, GeAs, GaP, InP, InAs, and / or InSb; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof.

[0052] like Figure 8 As shown in FIG. 2 , the semiconductor cap layer 238 may have a thickness T above the buried source / drain features 236. 238 In some embodiments, the thickness T 238In some embodiments, the top surface 238f of the semiconductor cap layer 238 may intersect the bottommost inner spacer 232L such that the semiconductor cap layer 238 covers the well portion 212 of the substrate 210 while leaving the bottommost semiconductor layer 216 exposed.

[0053] In some embodiments, the top surface 238f of the semiconductor cap layer 238 has a convex profile in the XZ plane. In particular, the top surface 238f is higher in the Z direction near the central region and lower near the lowermost inner spacer 232L. This is because the inner spacer 232 is formed of a dielectric material and the semiconductor cap layer 238 cannot grow from the inner spacer 232. Therefore, the subsequently formed source / drain regions have matching profiles.

[0054] In operation 118, epitaxial source / drain regions 240 are formed in source / drain recesses 234, such as Fig. 9 As shown in Fig. 9 2 is a schematic perspective view of a semiconductor device 200. In some embodiments, a pre-cleaning process may be performed before epitaxially growing an epitaxial source / drain region 240 in the source / drain recess 234. The epitaxial source / drain region 240 is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). The epitaxial source / drain region 240 may be used for a p-type device or an n-type device. To form an n-type FET, the epitaxial source / drain region 240 may include a CuO layer having a concentration of 5E19 to 5E21 / cm 3 One or more layers of SiAs, SiP with n-type dopants such as As and P. To form a p-type FET, the epitaxial source / drain regions 240 may include a Ge concentration in a range between about 10% and 50% and a concentration of 5E19-5E21 / cm 3 One or more layers of SiGe, SiGeB having a p-type dopant (such as B).

[0055] The epitaxial source / drain region 240 grows from the exposed semiconductor surface, such as the second semiconductor layer 216 under the sacrificial gate structure 228 and the top surface 238f of the semiconductor cap layer 238. Because the epitaxial source / drain region 240 grows from the top surface 238f of the semiconductor cap layer 238 in the bottom portion of the source / drain recess 234, the epitaxial source / drain region 240 can fill the source / drain recess 234 without any voids. In some embodiments, the epitaxial source / drain region 240 grows through the topmost semiconductor channel (i.e., the second semiconductor layer 216 under the sacrificial gate structure 228) to contact the gate sidewall spacer layer 230. The first semiconductor layer 214 under the sacrificial gate structure 228 is separated from the epitaxial source / drain region 240 by the internal spacer 232.

[0056] The epitaxial source / drain region 240 can be used as a source region and a drain region, and then connected to a power line or a signal line according to the circuit design. For example, the epitaxial source / drain region 240 used as a drain region can be connected to a signal line; and the epitaxial source / drain region 240 used as a source region can be connected to a power rail. According to an embodiment of the present disclosure, a portion of the epitaxial source / drain region 240 can be connected to a signal line or a power line by a connector formed through the front side 240f of the epitaxial source / drain region 240, and another portion of the epitaxial source / drain region 240 can be connected to a signal line or a power line by a connector formed through the back side 240b of the epitaxial source / drain region 240. In some embodiments, the back side 240b of the source / drain region 240 has an inverted smiley face profile.

[0057] In operation 120, a contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 are formed over the exposed surface, such as Fig.10 As shown in Fig.10 2 is a schematic perspective view of a semiconductor device 200. CESL 242 is formed on the epitaxial source / drain regions 240 and the gate sidewall spacer layer 230. In some embodiments, CESL 242 has a thickness in a range between about 1 nm and about 15 nm. CESL 242 may include Si3N4, SiON, SiCN, or any other suitable material, and may be formed by CVD, PVD, or ALD.

[0058] An interlayer dielectric (ILD) layer 244 is formed over the contact etch stop layer (CESL) 242. Materials for the ILD layer 244 include compounds including Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers may be used for the ILD layer 244. After the ILD layer 244 is formed, a planarization operation such as CMP is performed to expose the sacrificial gate electrode layer 226 for subsequent removal of the sacrificial gate structure 228. During the removal of the sacrificial gate structure 228, the ILD layer 244 protects the epitaxial source / drain regions 240.

[0059] In operation 122, a replacement gate structure 250 is formed to replace the sacrificial gate structure 228, such as Fig.10. The sacrificial gate structure 228 is first removed. In particular, the sacrificial gate electrode layer 226 and the sacrificial gate dielectric layer 224 are removed in sequence to form a gate opening and expose the semiconductor stack 218. The sacrificial gate electrode layer 226 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 226 is polysilicon and the ILD layer 244 is silicon oxide, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 226 without removing the dielectric material of the ILD layer 244, the CESL 242, and the gate sidewall spacer layer 230. After removing the sacrificial gate electrode layer 226, the sacrificial gate dielectric layer 224 is exposed. The sacrificial gate dielectric layer 224 can be removed using a suitable etching method, such as plasma dry etching and / or wet etching.

[0060] After removing the sacrificial gate dielectric layer 224, the first semiconductor layer 214 and the second semiconductor layer 216 are exposed to the gate opening. Then, the first semiconductor layer 214 is selectively removed using an etchant having an etch rate relative to the first semiconductor layer 214 that is higher than the etch rate relative to the second semiconductor layer 216. When the first semiconductor layer 214 is Ge or SiGe and the second semiconductor layer 216 is Si, the first semiconductor layer 214 can be selectively removed using a wet etchant, such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP) or potassium hydroxide (KOH) solution. After removing the first semiconductor layer 214, the second semiconductor layer 216 is exposed to the gate opening, resulting in a semiconductor channel region including the second semiconductor layer 216 connected to the epitaxial source / drain region 240.

[0061] A replacement gate structure 250 is then formed around the channel region. A gate dielectric layer 246 is formed around each of the second semiconductor layers 216, and a gate electrode layer 248 is formed on the gate dielectric layer 246. The gate dielectric layer 246 and the gate electrode layer 248 may be referred to as a replacement gate structure 250.

[0062] The gate dielectric layer 246 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 246 is formed using a highly conformal deposition process such as ALD to ensure that the gate dielectric layer 246 having a uniform thickness is formed around each of the second semiconductor layer 216. In some embodiments, the thickness of the gate dielectric layer 246 is in a range between about 1 nm and about 6 nm.

[0063] The gate dielectric layer 246 includes one or more dielectric material layers, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials and / or combinations thereof. In some embodiments, an interfacial layer (not shown) is formed between the second semiconductor layer 216 and the gate dielectric layer 246. In some embodiments, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer 246 and the gate electrode layer 248.

[0064] The gate electrode layer 248 is formed on the gate dielectric layer 246 to surround each of the second semiconductor layer 216 (i.e., each channel) and the gate dielectric layer 246. The gate electrode layer 248 includes one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The gate electrode layer 248 can be formed by CVD, ALD, electroplating or other suitable methods.

[0065] After forming the gate electrode layer 248 , a planarization process, such as a CMP process, is performed to remove excess deposition of gate electrode material and expose a top surface of the ILD layer 244 .

[0066] In operation 124, a front side source / drain contact 252 is formed in the ILD layer 244 through the front side 240f of the epitaxial source / drain region 240, such as Fig.11 As shown in Fig.11 is a schematic perspective view of semiconductor device 200. Before forming front side source / drain contacts 252, contact holes are formed in portions of ILD layer 244, CESL 242, and epitaxial source / drain regions 240. Suitable photolithography and etching techniques are used to form contact holes through the various layers (including ILD layer 244 and CESL 242) to expose epitaxial source / drain regions 240.

[0067] After forming the contact holes, a silicide layer 254 is selectively formed over the exposed surface of the epitaxial source / drain region 240. The silicide layer 254 conductively couples the epitaxial source / drain region 240 to the subsequently formed front side source / drain contact 252. The silicide layer 254 can be formed by depositing a metal source layer to cover the epitaxial source / drain region 240 and performing a rapid thermal annealing process. In some embodiments, the metal source layer includes a metal layer selected from W, Co, Ni, Ti, Mo, and Ta or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. After forming the metal source layer, a rapid thermal annealing process is performed, for example, a rapid annealing at a temperature between about 700° C. and about 900° C. During the rapid annealing process, a portion of the metal source layer located over the epitaxial source / drain region 240 reacts with silicon in the epitaxial source / drain region 240 to form the silicide layer 254. The unreacted portion of the metal source layer is then removed. In some embodiments, the silicide layer 254 includes one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. In some embodiments, the silicide layer 254 has a thickness in a range between about 4 nm and 10 nm, for example, between 5 nm and 6 nm.

[0068] After forming the silicide layer 254, the front side source / drain contact 252 is formed in the contact hole by CVD, ALD, electroplating or other suitable methods. The front side source / drain contact 252 may contact the silicide layer 254. The front side source / drain contact 252 may include one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN. In some embodiments, before forming the front side source / drain contact 252, a barrier layer (not shown) may be formed on the sidewall of the contact hole.

[0069] In some embodiments, the front side source / drain contacts 252 are selectively formed over some of the epitaxial source / drain regions 240, depending on the circuit design. The front side source / drain contacts 252 are formed over the epitaxial source / drain regions 240, and the front side source / drain contacts 252 are designed to be directly connected to the subsequently formed front side interconnect structure (but not located over the epitaxial source / drain region 240), and the epitaxial source / drain region 240 is designed to be connected to the front side contacts of the signal line or power line formed on the back side. A suitable patterning process can be implemented to selectively form the front side source / drain contacts 252. In other embodiments, the front side source / drain contacts 252 are formed over the epitaxial source / drain regions 240 for structural balance in the circuit design, regardless of the subsequent design scheme. Some of the front side source / drain contacts 252 may be dummy contacts that are not connected to the interconnect structure.

[0070] In some embodiments, a gate contact may be formed by a self-aligned contact layer 251 to connect to the gate electrode layer 248. After forming the front side source / drain contacts 252 and forming the gate contacts, a front side interconnect structure 253 (details not shown) is formed by a middle end process. The front side interconnect structure 253 includes a plurality of dielectric layers in which metal lines and vias are formed. The metal lines and vias in the front side interconnect structure may be formed of copper or copper alloy using one or more damascene processes. The front side interconnect structure may include multiple sets of interlayer dielectric (ILD) layers and intermetallic dielectric (IMD) layers.

[0071] In operation 126, the semiconductor device 200 is turned over and a backside thinning process is performed, such as Fig.12 As shown in Fig.12 2 is a schematic perspective view of the semiconductor device 200. In some embodiments, a carrier wafer (not shown) can be bonded to the front side of the semiconductor device 200, and the substrate 210 can be flipped so that the back side (i.e., back side 210b) of the substrate 210 faces upward for back side processing. Back side grinding is performed to thin down the substrate 210. For example, back side grinding, such as a CMP process, can be performed to expose the buried source / drain features 236. Fig.12 As shown in , after the thinning process, the semiconductor device 200 forms a planar back side 210 b ′ including the isolation layer 222 , the well portion 212 , and the buried source / drain features 236 .

[0072] In operation 128, backside source / drain contact openings 258 are formed, such as Fig.13 As shown in Fig.13 2 is a perspective view of semiconductor device 200. In some embodiments, a mask layer 256 may be formed over back surface 210b'. Mask layer 256 is patterned to form openings 260 over selected source / drain regions 240 according to circuit design. A suitable patterning process is performed to form openings 260 through mask layer 256. In some embodiments, source / drain regions 240 are used as sources in semiconductor device 200.

[0073] Each opening 260 exposes a buried source / drain feature 236. The opening 260 is larger than the buried source / drain feature 236, thus exposing the adjacent well portion 212 and the isolation layer 222. Because the buried source / drain feature 236 and the well portion 212 of the substrate 210 have a high etch selectivity, the buried source / drain feature 236 can be selectively removed from the well portion 212, thereby forming a backside source / drain contact opening 258 aligned with the source / drain region 240. In some embodiments, the source / drain contact opening 258 can be formed by an isotropic etching process. During the removal of the buried source / drain feature 236, the semiconductor cap layer 238 acts as an etch stop layer to protect the source / drain region 240 from the etching chemistry.

[0074] After removing the buried source / drain features 236 , an etching process may be performed to remove the semiconductor capping layer 238 and expose the source / drain regions 240 .

[0075] In operation 130, backside source / drain contact pads 262 are formed on the sidewalls of the source / drain contact openings 258, such as Fig.14 As shown in Fig.14 is a perspective view of the semiconductor device 200 .

[0076] The back side source / drain contact liner 262 is intended to provide electrical isolation from the surrounding material for the subsequently formed back side source / drain contacts. The back side source / drain contact liner 262 may be formed by conformal formation of an insulating material and subsequent anisotropic etching (such as dry etching) to remove the insulating material from the horizontal surface. The back side source / drain contact liner 262 may have a thickness T in the range between about 0 nm and about 8 nm. 262 In some embodiments, the insulating material of the back side source / drain contact pad 262 may be a low-k dielectric material including Si, O, C, N. For example, the back side source / drain contact pad 262 may include SiO, SiN, SiON, SiOCN, SiCN, or a combination thereof.

[0077] like Fig.14 As shown in , depending on the relative sizes of the backside source / drain contact pad 262 and the inner spacers 232 , the backside source / drain contact pad 262 may contact the bottommost inner spacer 232L.

[0078] In operation 132, backside source / drain contacts 264 are formed in backside source / drain contact openings 258, such as Fig.15 As shown in Fig.152 is a schematic perspective view of a semiconductor device 200. In some embodiments, before forming the backside source / drain contact 264, a silicide layer 266 is first formed over the exposed source / drain region 240. In some embodiments, a plasma process can be used to implement a pre-cleaning process. After pre-cleaning, a metal source layer can be formed on the surface of the exposed source / drain region 240. The metal source layer can include W, Ru, Co, Cu, Ni, Ti, Mo and Ta or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride and tantalum nitride. Depositing the metal source layer is followed by a rapid thermal annealing process at a certain temperature to form a silicide layer 266 on the exposed surface of the epitaxial source / drain region 240. In some embodiments, the silicide layer 266 includes one or more of TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, Ysi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi and YbSi. In some embodiments, the silicide layer 266 has a thickness ranging between approximately 1 nm and 10 nm.

[0079] The back side source / drain contact 264 is formed in the back side source / drain contact opening 258. The back side source / drain contact 264 may be formed by filling the source / drain contact opening 258 with a conductive material. Fig.15 As shown in , the back side source / drain contact 264 is electrically connected to the source / drain region 240 via the silicide layer 266. The conductive material can be a metal, such as Ti, W, Ru, Mo, Co, Al, Cu or a compound thereof. In some embodiments, the conductive material is filled in the contact hole by CVD, ALD, electroplating or other suitable methods.

[0080] In operation 134, a planarization process is performed to remove excess conductive material and expose buried source / drain features 236, such as Fig.16 As shown in Fig.16 2 is a schematic perspective view of semiconductor device 200. A planarization process, such as CMP, is performed to expose isolation layer 222. Mask layer 256 and excess conductive material are removed from the CMP process, resulting in back side 210b". Fig.16 As shown in FIG. 1 , the back side 210 b ″ includes the isolation layer 222 , the back side source / drain contacts 264 , the back side source / drain contact pads 262 , the buried source / drain features 236 , and the well portion 212 .

[0081] In operation 136, the buried source / drain features 236 exposed on the back side 210b" are removed, as shown in FIG. Fig.17 As shown in Fig.172 is a schematic perspective view of the semiconductor device 200. One or more etching processes may be performed to remove the buried source / drain features 236. A cavity 268 is formed over the semiconductor cap layer 238.

[0082] In operation 138, the semiconductor cap layer 238 is at least partially removed from the via cavity 268, such as Fig.18 As shown in Fig.18 2 is a schematic perspective view of a semiconductor device 200. The semiconductor cap layer 238 may be selectively removed from the well portion 212 and the epitaxial source / drain region 240 of the substrate 210. Fig.18 As shown in , after the semiconductor capping layer 238 is removed, the lowermost inner spacer 232L and the gate sidewall spacer layer 230 may be exposed to the cavity 268 .

[0083] In operation 140, a dielectric fill layer 270 is deposited in the cavity 268, followed by a planarization process to expose the well portion 212 of the semiconductor fin 220, as shown in FIG. Fig.19 As shown in Fig.19 2 is a schematic perspective view of a semiconductor device 200. The dielectric fill layer 270 may be formed of any suitable dielectric material, such as a low-k dielectric material. In some embodiments, the dielectric fill layer 270 may be formed of SiO, SiOC, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, SiCN, or a combination thereof. In some embodiments, the dielectric fill layer 270 includes silicon nitride. The dielectric fill layer 270 is in direct contact with the source / drain region 240 and the well portion 212 of the semiconductor fin 220, and provides isolation between the source / drain region 240 and the well portion 212 of the semiconductor fin 220.

[0084] In operation 142, the well portion 212 of the semiconductor fin 220 is recessed to form a groove 272, such as Fig. 20 As shown in Fig. 20 2 is a schematic perspective view of semiconductor device 200. In some embodiments, well portion 212 is recessed to a depth in a range between 5 nm and about 40 nm. Well portion 212 is removed to have a sufficiently deep recess 272 for a dielectric plug sufficient to provide isolation between the remaining semiconductor material and a subsequently formed conductive layer. In some embodiments, remaining well portion 212 has a thickness T in a range between about 2 nm and about 30 nm. 212 .

[0085] In operation 144, a dielectric cap 274 is formed in the recess 272, such as FIG. 21A to FIG. 21B as shown in . Fig.21A is a schematic perspective view of a semiconductor device 200 . Fig.21Bis a schematic cross-sectional view of a semiconductor device.

[0086] The dielectric cap 274 may be formed by filling the recess 272 with a suitable dielectric material and a subsequent CMP process. The dielectric cap 274 may have a thickness T in a range between 5 nm and about 40 nm. 274 . The dielectric cap 274 may be formed of any suitable dielectric material, such as a low-k dielectric material. In some embodiments, the dielectric cap 274 may be formed of SiO, SiOC, AlO, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, SiCN, or a combination thereof. In some embodiments, the dielectric cap 274 includes silicon nitride. After operation 144, a backside interconnect structure may be formed to provide a conductive path to the backside source / drain contacts 264. The dielectric cap 274 may provide isolation between the well portion 212 of the semiconductor fin 220 and the conductive material in the subsequently formed backside interconnect structure. The dielectric cap 274 has a height H in the Z direction. 274 In some embodiments, the height H 274 In the range between about 5 nm and about 40 nm.

[0087] The backside source / drain contacts 264 according to the disclosed embodiments include unique structural features. Fig.21B As shown in FIG. 2 , the backside source / drain contact 264 includes a step 265 along a sidewall 264s of the well portion 212 facing the semiconductor fin 220. The step 265 reflects the step 233 formed at the entrance of the deep recess 235 during the front side processing. Due to the step 265, the backside source / drain contact 264 has a wider portion 264b adjacent to the source / drain region 240 and a narrower portion 264t at a distal end away from the source / drain region 240. In some embodiments, the wider portion 264b has a width W in the range between about 10 nm and about 50 nm along the x direction. 264b , and the narrower portion 264t has a width W in a range between about 8 nm and about 40 nm. 264t In some embodiments, the width W 264t With width W 264b The back side source / drain contact 264 has a height H along the Z direction. 264 In some embodiments, the height H 264 In some embodiments, the upper step 233u remains in the semiconductor device 200 and exists in the cross section of the source / drain region 240, such as Fig.21B as shown in .

[0088] As previously discussed, the bottom surface 240b has a concave profile due to the semiconductor cap layer 238. Even after the semiconductor cap layer 238 is removed, the bottom surface 240b maintains the same concave profile, or Fig.21B The smiley face outline shown in . Fig.21B In some embodiments, the bottom surface 240b is lower at the center region and higher near the lowermost inner spacer 232L. In some embodiments, the bottom surface 240b has a distance variation D between the center and the edge regions. 240 In some embodiments, the distance variation D 240 In the range between about 1 nm and 5 nm.

[0089] Fig. 22 A semiconductor device 200a according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200a is substantially similar to the semiconductor device 200, except that in the semiconductor device 200a, only the buried source / drain feature 236 on the drain side (or the side without the backside source / drain contact) is partially removed. The semiconductor cap layer 238 remains between the source / drain region 240 and the partially removed buried source / drain feature 236. In some embodiments, the semiconductor device 200a can be manufactured using the method 100, wherein operations 136, 138, and 140 are omitted, and in operation 142, the well portion 212 of the semiconductor fin 220 and the buried source / drain feature 236 are recessed.

[0090] Fig.23 A semiconductor device 200b according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200b is substantially similar to the semiconductor device 200, except that the semiconductor cap layer 238 is not removed in the semiconductor device 200b. The semiconductor cap layer 238 remains between the source / drain regions 240 and the dielectric fill layer 270. In some embodiments, the semiconductor device 200b can be manufactured using the method 100, wherein operation 138 is omitted.

[0091] Fig.24 A semiconductor device 200c according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200c is substantially similar to the semiconductor device 200, except that an air gap 271 is formed in the dielectric filling layer 270 in the semiconductor device 200c. In some embodiments, the semiconductor device 200c can be manufactured using the method 100, and the process parameters in operation 140 are selected to generate the air gap 271 in the dielectric filling layer 270.

[0092] Fig.25A semiconductor device 200d is schematically illustrated according to an embodiment of the present disclosure. The semiconductor device 200d is substantially similar to the semiconductor device 200a, except that the dielectric cap 274 is omitted. In some embodiments, the semiconductor device 200d can be manufactured using the method 100, wherein operations 136, 138, 140, 142, and 144 are omitted.

[0093] Fig.26 A semiconductor device 200e is schematically illustrated according to an embodiment of the present disclosure. The semiconductor device 200e is substantially similar to the semiconductor device 200b, except that the dielectric cap 274 is omitted. In some embodiments, the semiconductor device 200e can be manufactured using the method 100, wherein operations 138, 142, and 144 are omitted.

[0094] Fig. 27 A semiconductor device 200f according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200f is substantially similar to the semiconductor device 200, except that the dielectric cap 274 is omitted. In some embodiments, the semiconductor device 200f can be manufactured using the method 100, wherein operations 142 and 144 are omitted.

[0095] Fig.28 A semiconductor device 200g according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200g is substantially similar to the semiconductor device 200c, except that the dielectric cap 274 is omitted in the semiconductor device 200c, but remains in the semiconductor device 200g. In some embodiments, the semiconductor device 200g can be manufactured using the method 100, wherein operations 142 and 144 are omitted, and the process parameters in operation 140 are selected to generate air gaps 271 in the dielectric fill layer 270.

[0096] In the semiconductor devices 200 and 200a-200g, a backside source / drain recess is performed for all drain regions, wherein the buried source / drain features 236 are removed. Alternatively, the backside source / drain recess may be partially performed such that only a portion of the buried source / drain features 236 is removed, while a portion of the buried source / drain features 236 remains in the semiconductor device. Figure 29 to Figure 30 An embodiment with partially backside source / drain recesses is schematically shown.

[0097] Fig.29 A semiconductor device 200 h according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200 h is substantially similar to the semiconductor device 200 , except that buried source / drain features 236 remain on portions of the source / drain regions 240 .

[0098] Fig.30A semiconductor device 200 i according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200 i is substantially similar to the semiconductor device 200 e , except that buried source / drain features 236 remain on portions of the source / drain regions 240 .

[0099] Fig.31 A semiconductor device 200 j according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200 j is substantially similar to the semiconductor device 200 g except that buried source / drain features 236 remain on portions of the source / drain regions 240 .

[0100] Various embodiments or examples described herein provide multiple advantages over the prior art. Embodiments of the present disclosure provide methods of forming a semiconductor cap layer between a buried source / drain component and a source / drain region. The buried source / drain component and the semiconductor cap layer enable self-aligned backside source / drain contacts and backside isolation. The semiconductor cap layer serves as an etch stop layer during backside contact formation while enabling source / drain region growth without manufacturing losses, such as voids in the source / drain region.

[0101] It should be understood that not all advantages are necessarily discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0102] Some embodiments of the present disclosure provide methods. The methods include: forming a semiconductor fin on a front side of a substrate; forming a sacrificial gate structure above the semiconductor fin; etching the semiconductor fin and the substrate to form a first source / drain recess and a second source / drain recess on both sides of the sacrificial gate structure; depositing a first buried source / drain component and a second buried source / drain component in the first source / drain recess and the second source / drain recess; forming a first semiconductor cap layer and a second semiconductor cap layer above the first buried source / drain component and the second buried source / drain component; forming a first source / drain region and a second source / drain region above the first semiconductor cap layer and the second semiconductor cap layer; forming a replacement gate structure; thinning the back side of the substrate to expose the first buried source / drain component and the second buried source / drain component; removing the first buried source / drain component and the first semiconductor cap layer to expose the first source / drain region; and forming a first backside source / drain contact on the first source / drain region.

[0103] Some embodiments of the present disclosure provide methods. The methods include: forming a semiconductor fin on a front side of a substrate, wherein the semiconductor fin includes two or more first semiconductor layers interposed with two or more second semiconductor layers; forming isolation on the substrate and around a lower portion of the semiconductor fin; forming a sacrificial gate structure above the semiconductor fin; depositing a sidewall spacer layer; etching the semiconductor fin to a first depth; forming an inner spacer on an exposed end of the second semiconductor layer; etching the semiconductor fin to a second depth, wherein the second depth is greater than the first depth; forming buried source / drain features on both sides of the semiconductor fin; and forming a source / drain region above the buried source / drain features.

[0104] Some embodiments provide a semiconductor device. The semiconductor device includes: a first source / drain region; a second source / drain region; a semiconductor channel disposed between the first source / drain region and the second source / drain region, wherein the semiconductor channel includes two or more semiconductor layers; a gate dielectric layer formed around the two or more semiconductor layers; a gate electrode layer disposed on the gate dielectric layer; a first front side source / drain contact disposed on the front side of the first source / drain region; a first back side source / drain contact disposed on the back side of the first source / drain region; and a second front side source / drain contact disposed on the front side of the second source / drain region, wherein the back side of the second source / drain region has a convex shape.

[0105] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a semiconductor fin on a front side of a substrate; forming a sacrificial gate structure above the semiconductor fin; etching the semiconductor fin and the substrate to form a first source / drain groove and a second source / drain groove on both sides of the sacrificial gate structure; depositing a first buried source / drain component and a second buried source / drain component in the first source / drain groove and the second source / drain groove; forming a first semiconductor cap layer and a second semiconductor cap layer above the first buried source / drain component and the second buried source / drain component; forming a first source / drain region and a second source / drain region above the first semiconductor cap layer and the second semiconductor cap layer; forming a replacement gate structure; thinning the back side of the substrate to expose the first buried source / drain component and the second buried source / drain component; removing the first buried source / drain component and the first semiconductor cap layer to expose the first source / drain region; and forming a first back side source / drain contact on the first source / drain region.

[0106] In some embodiments, the method further comprises: before forming the first backside source / drain contact, forming a dielectric liner on the sidewalls of the opening above the first source / drain region. In some embodiments, the method further comprises: after forming the first backside source / drain contact, removing the second buried source / drain feature; and depositing a dielectric fill layer to replace the second buried source / drain feature. In some embodiments, the method further comprises: before depositing the dielectric fill layer, removing the second semiconductor cap layer to expose the second source / drain region. In some embodiments, depositing the dielectric fill layer comprises forming an air gap in the dielectric fill layer. In some embodiments, the method further comprises: etching a portion of the substrate to form a groove between the first backside source / drain contact and the dielectric fill layer; and depositing a dielectric cap in the groove. In some embodiments, the method further comprises: after forming the first backside source / drain contact, performing a planarization process to expose the substrate adjacent to the first backside source / drain contact; etching a portion of the substrate to form a groove in the substrate; and depositing a dielectric cap in the groove. In some embodiments, the method further includes etching a portion of the second buried source / drain feature, wherein the dielectric cap is deposited on the second buried source / drain feature and the substrate.

[0107] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a semiconductor fin on a front side of a substrate, wherein the semiconductor fin comprises two or more first semiconductor layers sandwiched between two or more second semiconductor layers; forming isolation on the substrate and around a lower portion of the semiconductor fin; forming a sacrificial gate structure above the semiconductor fin; depositing a sidewall spacer layer; etching the semiconductor fin to a first depth; forming an internal spacer on an exposed end of the second semiconductor layer; etching the semiconductor fin to a second depth, wherein the second depth is greater than the first depth; forming buried source / drain components on both sides of the semiconductor fin; and forming a source / drain region above the buried source / drain components.

[0108] In some embodiments, the method further comprises: forming a semiconductor cap layer over the buried source / drain feature, wherein the source / drain region is formed on the semiconductor cap layer. In some embodiments, the method further comprises: thinning the back side of the substrate to expose the buried source / drain feature; removing the buried source / drain feature to expose the source / drain region; and forming a back side source / drain contact on the source / drain region. In some embodiments, the method further comprises: depositing a protective layer over the sidewall spacer layer; and etching back the protective layer to expose the sidewall spacer layer on the top surface of the semiconductor fin. In some embodiments, the buried source / drain feature has a step at the first depth.

[0109] Some other embodiments of the present application provide a semiconductor device, including: a first source / drain region; a second source / drain region; a semiconductor channel, arranged between the first source / drain region and the second source / drain region, wherein the semiconductor channel includes two or more semiconductor layers; a gate dielectric layer, formed around the two or more semiconductor layers; a gate electrode layer, arranged on the gate dielectric layer; a first front side source / drain contact, arranged on the front side of the first source / drain region; a first back side source / drain contact, arranged on the back side of the first source / drain region; and a second front side source / drain contact, arranged on the front side of the second source / drain region, wherein the back side of the second source / drain region has a convex shape.

[0110] In some embodiments, the semiconductor device further comprises a semiconductor cap layer, and the back side of the second source / drain region contacts the semiconductor cap layer. In some embodiments, the semiconductor device further comprises a buried source / drain component in contact with the semiconductor cap layer. In some embodiments, the semiconductor device further comprises a dielectric filling layer in contact with the semiconductor cap layer. In some embodiments, the semiconductor device further comprises a dielectric filling layer in contact with the back side of the second source / drain region. In some embodiments, the first back side source / drain contact has a wider portion adjacent to the first source / drain region and a narrower portion disposed away from the first source / drain region. In some embodiments, the first back side source / drain contact comprises a step formed along a sidewall, and the step is formed between the wider portion and the narrower portion.

[0111] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a semiconductor fin on a front side of the substrate; forming a sacrificial gate structure over the semiconductor fin; etching the semiconductor fin and the substrate to form a first source / drain recess and a second source / drain recess on both sides of the sacrificial gate structure; depositing a first buried source / drain feature and a second buried source / drain feature in the first source / drain recess and the second source / drain recess; forming a first semiconductor cap layer and a second semiconductor cap layer over the first buried source / drain feature and the second buried source / drain feature; forming a first source / drain region and a second source / drain region over the first semiconductor cap layer and the second semiconductor cap layer; forming a replacement gate structure; thinning a back side of the substrate to expose the first buried source / drain feature and the second buried source / drain feature; removing the first buried source / drain feature and the first semiconductor cap layer to expose the first source / drain region; as well as A first backside source / drain contact is formed on the first source / drain region.

2. The method according to claim 1, further comprising: Prior to forming the first backside source / drain contact, a dielectric liner is formed on sidewalls of the opening over the first source / drain region.

3. The method according to claim 1, further comprising: after forming the first backside source / drain contact, removing the second buried source / drain feature; as well as A dielectric fill layer is deposited in place of the second buried source / drain features.

4. The method according to claim 3, further comprising: Before depositing the dielectric filling layer, the second semiconductor capping layer is removed to expose the second source / drain region.

5. The method according to claim 3, wherein: Depositing the dielectric fill layer includes forming air gaps in the dielectric fill layer.

6. The method according to claim 3, further comprising: etching a portion of the substrate to form a recess between the first backside source / drain contact and the dielectric fill layer; as well as A dielectric cap is deposited in the recess.

7. The method according to claim 1, further comprising: After forming the first backside source / drain contact, performing a planarization process to expose the substrate adjacent to the first backside source / drain contact; etching a portion of the substrate to form a recess in the substrate; as well as A dielectric cap is deposited in the recess.

8. The method according to claim 7, further comprising: A portion of the second buried source / drain feature is etched, wherein the dielectric cap is deposited on the second buried source / drain feature and the substrate.

9. A method for manufacturing a semiconductor device, comprising: forming a semiconductor fin on the front side of the substrate, wherein the semiconductor fin comprises two or more first semiconductor layers sandwiched between two or more second semiconductor layers; forming isolation on the substrate and around a lower portion of the semiconductor fin; forming a sacrificial gate structure over the semiconductor fin; depositing a sidewall spacer layer; etching the semiconductor fin to a first depth; forming an inner spacer on the exposed end of the second semiconductor layer; Etching the semiconductor fin to a second depth, wherein the second depth is greater than the first depth; forming buried source / drain features on both sides of the semiconductor fin; and A source / drain region is formed over the buried source / drain feature.

10. A semiconductor device comprising: a first source / drain region; a second source / drain region; a semiconductor channel disposed between the first source / drain region and the second source / drain region, wherein the semiconductor channel comprises two or more semiconductor layers; a gate dielectric layer formed around the two or more semiconductor layers; A gate electrode layer, disposed on the gate dielectric layer; a first front side source / drain contact disposed on the front side of the first source / drain region; a first backside source / drain contact disposed on the backside of the first source / drain region; and A second front side source / drain contact is disposed on a front side of the second source / drain region, wherein a back side of the second source / drain region has a convex shape.

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