Transistor circuit and manufacturing method thereof

Abstract

The invention provides a transistor circuit and a manufacturing method thereof, and belongs to the field of semiconductor devices. The transistor circuit includes: a first transistor and a second transistor; the first transistor and the second transistor comprise a common substrate, and a channel layer and a barrier layer which are sequentially stacked on the substrate; the barrier layer is provided with a groove extending into the channel layer; the first transistor further comprises a first dielectric layer, a first source electrode, a first drain electrode and a first grid electrode; the second transistor further comprises a second dielectric layer, a second source electrode, a second drain electrode and a second grid electrode; the first dielectric layer covers the bottom of the groove, the second dielectric layer is located on the barrier layer, and the first source electrode, the first drain electrode, the second source electrode and the second drain electrode penetrate through the barrier layer and are connected with the channel layer; the groove is located between the first source electrode and the first drain electrode, and the second dielectric layer is located between the second source electrode and the second drain electrode; the first gate is located in the groove, the second gate is located on the second dielectric layer, the first source is electrically connected with the second gate, and the first drain is electrically connected with the second source.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, and in particular to a transistor circuit and a manufacturing method thereof. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor that is widely used in various circuits.

[0003] The related technology provides a transistor circuit, which includes a first transistor and a second transistor, wherein the source of the first transistor is electrically connected to the gate of the second transistor, and the drain of the first transistor is electrically connected to the source of the second transistor, thereby achieving the effect of controlling the on and off of the second transistor by controlling the on and off of the first transistor.

[0004] In the above transistor circuit structure, the first transistor is an enhancement-mode HEMT, and the second transistor is a metal-oxide-semiconductor field-effect transistor (MOSFET). On the one hand, if an enhancement-mode HEMT is to be realized, an additional P-type GaN layer needs to be provided in the above transistor structure, which makes the process difficult. On the other hand, the first transistor and the second transistor need to be manufactured separately, which makes the process complicated, and the wire bonding connection after the separate manufacturing will increase additional parasitic effects. Summary of the invention

[0005] The disclosed embodiment provides a transistor circuit and a manufacturing method thereof, which can reduce the difficulty of the manufacturing process of the enhanced HEMT, and the transistors in the transistor circuit can be manufactured at the same time, reducing the manufacturing complexity. The technical solution is as follows:

[0006] In one aspect, a transistor circuit is provided, the transistor circuit comprising: a first transistor and a second transistor;

[0007] The first transistor and the second transistor include a common substrate, a channel layer and a barrier layer sequentially stacked on the substrate; the barrier layer has a groove extending into the channel layer;

[0008] The first transistor further comprises a first dielectric layer, a first source, a first drain and a first gate; the second transistor further comprises a second dielectric layer, a second source, a second drain and a second gate;

[0009] The first dielectric layer covers the bottom of the groove, the second dielectric layer is located on the barrier layer, the first source, the first drain, the second source, and the second drain penetrate the barrier layer and are connected to the channel layer; the groove is located between the first source and the first drain, and the second dielectric layer is located between the second source and the second drain;

[0010] The first gate is located in the groove, the second gate is located on the second dielectric layer, the first source is electrically connected to the second gate, and the first drain is electrically connected to the second source.

[0011] Optionally, along a direction perpendicular to the substrate, a width A of the groove cross section is 0.5 to 2 μm, and a depth B of the groove cross section is 30 to 100 nm.

[0012] Optionally, the first dielectric layer and the second dielectric layer have a thickness of 10-50 nm.

[0013] Optionally, along a direction from the first source electrode to the first drain electrode, a distance X from the first dielectric layer to the first drain electrode is 5-7 μm.

[0014] Optionally, along a direction from the second source to the second drain, a width Y of the second dielectric layer not covered by the second gate is 15-21 μm.

[0015] Optionally, the first gate and the second gate each include a main body, a first extension and a second extension; the second extension, the first extension and the main body are in a two-step structure, and at least part of the main body of the first gate is located in the groove.

[0016] Optionally, along a direction perpendicular to the substrate,

[0017] The width C of the cross section of the first extension portion is greater than the width A of the cross section of the groove;

[0018] A width D of a cross section of the second extension portion is greater than a width A of a cross section of the groove.

[0019] Optionally, a threshold voltage of the first transistor is related to a stress level of the first dielectric layer.

[0020] Optionally, the first drain and the second source share a same electrode.

[0021] In another aspect, a method for manufacturing a transistor circuit is provided, the method comprising:

[0022] forming a channel layer on a substrate;

[0023] forming a barrier layer on the channel layer, wherein the barrier layer has a groove extending into the channel layer;

[0024] Forming a first dielectric layer and a second dielectric layer on the barrier layer, wherein the first dielectric layer covers the bottom of the groove, and the second dielectric layer is located on the barrier layer;

[0025] Manufacturing a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode penetrate the barrier layer and are connected to the channel layer; the groove is located between the first source electrode and the first drain electrode, and the second dielectric layer is located between the second source electrode and the second drain electrode;

[0026] A first gate and a second gate are manufactured, wherein the first gate is located in the groove, the second gate is located on the second dielectric layer, the first source is electrically connected to the second gate, and the first drain is electrically connected to the second source.

[0027] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0028] In the disclosed embodiment, a channel layer and a barrier layer are sequentially formed on the substrate, wherein a groove extending to the channel layer is provided in the barrier layer, a first dielectric layer is provided in the groove, and then a first gate is provided in the groove. By providing a groove, the concentration of the two-dimensional electron gas (2DEG) can be changed, and a first dielectric layer is provided in the groove. The first dielectric layer will introduce stress during the growth process, and the stress will change the degree of polarization of the heterojunction and change the concentration of 2DEG, thereby being able to adjust the threshold voltage of the transistor. Therefore, this method can adjust the threshold voltage to obtain an enhanced first transistor without growing a P-GaN layer, thereby reducing the difficulty of the manufacturing process of the enhanced transistor. At the same time, the second transistor does not provide a groove, and a second dielectric layer is directly provided to form a depletion-type transistor to replace the MOSFET. In this transistor circuit, the first transistor and the second transistor can be manufactured at the same time, thereby reducing the manufacturing complexity and avoiding parasitic effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 is a circuit diagram of a transistor circuit provided by an embodiment of the present disclosure;

[0031] Figure 2is a schematic diagram of a transistor circuit provided by an embodiment of the present disclosure;

[0032] Figure 3 A schematic diagram of the structure of another transistor circuit provided in an embodiment of the present disclosure;

[0033] Figure 4 is a schematic diagram of a transistor circuit package provided by an embodiment of the present disclosure;

[0034] Figure 5 is a flow chart of a method for manufacturing a transistor circuit provided by an embodiment of the present disclosure;

[0035] Figure 6 It is a flow chart of another method for manufacturing a transistor circuit provided in an embodiment of the present disclosure.

[0036] The reference numerals are as follows:

[0037] 10: first transistor; 20: second transistor; 100: substrate; 101: channel layer; 102: barrier layer; 120: groove; 131: first dielectric layer; 132: second dielectric layer; 141: first source; 151: first drain; 161: first gate; 142: second source; 152: second drain; 162: second gate; 143: source connection portion; 107: nucleation layer; 108: buffer layer; 109: interlayer insulating layer; 1601: main body; 1602: first extension portion; 1603: second extension portion; 1410: source pin; 1510: drain pin; 1610: gate pin; 2000: epitaxial structure. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0039] Figure 1 is a circuit diagram of a transistor circuit provided by an embodiment of the present disclosure. Figure 1 As shown, the transistor circuit includes a first transistor 10 and a second transistor 20 , wherein the first source 141 of the first transistor 10 is electrically connected to the second gate 162 of the second transistor 20 , and the first drain 151 of the first transistor 10 is electrically connected to the second source 142 of the second transistor 20 .

[0040] Figure 2 is a schematic diagram of a transistor circuit provided by an embodiment of the present disclosure. Figure 2 The first transistor 10 and the second transistor 20 include a common substrate 100 , a channel layer 101 and a barrier layer 102 sequentially stacked on the substrate 100 ; the barrier layer 102 has a groove 120 extending into the channel layer 101 .

[0041] The first transistor 10 further includes a first dielectric layer 131 , a first source 141 , a first drain 151 and a first gate 161 ; the second transistor 20 further includes a second dielectric layer 132 , a second source 142 , a second drain 152 and a second gate 162 .

[0042] The first dielectric layer 131 covers the bottom of the groove 120, the second dielectric layer 132 is located in the barrier layer 102, the first source 141, the first drain 151, the second source 142, and the second drain 152 penetrate the barrier layer 102 and are connected to the channel layer 101; the groove 120 is located between the first source 141 and the first drain 151, and the second dielectric layer 132 is located between the second source 142 and the second drain 152.

[0043] The first gate 161 is located in the groove 120 , and the second gate 162 is located on the second dielectric layer 132 .

[0044] It should be noted that Figure 2 Only the hierarchical structure of the transistor is shown, and the connection relationship between electrodes is not shown.

[0045] In the disclosed embodiment, a channel layer and a barrier layer are sequentially formed on the substrate, wherein a groove extending to the channel layer is provided in the barrier layer, a first dielectric layer is provided in the groove, and then a first gate is provided in the groove. By providing a groove, the concentration of the two-dimensional electron gas (2DEG) can be changed, and a first dielectric layer is provided in the groove. The first dielectric layer will introduce stress during the growth process, and the stress will change the degree of polarization of the heterojunction and change the concentration of 2DEG, thereby being able to adjust the threshold voltage of the transistor. Therefore, this method can adjust the threshold voltage to obtain an enhanced first transistor without growing a P-GaN layer, thereby reducing the difficulty of the manufacturing process of the enhanced transistor. At the same time, the second transistor does not provide a groove, and a second dielectric layer is directly provided to form a depletion-type transistor to replace the MOSFET. In this transistor circuit, the first transistor and the second transistor can be manufactured at the same time, thereby reducing the manufacturing complexity and avoiding parasitic effects.

[0046] In the first transistor, the threshold voltage of the first transistor can be adjusted between -20 and +10 V by designing the first dielectric layer and the groove, for example, the threshold voltage is controlled within 1 to 5 V to realize an enhanced transistor (E-mode) without providing a P-GaN layer.

[0047] In the second transistor, a depletion mode transistor (D-mode) is formed by providing a second dielectric layer but not providing a groove, and the threshold voltage may be -12 to -16V.

[0048] In the embodiment of the present disclosure, the first dielectric layer and the second dielectric layer also play the role of isolating the gate metal and the semiconductor, forming a Metal Insulation Semiconductor Field Effect Transistor (MISFET) structure, which can increase the gate breakdown resistance so that the transistor threshold withstand voltage reaches -30V to +30V and the collapse voltage is greater than 1200V.

[0049] In the embodiment of the present disclosure, the substrate 100 may be a Si substrate, a SiC substrate, a sapphire substrate, or the like.

[0050] In the embodiment of the present disclosure, the channel layer 101 may be a non-doped GaN channel layer.

[0051] The thickness of the channel layer 101 may be 1-5 μm.

[0052] Exemplarily, the thickness of the channel layer 101 is 3 μm.

[0053] In the embodiment of the present disclosure, the barrier layer 102 may be Al x Ga 1-x N barrier layer, the barrier layer 102 and the channel layer 101 form a two-dimensional electron gas (2DEG), wherein the value of x is 0.1-0.3.

[0054] The barrier layer 102 may have a thickness of 3-30 nm.

[0055] Exemplarily, the thickness of the barrier layer 102 is 20 nm.

[0056] It can be seen that the transistor is a GaN / AlGaN device. Based on the characteristics of the GaN / AlGaN device, it can also achieve no hysteresis phenomenon and enhance the sensitivity of the transistor circuit.

[0057] In the embodiment of the present disclosure, along a direction perpendicular to the substrate 100 , a width A of a cross section of the groove 120 is greater than a depth B of the cross section of the groove 120 .

[0058] It is worth noting that the attached drawings are only structural examples and do not show the size multiples between the film layers.

[0059] Illustratively, along a direction perpendicular to the substrate 100 , a width A of a cross section of the groove 120 is 0.5 to 2 μm, and a depth B of a cross section of the groove 120 is 30 to 100 nm.

[0060] For example, along a direction perpendicular to the substrate 100 , a width A of a cross section of the groove 120 is 1 μm, and a depth B of a cross section of the groove 120 is 30 nm.

[0061] In this implementation, a groove with a relatively large width is provided to avoid the short channel effect caused by a gate length that is too small. In addition, the groove with the above size is provided to ensure that the dielectric layer located in the groove can play a role in adjusting the threshold voltage.

[0062] In the embodiment of the present disclosure, the depth of the groove 120 can be opened to the channel layer, so that the 2DEG is etched through, so that the threshold voltage of the first transistor can be adjusted to a positive voltage.

[0063] In the embodiment of the present disclosure, the first dielectric layer and the second dielectric layer can be manufactured by a chemical vapor deposition (CVD) process. For example, the first dielectric layer and the second dielectric layer can be manufactured by a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure chemical vapor deposition (LPCVD) process, an atomic layer deposition (ALD) process, a metal organic chemical vapor deposition (MOCVD) process or a molecular beam epitaxy (MBE) process.

[0064] In the embodiment of the present disclosure, the thickness of the first dielectric layer 131 and the second dielectric layer 132 may be 10 nm to 50 nm, and the thickness is selected within this numerical range according to the threshold voltage requirement.

[0065] Selecting the thickness within this thickness range can provide a sufficient range for adjusting the threshold voltage while not making the overall size of the transistor too large.

[0066] In the embodiment of the present disclosure, the material of the first dielectric layer 131 and the second dielectric layer 132 may be silicon nitride, silicon oxide, aluminum oxide or aluminum nitride.

[0067] In the embodiment of the present disclosure, the threshold voltage of the first transistor is related to the stress of the first dielectric layer 131 .

[0068] In the disclosed embodiment, the formation principle of 2DEG between the barrier layer 102 and the channel layer 101 is the mixed effect of spontaneous polarization and piezoelectric polarization. The stress of the first dielectric layer is equivalent to regulating the degree of piezoelectric polarization, which can control the concentration of 2DEG and thus change the threshold voltage.

[0069] The first dielectric layer acts as a field effect control layer, reduces gate leakage and increases gate withstand voltage. The barrier layer is affected by applying internal stress during the growth of the first dielectric layer, thereby achieving the purpose of adjusting the threshold voltage in a small range.

[0070] In the embodiments of the present disclosure, the threshold voltage of the transistor is greater than 0 in any of the following cases, that is, an enhancement mode transistor (E-mode) is implemented:

[0071] The first dielectric layer 131 has a compressive stress (compressive) ≥ 0, and the greater the compressive stress, the greater the threshold voltage.

[0072] Among them, compressive stress will cause the threshold voltage to shift positively, while tensile stress will cause the threshold voltage to shift negatively.

[0073] In the embodiment of the present disclosure, when the groove depth and the thickness of the first dielectric layer are used, the corresponding relationship between the stress and the threshold voltage of the first dielectric layer can be experimentally determined. During manufacturing, the required stress can be determined based on the target threshold voltage and the corresponding relationship.

[0074] In the embodiments of the present disclosure, the stress of the first dielectric layer is introduced during the growth process. For example, when the first dielectric layer is produced, the stress can be controlled by controlling the frequency of the deposition equipment and / or the ratio of elements. For example, when the first dielectric layer is made of silicon nitride material, controlling the ratio of Si and N can change the silicon nitride composition and the size of the optical band gap, thereby adjusting the stress applied to the first dielectric layer during the growth process. The process is convenient and easy to implement.

[0075] During the experiment, the stress of the first dielectric layer can be measured by mechanical method, interference method, diffraction method, etc. Among them, the mechanical method and interference method indirectly infer the stress by measuring the bending degree of the substrate, while the diffraction method obtains stress information by measuring the change of the lattice constant of the film. In addition, the X-ray diffraction method can also characterize the internal stress.

[0076] In the embodiment of the present disclosure, the first source electrode 141 , the first drain electrode 151 , the second source electrode 142 , and the second drain electrode 152 may each include a Ti sublayer, an Al sublayer, a Ni sublayer, and an Au sublayer stacked in sequence.

[0077] In the embodiment of the present disclosure, the Ti sublayer and the Ni sublayer in the source and the drain are used to improve the adhesion between the sublayers and between the sublayers and the barrier layer, the Al sublayer is used to ensure the conductivity of the electrode, and the Au sublayer is used to protect the other sublayers to prevent the source and the drain from being oxidized or corroded.

[0078] In the source and drain electrodes, the thickness of the Ti sublayer may be 5 to 30 nm, the thickness of the Al sublayer may be 100 to 200 nm, the thickness of the Ni sublayer may be 30 to 80 nm, and the thickness of the Au sublayer may be 30 to 80 nm.

[0079] Exemplarily, in the source and drain electrodes, the thickness of the Ti sublayer is 20 nm, the thickness of the Al sublayer is 120 nm, the thickness of the Ni sublayer is 40 nm, and the thickness of the Au sublayer is 50 nm.

[0080] In the embodiment of the present disclosure, the first gate 161 and the second gate 162 include a Ni sublayer and an Au sublayer, wherein the Ni sublayer is used to improve the adhesion between the sublayers, and the Au sublayer is used to protect the other sublayers from being oxidized or corroded.

[0081] In the gate electrode, the thickness of the Ni sublayer may be 10 to 50 nm, and the thickness of the Au sublayer may be 10 to 50 nm.

[0082] Exemplarily, in the gate, the thickness of the Ni sublayer is 40 nm, and the thickness of the Au sublayer is 50 nm.

[0083] Figure 3 is a schematic diagram of the structure of another transistor circuit provided by an embodiment of the present disclosure. Figure 3 As shown, the transistor circuit may further include a nucleation layer 107 and a buffer layer 108, which are sequentially stacked between the substrate 100 and the channel layer 101. The first transistor 10 and the second transistor 20 share the nucleation layer 107 and the buffer layer 108.

[0084] In the embodiment of the present disclosure, the nucleation layer 107 may be an AlN nucleation layer.

[0085] The thickness of the nucleation layer 107 may be 100-300 nm.

[0086] Exemplarily, the thickness of the nucleation layer 107 is 200 nm.

[0087] In the embodiment of the present disclosure, the buffer layer 108 may be a GaN buffer layer and / or an AlGaN buffer layer.

[0088] The thickness of the buffer layer 108 is 500-2000 nm.

[0089] Exemplarily, the thickness of the buffer layer 108 is 1000 nm.

[0090] In the embodiment of the present disclosure, if the thickness of the buffer layer is relatively thick, the manufacturing cost will increase. If the thickness of the buffer layer is relatively thin, it will be detrimental to the buffering effect of the buffer layer, and a good growth interface cannot be formed on the surface of the buffer layer, which is detrimental to the growth of subsequent device layers.

[0091] Alternatively, if Figure 3 As shown, the transistor may further include an interlayer insulating layer 109 , which is located between the first source electrode 141 and the second drain electrode 152 and covers the first gate electrode 161 and the second gate electrode 162 .

[0092] In the embodiment of the present disclosure, the interlayer insulating layer 109 may be a SiN layer, a SiO 2 layer or an Al 2 O 3 layer.

[0093] In the embodiment of the present disclosure, the thickness of the interlayer insulating layer 109 may be 0.1-10 μm.

[0094] Illustratively, the thickness of the interlayer insulating layer 109 is 5 μm.

[0095] See again Figure 3 The first gate 161 and the second gate 162 both include a main body 1601, a first extension portion 1602 and a second extension portion 1603; the second extension portion 1603, the first extension portion 1602 and the main body 1601 present a two-step structure, and at least part of the main body 1601 of the first gate 161 is located in the groove 120.

[0096] By providing the first extension portion 1602 and the second extension portion 1603, a field plate structure design is formed, so that the electric field is distributed around the field plate rather than at a single point, that is, the electric field strength is sequentially transferred to the first extension portion 1602 and the second extension portion 1603, so that the high-voltage electric field of the drain is evenly distributed around the field plate, thereby increasing the breakdown voltage and making the maximum breakdown voltage of the device greater than 1200V (4*300V / 1μm gallium nitride material characteristics).

[0097] See also Figure 3 In the embodiment of the present disclosure, the first source 141 is connected to the source connecting portion 143, and is connected to the source connecting portion 143 on the bottom surface of the substrate 100 through the source connecting portion 143 passing through the semiconductor structure layer (insulated through), and is then electrically connected to the second gate 162 through the source connecting portion 143 passing through the semiconductor structure layer (insulated through).

[0098] See also Figure 3 In the embodiment of the present disclosure, the first drain electrode 151 and the second source electrode 142 share the same electrode. This method not only realizes the electrical connection between the first drain electrode 151 and the second source electrode 142, but also facilitates manufacturing.

[0099] In the embodiment of the present disclosure, along a direction perpendicular to the substrate 100,

[0100] The width C of the cross section of the first extension portion 1602 is greater than the width A of the cross section of the groove 120;

[0101] A width D of a cross section of the second extension portion 1603 is greater than a width A of a cross section of the groove 120 .

[0102] In the embodiment of the present disclosure, the width C is 2 to 3 times the width A;

[0103] The width D is 2 to 3 times the width A.

[0104] For example, the width C is twice the width A;

[0105] The width D is twice the width A.

[0106] Since the field plate design is related to the height and length of the field plate, the use of the above dimensions can better achieve the transfer of electric field strength and improve the voltage resistance, breakdown voltage and other performance of the transistor.

[0107] like Figure 3 As shown, along the direction from the first source 141 to the first drain 151 , the distance X from the first dielectric layer 131 to the first drain 151 is 5-7 μm.

[0108] Exemplarily, X is 6 μm.

[0109] like Figure 3 As shown, along the direction from the second source 142 to the second drain 152 , the width Y of the second dielectric layer 132 not covered by the second gate 162 is 15-21 μm.

[0110] Exemplarily, Y is 18 μm.

[0111] In this implementation, the above value of Y is adopted, so that the second transistor can withstand a larger voltage.

[0112] In the transistor circuit provided by the embodiment of the present disclosure, the first transistor and the second transistor are manufactured at the same time, so the integration is higher and the packaging is simpler.

[0113] Figure 4 is a schematic diagram of a transistor circuit package provided by an embodiment of the present disclosure. Figure 4 When packaging the transistor circuit provided by the embodiment of the present disclosure, two transistors are packaged on the same circuit board, wherein the reference numerals 1410, 1510 and 1610 are the source pin, the drain pin and the gate pin on the circuit board, respectively, wherein the source pin 1410 and the gate pin 1610 are input pins, and the drain pin 1510 is an output pin. The gate pin 1610 is connected to the first gate 161, the source pin 1410 is connected to the second source 142, the drain pin 1510 is connected to the second drain 152, and the second gate 162 is connected to the first source 141, and no connection pin control is required. Figure 4 As shown, the left epitaxial structure 2000 is the epitaxial structure of the first transistor, and the right epitaxial structure 2000 is the epitaxial structure of the second transistor.

[0114] The transistor circuit provided in the embodiment of the present disclosure can be called a cascade circuit. Although the circuit includes two transistors, it still only needs two signals when working. One signal controls the gate of the first transistor; the other signal is transmitted to the drain of the first transistor and the source of the second transistor. The signal transmitted to the drain of the first transistor controls the gate of the second transistor through the source of the first transistor when the first transistor is turned on, and the signal transmitted to the source of the second transistor is output through the drain of the second transistor when the second transistor is turned on.

[0115] Figure 5 is a flow chart of a method for manufacturing a transistor circuit provided by an embodiment of the present disclosure, which is used to manufacture the transistor described above. Figure 5 The method steps include:

[0116] S11. Fabricating a channel layer on a substrate.

[0117] S12, forming a barrier layer on the channel layer, wherein the barrier layer has a groove extending into the channel layer.

[0118] S13, forming a first dielectric layer and a second dielectric layer on the barrier layer, wherein the first dielectric layer covers the bottom of the groove, and the second dielectric layer is located on the barrier layer.

[0119] S14, manufacturing a first source, a first drain, a second source and a second drain, wherein the first source, the first drain, the second source and the second drain penetrate the barrier layer and are connected to the channel layer; the groove is located between the first source and the first drain, and the second dielectric layer is located between the second source and the second drain.

[0120] S15, manufacturing a first gate and a second gate, wherein the first gate is located in the groove, the second gate is located on the second dielectric layer, the first source is electrically connected to the second gate, and the first drain is electrically connected to the second source.

[0121] In the disclosed embodiment, a channel layer and a barrier layer are sequentially formed on the substrate, wherein a groove extending to the channel layer is provided in the barrier layer, a first dielectric layer is provided in the groove, and then a first gate is provided in the groove. By providing a groove, the concentration of the two-dimensional electron gas (2DEG) can be changed, and a first dielectric layer is provided in the groove. The first dielectric layer will introduce stress during the growth process, and the stress will change the degree of polarization of the heterojunction and change the concentration of 2DEG, thereby being able to adjust the threshold voltage of the transistor. Therefore, this method can adjust the threshold voltage to obtain an enhanced first transistor without growing a P-GaN layer, thereby reducing the difficulty of the manufacturing process of the enhanced transistor. At the same time, the second transistor does not provide a groove, and a second dielectric layer is directly provided to form a depletion-type transistor to replace the MOSFET. In this transistor circuit, the first transistor and the second transistor can be manufactured at the same time, thereby reducing the manufacturing complexity and avoiding parasitic effects.

[0122] Figure 6 is a flow chart of another method for manufacturing a transistor circuit provided by an embodiment of the present disclosure, which is used to manufacture the transistor described above. Figure 6 The method steps include:

[0123] S21. Growing a nucleation layer on the substrate.

[0124] In the embodiment of the present disclosure, the substrate is one of a Si substrate, a SiC substrate, a sapphire substrate and the like.

[0125] In the embodiment of the present disclosure, the nucleation layer 107 may be an AlN nucleation layer.

[0126] The thickness of the nucleation layer 107 may be 100-300 nm.

[0127] Exemplarily, the thickness of the nucleation layer 107 is 200 nm.

[0128] In the embodiments of the present disclosure, high-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixed gas of high-purity H2 and high-purity N2 is used as a carrier gas, high-purity NH3 is used as a nitrogen source, trimethylgallium (TMGa) and triethylgallium (TEGa) are used as gallium sources, trimethylindium (TMIn) is used as an indium source, silane (SiH4) is used as an N-type dopant, trimethylaluminum (TMAl) is used as an aluminum source, and bis(cyclopentadienyl)magnesium (CP2Mg) is used as a P-type dopant.

[0129] S22. Growing a buffer layer on the nucleation layer.

[0130] In the embodiment of the present disclosure, the buffer layer 108 may be a GaN buffer layer and / or an AlGaN buffer layer.

[0131] The thickness of the buffer layer 108 is 500-2000 nm.

[0132] Exemplarily, the thickness of the buffer layer 108 is 1000 nm.

[0133] In the embodiment of the present disclosure, if the thickness of the buffer layer is relatively thick, the manufacturing cost will increase. If the thickness of the buffer layer is relatively thin, it will be detrimental to the buffering effect of the buffer layer, and a good growth interface cannot be formed on the surface of the buffer layer, which is detrimental to the growth of subsequent device layers.

[0134] S23 . Growing a channel layer on the buffer layer.

[0135] In the embodiment of the present disclosure, the channel layer 101 may be a non-doped GaN channel layer.

[0136] The thickness of the channel layer 101 may be 1-5 μm.

[0137] Exemplarily, the thickness of the channel layer 101 is 3 μm.

[0138] S24 . Growing a barrier layer on the channel layer, wherein the barrier layer has a groove extending into the channel layer.

[0139] In the embodiment of the present disclosure, the barrier layer 102 may be Al x Ga 1-x N barrier layer, the barrier layer 102 and the channel layer 101 form a two-dimensional electron gas (2DEG), wherein the value of x is 0.1-0.3.

[0140] The barrier layer 102 may have a thickness of 3-30 nm.

[0141] Exemplarily, the thickness of the barrier layer 102 is 20 nm.

[0142] It can be seen that the transistor is a GaN / AlGaN device. Based on the characteristics of the GaN / AlGaN device, it can also achieve no hysteresis phenomenon and enhance the sensitivity of the transistor circuit.

[0143] In the embodiment of the present disclosure, along a direction perpendicular to the substrate 100 , a width A of a cross section of the groove 120 is greater than a depth B of the cross section of the groove 120 .

[0144] Illustratively, along a direction perpendicular to the substrate 100 , a width A of a cross section of the groove 120 is 0.5 to 2 μm, and a depth B of a cross section of the groove 120 is 30 to 100 nm.

[0145] For example, along a direction perpendicular to the substrate 100 , a width A of a cross section of the groove 120 is 1 μm, and a depth B of a cross section of the groove 120 is 30 nm.

[0146] In this implementation, a groove with a relatively large width is provided to avoid the short channel effect caused by a gate length that is too small. In addition, the groove with the above size is provided to ensure that the dielectric layer located in the groove can play a role in adjusting the threshold voltage.

[0147] In the embodiment of the present disclosure, the depth of the groove 120 can be opened to the channel layer, so that the 2DEG is etched through, so that the threshold voltage of the first transistor can be adjusted to a positive voltage.

[0148] S25, forming a first dielectric layer and a second dielectric layer on the barrier layer, wherein the first dielectric layer covers the bottom of the groove, and the second dielectric layer is located on the barrier layer.

[0149] In the embodiment of the present disclosure, the first dielectric layer and the second dielectric layer can be manufactured by a CVD process. For example, the first dielectric layer and the second dielectric layer can be manufactured by a PECVD process, a LPCVD process, an ALD process, a MOCVD process, or an MBE process.

[0150] In the embodiment of the present disclosure, the thickness of the first dielectric layer 131 and the second dielectric layer 132 may be 10 nm to 50 nm, and the thickness is selected within this numerical range according to the threshold voltage requirement.

[0151] Selecting the thickness within this thickness range can provide a sufficient range for adjusting the threshold voltage while not making the overall size of the transistor too large.

[0152] In the embodiment of the present disclosure, the material of the first dielectric layer 131 and the second dielectric layer 132 may be silicon nitride, silicon oxide, aluminum oxide or aluminum nitride.

[0153] In the embodiment of the present disclosure, the threshold voltage of the first transistor is related to the stress of the first dielectric layer 131 .

[0154] In the disclosed embodiment, the formation principle of 2DEG between the barrier layer 102 and the channel layer 101 is the mixed effect of spontaneous polarization and piezoelectric polarization. The stress of the first dielectric layer is equivalent to regulating the degree of piezoelectric polarization, which can control the concentration of 2DEG and thus change the threshold voltage.

[0155] The first dielectric layer acts as a field effect control layer, reduces gate leakage and increases gate withstand voltage. The barrier layer is affected by applying internal stress during the growth of the first dielectric layer, thereby achieving the purpose of adjusting the threshold voltage in a small range.

[0156] In the embodiments of the present disclosure, the threshold voltage of the transistor is greater than 0 in any of the following cases, that is, an enhancement mode transistor (E-mode) is implemented:

[0157] The first dielectric layer 131 has a compressive stress (compressive) ≥ 0, and the greater the compressive stress, the greater the threshold voltage.

[0158] Among them, compressive stress will cause the threshold voltage to shift positively, while tensile stress will cause the threshold voltage to shift negatively.

[0159] In the embodiment of the present disclosure, when the groove depth and the thickness of the first dielectric layer are used, the corresponding relationship between the stress and the threshold voltage of the first dielectric layer can be experimentally determined. During manufacturing, the required stress can be determined based on the target threshold voltage and the corresponding relationship.

[0160] In the embodiments of the present disclosure, the stress of the first dielectric layer is introduced during the growth process. For example, when the first dielectric layer is produced, the stress can be controlled by controlling the frequency of the deposition equipment and / or the ratio of elements. For example, when the first dielectric layer is made of silicon nitride material, controlling the ratio of Si and N can change the silicon nitride composition and the size of the optical band gap, thereby adjusting the stress applied to the first dielectric layer during the growth process. The process is convenient and easy to implement.

[0161] During the experiment, the stress of the first dielectric layer can be measured by mechanical method, interference method, diffraction method, etc. Among them, the mechanical method and interference method indirectly infer the stress by measuring the bending degree of the substrate, while the diffraction method obtains stress information by measuring the change of the lattice constant of the film. In addition, the X-ray diffraction method can also characterize the internal stress.

[0162] S26, manufacturing a first gate and a second gate, wherein the first gate is located in the groove, and the second gate is located on the second dielectric layer.

[0163] In the embodiment of the present disclosure, the first gate 161 and the second gate 162 include a Ni sublayer and an Au sublayer, wherein the Ni sublayer is used to improve the adhesion between the sublayers, and the Au sublayer is used to protect the other sublayers from being oxidized or corroded.

[0164] In the gate electrode, the thickness of the Ni sublayer may be 10 to 50 nm, and the thickness of the Au sublayer may be 10 to 50 nm.

[0165] Exemplarily, in the gate, the thickness of the Ni sublayer is 40 nm, and the thickness of the Au sublayer is 50 nm.

[0166] See again Figure 3 The first gate 161 and the second gate 162 both include a main body 1601, a first extension portion 1602 and a second extension portion 1603; the second extension portion 1603, the first extension portion 1602 and the main body 1601 present a two-step structure, and at least part of the main body 1601 of the first gate 161 is located in the groove 120.

[0167] By providing the first extension portion 1602 and the second extension portion 1603, a field plate structure design is formed, so that the electric field is distributed around the field plate rather than at a single point, that is, the electric field strength is sequentially transferred to the first extension portion 1602 and the second extension portion 1603, so that the high-voltage electric field of the drain is evenly distributed around the field plate, thereby increasing the breakdown voltage and making the maximum breakdown voltage of the device greater than 1200V (4*300V / 1μm gallium nitride material characteristics).

[0168] See also Figure 3 In the embodiment of the present disclosure, the first source 141 is connected to the source connecting portion 143, and is connected to the source connecting portion 143 on the bottom surface of the substrate 100 through the source connecting portion 143 passing through the semiconductor structure layer (insulated through), and is then electrically connected to the second gate 162 through the source connecting portion 143 passing through the semiconductor structure layer (insulated through).

[0169] In this implementation, the method further includes: making a source connection portion.

[0170] When making the source connection part, first open a through hole through the semiconductor structure layer, and then make the source connection part on the other side of the substrate. Part of the source connection part passes through the through hole and is electrically connected to the source and the gate.

[0171] See also Figure 3 In the embodiment of the present disclosure, the first drain electrode 151 and the second source electrode 142 share the same electrode. This method not only realizes the electrical connection between the first drain electrode 151 and the second source electrode 142, but also facilitates manufacturing.

[0172] In the embodiment of the present disclosure, along a direction perpendicular to the substrate 100,

[0173] The width C of the cross section of the first extension portion 1602 is greater than the width A of the cross section of the groove 120;

[0174] A width D of a cross section of the second extension portion 1603 is greater than a width A of a cross section of the groove 120 .

[0175] In the embodiment of the present disclosure, the width C is 2 to 3 times the width A;

[0176] The width D is 2 to 3 times the width A.

[0177] For example, the width C is twice the width A;

[0178] The width D is twice the width A.

[0179] Since the field plate design is related to the height and length of the field plate, the use of the above dimensions can better achieve the transfer of electric field strength and improve the voltage resistance, breakdown voltage and other performance of the transistor.

[0180] like Figure 3 As shown, along the direction from the first source 141 to the first drain 151 , the distance X from the first dielectric layer 131 to the first drain 151 is 5-7 μm.

[0181] Exemplarily, X is 6 μm.

[0182] like Figure 3 As shown, along the direction from the second source 142 to the second drain 152 , the width Y of the second dielectric layer 132 not covered by the second gate 162 is 15-21 μm.

[0183] Exemplarily, Y is 18 μm.

[0184] In this implementation, the above value of Y is adopted, so that the second transistor can withstand a larger voltage.

[0185] S27, making an interlayer insulating layer, wherein the interlayer insulating layer covers the first gate and the second gate.

[0186] In the embodiment of the present disclosure, the interlayer insulating layer 109 may be a SiN layer, a SiO 2 layer or an Al 2 O 3 layer.

[0187] In the embodiment of the present disclosure, the thickness of the interlayer insulating layer 109 may be 0.1-10 μm.

[0188] Illustratively, the thickness of the interlayer insulating layer 109 is 5 μm.

[0189] S28, manufacturing a first source, a first drain, a second source and a second drain, wherein the first source, the first drain, the second source and the second drain sequentially penetrate the interlayer insulating layer, the barrier layer and are connected to the channel layer.

[0190] Figure 3 The figure shows only a cross-sectional view of the transistor circuit. Figure 3 The portion of the first drain electrode and the second drain electrode extending out of the interlayer insulating layer is not shown in the cross section.

[0191] In the embodiment of the present disclosure, the first source electrode 141 , the first drain electrode 151 , the second source electrode 142 , and the second drain electrode 152 may each include a Ti sublayer, an Al sublayer, a Ni sublayer, and an Au sublayer stacked in sequence.

[0192] In the embodiment of the present disclosure, the Ti sublayer and the Ni sublayer in the source and the drain are used to improve the adhesion between the sublayers and between the sublayers and the barrier layer, the Al sublayer is used to ensure the conductivity of the electrode, and the Au sublayer is used to protect the other sublayers to prevent the source and the drain from being oxidized or corroded.

[0193] In the source and drain electrodes, the thickness of the Ti sublayer may be 5 to 30 nm, the thickness of the Al sublayer may be 100 to 200 nm, the thickness of the Ni sublayer may be 30 to 80 nm, and the thickness of the Au sublayer may be 30 to 80 nm.

[0194] Exemplarily, in the source and drain electrodes, the thickness of the Ti sublayer is 20 nm, the thickness of the Al sublayer is 120 nm, the thickness of the Ni sublayer is 40 nm, and the thickness of the Au sublayer is 50 nm.

[0195] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A transistor circuit, characterized in that: The transistor circuit comprises: a first transistor (10) and a second transistor (20); The first transistor (10) and the second transistor (20) comprise a common substrate (100), a channel layer (101) and a barrier layer (102) sequentially stacked on the substrate (100); the barrier layer (102) has a groove (120) extending into the channel layer (101); The first transistor (10) further comprises a first dielectric layer (131), a first source electrode (141), a first drain electrode (151) and a first gate electrode (161); the second transistor (20) further comprises a second dielectric layer (132), a second source electrode (142), a second drain electrode (152) and a second gate electrode (162); The first dielectric layer (131) covers the bottom of the groove (120); the second dielectric layer (132) is located on the barrier layer (102); the first source electrode (141), the first drain electrode (151), the second source electrode (142), and the second drain electrode (152) penetrate the barrier layer (102) and are connected to the channel layer (101); the groove (120) is located between the first source electrode (141) and the first drain electrode (151); and the second dielectric layer (132) is located between the second source electrode (142) and the second drain electrode (152); The first gate (161) is located in the groove (120), the second gate (162) is located on the second dielectric layer (132), the first source (141) is electrically connected to the second gate (162), and the first drain (151) is electrically connected to the second source (142).

2. The transistor circuit according to claim 1, characterized in that Along a direction perpendicular to the substrate (100), the width A of the cross section of the groove (120) is 0.5 to 2 μm, and the depth B of the cross section of the groove (120) is 30 to 100 nm.

3. The transistor circuit according to claim 1, characterized in that: The thickness of the first dielectric layer (131) and the second dielectric layer (132) is 10 to 50 nm.

4. The transistor circuit according to claim 1, characterized in that Along the direction from the first source (141) to the first drain (151), a distance X from the first dielectric layer (131) to the first drain (151) is 5 to 7 μm.

5. The transistor circuit according to claim 1, characterized in that: Along the direction from the second source (142) to the second drain (152), the width Y of the second dielectric layer (132) not covered by the second gate (162) is 15 to 21 μm.

6. The transistor circuit according to any one of claims 1 to 5, characterized in that: The first gate (161) and the second gate (162) both comprise a main body (1601), a first extension (1602) and a second extension (1603); the second extension (1603), the first extension (1602) and the main body (1601) present a two-step structure, and at least a portion of the main body (1601) of the first gate (161) is located in the groove (120).

7. The transistor circuit according to claim 6, characterized in that In a direction perpendicular to the substrate (100), The width C of the cross section of the first extension portion (1602) is greater than the width A of the cross section of the groove (120); The width D of the cross section of the second extension portion (1603) is greater than the width A of the cross section of the groove (120).

8. The transistor circuit according to any one of claims 1 to 5, characterized in that: The threshold voltage of the first transistor (10) is related to the stress of the first dielectric layer (131).

9. The transistor circuit according to any one of claims 1 to 5, characterized in that: The first drain (151) and the second source (142) share the same electrode.

10. A method for manufacturing a transistor circuit, characterized in that: The method comprises: Fabricating a channel layer (101) on a substrate (100); Fabricating a barrier layer (102) on the channel layer (101), wherein the barrier layer (102) has a groove (120) extending into the channel layer (101); Fabricating a first dielectric layer (131) and a second dielectric layer (132) on the barrier layer (102), wherein the first dielectric layer (131) covers the bottom of the groove (120), and the second dielectric layer (132) is located on the barrier layer (102); A first source electrode (141), a first drain electrode (151), a second source electrode (142) and a second drain electrode (152) are manufactured, wherein the first source electrode (141), the first drain electrode (151), the second source electrode (142) and the second drain electrode (152) penetrate the barrier layer (102) and are connected to the channel layer (101); the groove (120) is located between the first source electrode (141) and the first drain electrode (151), and the second dielectric layer (132) is located between the second source electrode (142) and the second drain electrode (152); A first gate (161) and a second gate (162) are manufactured, wherein the first gate (161) is located in the groove (120), the second gate (162) is located on the second dielectric layer (132), the first source (141) is electrically connected to the second gate (162), and the first drain (151) is electrically connected to the second source (142).

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