Light-emitting element, display device, and method of manufacturing light-emitting element

Abstract

The invention relates to a light-emitting element, a display device, and a method of manufacturing the light-emitting element. The light emitting element includes: a first semiconductor layer doped to a first conductivity type; the active layer is arranged on the first semiconductor layer; a second semiconductor layer disposed on the active layer, the second semiconductor layer being doped to a second conductivity type; and a passivation layer surrounding a plurality of surfaces of the active layer, the plurality of surfaces including a side surface of the active layer. The passivation layer includes a semiconductor material that matches a lattice of a semiconductor material contained in the active layer, and the semiconductor material contained in the passivation layer has a higher band gap energy than a band gap energy of the semiconductor material contained in the active layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0096492 filed in the Korean Intellectual Property Office on July 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments relate to a light emitting element, a display device including the light emitting element, and a method of manufacturing the light emitting element. Background Art

[0004] As multimedia technology develops, display devices are becoming more and more important. Therefore, various display devices such as liquid crystal display devices and light-emitting display devices are currently being developed. Among these, light-emitting display devices using light-emitting elements are also adopted by various types of electronic devices including virtual reality (VR) devices and augmented reality (AR) devices in addition to portable electronic devices and televisions.

[0005] It will be understood that this background technology section is intended, in part, to provide a useful background for understanding the technology. However, this background technology section may also include ideas, concepts or realizations that were not known or understood as part of the subject matter disclosed herein by a person skilled in the relevant art before the corresponding effective filing date. Summary of the invention

[0006] Aspects of the present disclosure provide a light emitting element having improved emission efficiency, a display device including the light emitting element, and a method of manufacturing the light emitting element.

[0007] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one aspect of the present disclosure, a light-emitting element is provided, which may include: a first semiconductor layer doped to a first conductivity type; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer, the second semiconductor layer doped to a second conductivity type; and a passivation layer surrounding multiple surfaces of the active layer, the multiple surfaces including side surfaces of the active layer, wherein the passivation layer may include a semiconductor material that is lattice-matched to a semiconductor material contained in the active layer, and the semiconductor material contained in the passivation layer has a band gap energy higher than the band gap energy of the semiconductor material contained in the active layer.

[0009] In an embodiment, the active layer may include a quantum well layer including GaInP and a barrier layer including AlGaInP, and the passivation layer may be formed as a semiconductor layer including AlInP.

[0010] In an embodiment, the passivation layer may be formed as an intrinsic semiconductor layer including AlInP.

[0011] In an embodiment, the passivation layer may be disposed between the first semiconductor layer and the second semiconductor layer, and the passivation layer may completely surround the plurality of surfaces of the active layer including the first bottom surface, the second bottom surface, and the side surfaces of the active layer.

[0012] In an embodiment, the passivation layer may include: a first passivation layer, disposed between the first semiconductor layer and the active layer; a second passivation layer, disposed at a peripheral region of the first passivation layer and contacting the side surface of the active layer; a third passivation layer, disposed at a central region of the first passivation layer and contacting the first bottom surface of the active layer; and a fourth passivation layer, disposed on the active layer and contacting the second bottom surface of the active layer.

[0013] In an embodiment, the light emitting element may further include: an etching stop layer disposed between the first passivation layer and the second passivation layer and surrounding the third passivation layer.

[0014] In an embodiment, the etch stop layer may include an opening overlapping the active layer.

[0015] In an embodiment, the etch stop layer may be formed as an intrinsic semiconductor layer including AlGaAs.

[0016] In an embodiment, the passivation layer may include a side surface including an inclined surface.

[0017] In an embodiment, the light emitting element may further include: an insulating layer disposed at a peripheral region of the passivation layer.

[0018] According to an aspect of the present disclosure, a display device is provided that may include a plurality of pixels, each of the plurality of pixels including a first electrode, a second electrode, and a light-emitting element electrically connected between the first electrode and the second electrode, wherein the light-emitting element may include: a first semiconductor layer doped to a first conductivity type; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer and doped to a second conductivity type; and a passivation layer surrounding a plurality of surfaces of the active layer, the plurality of surfaces including a side surface of the active layer, and wherein the passivation layer may include a semiconductor material that is lattice-matched to a semiconductor material contained in the active layer, and the semiconductor material contained in the passivation layer has a band gap energy higher than the band gap energy of the semiconductor material contained in the active layer.

[0019] In an embodiment, the active layer may include a quantum well layer including GaInP and a barrier layer including AlGaInP, and the passivation layer may be formed as a semiconductor layer including AlInP.

[0020] In an embodiment, the passivation layer may be disposed between the first semiconductor layer and the second semiconductor layer, and the passivation layer may completely surround the plurality of surfaces of the active layer including the first bottom surface, the second bottom surface, and the side surfaces of the active layer.

[0021] In an embodiment, the passivation layer may include: a first passivation layer, disposed between the first semiconductor layer and the active layer; a second passivation layer, disposed at a peripheral region of the first passivation layer and contacting the side surface of the active layer; a third passivation layer, disposed at a central region of the first passivation layer and contacting the first bottom surface of the active layer; and a fourth passivation layer, disposed on the active layer and contacting the second bottom surface of the active layer.

[0022] In an embodiment, the light emitting element may further include: an etching stop layer disposed between the first passivation layer and the second passivation layer and surrounding the third passivation layer.

[0023] In an embodiment, the passivation layer may include a side surface including an inclined surface.

[0024] According to one aspect of the present disclosure, a method for manufacturing a light-emitting element is provided, the method comprising: sequentially forming a first semiconductor layer, a first passivation layer, an etch stop layer, a second passivation layer and an insulating layer on a substrate; etching a portion of the insulating layer to expose a portion of the second passivation layer; exposing a portion of the etch stop layer by etching the exposed portion of the second passivation layer; exposing a portion of the first passivation layer by etching the exposed portion of the etch stop layer; and sequentially forming a third passivation layer, an active layer, a fourth passivation layer and a second semiconductor layer on the exposed portion of the first passivation layer.

[0025] In an embodiment, the first passivation layer, the second passivation layer, the third passivation layer and the fourth passivation layer can be formed by using a semiconductor material that is lattice matched with the semiconductor material contained in the active layer, and the semiconductor material contained in the first passivation layer, the second passivation layer, the third passivation layer and the fourth passivation layer has a band gap energy higher than the band gap energy of the semiconductor material contained in the active layer.

[0026] In an embodiment, forming the active layer may include alternately forming a barrier layer containing AlGaInP and a quantum well layer containing GaInP on the third passivation layer, and the first passivation layer, the second passivation layer, the third passivation layer and the fourth passivation layer may be formed using AlInP as a material.

[0027] In an embodiment, the method may further include: forming a plurality of light emitting elements on the substrate at the same time; and at least partially separating the plurality of light emitting elements from each other after the second semiconductor layer has been formed.

[0028] Aspects of the present disclosure provide a light emitting element in which the surface of an active layer can be surrounded by a passivation layer including a semiconductor material lattice-matched to the semiconductor material contained in the active layer. By doing so, surface defects of the light emitting element can be suppressed or reduced and the emission efficiency of the light emitting element can be improved.

[0029] The passivation layer may be formed of a semiconductor material having a bandgap energy higher than that of the semiconductor material contained in the active layer. By doing so, non-emissive recombination of electrons and holes may be suppressed or reduced and the emission efficiency of the light emitting element may be improved.

[0030] The display device according to the embodiment may include a pixel including a light emitting element. Therefore, the emission efficiency of the pixel and the display device including the pixel may be improved.

[0031] However, the effects according to the embodiments of the present disclosure are not limited to the effects described above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0033] Figure 1 is a schematic cross-sectional view showing a light emitting element according to an embodiment.

[0034] Figure 2 It is shown Figure 1 An enlarged schematic cross-sectional view of a region A1 of FIG.

[0035] Figure 3 is a graph showing band gap energy versus lattice constant for example semiconductor materials.

[0036] Figure 4 is a schematic cross-sectional view showing a light emitting element according to an embodiment.

[0037] Figure 5 is a schematic cross-sectional view showing a light emitting element according to an embodiment.

[0038] Figure 6 is a schematic cross-sectional view showing a light emitting element according to an embodiment.

[0039] Figures 7 to 19 is a schematic cross-sectional view illustrating a method of manufacturing a light emitting element according to an embodiment.

[0040] Figure 20 to Figure 24 is a schematic cross-sectional view illustrating a method of manufacturing a light emitting element according to an embodiment.

[0041] Figure 25 to Figure 27 is a schematic cross-sectional view illustrating a method of manufacturing a light emitting element according to an embodiment.

[0042] Fig.28 is a schematic perspective view showing a display device according to an embodiment.

[0043] Fig.29 It is shown Fig.28 A schematic plan view of an example of area A2.

[0044] Fig.30 It is shown Fig.28 A schematic plan view of an example of area A2.

[0045] Fig.31 It is shown along Fig.30 Schematic cross-sectional view of an example of a cross section of a display panel taken along line X1 - X1 ′.

[0046] Fig.32 is a view showing an example of a virtual reality device including a display device according to an embodiment.

[0047] Fig.33 is a view showing an example of a smart device including a display device according to an embodiment.

[0048] Fig.34 is a view showing an example of an instrument cluster and a center instrument panel for a vehicle including a display device according to an embodiment.

[0049] Fig.35 is a view showing an example of a transparent display device including a display device according to an embodiment. DETAILED DESCRIPTION

[0050] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0051] In the drawings, the size, thickness, ratio, and dimensions of elements may be exaggerated for convenience of description and for clarity. Like reference numerals refer to like elements throughout.

[0052] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0053] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or".

[0054] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0055] It will also be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer, or intervening elements or layers may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0056] It will be understood that when an element (or region, layer, portion, etc.) is referred to in the specification as being "on" another element, "connected to" or "coupled to" another element, the element may be directly disposed on the other element mentioned above, directly connected to or directly coupled to the other element mentioned above, or an intervening element may be disposed between the element and the other element mentioned above.

[0057] It will be understood that the terms “connected to” or “coupled to” may include a physical connection or physical coupling or an electrical connection or electrical coupling.

[0058] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0059] The term "overlap" or "overlapped" means that a first object may be above or below a second object or on one side of the second object, and vice versa. In addition, the term "overlap" or "overlapped" may include stacking, stacking, facing or facing, extending over, covering or partially covering, or any other suitable term that will be understood and appreciated by a person of ordinary skill in the art.

[0060] When an element is described as “not overlapping or to not overlap” another element, this may include the elements being spaced apart, offset or separated from each other or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0061] The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first element and the second element, the first element and the second element can be understood to be indirectly opposite to each other, but still facing each other.

[0062] When the terms “comprises, comprising,” “includes, including,” and / or “has, have, having,” and variations thereof are used in this specification, it indicates the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0063] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0064] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly so defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formalized sense.

[0065] The features of each of the various embodiments may be partially or completely combined with each other and may technically interact with each other in various ways, and the various embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0066] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0067] Figure 1 1 is a schematic cross-sectional view showing a light emitting element LE according to an embodiment. Figure 1 The light emitting element LE is disposed on the substrate SUB, but the embodiment is not limited thereto. For example, the light emitting element LE may be manufactured on the substrate SUB and may be separated from the substrate SUB.

[0068] Figure 2 It is shown Figure 1 For example, Figure 2 Shows Figure 1 4 , and the structure of the active layer EML and the interface JIF between the active layer EML and the passivation layer PSV.

[0069] refer to Figure 1 and Figure 2 , the light emitting element LE may include a first semiconductor layer SEM1, an active layer EML, and a second semiconductor layer SEM2 sequentially disposed and / or stacked on a substrate SUB, and may include a passivation layer PSV surrounding the active layer EML. According to an embodiment, the light emitting element LE may further include an etch stop layer EST disposed around the active layer EML and the passivation layer PSV, an insulating layer INS disposed on a portion of the passivation layer PSV, and a contact electrode CTE disposed on the second semiconductor layer SEM2.

[0070] Although in Figure 1 In the example shown in , the contact electrode CTE is included in the light emitting element LE, but the embodiment is not limited thereto. For example, the contact electrode CTE may be formed separately from the light emitting element LE and may be provided or disposed on one end or one end of the light emitting element LE.

[0071] The substrate SUB (also referred to as a growth substrate or a manufacturing substrate) may be a semiconductor substrate for forming the light emitting element LE. The substrate SUB may be a manufacturing substrate or a wafer suitable for epitaxial growth (or epitaxy). For example, the first semiconductor layer SEM1, the passivation layer PSV, the active layer EML, and the second semiconductor layer SEM2 of the light emitting element LE may be formed on the substrate SUB by epitaxial growth.

[0072] According to an embodiment, the substrate SUB may be a material including GaAs, silicon (Si), sapphire, SiC, GaN, and ZnO. x (It can be ZnO or ZnO 2 ) material. For example, the substrate SUB may be a semiconductor substrate made of GaAs.

[0073] In addition, the substrate SUB may be a substrate of various types and / or materials. For example, the type or material of the substrate SUB is not particularly limited as long as the epitaxial growth for manufacturing the light emitting element LE can be well performed. According to an embodiment, after the substrate SUB is used as a substrate for epitaxial growth for manufacturing the light emitting element LE, the substrate SUB may be finally separated from the light emitting element LE. For example, after the light emitting element LE is simultaneously formed by epitaxial growth on the substrate SUB, the light emitting element LE may be separated from the substrate SUB.

[0074] The first semiconductor layer SEM1, the active layer EML, and the second semiconductor layer SEM2 may be sequentially disposed and / or stacked on the substrate SUB in the third direction DR3. According to an embodiment, the third direction DR3 may be a thickness direction (or height direction) of the light emitting element LE.

[0075] According to an embodiment, the light emitting element LE may be an inorganic light emitting element formed of an inorganic material. For example, the light emitting element LE may be an inorganic light emitting diode (inorganic LED) formed of a phosphide semiconductor material (such as GaP, GaInP, AlGaP, AlInP, AlGaInP, AlP, and InP), a nitride semiconductor material (such as GaN, AlGaN, InGaN, AlInGaN, AlN, and InN), or other inorganic materials. According to an embodiment, the light emitting element LE may be a red LED that emits red light and is formed of a phosphide semiconductor material including GaInP, AlInP, and AlGaInP.

[0076] According to an embodiment, the light emitting element LE may be a vertical micro-LED extending in the third direction DR3. For example, the light emitting element LE may be a micro-LED having a length in the first direction DR1 (e.g., horizontal length), a length in the second direction DR2 (e.g., vertical length), and a length in the third direction DR3 (e.g., thickness or height) of several to several hundred micrometers (μm). According to an embodiment, each of the length of the light emitting element LE in the first direction DR1, the length of the light emitting element LE in the second direction DR2, and the length of the light emitting element LE in the third direction DR3 may be equal to or less than about 100 μm. It should be noted that the size of the light emitting element LE is not limited, and the light emitting element LE can be manufactured in various sizes.

[0077] According to an embodiment, the light emitting element LE may include a side surface substantially perpendicular to the substrate SUB and may have a substantially rectangular cross-section. For example, the light emitting element LE may have a rectangular (e.g., square) cross-section in which the width of the upper surface is substantially equal to the width of the lower surface, except for a protruding portion such as the contact electrode CTE.

[0078] It should be noted that the shape of the light emitting element LE is not limited, and the light emitting element LE can be manufactured in various shapes. For example, the light emitting element LE can at least partially have a trapezoidal (or inverted trapezoidal) cross-sectional shape.

[0079] When viewed from the top, the light emitting element LE may have various shapes. For example, when viewed on a plane defined by the first direction DR1 and the second direction DR2 (e.g., on a plane), the light emitting element LE may have a quadrilateral shape including a rectangle (e.g., a square), a non-rectangular shape including a circle or an ellipse, or other shapes.

[0080] The first semiconductor layer SEM1 may be disposed on the substrate SUB. The first semiconductor layer SEM1 may be formed of an inorganic material such as a phosphide semiconductor material and a nitride semiconductor material. For example, the first semiconductor layer SEM1 may include: a phosphide semiconductor material such as GaP, GaInP, AlGaP, AlInP, AlGaInP, AlP, and InP; a nitride semiconductor material such as GaN, AlGaN, InGaN, AlInGaN, AlN, and InN; or other inorganic materials.

[0081] The first semiconductor layer SEM1 may be doped to a first conductivity type. For example, the first semiconductor layer SEM1 may include a semiconductor material doped with a first conductivity type dopant. According to an embodiment, the first semiconductor layer SEM1 may be an n-type semiconductor layer doped with an n-type dopant (e.g., Si, Ge, Se, Sn, or other n-type dopant) for forming an n-type semiconductor.

[0082] According to an embodiment, the first semiconductor layer SEM1 may be a single-layer semiconductor layer or a multi-layer semiconductor layer including at least one of an n-GaInP semiconductor layer, an n-AlGaInP semiconductor layer, and an n-AlInP semiconductor layer doped with an n-type dopant. For example, the first semiconductor layer SEM1 may include an n-GaInP semiconductor layer, an n-AlGaInP semiconductor layer, and an n-AlInP semiconductor layer sequentially disposed on the substrate SUB. The material and / or structure of the first semiconductor layer SEM1 may be changed in various ways.

[0083] The active layer EML and the passivation layer PSV may be disposed on the first semiconductor layer SEM1. The active layer EML may be disposed on the first semiconductor layer SEM1 so that the active layer EML is surrounded by the passivation layer PSV. According to an embodiment, the passivation layer PSV may be a semiconductor layer (also referred to as a third semiconductor layer) including a semiconductor material. According to an embodiment, an additional semiconductor layer may be disposed around the active layer EML and the passivation layer PSV. For example, an etching stop layer EST (also referred to as a fourth semiconductor layer) including a semiconductor material may be disposed around the active layer EML and the passivation layer PSV.

[0084] The active layer EML may be disposed between the first semiconductor layer SEM1 and the second semiconductor layer SEM2. In response to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2, the active layer EML may emit light as electron-hole pairs are recombined therein. For example, the active layer EML may be an emission layer of the light emitting element LE.

[0085] According to an embodiment, the active layer EML may be an emission layer having a multi-quantum well MQW structure. Figure 2 As shown in , the active layer EML may have a multi-quantum well MQW structure in which quantum well layers QWL and barrier layers QBR are alternately stacked with each other. The active layer EML may include other group III to group V semiconductor materials according to the wavelength band of emitted light.

[0086] According to an embodiment, the active layer EML may be formed of an inorganic material such as a phosphide semiconductor material and a nitride semiconductor material. For example, the active layer EML may include: a phosphide semiconductor material such as GaP, GaInP, AlGaP, AlInP, AlGaInP, AlP, and InP; a nitride semiconductor material such as GaN, AlGaN, InGaN, AlInGaN, AlN, and InN; or other inorganic materials.

[0087] According to an embodiment, the active layer EML may include a phosphide semiconductor material and may emit red light. For example, the quantum well layer QWL of the active layer EML may be formed of GaInP, and the barrier layer QBR may be formed of AlGaInP.

[0088] The passivation layer PSV (also referred to as a passivation film) may cover a surface of the active layer EML including a side surface (or multiple side surfaces). For example, the passivation layer PSV may completely cover a surface of the active layer EML including a first bottom surface (e.g., bottom surface), a second bottom surface (e.g., top surface), and a side surface of the active layer EML. According to an embodiment, the passivation layer PSV may include a first passivation layer PSV1, a second passivation layer PSV2, a third passivation layer PSV3, and a fourth passivation layer PSV4 forming different parts of the passivation layer PSV.

[0089] The first passivation layer PSV1 may be disposed between the first semiconductor layer SEM1 and the active layer EML. The first passivation layer PSV1 may be a first portion of the passivation layer PSV covering the first semiconductor layer SEM1.

[0090] The second passivation layer PSV2 may be disposed at a peripheral region of the first passivation layer PSV1 that does not overlap the active layer EML. The second passivation layer PSV2 may be a second portion of the side surface of the passivation layer PSV surrounding the active layer EML.

[0091] The third passivation layer PSV3 may be disposed at a central region (eg, a region overlapping the active layer EML) of the first passivation layer PSV1. The third passivation layer PSV3 may be a third portion of the first bottom surface of the passivation layer PSV surrounding the active layer EML.

[0092] The fourth passivation layer PSV4 may be disposed on the active layer EML. The fourth passivation layer PSV4 may be a fourth portion of the passivation layer PSV surrounding the second bottom surface of the active layer EML.

[0093] The passivation layer PSV may contact the surface of the active layer EML. For example, the second passivation layer PSV2, the third passivation layer PSV3, and the fourth passivation layer PSV4 may contact the side surface of the active layer EML, the first bottom surface of the active layer EML, and the second bottom surface of the active layer EML, respectively.

[0094] The passivation layer PSV may include a semiconductor material that can suppress a decrease in efficiency due to surface defects of the active layer EML. For example, the passivation layer PSV may be formed of a semiconductor material having a lattice matching or the same lattice as that of the semiconductor material included in the active layer EML and having a higher band gap energy. According to an embodiment, the passivation layer PSV may include at least one semiconductor material included in the active layer EML (for example, forming Figure 2The semiconductor material may include a semiconductor compound of the quantum well layer QWL and the barrier layer QBR, and may include a semiconductor material having a band gap energy higher than that of a semiconductor material included in the active layer EML.

[0095] According to an embodiment, the active layer EML may have a multi-quantum well structure including a quantum well layer QWL containing GaInP and a barrier layer QBR containing AlGaInP. The passivation layer PSV may be formed of a semiconductor layer containing AlInP, or may include a semiconductor layer containing AlInP. For example, the passivation layer PSV may be formed as an intrinsic semiconductor layer (e.g., i-AlInP layer) containing AlInP and manufactured without doping.

[0096] The etch stop layer EST may be disposed between the first passivation layer PSV1 and the second passivation layer PSV2. The etch stop layer EST may be disposed to surround the third passivation layer PSV3.

[0097] The etch stop layer EST may be disposed below (or under) the active layer EML, but not overlapping the active layer EML. For example, the etch stop layer EST may be disposed on a portion (e.g., an edge) of the first passivation layer PSV1 that does not overlap the active layer EML, and may include an opening that is in line with the active layer EML. The third passivation layer PSV3 may be disposed in the opening of the etch stop layer EST. For example, the third passivation layer PSV3 may be disposed higher than the etch stop layer EST and may contact the first bottom surface of the active layer EML.

[0098] The etch stop layer EST may include a material that can be used as an etch stop layer so that a surface on which the third passivation layer PSV3, etc. is to be regrown can be neatly formed during the process of manufacturing the light emitting element LE. For example, the etch stop layer EST may include a semiconductor material that can act as a suitable etch stop layer during the process of etching the passivation layer PSV. According to an embodiment, the etch stop layer EST may include an intrinsic semiconductor made of AlGaAs and manufactured without doping. For example, the etch stop layer EST may be formed as an intrinsic semiconductor layer (e.g., an i-AlInP layer) containing AlInP and manufactured without doping.

[0099] The second semiconductor layer SEM2 and the insulating layer INS may be disposed on the passivation layer PSV.

[0100] The second semiconductor layer SEM2 may be disposed on the active layer EML and the passivation layer PSV. For example, the second semiconductor layer SEM2 may be disposed on the fourth passivation layer PSV4 such that the second semiconductor layer SEM2 overlaps the active layer EML.

[0101] The second semiconductor layer SEM2 may be formed of an inorganic material such as a phosphide semiconductor material and a nitride semiconductor material. For example, the second semiconductor layer SEM2 may include: a phosphide semiconductor material such as GaP, GaInP, AlGaP, AlInP, AlGaInP, AlP, and InP; a nitride semiconductor material such as GaN, AlGaN, InGaN, AlInGaN, AlN, and InN; or other inorganic materials.

[0102] The second semiconductor layer SEM2 may be doped to a second conductivity type. For example, the second semiconductor layer SEM2 may include a semiconductor material doped with a second conductivity type dopant. According to an embodiment, the second semiconductor layer SEM2 may be a p-type semiconductor layer having a p-type dopant (e.g., Mg, Zn, Ca, Ba, or other p-type dopant) for forming a p-type semiconductor.

[0103] According to an embodiment, the second semiconductor layer SEM2 may be a single-layer semiconductor layer or a multi-layer semiconductor layer including at least one of a p-AlInP semiconductor layer, a p-AlGaInP semiconductor layer, and a p-GaP semiconductor layer doped with a p-type dopant. For example, the second semiconductor layer SEM2 may include a p-AlInP semiconductor layer, a p-AlGaInP semiconductor layer, and a p-GaP semiconductor layer sequentially disposed on the passivation layer PSV. The material and / or structure of the second semiconductor layer SEM2 may be changed in various ways.

[0104] The insulating layer INS may be disposed on a portion of the passivation layer PSV (e.g., a peripheral region of the passivation layer PSV that does not overlap the active layer EML). The insulating layer INS may cover the peripheral region of the passivation layer PSV and at least partially cover one side surface (or multiple side surfaces) of the second semiconductor layer SEM2. The insulating layer INS may improve the electrical stability of the light emitting element LE.

[0105] The insulating layer INS may include a silicon oxide (SiO x )(For example, SiO 2 ), silicon nitride (Si x N y )(For example, Si 3 N 4 ), aluminum oxide (Al x O y )(For example, Al 2 O 3 ), titanium oxide (Ti x O y )(For example, TiO 2 ) and hafnium oxide (HfO x) or other insulating materials. The insulating layer INS may be composed of a single layer or multiple layers. It should be noted that the material and / or structure of the insulating layer INS is not particularly limited, but may be changed according to the embodiment.

[0106] The contact electrode CTE may be disposed at one end or one end of the light emitting element LE on which the second semiconductor layer SEM2 is disposed. For example, the contact electrode CTE may be disposed and / or formed on the second semiconductor layer SEM2.

[0107] The contact electrode CTE may protect the second semiconductor layer SEM2 and stably connect the second semiconductor layer SEM2 to at least one circuit element, electrode and / or line. The contact electrode CTE may include metal, metal oxide or other conductive materials.

[0108] Figure 3 is a graph showing band gap energy versus lattice constant for example semiconductor materials.

[0109] Combination Figure 1 and Figure 2 refer to Figure 3 , the semiconductor material (e.g., AlInP) forming the passivation layer PSV may have the same lattice constant as that of the semiconductor material (e.g., GaInP and AlGaInP) forming the active layer EML, and may have a higher band gap energy (e.g., in the range of about 2.3 eV to about 2.4 eV) than the semiconductor material forming the active layer EML. According to an embodiment, by adjusting the ratio of elements (ratio of aluminum (Al), indium (In), and phosphorus (P)) forming AlInP serving as a material for the passivation layer PSV, the passivation layer PSV having a higher band gap energy than the active layer EML may be formed.

[0110] According to the above reference Figures 1 to 3 The described embodiments can improve the emission efficiency of the light emitting element LE. For example, according to the above embodiments, the emission efficiency of the light emitting element LE can be improved by suppressing surface defects of the light emitting element LE and preventing or reducing non-emitting recombination of electrons and holes through the passivation layer PSV.

[0111] For example, according to an embodiment, the surface of the active layer EML may be surrounded by a passivation layer PSV including a semiconductor material (e.g., a semiconductor compound such as i-AlInP) having a lattice matching or the same lattice as the semiconductor material (e.g., a semiconductor compound such as GaInP and AlGaInP) contained in the active layer EML. Therefore, surface defects of the light-emitting element LE can be suppressed. By forming the passivation layer PSV with a semiconductor material having a higher band gap energy than the semiconductor material contained in the active layer EML, the recombination of electrons and holes in the quantum well layer QWL can be induced. In this way, the recombination of electrons and holes without emitting light (e.g., non-emission recombination) can be prevented or reduced. For example, as the size of the light-emitting element LE decreases, the ratio of volume to surface area can increase. Therefore, by providing a passivation layer PSV having a band gap energy higher than the band gap energy of the active layer EML on the surface of the active layer EML, the non-emission recombination of electrons and holes can be prevented, suppressed or reduced. In this way, the decrease in emission efficiency as the size of the light-emitting element LE decreases can be prevented or reduced.

[0112] Figure 4 2 is a schematic cross-sectional view showing a light emitting element LE according to an embodiment. In the following description, the same reference numerals are given to elements similar to or identical to those of the above-described embodiment, and redundant description will be omitted.

[0113] Combination Figures 1 to 3 refer to Figure 4 , the light emitting element LE may at least partially have an inclined surface (or multiple inclined surfaces) ICS. For example, the passivation layer PSV (eg, the second passivation layer PSV2) and the insulating layer INS of the light emitting element LE may be etched at an appropriate angle to have a side surface including the inclined surface ICS.

[0114] According to an embodiment, the second passivation layer PSV2 and the insulating layer INS may have a trapezoidal cross-sectional shape whose lower surface is wider than the upper surface. According to an embodiment, the second passivation layer PSV2 and the insulating layer INS may have an inverted trapezoidal cross-sectional shape whose upper surface is wider than the lower surface. The shape of the light emitting element LE may be variously modified according to different embodiments.

[0115] In a device (e.g., a display device or an illuminator) using a light emitting element LE as a light source, the position, direction, and / or angle of the inclined surface ICS formed in the light emitting element LE may be appropriately adjusted in consideration of the direction in which the light emitting element LE is disposed or the emission efficiency, etc. Therefore, the emission efficiency of the light emitting element LE may be improved.

[0116] Figure 5 is a schematic cross-sectional view showing a light emitting element LE according to the embodiment. Figure 6is a schematic cross-sectional view showing a light emitting element LE according to an embodiment. For example, Figure 5 and Figure 6 Different shapes of the passivation layer PSV and the insulating layer INS according to different embodiments are shown.

[0117] Combination Figures 1 to 4 refer to Figure 5 and Figure 6 , the light emitting element LE may include auxiliary light emitting elements LEa, LEb, and LEc that are partially connected to each other and positioned (or disposed) in the light emitting area LEA (or auxiliary area). Figure 5 and Figure 6 In the embodiment, the light emitting element LE may include three auxiliary light emitting elements LEa, LEb and LEc arranged (or disposed) in the first direction DR1, but the number and / or arrangement structure of the auxiliary light emitting elements LEa, LEb and LEc may be changed in various ways.

[0118] The auxiliary light emitting elements LEa, LEb, and LEc may have portions connected to each other including the first semiconductor layer SEM1, and may share the portions. For example, the auxiliary light emitting elements LEa, LEb, and LEc may be manufactured so that the elements disposed under the etching stop layer EST are connected to each other. For example, the auxiliary light emitting elements LEa, LEb, and LEc may share the first semiconductor layer SEM1, and may include individual active layers EML and individual second semiconductor layers SEM2 that are separated individually.

[0119] The auxiliary light emitting elements LEa, LEb and LEc may have the same Figures 1 to 4 The configuration and / or structure of each light emitting element LE of the described embodiment is substantially similar to that of the auxiliary light emitting elements LEa, LEb, and LEc. Therefore, the configuration and / or structure of the auxiliary light emitting elements LEa, LEb, and LEc will not be described in detail.

[0120] According to an embodiment, Figure 5 As shown in , the auxiliary light emitting elements LEa, LEb and LEc may include substantially vertical side surfaces, wherein the substantially vertical side surfaces are separated from each other. Figure 6 As shown in , the auxiliary light emitting elements LEa, LEb and LEc may include an inclined side surface having an inclined surface ICS, wherein the inclined surfaces ICS are separated from each other. For example, the light emitting element LE may have an inclined surface ICS between the auxiliary light emitting elements LEa, LEb and LEc, and the emission efficiency of the light emitting element LE may be adjusted or improved by adjusting the angle at which the inclined surface ICS is formed.

[0121] Figures 7 to 19 is a schematic cross-sectional view showing a method of manufacturing a light emitting element LE according to an embodiment. For example, Figures 7 to 19 is shown for manufacturing according to Figure 1 Schematic cross-sectional view of the process steps of the light emitting element LE of the embodiment. Figures 4 to 6 The light emitting element LE of the embodiment can be manufactured according to Figure 1 The light emitting element LE of the embodiment is manufactured by basically the same method.

[0122] Combination Figures 1 to 6 refer to Figure 7 First, a substrate SUB for manufacturing the light emitting element LE may be prepared by epitaxial growth. According to an embodiment, the substrate SUB may be a semiconductor substrate suitable for epitaxial growth of a semiconductor. For example, the substrate SUB may be a semiconductor substrate made of GaAs.

[0123] According to an embodiment, a buffer layer (not shown) may be first formed on a substrate SUB. The buffer layer may be formed as at least one semiconductor layer including a semiconductor layer not doped with a dopant.

[0124] Combination Figures 1 to 7 refer to Figures 8 to 11 , on the substrate SUB (or a buffer layer formed on the substrate SUB), a first semiconductor layer SEM1, a first passivation layer PSV1, an etch stop layer EST, and a second passivation layer PSV2 may be sequentially formed. For example, the first semiconductor layer SEM1, the first passivation layer PSV1, the etch stop layer EST, and the second passivation layer PSV2 may be sequentially formed on the substrate SUB by epitaxial growth.

[0125] The first semiconductor layer SEM1 may be formed of the materials of the first semiconductor layer SEM1 listed above. For example, the first semiconductor layer SEM1 may be formed of at least one of GaInP, AlGaInP, and AlInP, and may be formed as a single semiconductor layer or a multi-layer semiconductor layer. The first semiconductor layer SEM1 may be doped to include a first conductive type dopant (e.g., an n-type dopant).

[0126] The first passivation layer PSV1 may be formed using the materials of the passivation layer PSV listed above. For example, the first passivation layer PSV1 may be formed of a semiconductor material having a lattice matching or the same lattice as that of the semiconductor material included in the active layer EML and having a band gap energy higher than that of the semiconductor material (eg, AlInP), and may not be doped.

[0127] The etch stop layer EST may be formed using the materials of the etch stop layer EST listed above. For example, the etch stop layer EST may be formed of AlGaAs and may not be doped.

[0128] The second passivation layer PSV2 may be formed using the materials of the passivation layer PSV listed above. For example, the second passivation layer PSV2 may be formed of a semiconductor material (e.g., AlInP) having a lattice matching or the same lattice as the semiconductor material included in the active layer EML and having a band gap energy higher than that of the semiconductor material, and may not be doped.

[0129] The first semiconductor layer SEM1, the first passivation layer PSV1, the etch stop layer EST, and the second passivation layer PSV2 may be formed by epitaxial growth using process technologies such as metal organic chemical vapor deposition (MOCVD), metal organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and vapor phase epitaxy (VPE). According to an embodiment, the first semiconductor layer SEM1, the first passivation layer PSV1, the etch stop layer EST, and the second passivation layer PSV2 may be formed by epitaxial growth using, but not limited to, MOCVD technology. Through the above process, a semiconductor substrate for regrowing an active layer EML, etc. may be prepared within the spirit and scope of the present disclosure.

[0130] Combination Figures 1 to 11 refer to Figures 12 to 15 After the insulating layer INS is formed on the second passivation layer PSV2, the insulating layer INS, the second passivation layer PSV2 and the etching stop layer EST can be sequentially patterned to expose a portion of the first passivation layer PSV1 corresponding to a region where an active layer EML, etc. is to be formed (for example, a region having an optional shape and / or area including the center of a region where a light-emitting element LE is to be formed).

[0131] For example, Fig.12 As shown in FIG. 1 , after the insulating layer INS is formed on the substrate SUB on which the second passivation layer PSV2 and the like have been formed, as shown in FIG. Fig.13 As shown in , the insulating layer INS may be partially etched so that a portion of the second passivation layer PSV2 (e.g., a portion of the center of the region where the light emitting element LE is to be formed) is exposed. The insulating layer INS may be formed using the materials for the insulating layer INS listed above. The insulating layer INS may be formed by a deposition technique using process techniques such as ALD and CVD, but the method of forming the insulating layer INS is not limited thereto. Therefore, the insulating layer INS may be patterned via an etching process to have an opening having a position and a size corresponding to the region where the active layer EML is to be formed.

[0132] Then, if Fig.14As shown in , the portion of the second passivation layer PSV2 exposed by the opening of the insulating layer INS can be etched away. As a result, the second passivation layer PSV2 can be patterned to have an opening having a position and a size corresponding to the area where the active layer EML is to be formed. According to an embodiment, the second passivation layer PSV2 can be patterned via a dry etching process, but the method of patterning the second passivation layer PSV2 is not limited thereto. A portion of the etch stop layer EST can be exposed through the opening of the second passivation layer PSV2.

[0133] Then, if Fig.15 As shown in , the exposed portion of the etch stop layer EST may be etched away. Therefore, the etch stop layer EST may be patterned to have an opening having a position and a size corresponding to the area where the active layer EML is to be formed. According to an embodiment, the etch stop layer EST may be patterned via an etching process including a wet etching process, but the method of patterning the etch stop layer EST is not limited thereto. A portion of the first passivation layer PSV1 (e.g., an area corresponding to the area where the active layer EML is to be formed) may be exposed through the opening of the etch stop layer EST.

[0134] Through the above-described processes, a pattern substrate on which an active region where an active layer EML or the like is to be formed is defined may be prepared.

[0135] Combination Figures 1 to 15 refer to Figures 16 to 19 , a third passivation layer PSV3, an active layer EML, a fourth passivation layer PSV4, and a second semiconductor layer SEM2 may be sequentially formed on the pattern substrate where a portion of the first passivation layer PSV1 is exposed. For example, on the exposed portion of the first passivation layer PSV1, a third passivation layer PSV3, an active layer EML, a fourth passivation layer PSV4, and a second semiconductor layer SEM2 may be sequentially formed by epitaxial regrowth.

[0136] The third passivation layer PSV3 may be formed using the materials of the passivation layer PSV listed above. For example, the third passivation layer PSV3 may be formed of a semiconductor material having a lattice matching or the same lattice as the semiconductor material included in the active layer EML and having a band gap energy higher than that of the semiconductor material (e.g., AlInP), and may not be doped.

[0137] The active layer EML may be formed using the materials of the active layer EML listed above. For example, the active layer EML having a multi-quantum well structure may be formed by alternately forming barrier layers QBR including AlGaInP and quantum well layers QWL including GaInP on the third passivation layer PSV3.

[0138] The fourth passivation layer PSV4 may be formed using the materials of the passivation layer PSV listed above. For example, the fourth passivation layer PSV4 may be formed of a semiconductor material having a lattice matching or the same lattice as the semiconductor material included in the active layer EML and having a band gap energy higher than that of the semiconductor material (e.g., AlInP), and may not be doped. According to an embodiment, the first passivation layer PSV1, the second passivation layer PSV2, the third passivation layer PSV3, and the fourth passivation layer PSV4 may be formed of the same material and may be considered to form different parts of a single passivation layer PSV.

[0139] The second semiconductor layer SEM2 may be formed of the materials of the second semiconductor layer SEM2 listed above. For example, the second semiconductor layer SEM2 may be formed of at least one of AlInP, AlGaInP, and GaP, and may be formed as a single semiconductor layer or a multi-layer semiconductor layer. The second semiconductor layer SEM2 may be doped to include a second conductive type dopant (e.g., a p-type dopant).

[0140] The third passivation layer PSV3, the active layer EML, the fourth passivation layer PSV4, and the second semiconductor layer SEM2 may be formed by epitaxial regrowth (or epitaxial growth) using process techniques such as MOCVD, MOVPE, MBE, LPE, and VPE. According to an embodiment, the third passivation layer PSV3, the active layer EML, the fourth passivation layer PSV4, and the second semiconductor layer SEM2 may be formed by, but not limited to, epitaxial regrowth using MOCVD technology.

[0141] According to Figure 1 According to the embodiment of manufacturing the light emitting element LE including the contact electrode CTE, a process of forming the contact electrode CTE on the second semiconductor layer SEM2 may be additionally performed. According to the embodiment of separating the light emitting element LE from the substrate SUB, a process of separating the light emitting element LE from the substrate SUB may be additionally performed.

[0142] Figure 20 to Figure 24 is a schematic cross-sectional view showing a method of manufacturing a light emitting element LE according to an embodiment. For example, Figure 20 to Figure 24 It shows that according to Figure 5 and Figure 6 Schematic cross-sectional view of a method of manufacturing a light emitting element LE according to an embodiment of the present invention.

[0143] Combination Figures 1 to 19 refer to Fig. 20Auxiliary light emitting elements LEa, LEb, and LEc may be formed in the light emitting area LEA, respectively. For example, on the substrate SUB including the light emitting area LEA, a first semiconductor layer SEM1, a passivation layer PSV, an etch stop layer EST, an insulating layer INS, an active layer EML, and a second semiconductor layer SEM2 may be formed. The method of forming the first semiconductor layer SEM1, the passivation layer PSV, the etch stop layer EST, the insulating layer INS, the active layer EML, and the second semiconductor layer SEM2 may be the same as that of Figures 7 to 19 The methods in the embodiments are basically the same.

[0144] Combination Figures 1 to 20 refer to Fig.21 and Fig. 22 , the insulating layer INS between the light emitting areas LEA and a portion of the passivation layer PSV (e.g., the second passivation layer PSV2) may be sequentially etched away. Thus, the insulating layer INS and a portion of the passivation layer PSV (e.g., the second passivation layer PSV2) of the auxiliary light emitting elements LEa, LEb, and LEc may be separated from each other. For example, the insulating layer INS between the light emitting areas LEA and the second passivation layer PSV2 may be vertically etched to form a semiconductor device according to the present invention. Figure 5 The light emitting element LE of the embodiment.

[0145] Combination Figures 1 to 22 refer to Fig.23 In the step of etching the insulating layer INS and / or the passivation layer PSV, the insulating layer INS and / or the passivation layer PSV may be etched to have an inclined surface ICS with a selectable angle or range, so that a light emitting element LE including the inclined surface ICS may be manufactured. For example, the angle of the inclined surface ICS formed on the side surface of the second passivation layer PSV2 may be adjusted by adjusting the angle at which the second passivation layer PSV2 is etched between the light emitting areas LEA. According to an embodiment, the angle or range of forming the inclined surface ICS may be adjusted in consideration of the emission efficiency of the light emitting element LE.

[0146] Combination Figures 1 to 23 refer to Fig.24 In order to manufacture a light emitting element LE including a contact electrode CTE, a process of forming a contact electrode CTE on the second semiconductor layer SEM2 may be additionally performed. For example, the contact electrode CTE may be formed on the second semiconductor layer SEM2. In order to manufacture a light emitting element LE separated from a substrate SUB, one end or one end of the light emitting element LE where the contact electrode CTE is formed may be placed on a transfer substrate TSUB (or a transport substrate), and the substrate SUB may be separated from the light emitting element LE. According to an embodiment, the substrate SUB may be separated from the light emitting element LE by electro-etching and / or chemical etching, laser lift-off, or other techniques.

[0147] Figure 25 to Figure 27is a diagram showing the manufacture of a light emitting element LE (see Fig.24 ) is a schematic cross-sectional view of a method. For example, Figure 25 to Figure 27 Different embodiments of manufacturing the auxiliary light emitting elements LEa, LEb and LEc and / or the light emitting elements LE on a single substrate SUB in terms of separating the auxiliary light emitting elements LEa, LEb and LEc or the light emitting elements LE are shown.

[0148] Combination Figures 1 to 24 refer to Fig.25 , the auxiliary light emitting elements LEa, LEb and LEc respectively formed in the light emitting area LEA can be at least partially separated from each other. For example, after the second semiconductor layer SEM2 has been formed, a portion of the first semiconductor layer SEM1 (e.g., the upper portion above an optional height), the passivation layer PSV, the etching stop layer EST and the insulating layer INS can be etched so that the auxiliary light emitting elements LEa, LEb and LEc only share a portion of the first semiconductor layer SEM1 (e.g., the lower portion). In this way, the auxiliary light emitting elements LEa, LEb and LEc can be separated from each other above a given height of the first semiconductor layer SEM1. The light emitting area LEA can be arranged in a shape, size and / or interval corresponding to the respective auxiliary light emitting elements LEa, LEb and LEc. According to an embodiment, a process of forming a contact electrode CTE in each of the plurality of light emitting areas LEA can be added.

[0149] Combination Figures 1 to 25 refer to Fig.26 , the light emitting elements LE can be separated from each other so that they are respectively formed in the light emitting areas LEA. For example, after forming the second semiconductor layer SEM2, the first semiconductor layer SEM1, the passivation layer PSV, the etching stop layer EST and the insulating layer INS between the light emitting areas LEA are completely etched to the total thickness to form the light emitting elements LE. The light emitting areas LEA can be arranged in a shape, size and / or interval corresponding to each light emitting element LE. A plurality of light emitting elements LE can be simultaneously manufactured on one substrate SUB in the above manner. According to an embodiment, a process of forming a contact electrode CTE in each of the plurality of light emitting areas LEA can be added.

[0150] Apart from Figures 1 to 26 In addition, refer to Fig. 27, a light emitting element LE including at least two auxiliary light emitting elements LEa, LEb and LEc may be formed in each of a plurality of unit areas ULEA including at least two light emitting areas LEA. For example, light emitting elements LE each including at least two auxiliary light emitting elements LEa, LEb and LEc may be simultaneously manufactured on a single substrate SUB including the light emitting area LEA. According to an embodiment, the auxiliary light emitting elements LEa, LEb and LEc may be formed so that they include at least a portion of the first semiconductor layer SEM1 and are connected to each other, and the light emitting elements LE may be formed on the substrate SUB so that they are separated or spaced apart from each other. The light emitting area LEA may be arranged in a shape, size and / or interval corresponding to the respective auxiliary light emitting elements LEa, LEb and LEc and the respective light emitting elements LE. According to an embodiment, a process of forming a contact electrode CTE in each of the plurality of light emitting areas LEA may be added.

[0151] Fig.28 is a schematic perspective view showing a display device 10 according to the embodiment. Fig.29 It is shown Fig.28 A schematic plan view of an example of area A2.

[0152] exist Fig.28 and Fig.29 In the example shown in FIG. 1 , the display device 10 according to the embodiment is implemented as a semiconductor circuit substrate 101 (see FIG. 1 ) formed by a semiconductor process using a silicon wafer. Fig.31 ) is a light emitting diode on silicon (LEDoS) display having a light emitting diode as a light emitting element LE. However, it should be understood that the device including the light emitting element LE according to the embodiment is not limited thereto. For example, the light emitting element LE according to the embodiment may be applied to a display device of a different type and / or structure from LEDoS, or may be applied to a device of a different type and / or structure such as an illuminator.

[0153] exist Fig.28 and Fig.29, the first direction DR1 may indicate the horizontal direction of the display panel 100, the second direction DR2 may indicate the vertical direction of the display panel 100, and the third direction DR3 may indicate the thickness direction of the display panel 100 (or the semiconductor circuit substrate 101). As used herein, the terms "left" side, "right" side, "upper" side, and "lower" side may indicate relative positions when the display panel 100 is viewed from the top. For example, the right side may refer to one side or one side in the first direction DR1, the left side may refer to the other side or one side in the first direction DR1, the upper side may refer to one side or one side in the second direction DR2, and the lower side may refer to the other side or one side in the second direction DR2. The upper part may refer to the side indicated by the arrow of the third direction DR3, and the lower part may refer to the opposite side in the third direction DR3.

[0154] refer to Figure 28 to Figure 29 , the display device 10 according to the embodiment may include a display panel 100 including a display area DA and a non-display area NDA.

[0155] When viewed from the top, the display panel 100 may have a rectangular shape having longer sides in the first direction DR1 and shorter sides in the second direction DR2. However, it should be understood that the shape of the display panel 100 when viewed from the top is not limited thereto. When viewed from the top, it may have a polygonal shape other than a rectangular shape, a circular shape, an elliptical shape, or an irregular shape.

[0156] In the display area DA, an image may be displayed. In the non-display area NDA, no image may be displayed. According to an embodiment, the shape of the display area DA may follow the shape of the display panel 100 when viewed from the top. Fig.28 In the example shown in , the display area DA has a rectangular shape when viewed from the top. The display area DA may be disposed at a central area of ​​the display panel 100. The non-display area NDA may be disposed around the display area DA. For example, the non-display area NDA may surround the display area DA or may be adjacent to the display area DA.

[0157] The display area DA of the display panel 100 may include pixels PX. The pixels PX may include light emitting elements LE. Each of the plurality of pixels PX may be defined as a minimum light emitting unit capable of displaying white light by combining light emitted from the light emitting elements LE.

[0158] Each of the plurality of pixels PX may include a first light emitting element LE1 , a second light emitting element LE2 , a third light emitting element LE3 , and a fourth light emitting element LE4 .

[0159] The first light emitting element LE1 may emit a first light. The first light may be red light. For example, a main peak wavelength R-peak of the first light may be in a range of about 600 nm to about 750 nm, but the embodiments of the present disclosure are not limited thereto.

[0160] The second light emitting element LE2 and the fourth light emitting element LE4 may emit a second light. The second light may be green light. For example, a main peak wavelength G-peak of the second light may be in the range of about 480 nm to about 560 nm, but the embodiment is not limited thereto.

[0161] The third light emitting element LE3 may emit a third light. The third light may be blue light. For example, a main peak wavelength B-peak of the third light may be in the range of about 370 nm to about 460 nm, but the embodiment is not limited thereto.

[0162] In the display area DA, the first light emitting elements LE1 and the third light emitting elements LE3 may be alternately arranged in the first direction DR1. In the display area DA, the second light emitting elements LE2 and the fourth light emitting elements LE4 may be alternately arranged in the second direction DR2.

[0163] In the display area DA, the first light emitting element LE1, the second light emitting element LE2, the third light emitting element LE3 and the fourth light emitting element LE4 may be sequentially and repeatedly arranged in a first oblique direction DD1 and a second oblique direction DD2. The first oblique direction DD1 may be an oblique direction between the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be perpendicular to the first oblique direction DD1.

[0164] In each of the plurality of pixels PX, the first light emitting element LE1 and the third light emitting element LE3 may be arranged in the first direction DR1, and the second light emitting element LE2 and the fourth light emitting element LE4 may be arranged in the second direction DR2. In each of the plurality of pixels PX, the first light emitting element LE1 and the second light emitting element LE2 may be arranged in the first oblique direction DD1, the second light emitting element LE2 and the third light emitting element LE3 may be arranged in the second oblique direction DD2, and the third light emitting element LE3 and the fourth light emitting element LE4 may be arranged in the first oblique direction DD1. However, it should be understood that the embodiment is not limited thereto. The type, quantity, ratio and / or arrangement structure of the light emitting element LE included in each of the plurality of pixels PX may be modified according to different embodiments.

[0165] The fourth light emitting element LE4 may be substantially the same as the second light emitting element LE2. For example, the fourth light emitting element LE4 may emit the second light and have the same structure as the second light emitting element LE2. The second light and the fourth light may be green light.

[0166] like Fig.29 As shown in , the area of ​​the first light emitting element LE1, the area of ​​the second light emitting element LE2, the area of ​​the third light emitting element LE3, and the area of ​​the fourth light emitting element LE4 may be substantially all equal. However, it should be understood that the embodiment is not limited thereto. Fig.29 As shown in , the distance between the first light emitting element LE1 and the second light emitting element LE2 adjacent to each other, the distance between the second light emitting element LE2 and the third light emitting element LE3 adjacent to each other, the distance between the first light emitting element LE1 and the fourth light emitting element LE4 adjacent to each other, and the distance between the third light emitting element LE3 and the fourth light emitting element LE4 adjacent to each other may be substantially all equal. However, it should be understood that the embodiment is not limited thereto. For example, the size of each of the plurality of light emitting elements LE and / or the intervals between the light emitting elements LE may be modified according to different embodiments.

[0167] Although according to the embodiment, when viewed from the top, the light emitting element LE may have a circular shape, the embodiment is not limited thereto. For example, the light emitting element LE may have a polygonal shape, an elliptical shape, or an atypical shape. When viewed from the top, the light emitting elements LE may have substantially the same shape or may have different shapes for different groups.

[0168] The non-display area NDA may include a first common voltage supply area CVA1, a second common voltage supply area CVA2, a first pad area PDA1, a second pad area PDA2, and a peripheral area PHA.

[0169] The first common voltage supply area CVA1 may be disposed between the first pad area PDA1 and the display area DA. The second common voltage supply area CVA2 may be disposed between the second pad area PDA2 and the display area DA. Each of the first common voltage supply area CVA1 and the second common voltage supply area CVA2 may include a common electrode (e.g., Fig.31 The common electrode connector CVS of the second electrode ET2) of the common electrode. The common voltage can be supplied to the common electrode through the common electrode connector CVS.

[0170] The common electrode connector CVS of the first common voltage supply area CVA1 may be electrically connected to one of the plurality of first pads PD1 of the first pad area PDA1. For example, the common electrode connector CVS of the first common voltage supply area CVA1 may receive a common voltage from one of the plurality of first pads PD1 of the first pad area PDA1.

[0171] The common electrode connector CVS of the second common voltage supply area CVA2 may be electrically connected to one of the plurality of second pads of the second pad area PDA2. For example, the common electrode connector CVS of the second common voltage supply area CVA2 may receive a common voltage from one of the plurality of second pads of the second pad area PDA2.

[0172] The first pad area PDA1 may be disposed at one side or one side (eg, an upper side) of the display panel 100. The first pad area PDA1 may include first pads PD1 connected to an external circuit board.

[0173] The second pad area PDA2 may be disposed on the other side or sides (eg, the lower side of the display panel 100). The second pad area PDA2 may include a second pad connected to an external circuit board. According to an embodiment, the display panel 100 may not include the second pad area PDA2.

[0174] The peripheral area PHA may refer to other areas of the non-display area NDA except the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2. In addition to the display area DA, the peripheral area PHA may also surround the first common voltage supply area CVA1, the second common voltage supply area CVA2, the first pad area PDA1, and the second pad area PDA2.

[0175] Fig.30 It is shown Fig.28 A schematic plan view of an example of area A2. For example, Fig.30 It shows that according to Fig.29 Embodiments of different embodiments include a light emitting element LE in each pixel PX.

[0176] Combination Fig.28 and Fig.29 refer to Fig.30 , each of the plurality of pixels PX may include three light emitting elements LE. For example, each of the plurality of pixels PX may include a first light emitting element LE1, a second light emitting element LE2, and a third light emitting element LE3.

[0177] The first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 of the pixel PX may be sequentially and repeatedly arranged in the first direction DR1. For example, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may be arranged in the first direction DR1 in the order of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3. In each of the plurality of pixels PX, the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may be arranged in the first direction DR1. The first light emitting element LE1 may be arranged in the second direction DR2. The second light emitting element LE2 may be arranged in the second direction DR2. The third light emitting element LE3 may be arranged in the second direction DR2. The arrangement structure of the first light emitting element LE1, the second light emitting element LE2, and the third light emitting element LE3 may be modified according to different embodiments.

[0178] Fig.31 It is shown along Fig.30 Schematic cross-sectional view of an example of a cross section of the display panel 100 taken along line X1 - X1 ′.

[0179] Combination Figures 1 to 30 refer to Fig.31 , the display panel 100 may include a semiconductor circuit substrate 101 and a light emitting element layer 200 .

[0180] The semiconductor circuit substrate 101 may include a first substrate 110, a pixel circuit PXC, a first electrode ET1, a common electrode connector CVS, and a first pad PD1. According to an embodiment, the first electrode ET1 may be a pixel electrode individually and / or independently connected to each of a plurality of pixel circuits PXC, and the second electrode ET2 may be a common electrode commonly connected to the light emitting element LE.

[0181] According to an embodiment, the first substrate 110 may be a silicon wafer substrate. For example, the first substrate 110 may be made of single crystal silicon.

[0182] Each of the plurality of pixel circuits PXC may be disposed on the first substrate 110. Each of the plurality of pixel circuits PXC may include a complementary metal oxide semiconductor (CMOS) circuit formed using a semiconductor process. Each of the plurality of pixel circuits PXC may include at least one transistor formed via a semiconductor process. Each of the plurality of pixel circuits PXC may also include at least one capacitor formed via a semiconductor process.

[0183] The pixel circuit PXC may be disposed in the display area DA. Among the pixel circuits PXC, a plurality of pixel circuits PXC disposed in the display area DA may be electrically connected to a plurality of first electrodes ET1, respectively. For example, the pixel circuits PXC may be connected to the first electrodes ET1 in a one-to-one correspondence. The plurality of pixel circuits PXC may apply pixel voltages to the first electrodes ET1 connected thereto, respectively.

[0184] The first electrode ET1 may be disposed in the display area DA. The first electrode ET1 may be disposed on each pixel circuit PXC (also referred to as a pixel driving unit or a pixel circuit unit). Each of the plurality of first electrodes ET1 may be integrated with the pixel circuit PXC and may be an electrode exposed from the pixel circuit PXC. For example, each of the plurality of first electrodes ET1 may protrude from the upper surface of the pixel circuit PXC. Each of the plurality of first electrodes ET1 may receive a pixel voltage from the pixel circuit PXC. The first electrode ET1 may include a metal material such as aluminum (Al).

[0185] The common electrode connector CVS may be disposed in a common voltage supply area (e.g., a first common voltage supply area CVA1 and / or a second common voltage supply area CVA2) of the non-display area NDA. The present disclosure is not limited thereto. In an embodiment, a plurality of common electrode connectors CVS may be disposed on a plurality of pixel circuits PXC, respectively. Each of the plurality of common electrode connectors CVS may be integrated with a corresponding one of the plurality of pixel circuits PXC, and may be an electrode exposed from a corresponding one of the plurality of pixel circuits PXC. For example, each of the plurality of common electrode connectors CVS may protrude from an upper surface of a corresponding one of the plurality of pixel circuits PXC. The common electrode connector CVS may include a metal material such as aluminum (Al).

[0186] The first pads PD1 may be disposed in the first pad area PDA1 of the non-display area NDA. Each of the plurality of first pads PD1 may be connected to the circuit pad CPD1 of the circuit board 300 through a conductive connection member such as a wiring WR. For example, the first pads PD1 and the circuit pad CPD1 may be electrically connected to each other through the wiring WR.

[0187] The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), a flexible printed circuit (FPC), a flexible film (such as a chip on film (COF)), or other circuit boards. Although not shown in the drawings, the semiconductor circuit substrate 101 and the circuit board 300 may be disposed on a separate lower substrate. For example, the semiconductor circuit substrate 101 and the circuit board 300 may be attached to the upper surface of the lower substrate using an adhesive member such as a pressure-sensitive adhesive.

[0188] The light emitting element layer 200 may include a light emitting element LE, a second electrode ET2 and a connection electrode CNE. According to an embodiment, the light emitting element layer 200 may further include additional elements. For example, the light emitting element layer 200 may further include an organic film, a light shielding layer and / or a reflective layer disposed between the light emitting elements LE.

[0189] The plurality of light emitting elements LE may be disposed on the plurality of first electrodes ET1, respectively. Each of the plurality of light emitting elements LE may be connected between a corresponding one of the plurality of first electrodes ET1 and the second electrode ET2.

[0190] The light emitting element LE may be formed by growing on a semiconductor substrate. Each of the plurality of light emitting elements LE may be transferred from the semiconductor substrate to the first electrode ET1 of the semiconductor circuit substrate 101, or may be transferred to the first electrode ET1 of the semiconductor circuit substrate 101 by an electrostatic method using an electrostatic head or by a stamping method using an elastic polymer material such as polydimethylsiloxane (PDMS) and silicon as a transfer substrate.

[0191] Each of the plurality of light emitting elements LE may include a corresponding one of the first semiconductor layers SEM1, SEM1a, and SEM1b, a corresponding one of the active layers EML, EMLa, and EMLb, and a corresponding one of the second semiconductor layers SEM2, SEM2a, and SEM2b. At least one of the plurality of light emitting elements LE (e.g., the first light emitting element LE1) may further include a passivation layer PSV. Each of the plurality of light emitting elements LE may further include a corresponding one of the insulating layers INS, INSa, and INSb. According to an embodiment, each of the plurality of light emitting elements LE may further include a corresponding one of the contact electrodes CTE, CTEa, and CTEb.

[0192] According to an embodiment, the pixel PX may include a light emitting element LE having a different structure. For example, the pixel PX may include a light emitting element LE having a structure according to the above reference Figures 1 to 27 The first light emitting element LE1 of at least one of the multiple embodiments described above and the second light emitting element LE2 and the third light emitting element LE3 having structures different from the structure of the first light emitting element LE1. However, it should be understood that the embodiments are not limited thereto. For example, at least one of the second light emitting element LE2 and the third light emitting element LE3 may have a structure substantially similar to or the same as the structure of the first light emitting element LE1.

[0193] Although in Fig.31In the example shown in , each of the plurality of light emitting elements LE has a vertical side surface, but the embodiment is not limited thereto. For example, at least one light emitting element LE may include an inclined side surface so that the width is at least partially gradually reduced or increased. For example, the passivation layer PSV of the first light emitting element LE1 may include an inclined surface (e.g., Figure 4 The inclined surface ICS) is the side surface.

[0194] The first light emitting element LE1 may include a first semiconductor layer SEM1, a passivation layer PSV, an active layer EML, and a second semiconductor layer SEM2. The first light emitting element LE1 may also include at least one of an etching stop layer EST, an insulating layer INS, and a contact electrode CTE. The first light emitting element LE1 may have a structure and / or shape according to the above-described embodiments. The first semiconductor layer SEM1, the passivation layer PSV, the active layer EML, the second semiconductor layer SEM2, the etching stop layer EST, the insulating layer INS, and the contact electrode CTE of the first light emitting element LE1 may include the materials according to the above-described embodiments.

[0195] The passivation layer PSV of the first light emitting element LE1 may include a semiconductor material having a lattice matching or the same lattice as that of the semiconductor material included in the active layer EML, and may surround the active layer EML. Therefore, surface defects of the first light emitting element LE1 may be suppressed or reduced, and the emission efficiency of the first light emitting element LE1 and the pixel PX including the first light emitting element LE1 may be improved.

[0196] The passivation layer PSV of the first light emitting element LE1 may be formed of a semiconductor material having a bandgap energy higher than that of the semiconductor material included in the active layer EML. Therefore, non-emissive recombination of electrons and holes may be prevented or reduced, and the emission efficiency of the first light emitting element LE1 and the pixel PX including the first light emitting element LE1 may be improved.

[0197] The second light emitting element LE2 may include a first semiconductor layer SEM1a, an active layer EMLa, and a second semiconductor layer SEM2a sequentially disposed in a thickness direction (e.g., in a third direction DR3). The second light emitting element LE2 may also include at least one of an insulating layer INSa and a contact electrode CTEa. The insulating layer INSa may surround the first semiconductor layer SEM1a, the active layer EMLa, and the second semiconductor layer SEM2a. The contact electrode CTEa may be disposed at an end portion where the second semiconductor layer SEM2a of the second light emitting element LE2 is located. For example, the contact electrode CTEa may be disposed between the first electrode ET1 associated with the second light emitting element LE2 and the second semiconductor layer SEM2a of the second light emitting element LE2.

[0198] The third light emitting element LE3 may include a first semiconductor layer SEM1b, an active layer EMLb, and a second semiconductor layer SEM2b sequentially arranged in a thickness direction (e.g., in a third direction DR3). The third light emitting element LE3 may also include at least one of an insulating layer INSb and a contact electrode CTEb. The insulating layer INSb may surround the first semiconductor layer SEM1b, the active layer EMLb, and the second semiconductor layer SEM2b. The contact electrode CTEb may be disposed at an end portion where the second semiconductor layer SEM2b of the third light emitting element LE3 is located. For example, the contact electrode CTEb may be disposed between the first electrode ET1 associated with the third light emitting element LE3 and the second semiconductor layer SEM2b of the third light emitting element LE3.

[0199] According to an embodiment, the second light emitting element LE2 and the third light emitting element LE3 may be inorganic light emitting elements formed of inorganic materials. For example, the second light emitting element LE2 and the third light emitting element LE3 may be inorganic light emitting diodes (inorganic LEDs) formed of phosphide semiconductor materials (such as GaP, GaInP, AlGaP, AlInP, AlGaInP, AlP, and InP), nitride semiconductor materials (such as GaN, AlGaN, InGaN, AlInGaN, AlN, and InN), or other inorganic materials.

[0200] According to an embodiment, the second light emitting element LE2 may be a green LED (e.g., a green micro LED) formed of a nitride semiconductor material and emitting green light. For example, the first semiconductor layer SEM1a, the active layer EMLa, and the second semiconductor layer SEM2a of the second light emitting element LE2 may include a nitride semiconductor material (such as GaN, AlGaN, InGaN, AlInGaN, AlN, and InN). The first semiconductor layer SEM1a of the second light emitting element LE2 may be a first conductive type semiconductor layer doped to a first conductive type (e.g., n-type), and the second semiconductor layer SEM2a of the second light emitting element LE2 may be a second conductive type semiconductor layer doped to a second conductive type (e.g., p-type). The active layer EMLa of the second light emitting element LE2 may be a green emission layer having a multi-quantum well structure and emitting green light.

[0201] According to an embodiment, the third light emitting element LE3 may be a blue LED (e.g., a blue micro LED) formed of a nitride semiconductor material and emitting blue light. For example, the first semiconductor layer SEM1b, the active layer EMLb, and the second semiconductor layer SEM2b of the third light emitting element LE3 may include nitride semiconductor materials such as GaN, AlGaN, InGaN, AlInGaN, AlN, and InN. The first semiconductor layer SEM1b of the third light emitting element LE3 may be a first conductive type semiconductor layer doped to a first conductive type (e.g., n-type), and the second semiconductor layer SEM2b of the third light emitting element LE3 may be a second conductive type semiconductor layer doped to a second conductive type (e.g., p-type). The active layer EMLb of the third light emitting element LE3 may be a blue emission layer having a multi-quantum well structure and emitting blue light.

[0202] The insulating layers INSa and INSb of the second light emitting element LE2 and the third light emitting element LE3 may include a silicon oxide (SiO x )(For example, SiO 2 ), silicon nitride (Si x N y )(For example, Si 3 N 4 ), aluminum oxide (Al x O y )(For example, Al 2 O 3 ), titanium oxide (Ti x O y )(For example, TiO 2 ) and hafnium oxide (HfO x ) or other insulating materials. The insulating layers INS, INSa and INSb of the first light emitting element LE1, the second light emitting element LE2 and the third light emitting element LE3 may include the same insulating material or different insulating materials.

[0203] The contact electrodes CTEa and CTEb of the second light emitting element LE2 and the third light emitting element LE3 may include metal, metal oxide or other conductive materials. The contact electrodes CTE, CTEa and CTEb of the first light emitting element LE1, the second light emitting element LE2 and the third light emitting element LE3 may include the same conductive material or different conductive materials. The contact electrodes CTE, CTEa and CTEb may be used as a bonding metal for adhering and / or connecting the light emitting element LE to the first electrode ET1 during the manufacturing process.

[0204] The second electrode ET2 may be disposed on the light emitting element LE. The second electrode ET2 may be a common electrode shared by the light emitting elements LE, and may be connected to the second semiconductor layers SEM2, SEM2a, and SEM2b of the light emitting elements LE.

[0205] The second electrode ET2 may be electrically connected to the common electrode connector CVS of the semiconductor circuit substrate 101 through the connection electrode CNE disposed in the common voltage supply area (e.g., the first common voltage supply area CVA1 and / or the second common voltage supply area CVA2). Therefore, the second electrode ET2 may receive the common voltage through the common electrode connector CVS of the semiconductor circuit substrate 101.

[0206] The plurality of connection electrodes CNE may be connected to the plurality of common electrode connectors CVS, respectively. For example, the plurality of connection electrodes CNE may be disposed on the plurality of common electrode connectors CVS, respectively. The connection electrode CNE may extend in the third direction DR3 and may be connected to the second electrode ET2. For example, the height of the connection electrode CNE may be substantially equal to the height of the light emitting element LE.

[0207] The connection electrode CNE may include a material electrically connected to the second electrode ET2. According to an embodiment, the connection electrode CNE may be made of, but not limited to, the same material as the contact electrodes CTE, CTEa, and CTEb.

[0208] According to an embodiment, the display panel 100 may further include additional elements. For example, the display panel 100 may further include a passivation layer (eg, an encapsulation layer or an encapsulation substrate) covering at least the light emitting element layer 200 .

[0209] Fig.32 1 is a view showing an example of a virtual reality device 1 including a display device 10_1 according to an embodiment.

[0210] refer to Fig.32 The virtual reality device 1 according to the embodiment may be a device in the form of glasses. The virtual reality device 1 according to the embodiment may include a display device 10_1, a left eyeglass 10a, a right eyeglass 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display housing 50.

[0211] although Fig.32 The virtual reality device 1 including the temples 30a and 30b is shown, but as the virtual reality device 1 according to the embodiment, a head mounted display having a headband may be used instead of the temples 30a and 30b. For example, the virtual reality device 1 according to the embodiment is not limited to Fig.32 The virtual reality device 1 shown in FIG. 1 may be applied to various electronic devices in various forms.

[0212] The display housing 50 may include a display device 10_1 and a reflective member 40. The image displayed in the display device 10_1 may be reflected by the reflective member 40 and provided to the user's right eye through the right eye lens 10b. Therefore, the user may view the virtual reality image displayed in the display device 10_1 through the right eye.

[0213] Despite Fig.32 In the example shown in , the display housing 50 is arranged at the right end of the supporting frame 20, but the embodiment is not limited thereto. For example, the display housing 50 can be arranged at the left end of the supporting frame 20. In this case, the image displayed in the display device 10_1 can be reflected by the reflection member 40 and provided to the left eye of the user through the left eye lens 10a. Therefore, the user can watch the virtual reality image displayed in the display device 10_1 through the left eye. By way of example, the display housing 50 can be respectively arranged at the left end and the right end of the supporting frame 20. In this case, the user can watch the virtual reality image displayed in the display device 10_1 through the left eye and the right eye.

[0214] Fig.33 10_2 is a view showing an example of a smart device including a display device 10_2 according to an embodiment.

[0215] refer to Fig.33 , the display device 10_2 according to the embodiment can be applied to a smart watch 2 which is one of a variety of smart devices. When observed from the top, the shape of the watch display unit of the smart watch 2 may follow the flat shape of the display device 10_2. For example, in a case where the display device 10_2 according to the embodiment has a circular or oval shape when observed from the top, the watch display unit of the smart watch 2 may have a circular shape or an oval shape when observed from the top. By way of example, in a case where the display device 10_2 according to the embodiment has a rectangular shape when observed from the top, the watch display unit of the smart watch 2 may have a rectangular shape when observed from the top. However, it should be understood that the present disclosure is not limited to this. The watch display unit of the smart watch 2 may not follow the shape of the display device 10_2 when observed from the top.

[0216] Fig.34 An example of an instrument cluster and a center instrument panel for a vehicle including display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to the embodiments is shown. Fig.34 Vehicles in which the display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to the embodiments are applied are shown.

[0217] refer to Fig.34The display devices 10_a, 10_b and 10_c according to the embodiments may be applied to the instrument cluster of the vehicle, may be applied to the central instrument panel of the vehicle, or may be applied to the central information display (CID) set on the dashboard of the vehicle. By way of example, the display devices 10_d and 10_e according to the embodiments may be applied to the in-vehicle rearview mirror display that may replace the side mirrors of the vehicle.

[0218] Fig.35 10_3 is a view showing an example of a transparent display device including a display device 10_3 according to an embodiment.

[0219] refer to Fig.35 , the display device 10_3 according to the embodiment can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. Therefore, a user positioned at the front side of the transparent display device can observe not only the image IM displayed in the display device 10_3, but also an object RS or a background positioned at the rear side of the transparent display device. In the case where the display device 10_3 is applied to a transparent display device, the display panel may include a light-transmitting portion that can transmit light, or may be formed on a base member made of a material that can transmit light.

[0220] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments are intended to be general and descriptive only and not for purposes of limitation.

Claims

1. A light emitting element, wherein: The light emitting element comprises: A first semiconductor layer is doped to a first conductivity type; An active layer, disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer, wherein the second semiconductor layer is doped into a second conductivity type; and a passivation layer surrounding a plurality of surfaces of the active layer, the plurality of surfaces including side surfaces of the active layer, wherein: The passivation layer includes a semiconductor material that is lattice matched to a semiconductor material contained in the active layer, and The semiconductor material included in the passivation layer has a band gap energy higher than a band gap energy of the semiconductor material included in the active layer.

2. The light-emitting element according to claim 1, wherein The active layer includes a quantum well layer comprising GaInP and a barrier layer comprising AlGaInP, and The passivation layer is formed as a semiconductor layer including AlInP.

3. The light-emitting element according to claim 2, wherein The passivation layer is formed as an intrinsic semiconductor layer including AlInP.

4. The light-emitting element according to claim 1, wherein The passivation layer is disposed between the first semiconductor layer and the second semiconductor layer, and The passivation layer completely surrounds the plurality of surfaces of the active layer including the first bottom surface, the second bottom surface, and the side surfaces of the active layer.

5. The light emitting element according to claim 4, wherein The passivation layer comprises: a first passivation layer, disposed between the first semiconductor layer and the active layer; a second passivation layer disposed at a peripheral region of the first passivation layer and contacting the side surface of the active layer; a third passivation layer disposed at a central region of the first passivation layer and contacting the first bottom surface of the active layer; and A fourth passivation layer is disposed on the active layer and contacts the second bottom surface of the active layer.

6. The light-emitting element according to claim 5, wherein The light emitting element further comprises: An etch stop layer is disposed between the first passivation layer and the second passivation layer and surrounds the third passivation layer.

7. The light-emitting element according to claim 6, wherein The etch stop layer includes an opening overlapping the active layer.

8. The light emitting element according to claim 6, wherein The etch stop layer is formed as an intrinsic semiconductor layer including AlGaAs.

9. The light-emitting element according to claim 1, wherein The passivation layer includes a side surface including an inclined surface.

10. The light emitting element according to claim 1, wherein The light emitting element further comprises: The insulating layer is disposed at the peripheral region of the passivation layer.

11. A display device, wherein: The display device comprises: A plurality of pixels, each of the plurality of pixels comprises a first electrode, a second electrode, and a light emitting element electrically connected between the first electrode and the second electrode, wherein: The light emitting element comprises: A first semiconductor layer is doped to a first conductivity type; An active layer, disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer and doped to a second conductivity type; and a passivation layer surrounding a plurality of surfaces of the active layer, the plurality of surfaces including a side surface of the active layer, The passivation layer includes a semiconductor material that is lattice matched to a semiconductor material contained in the active layer, and The semiconductor material included in the passivation layer has a band gap energy higher than a band gap energy of the semiconductor material included in the active layer.

12. The display device according to claim 11, wherein: The active layer includes a quantum well layer comprising GaInP and a barrier layer comprising AlGaInP, and The passivation layer is formed as a semiconductor layer including AlInP.

13. The display device according to claim 11, wherein: The passivation layer is disposed between the first semiconductor layer and the second semiconductor layer, and The passivation layer completely surrounds the plurality of surfaces of the active layer including the first bottom surface, the second bottom surface, and the side surfaces of the active layer.

14. The display device according to claim 13, wherein: The passivation layer comprises: a first passivation layer, disposed between the first semiconductor layer and the active layer; a second passivation layer disposed at a peripheral region of the first passivation layer and contacting the side surface of the active layer; a third passivation layer disposed at a central region of the first passivation layer and contacting the first bottom surface of the active layer; and A fourth passivation layer is disposed on the active layer and contacts the second bottom surface of the active layer.

15. The display device according to claim 14, wherein: The light emitting element further includes an etching stop layer disposed between the first passivation layer and the second passivation layer and surrounding the third passivation layer.

16. The display device according to claim 11, wherein: The passivation layer includes a side surface including an inclined surface.

17. A method for manufacturing a light emitting element, wherein: The method comprises: sequentially forming a first semiconductor layer, a first passivation layer, an etch stop layer, a second passivation layer and an insulating layer on a substrate; etching a portion of the insulating layer to expose a portion of the second passivation layer; exposing a portion of the etch stop layer by etching the exposed portion of the second passivation layer; exposing a portion of the first passivation layer by etching the exposed portion of the etch stop layer; and A third passivation layer, an active layer, a fourth passivation layer, and a second semiconductor layer are sequentially formed on the exposed portion of the first passivation layer.

18. The method according to claim 17, wherein: The first passivation layer, the second passivation layer, the third passivation layer, and the fourth passivation layer are formed of a semiconductor material having the same lattice as that of a semiconductor material included in the active layer, and The semiconductor material included in the first, second, third, and fourth passivation layers has a band gap energy higher than a band gap energy of the semiconductor material included in the active layer.

19. The method according to claim 18, wherein: The forming of the active layer includes alternately forming a barrier layer including AlGaInP and a quantum well layer including GaInP on the third passivation layer, and The first passivation layer, the second passivation layer, the third passivation layer, and the fourth passivation layer are formed using AlInP as a material.

20. The method according to claim 17, wherein: The method further comprises: forming a plurality of light emitting elements on the substrate at the same time; and After the second semiconductor layer has been formed, the plurality of light emitting elements are at least partially separated from one another.

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