High-speed, low-power and area-saving transmitter

Abstract

A transmitter employs a simple inverter to pre-drive a cascaded pull-up output stage and a pull-down output stage. Each output stage includes a drive transistor having a thin gate dielectric for fast switching. The drive transistor is cascade-connected to a set of transistors connected in parallel. Calibration circuitry selectively enables the transistors connected in parallel to calibrate the output resistance. Transistors connected in parallel converge at a single resistor.

Description

Technical Field

[0001] The present invention relates generally to the field of communications and, more particularly, to high speed electronic signal transmission within and between integrated circuits. Background Art

[0002] Electrical conductors, even very good ones, will resist the flow of electrical current and thus the transmission of electrical signals. This resistance (called "impedance") has two components, resistance and reactance. For ease of illustration and not limitation, this disclosure focuses on resistance.

[0003] A transmitter whose job it is to drive a signal through a conductor to a receiving device (load) presents an output resistance that should be matched to the load. This matching maximizes the efficiency of signal propagation, minimizes signal reflections that could interfere with reception, and becomes more important as speed performance increases. Therefore, high-speed transmitters include circuitry for calibrating the output resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An integrated circuit device having an area-saving transmitter supporting high-speed, low-power data transmission is shown by way of example and not limitation. DETAILED DESCRIPTION

[0005] Figure 1 An integrated circuit (IC) device 100 is depicted with an area-saving output amplifier 105, which is a transmitter that supports output resistance calibration and high-speed, low-power data transmission. Simple pre-driver and drive transistors switch quickly. Calibration circuitry for output resistance is not switched for data transmission, which relaxes design constraints and saves power. Parallel branches that are selectively enabled for resistance calibration converge at a single polysilicon resistor.

[0006] Amplifier 105 receives input data as a common signal Din and issues amplified single-ended output data Dout on output pad 110, which is a signal node that provides external electrical connection to IC 100. IC 100 can be, for example, a memory device, and amplifier 105 can be a transmitter for transmitting write data to the memory device. In one embodiment, IC 100 is a fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM), and amplifier 105 supports a data rate of at least 6.4 Gbps.

[0007] The output signal Dout switches between a relatively high voltage and a relatively low voltage to represent a pattern of data. The amplifier 105 is complementary, that is, it includes two circuits 115 and 120 that mirror each other to "pull" high and "pull" low output voltages, respectively. Starting from the pull-up circuit 115, an inverting amplifier or "inverter" 125 acts as a pre-driver, which amplifies and inverts the signal Din at the input node of the same identification to transmit the data signal DinP at the output node of the same identification. The term "pre-driver" refers to an early gain stage (gain refers to amplification) that feeds a second gain stage (called a "driver" or "output driver") in this example, which drives the data signal to the pad 110 and away from the device 100.

[0008] The second gain stage includes a first driver transistor 130, which is cascade connected to a set of parallel second driver transistors 135. Transistor 130 has a control terminal (gate) coupled to the output of pre-driver 125, a first current handling terminal (source) coupled to power supply node VDD, and a second current handling terminal (drain) cascaded to the uppermost current handling terminal of second driver transistors 135, which are parallel calibration branches that can be independently enabled or disabled to adjust their total resistance. In other embodiments, transistor 135 can be replaced or supplemented by a transistor that is calibrated via a controlled gate voltage.

[0009] Passive resistive element 140 (in this example, a polysilicon resistor) connects the lowermost current handling terminal of the second driver transistor 135 to the output node Dout. The output resistance of the pull-up circuit 115 is a function of the resistance of the second driver transistor 135 connected in parallel through resistor 140. The value of element 140 is approximate because the resistance is a function of the device geometry and doping concentration, both of which are difficult to control accurately. The resistance of the transistors 135 is also subject to difficult-to-control process variations, and their total resistance is also a function of the combination of enabled transistors. Calibration logic 150 coupled to the control terminal of transistor 135 can disable one or more transistors 135 to calibrate their combined resistance, thereby calibrating the total output resistance of the pull-up circuit 115.

[0010] Each transistor 135 is labeled with a multiple of the ratio W / L, which refers to the minimum width and length. The resistance of each transistor 135 is a function of its width, with wider widths providing lower resistance. The gate widths are binary weighted so that the set of enabled transistors 135 uniformly spans a range of values ​​suitable for achieving a desired calibration resistance (e.g., 240 Ohms) given expected variations in, for example, device characteristics, supply voltage, and temperature. The calibration logic 150 performs a NAND function of the enable signal EN and each of the six calibration values ​​PsideCal[5:0] to enable any subset of the transistors 135. Disabled transistors present a high resistance to the node Dout, effectively removing them from the circuit 115. The enable signal EN can be deasserted (turned low) to completely disable the amplifier 105.

[0011] Transistors 130 and 135 are PMOS, i.e., active devices whose control terminals are electrically isolated from their current handling terminals by gate dielectrics. The gate dielectric of transistor 130 may have the same or different thickness than the gate dielectric of transistor 135. A thinner gate dielectric increases switching speed, thereby increasing the speed performance of amplifier 105. In pull-up circuit 115, only inverter 125 and transistor 130 are switched during data transmission. Transistor 135, calibration logic 150, and resistor 140 are static after calibration and are less restricted. When transistor 135 is enabled, transistor 135 is biased to operate in the linear region during data transmission by having calibration logic 150 apply a gate voltage VSSREG selected for this purpose, where VSSREG=VDD-VREG.

[0012] The pull-down circuit 120 is similar in function to the pull-up circuit device 115, but includes NMOS transistors 160 and 165 to pull the voltage on the output node Dout toward a lower supply voltage (ground potential in this example). The gate dielectric of transistor 160 can be thin relative to the gate dielectric of transistor 165. Inverter 155 acts as a pre-driver, which amplifies and inverts the signal Din to transmit the signal PinN to transistor 160. The calibration logic 170 performs a NAND function of the enable signal EN and each of the calibration values ​​NsideCal[5:0] to enable any subset of transistors 165. When transistor 165 is enabled, by causing the calibration logic 170 to apply the gate voltage VREG, transistor 165 is biased to operate in the linear region during data transmission. The bias voltages VREG and VSSREG can be provided by a power supply external to IC 100, or can be obtained from internally available power supply voltages (e.g., VDD and ground).

[0013] Amplifier 105 advantageously employs simple pre-drivers 125 and 155 to improve power and speed performance. Calibration logic 150 and 170 are not switched for data transmission, which relaxes design constraints and saves power. The pull-up current path and the pull-down current path each converge at a single resistor 140, which minimizes the area required if a corresponding resistor is required in each branch.

[0014] In the foregoing description and drawings, specific terms and figure symbols are set forth to provide a comprehensive understanding of the present invention. In some cases, these terms and symbols may imply specific details that are not required for practicing the present invention. For example, the interconnects between circuit elements or circuit blocks may be shown or described as multi-conductor signal lines or single-conductor signal lines. Each multi-conductor signal line in the multi-conductor signal line may alternatively be a single-conductor signal line, and each single-conductor signal line in the single-conductor signal line may alternatively be a multi-conductor signal line. Signals and signal transmission paths shown or described as single-ended may also be differential, and vice versa. Similarly, in alternative embodiments, signals described or depicted as having effective high or effective low logic levels may have opposite logic levels. As another example, a circuit described or depicted as including a metal oxide semiconductor (MOS) transistor may alternatively be implemented using bipolar technology or any other technology that can realize signal control current. With regard to terminology, when a signal is driven to a low logic state or a high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition, the signal is referred to as "assertion". Conversely, a signal is referred to as "de-asserted" to indicate that the signal is charged or discharged to a state other than the asserted state, including a high or low logic state, or a floating state that may occur when the signal driving circuit transitions to a high impedance condition such as an open drain or open collector condition.

[0015] The output of a design process for an integrated circuit may include a computer readable medium (such as a magnetic tape) encoded with data structures defining how circuit devices may be physically instantiated as an integrated circuit. These data structures are typically written in the Caltech Intermediate Format (CIF) or GDSII, a proprietary binary format. One skilled in the art of mask preparation may develop such data structures based on schematic diagrams of the type described above.

[0016] Although the present invention has been described with reference to specific embodiments of the present invention, it is apparent that various modifications and changes may be made to it without departing from the broader spirit and scope of the present invention. The variations of these embodiments will be apparent to those of ordinary skill in the art after reading this disclosure. In addition, some components are shown as being directly connected to each other, while other components are shown as being connected via intermediate components. In each case, the method of interconnection or "coupling" establishes some desired electrical communications between two or more circuit nodes or terminals. As will be appreciated by those skilled in the art, such coupling can often be accomplished using a variety of circuit configurations. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims that specifically describe "devices for..." or "steps for..." should be interpreted in the manner required by the sixth paragraph of 35 U.S.C. §112.

Claims

1. An integrated circuit device, comprising: a pre-driver having a pre-driver input node and a pre-driver output node; Drive with: a first driver transistor having a control terminal, a first current handling terminal coupled to the pre-driver output node, and a second current handling terminal, the control terminal being coupled to the pre-driver output node, the first current handling terminal being coupled to a power supply node; as well as second drive transistors connected in parallel, each second drive transistor having a control terminal, a first current handling terminal, and a second current handling terminal, the first current handling terminal being coupled to the second current handling terminal of the first drive transistor; calibration logic coupled to the control terminal of the second drive transistor, the calibration logic to selectively enable the second drive transistor; as well as An output pad is coupled to a second current handling terminal of the second driving transistor, and the output node is used to provide an external electrical connection from the integrated circuit device.

2. The integrated circuit device of claim 1, wherein the pre-driver is composed of an inverting amplifier. 3 . The integrated circuit device according to claim 1 , wherein each of the first drive transistor and the second drive transistor has a gate having the same gate thickness. 4 . The integrated circuit device of claim 1 , wherein the output pad is coupled to the second current handling terminal of the second drive transistor via a passive resistive element.

5. The integrated circuit device of claim 4, wherein the passive resistance element consists essentially of a single resistor.

6. The integrated circuit device of claim 5, wherein the single resistor consists essentially of polysilicon.

7. The integrated circuit device of claim 1, the pre-driver further comprising a second pre-driver input node and a second pre-driver output node.

8. The integrated circuit device according to claim 7, wherein the driver further comprises: a third driver transistor having a control terminal, a third current handling terminal, and a fourth current handling terminal, the control terminal being coupled to the second pre-driver output node, the third current handling terminal being coupled to a second power supply node; as well as Fourth drive transistors are connected in parallel, each having a control terminal, a first current handling terminal coupled to the second current handling terminal of the third drive transistor, and a second current handling terminal coupled to the output pad.

9. The integrated circuit device of claim 8, wherein the calibration logic is further coupled to the control terminal of the fourth driver transistor, the calibration logic being configured to selectively enable the fourth driver transistor.

10. The integrated circuit device according to claim 1, further comprising: An electrostatic discharge protection device is coupled between the output pad and the second current handling terminal of the second drive transistor.

11. A transmitter for sending a signal at a transmitter output node, the transmitter comprising: a first pre-driver, driving a pull-up transistor; a first parallel calibration branch commonly cascade-connected to the pull-up transistor; a first passive resistive element coupled between the first shunt calibration branch and the transmitter output node; a second pre-driver driving a pull-down transistor; a second parallel calibration branch commonly cascade-connected to the pull-down transistor; as well as A second passive resistive element is coupled between the second shunt calibration branch and the transmitter output node.

12. The transmitter of claim 11, integrated on an integrated circuit device, wherein the transmitter output node comprises a pad for external electrical connection to the integrated circuit device.

13. The transmitter of claim 11, further comprising: An electrostatic discharge protection device connected to the output node.

14. The transmitter of claim 11, further comprising calibration logic coupled to the first parallel calibration branch and the second parallel calibration branch to selectively disable some of the first parallel calibration branch and the second parallel calibration branch.

15. The transmitter of claim 11, wherein the passive resistive element comprises a polysilicon resistor.

16. The transmitter of claim 11, wherein at least one of the first pre-driver and the second pre-driver consists essentially of an inverter.

17. The transmitter of claim 11, wherein the pull-up transistor comprises a gate dielectric of a dielectric thickness, and the first calibration branch comprises second pull-up transistors, each second pull-up transistor having a gate dielectric of the same dielectric thickness.

18. The transmitter of claim 11, wherein the pull-down transistor comprises a gate dielectric of a dielectric thickness, and the second calibration branch comprises second pull-down transistors, each second pull-down transistor having a gate dielectric of the same dielectric thickness.

19. The transmitter of claim 11, wherein the pull-up transistor is a PMOS transistor and the pull-down transistor is an NMOS transistor.

20. An amplifier for amplifying a signal between an input node and an output node, the amplifier comprising: Power terminal; as well as A circuit connected between the power supply terminal and the output node, the circuit comprising: a drive transistor having a control terminal, a first current handling terminal, and a second current handling terminal, the control terminal being coupled to the input node; Passive resistor components; as well as parallel calibration branches, the parallel calibration branches being connected together in series; as well as Calibration logic is coupled to the parallel calibration branches to selectively disable some of the branches.

21. The amplifier of claim 19, wherein the passive resistance element is coupled between the calibration branch and the output node.

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