Acoustic sensor chip processing and packaging method

Abstract

The invention discloses an acoustic sensor chip processing and packaging method, which comprises the following steps of: firstly, carrying out first graphical shallow cavity etching on a device layer of a first SOI (Silicon On Insulator) wafer to form two shallow cavities and an anchor point; performing etching in the two shallow cavities to form a stop structure; generating a second oxide layer on the surface of the device layer through a thermal oxidation process; etching the device layer of the first SOI wafer to the buried oxide layer in a graphical manner, and physically isolating the backstop structure and the lower electrode from other silicon in the device layer; sequentially carrying out graphical etching on the device layer on the lower electrode to the buried oxide layer, then etching the buried oxide layer to the substrate layer, and finally etching the substrate layer by a certain depth to finally obtain a damping hole; performing face-to-face silicon-silicon bonding on the device layers of the two SOI wafers; and removing the first oxide layer, the substrate layer and the buried oxide layer on the substrate layer of the second SOI wafer. According to the processing method, the sensitivity, the signal-to-noise ratio, the bandwidth and other indexes of the vibration interference resistant MEMS fully differential microphone are improved.

Description

Technical Field

[0001] The present invention relates to the field of MEMS technology, and in particular to a method for processing and packaging an acoustic sensor chip. Background Art

[0002] Scalar MEMS microphones can only measure scalar information of sound pressure in the sound field. Vector microphones can not only measure scalar information of sound pressure, but also measure scalar information such as sound pressure gradient, which can reflect the sound field more comprehensively. Differential output can suppress the influence of common mode interference such as temperature on microphone performance, and can improve the linearity of the microphone. Existing MEMS microphones are mainly scalar. In order to realize the measurement of vector information, a processing and packaging method of a bottom-feeding vector acoustic chip that can simultaneously measure sound pressure information and sound pressure gradient information is proposed. Summary of the invention

[0003] The purpose of the present invention is to provide a method for processing and packaging an acoustic sensor chip to achieve measurement of an acoustic pressure signal and an acoustic pressure gradient signal in an acoustic field.

[0004] The technical solution of the present invention is: A method for processing an acoustic sensor chip comprises the following steps: S1. Select two SOI wafers, each SOI wafer comprising a device layer, a buried oxide layer, a substrate layer and a first oxide layer connected in sequence; S2, performing a first patterned shallow cavity etching on the device layer of the first SOI wafer to form two shallow cavities symmetrically distributed on the left and right, and the unetched portion between the two shallow cavities serves as an anchor point; S3, performing a second patterned shallow cavity etching on the device layer of the first SOI wafer to form a stopper structure in two shallow cavities; S4, generating a second oxide layer on the surface of the first SOI wafer device layer by a thermal oxidation process; S5, patterning and etching to remove a portion of the second oxide layer to form a bonding area between the first SOI wafer and the second SOI wafer and an area on the lower electrode where a damping hole is to be opened; S6, patterning and etching the device layer of the first SOI wafer to the buried oxide layer, and physically isolating the stopper structure and the lower electrode from other silicon in the device layer; S7, sequentially pattern-etching the device layer on the lower electrode to the buried oxide layer, then etching the buried oxide layer to the substrate layer, and finally etching the substrate layer to a certain depth, finally obtaining a damping hole; S8, performing face-to-face silicon-silicon bonding on the device layer of the second SOI wafer and the device layer of the first SOI wafer; S9, removing the first oxide layer, the substrate layer and the buried oxide layer on the second SOI wafer substrate layer; S10, pattern-etching the substrate layer and the first oxide layer of the first SOI wafer to increase the volume of air in the rear chamber; S11, patterning metal pads on the device layer of the first SOI wafer, including at least a sensitive structure pad and two lower electrode pads; S12, patterning and etching through the device layer of the second SOI wafer to form a slit, so as to physically isolate the sensitive structure from other parts of the device layer of the first SOI wafer.

[0005] The present invention also provides a packaging method for the above chip, comprising the steps of: A metal shell, a dedicated integrated circuit and a customized PCB board are used; the metal shell is fixed to the surface of the customized PCB board to form a cavity in the middle; the sensitive structure and the dedicated integrated circuit are arranged in the cavity formed by the metal shell and the customized PCB board, the sensitive structure and the dedicated integrated circuit are flip-chip soldered on the customized PCB board, and electrical connection is achieved through the wires on the customized PCB board; two sound inlet holes are provided on the customized PCB board.

[0006] Preferably, in step S1, the device layer and the substrate layer are heavily doped silicon.

[0007] Preferably, the depth of the first patterned shallow cavity etching in step S2 is the distance between the stop structure and the sensitive structure.

[0008] Preferably, in step S3, the second patterned shallow cavity etching is performed to define the size and position of the stop structure, and the sum of the two etching depths is the distance between the sensitive structure and the lower electrode.

[0009] Preferably, the method for removing the first oxide layer, substrate layer and buried oxide layer on the substrate layer of the second SOI wafer in step S9 includes: first reducing the thickness of the substrate layer of the second SOI wafer to a certain thickness by a mechanical thinning process, then completely removing the substrate layer by a wet process, and finally removing the buried oxide layer of the second SOI wafer by a wet process.

[0010] The advantages of the present invention are: 1. The present invention proposes a method for processing an acoustic sensor chip. The processing of the chip uses two SOI wafers, one of which is used as a sensitive structure and the other is used as a lower electrode. The two SOI wafers are formed into a whole through a silicon-silicon bonding process to achieve the measurement of the sound pressure signal and the sound pressure gradient signal in the sound field.

[0011] 2. The present invention proposes a method for packaging a sound sensor chip, wherein a MEMS chip and a dedicated integrated circuit chip are flipped on a printed circuit board, interconnected by wires on the printed circuit board, and two sound inlet holes are opened on the printed circuit board to realize the effect of sound waves on two sensitive structures, thereby finally realizing the measurement of scalar and vector signals in the sound field. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention will be further described below in conjunction with the accompanying drawings and embodiments: Figure 1 It is a schematic diagram of the composition of SOI wafer; Figure 2 This is the result after the first shallow cavity etching; Figure 3 This is the result after the second shallow cavity etching; Figure 4 This is the result after oxidation; Figure 5 This is the result after graphically removing the oxide layer; Figure 6 This is the result of etching the device layer to the buried oxide layer; Figure 7 is the etching result of the damping hole of the lower electrode; Figure 8 The bonding result of two SOI wafers; Fig. 9 This is the result after removing the second SOI wafer substrate layer and buried oxide layer; Fig.10 This is the result image after etching the back side of the first SOI wafer; Fig.11 This is the result diagram after processing the metal electrode; Fig.12 This is the result diagram after the sensitive structure is released; Fig.13 This is the result after packaging. DETAILED DESCRIPTION

[0013] In order to measure the sound pressure signal and the sound pressure gradient signal in the sound field, this embodiment proposes a method for processing and packaging a bottom-entry sound MEMS acoustic chip. The processing of the chip requires two SOI (Silicon on Insulator) wafers, one of which is used to process the sensitive structure and the other is used to process the lower electrode. The two SOI wafers are formed into a whole through a silicon-silicon bonding process.

[0014] S1, SOI wafer such as Figure 1 As shown, it is mainly composed of a device layer 11, a buried oxide layer 12, a substrate layer 13 and an oxide layer 14 on the substrate layer. The device layer 11 and the substrate layer 13 are heavily doped silicon. The specific processing is as follows: S2, the device layer 11 of the first SOI wafer is subjected to a first patterned shallow cavity etching, the etching depth is the distance between the stop structure and the sensitive structure, and the two shallow cavities 21 are symmetrically distributed about the anchor point 22, such as Figure 2 As shown; S3, perform a second patterned shallow cavity etching on the device layer 11 of the first SOI wafer to define the size and position of the stop structure 31. The sum of the two etching depths is the distance between the sensitive structure and the lower electrode, such as Figure 3 As shown; S4, forming an oxide layer 41 on the surface of the first SOI wafer device layer 11 by a thermal oxidation process, such as Figure 4 As shown; S5, patterning and etching the oxide layer 41 on the first SOI wafer device layer, the area where the oxide layer is removed includes the bonding area 51 between the first SOI wafer and the second SOI wafer, and the area 52 on the lower electrode where the damping hole is to be opened, such as Figure 5 As shown; S6, patterning and etching the device layer 11 of the first SOI wafer to the buried oxide layer 12, and physically isolating the stopper structure 61 and the lower electrode 62 from other silicon in the device layer 11, such as Figure 6 As shown; S7, sequentially pattern-etching the device layer 11 on the lower electrode to the buried oxide layer 12, then etching the buried oxide layer 12 to the substrate layer 13, and finally etching the substrate layer 13 to a certain depth, finally obtaining the damping hole 71, such as Figure 7 As shown; S8, performing face-to-face silicon-silicon bonding of the device layer 11 of the second SOI wafer and the device layer 11 of the first SOI wafer, such as Figure 8 As shown; S9, remove the oxide layer 14, the substrate layer 13 and the buried oxide layer 12 on the substrate layer 13 of the second SOI wafer. First, use a mechanical thinning process to reduce the thickness of the substrate layer 13 of the second SOI wafer to about 100 mm, then use a wet process to completely remove the substrate layer 13, and finally use a wet process to remove the buried oxide layer 12 of the second SOI wafer. Fig. 9 As shown; S10, patterning and etching the first SOI wafer substrate layer 13 and the oxide layer 14 on the substrate layer 13, increasing the volume of the air in the rear chamber, such as Fig.10 As shown; S11, patterning metal pads 111 on the device layer 11 of the first SOI wafer, which should at least include a sensitive structure (common upper electrode) pad, two lower electrode pads, such as Fig.11 As shown; S12, patterning and cutting through the device layer 11 of the second SOI wafer to form a slit 121, so as to physically isolate the sensitive structure from other parts of the device layer 11 of the first SOI wafer, such as Fig.12 As shown; S13, encapsulate the processed acoustic chip. Use a metal shell 2, a dedicated integrated circuit 3 and a customized PCB board 4; the metal shell 2 is fixed to the surface of the customized PCB board 4, forming a cavity in the middle; the sensitive structure and the dedicated integrated circuit 4 are arranged in the cavity formed by the metal shell 2 and the customized PCB board 4, and the sensitive structure and the dedicated integrated circuit 4 are flip-chip soldered on the customized PCB board 4, and the electrical connection is achieved through the wires on the customized PCB board 4; two sound inlet holes 5 are set on the customized PCB board, such as Fig.13 shown.

[0015] In order to achieve the measurement of sound pressure scalar information and sound pressure gradient vector information in the sound field, the present invention proposes a bottom-input fully differential MEMS microphone chip processing and packaging method. The microphone is mainly composed of an anti-fully differential MEMS chip, a dedicated integrated circuit chip, a metal cover plate and a PCB board. The fully differential MEMS chip consists of three layers: a cover layer, a sensitive structure layer and a base layer. The two pads of differential output and the power supply pad are distributed on the cover layer. The cover layer is flip-chip welded on the PCB board, and a corresponding sound inlet hole is set on the PCB board at the position corresponding to the sound inlet hole of the cover. The dedicated integrated circuit chip and the MEMS fully differential chip are flip-chip welded on the PCB board, and are distributed in the space formed by the PCB board and the metal cover plate to realize the bottom sound inlet packaging of the MEMS fully differential microphone.

[0016] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any modifications made according to the spirit of the main technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for processing an acoustic sensor chip, characterized in that: Includes steps: S1. Select two SOI wafers, each SOI wafer comprising a device layer, a buried oxide layer, a substrate layer and a first oxide layer connected in sequence; S2, performing a first patterned shallow cavity etching on the device layer of the first SOI wafer to form two shallow cavities symmetrically distributed on the left and right, and the unetched portion between the two shallow cavities serves as an anchor point; S3, performing a second patterned shallow cavity etching on the device layer of the first SOI wafer to form a stopper structure in two shallow cavities; S4, generating a second oxide layer on the surface of the first SOI wafer device layer by a thermal oxidation process; S5, patterning and etching to remove a portion of the second oxide layer to form a bonding area between the first SOI wafer and the second SOI wafer and an area on the lower electrode where a damping hole is to be opened; S6, patterning and etching the device layer of the first SOI wafer to the buried oxide layer, and physically isolating the stopper structure and the lower electrode from other silicon in the device layer; S7, sequentially pattern-etching the device layer on the lower electrode to the buried oxide layer, then etching the buried oxide layer to the substrate layer, and finally etching the substrate layer to a certain depth, finally obtaining a damping hole; S8, performing face-to-face silicon-silicon bonding on the device layer of the second SOI wafer and the device layer of the first SOI wafer; S9, removing the first oxide layer, the substrate layer and the buried oxide layer on the second SOI wafer substrate layer; S10, pattern-etching the substrate layer and the first oxide layer of the first SOI wafer to increase the volume of air in the rear chamber; S11, patterning metal pads on the device layer of the first SOI wafer, including at least a sensitive structure pad and two lower electrode pads; S12, patterning and etching through the device layer of the second SOI wafer to form a slit, so as to physically isolate the sensitive structure from other parts of the device layer of the first SOI wafer.

2. A method for packaging an acoustic sensor chip according to claim 1, characterized in that: Including packaging steps: A metal shell, a dedicated integrated circuit and a customized PCB board are used; the metal shell is fixed to the surface of the customized PCB board to form a cavity in the middle; the sensitive structure and the dedicated integrated circuit are arranged in the cavity formed by the metal shell and the customized PCB board, the sensitive structure and the dedicated integrated circuit are flip-chip soldered on the customized PCB board, and electrical connection is achieved through the wires on the customized PCB board; two sound inlet holes are provided on the customized PCB board.

3. The method for processing an acoustic sensor chip according to claim 1, characterized in that: In step S1, the device layer and the substrate layer are heavily doped silicon.

4. The method for processing an acoustic sensor chip according to claim 1, characterized in that: The depth of the first patterned shallow cavity etching in step S2 is the distance between the stop structure and the sensitive structure.

5. The method for processing an acoustic sensor chip according to claim 1, characterized in that: In step S3, the second patterned shallow cavity etching is performed to define the size and position of the stop structure, and the sum of the two etching depths is the distance between the sensitive structure and the lower electrode.

6. The method for processing an acoustic sensor chip according to claim 1, characterized in that: The method for removing the first oxide layer, substrate layer and buried oxide layer on the substrate layer of the second SOI wafer in step S9 includes: firstly reducing the thickness of the substrate layer of the second SOI wafer to a certain thickness by a mechanical thinning process, then completely removing the substrate layer by a wet process, and finally removing the buried oxide layer of the second SOI wafer by a wet process.

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