Data reading method and device, data writing method and device, computer equipment, readable storage medium and program product

Abstract

The invention relates to a data reading and writing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: receiving a data reading request; if the resource type corresponding to the data reading request is a pixel buffer object, aligning the horizontal offset of the pixel buffer object with a target buffer position to obtain a first mapping logic address; and converting the first mapping logic address into a first physical address, reading first target data from the pixel buffer object according to the first physical address, and storing the first target data to the target cache. By adopting the method, the data reading efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and apparatus for reading and writing data, a computer device, a computer-readable storage medium, and a computer program product. Background Art

[0002] Because the CPU (Central Processing Unit) and GPU (Graphics Processing Unit) have different responsibilities for graphics processing, pixel data transfer between the GPU and CPU primarily occurs through the frame buffer, relying on synchronization. In this mode, pixel data must be transferred from video memory to system memory, and vice versa, and the CPU and GPU must wait for the data transfer to complete. This synchronous transfer leads to system inefficiencies, particularly when processing large amounts of image data, resulting in limited system bandwidth and low resource utilization.

[0003] Therefore, PBO (Pixel Buffer Object) was born. Its introduction brings greater flexibility and efficiency to pixel data transmission. PBO is a buffer object located in video memory that allows for asynchronous pixel data transmission. With PBO, the GPU can independently pack and unpack offset data without blocking the CPU. The CPU can continue to perform other tasks while data is being transferred, improving system parallelism.

[0004] However, traditional hardware design relies heavily on memory alignment to optimize performance. The mismatch between PBO and the hardware alignment mechanism leads to low reading efficiency. Summary of the Invention

[0005] Based on this, it is necessary to provide a data reading method, device, computer equipment, computer-readable storage medium and computer program product that can improve reading efficiency in response to the above technical problems.

[0006] In a first aspect, the present application provides a data reading method, the method comprising:

[0007] Receive data read request;

[0008] If the resource type corresponding to the data read request is a pixel buffer object, aligning the horizontal offset of the pixel buffer object with the target cache position to obtain a first mapping logical address;

[0009] The first mapped logical address is converted into a first physical address, first target data is read from the pixel buffer object according to the first physical address, and the first target data is stored in the target cache.

[0010] In one embodiment, aligning the horizontal offset of the pixel buffer object with the target cache location to obtain a first mapping logical address includes:

[0011] Get the unit cache of the target cache;

[0012] determining an alignment position according to the number of pixel bytes corresponding to the first target data and the unit buffer;

[0013] An alignment operation is performed on the horizontal offset according to the alignment position to obtain the first mapping logical address.

[0014] In one embodiment, performing an alignment operation on the horizontal offset according to the alignment position to obtain the first mapping logical address includes:

[0015] Performing a shift operation on the horizontal offset according to the alignment position to obtain a target horizontal offset;

[0016] Obtaining a reference coordinate according to the target horizontal offset;

[0017] Calculation is performed according to the reference coordinates to obtain the first mapping logical address.

[0018] In one embodiment, the reference coordinates include a row offset, a layer offset, and a target horizontal offset; and the calculating according to the reference coordinates to obtain the first mapping logical address includes:

[0019] Calculating a vertical displacement according to the layer offset and the row offset;

[0020] Calculating the horizontal displacement within the row according to the vertical displacement, the row length, and the target horizontal offset; the row length is the number of bytes occupied by each row in the first target data;

[0021] The first mapping logical address is obtained according to the intra-row offset, the pixel corresponding to the first target data, and the base address corresponding to the first target data.

[0022] In one embodiment, the method further comprises:

[0023] If the resource type corresponding to the data read request is not the pixel buffer object and the first target data does not exist in the target cache location, the logical address is converted into a second physical address, and the first target data is read according to the second physical address.

[0024] In one embodiment, before aligning the horizontal offset in the logical address with the target cache, the method further includes:

[0025] Splitting the pixel buffer object to obtain a plurality of data blocks;

[0026] Aligning a horizontal offset of the pixel buffer object in the logical address with a target cache location includes:

[0027] The horizontal offset corresponding to each of the data blocks is aligned with the target cache position.

[0028] In a second aspect, the present application further provides a data writing method, the method comprising:

[0029] Receive data write request;

[0030] If the resource type corresponding to the data write request is a pixel buffer object, aligning the horizontal offset of the pixel buffer object with the target cache position to obtain a second mapping logical address;

[0031] The second mapped logical address is converted into a third physical address, and the second target data in the target cache is written into the pixel buffer object according to the third physical address.

[0032] In a third aspect, the present application provides a data reading device, comprising:

[0033] A first request receiving module, configured to receive a data reading request;

[0034] a first alignment module, configured to align a horizontal offset in the logical address with a target cache to obtain a first mapped logical address if the logical address corresponding to the data read request is a pixel buffer object;

[0035] A reading module is configured to convert the first mapping logical address into a first physical address, read first target data from the pixel buffer object according to the first physical address, and read the first target data into the target cache.

[0036] In a fourth aspect, the present application provides a data writing device, the device comprising:

[0037] A second request receiving module, configured to receive a data writing request;

[0038] a second alignment module, configured to align a horizontal offset of the pixel buffer object with a target cache position to obtain a second mapping logical address if the resource type corresponding to the data write request is a pixel buffer object;

[0039] A writing module is configured to convert the second mapped logical address into a third physical address, and write the second target data in the target cache into the pixel buffer object according to the third physical address.

[0040] In a fifth aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0041] In a sixth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0042] In a seventh aspect, the present application provides a computer program product, comprising a computer program, which implements the steps of the above method when executed by a processor.

[0043] The above-mentioned data reading method, apparatus, computer device, computer-readable storage medium and computer program product, by aligning the horizontal offset of PBO with the cache position, can ensure that data access is consistent with the cache line boundary and avoids crossing multiple cache lines. This not only reduces unnecessary memory accesses but also significantly improves the efficiency of data reading and writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0045] FIG1 is a schematic diagram of PBO packing and unpacking in one embodiment;

[0046] FIG2 is a schematic diagram of aligning 2D_Texture_Array and PBO in one embodiment;

[0047] FIG3 is a schematic diagram of a flow chart of a data reading method in one embodiment;

[0048] FIG4 is a schematic diagram showing the correspondence between PBO resources and cache in one embodiment;

[0049] FIG5 is a schematic diagram of reading data from a memory and writing it into a “data cache” in one embodiment;

[0050] FIG6 is a schematic structural diagram of a data reading device in one embodiment;

[0051] Figure 7 1 is a flow chart of a data writing method according to an embodiment;

[0052] FIG8 is a schematic diagram of writing the results in the “data cache” into the memory in one embodiment;

[0053] FIG9 is a block diagram of a data reading device according to an embodiment;

[0054] FIG10 is a structural block diagram of a data writing device according to an embodiment;

[0055] Figure 11 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0057] When transferring data between the CPU and GPU, especially when transferring large amounts of pixel or texture data (such as reading data from a frame buffer or transferring data to a texture), early graphics programming models performed the data transfer synchronously.

[0058] In traditional data transfers, data is copied from video memory to system memory and then passed from system memory to the application. This transfer process is inefficient, especially when transferring large amounts of data. Frequent data copying can incur significant performance overhead. Furthermore, during synchronous transfers, the CPU is blocked waiting for the GPU to complete operations, and vice versa. This results in underutilized CPU or GPU resources. For example, when reading pixel data from the frame buffer into memory, the CPU waits for the GPU to finish reading all the data before proceeding to the next operation.

[0059] To solve these problems, PBO was born. PBO provides a more efficient asynchronous data transmission mechanism, allowing the CPU and GPU to work in parallel, thereby eliminating waiting time and reducing unnecessary data copying.

[0060] PBOs allow the CPU to write data to a buffer object in video memory, which the GPU can then process in the background while the CPU continues to perform other tasks. This asynchronous mechanism significantly improves overall system efficiency. The CPU and GPU can execute their respective tasks in parallel, rather than having to wait for a transfer operation to complete. This allows the full utilization of the computing power of both.

[0061] With PBO, pixel data can also be stored in a buffer object, and standard APIs can be used to pack and unpack PBO. Packing refers to reading data from the frame buffer and writing it to the PBO; unpacking refers to reading data from the PBO and writing it to the frame buffer.

[0062] To better understand the packing and unpacking process, it is explained in conjunction with Figure 1. Figure 1 is a schematic diagram of packing and unpacking in one embodiment. Figure 1 takes the resource type of 2D_Texture_Array (two-dimensional texture array) in the frame buffer as an example, and shows the packing and unpacking process between it and PBO. It can be seen that the API can treat a cache as a PBO from any "Offset", and then give it the two parameters of "Row_Length" (row length) and "Image_Height" (image height) and treat it as a three-dimensional image and copy it to and from a normal 2D_Text_Array. When copying, you can specify any sub-resource SubRegion for reading or writing.

[0063] As you can see, during the "packing" or "unpacking" process, PBO is also treated as a special 2D_Texture_Array. Its starting address is "Base_Address + Offset" specified by the API, its width and height are specified by the API as "Row_Length" and "Image_Height", and its ArraySize (array size) is calculated as "(PBO_size - Offset) / (Row_Length * Image_Height)". Here, Base_Address is the base address, PBO_Size is the PBO size, and Offset is the offset. Compared to a normal 2D_Texture_Array, adjacent rows of PBO offset data are closely aligned in memory. In a normal 2D_Texture_Array, the space occupied by each row of offset data in memory is aligned to the cache granularity, making it easier to design hardware.

[0064] Continuing with Figure 2, Figure 2 shows the alignment of 2D_Texture_Array and PBO in one embodiment. This assumes a 4Kb cache granularity. For a typical 2D_Texture with length = 120 and width = 5, although a row only has 120 * 32 = 3840 bits, a full 4Kb is allocated in memory, leaving the last 256 bits empty. However, for a PBO of the same size, each row only occupies 3840 bits in memory, so two adjacent rows may appear in the same 4Kb.

[0065] Combining Figures 1 and 2, when viewing a PBO as a 2D_Texture / 2D_Texture_Array and performing offset copying between it and the frame buffer, the cache segment starting at "Offset" must be treated as a tightly packed 2D_Texture / 2D_Texture_Array. Its starting address ("Base_Address + Offset") is not necessarily aligned to the cache granularity, and there are no alignment requirements for each row within it. Hardware typically assumes that the starting address of each row is aligned to a cache line boundary (e.g., 4KB). If PBO data rows are misaligned, and two adjacent rows straddle a 4KB cache line, multiple memory accesses will be required when accessing the data, spanning multiple cache lines. This misaligned storage pattern may be inconsistent with the hardware design's default approach, resulting in additional complexity. This is because hardware typically divides and splits memory access requests based on data coordinates. If each row of data is not aligned to the cache granularity, the hardware may require additional logic to handle data that straddles a cache line boundary.

[0066] Therefore, in order to realize the packing of PBO, based on the existing hardware design, this application proposes a data reading method, and the following is a detailed description of the solution.

[0067] In one embodiment, as shown in FIG3 , a data reading method is provided. In this embodiment, the method is applied to a data reading device. The method includes the following steps:

[0068] Step S302: receiving a data read request.

[0069] A data read request is a request from the CPU to access a logical address. The CPU converts the logical address into a physical address to access data in the memory. The logical address can point to multiple storage tiers, including cache, main memory, and hard disks.

[0070] Optionally, the data read request points to the pixel data in the PBO resource, and the logical address corresponding to the data read request specifies the position of the first target data to be read in the PBO, and the first target data is read from the PBO position specified by the corresponding logical address.

[0071] For example, when a data read request points to pixel data in a PBO resource, the logical address may correspond to the three-dimensional coordinates (x, y, z) of the pixel in the PBO, and the target pixel data may be located and read through these coordinates.

[0072] Optionally, when the data read request points to the memory, the logical address in the data read request specifies the location of the first target data to be read in the memory. The data reading device reads the first target data from the corresponding location in the memory according to the logical address.

[0073] Step S304 : If the resource type corresponding to the data read request is a pixel buffer object, align the horizontal offset of the pixel buffer object with the target cache position to obtain a first mapping logical address.

[0074] First, the logical address is used to check whether the resource pointed to by the data read request is a PBO. If it is a PBO resource, the alignment process is started.

[0075] The original hardware design requires that the starting address of each row be aligned to the target cache granularity, that is, the starting address of each row in the PBO is aligned with the target cache. Combined with the schematic diagram on the right side of Figure 2, this means that the starting address corresponding to each color block is aligned with the target cache. However, PBO storage is tightly arranged without padding or alignment, that is, data is stored across rows, so the hardware cannot directly perform address calculations based on the original assumptions. In view of this, in this embodiment, the horizontal offset of the PBO is aligned with the target cache position. The target cache position refers to the location in the target cache where the first target data is stored.

[0076] Furthermore, since PBOs are tightly packed, meaning data is laid out sequentially from left to right and top to bottom, the horizontal offset, or x-coordinate, determines the horizontal position of the data within a row. Therefore, to better align the data with the target cache's unit buffer, the x-coordinate needs to be aligned. Unit buffer refers to the capacity of each cache line to store data.

[0077] After that, based on the aligned x coordinate, the 3D coordinates of the pixel in the PBO are converted to a linear memory address, which is the first mapping logical address. Since memory is linear, but texture data is multidimensional, it is chosen to convert the 3D coordinates to a linear memory address so that it can be read from the memory.

[0078] Step S306 : converting the first mapped logical address into a first physical address, reading first target data from the pixel buffer object according to the first physical address, and storing the first target data in the target cache.

[0079] Here, it refers to the actual storage address in the physical memory obtained by converting the first mapping logical address.

[0080] In step S304, the first mapped logical address has been calculated based on the three-dimensional coordinates (x, y, z) of the pixel in the PBO. The first mapped logical address identifies the location of the data to be accessed in the virtual address space. Therefore, in this step, we only need to convert the first mapped logical address into a first physical address. Then, we read the first target data from the pixel buffer object based on the first physical address and store it in the target cache.

[0081] In the above embodiment, by acquiring the unit cache of the target cache and aligning it according to the number of pixel bytes of the first target data and the cache line size, the efficiency of memory access and data access can be effectively optimized.

[0082] Furthermore, the above-mentioned alignment of the horizontal offset of the pixel buffer object with the target cache position to obtain the first mapping logical address includes: obtaining the unit cache of the target cache; determining the alignment position according to the number of pixel bytes corresponding to the first target data and the unit cache; and performing an alignment operation on the horizontal offset according to the alignment position to obtain the first mapping logical address.

[0083] The unit cache refers to the size of a single cache line in a data reading device, that is, the capacity of the cache line. A common cache line size is 64 bytes or 4KB.

[0084] In this embodiment, the size of the unit cache is obtained to determine how to align data to the cache line boundary. The cache typically loads data from the memory in blocks, and the alignment operation ensures that the data is aligned with these blocks as much as possible, thereby reducing cross-cache line access.

[0085] The number of pixel bytes of the first target data refers to the storage space occupied by each pixel. For example, one pixel may occupy 128 bytes.

[0086] Optionally, based on the size of the unit cache and the number of pixel bytes, determine how to align the position, that is, align the data. The goal is to find a suitable alignment position so that the horizontal offset of each pixel can be neatly aligned to the cache line boundary.

[0087] For example, if the unit cache size is 4KB (4096 bytes) and each pixel occupies 128 bytes, then a cache line can store 32 pixels (because 4096÷128=32), and the alignment position can be the starting position of every 32 pixels.

[0088] In the above embodiment, the unit cache of the target cache is obtained and aligned according to the number of pixel bytes of the first target data and the cache line size, which can effectively optimize the efficiency of memory access and data access.

[0089] Optionally, a shift operation can be performed to align the x coordinate to the buffer boundary.

[0090] Further, in one embodiment, the above-mentioned alignment operation is performed on the horizontal offset according to the alignment position to obtain the first mapping logical address, including: performing a shift operation on the horizontal offset according to the alignment position to obtain a target horizontal offset; obtaining a reference coordinate according to the target horizontal offset; and performing coordinate mapping according to the reference coordinate to obtain the first mapping logical address.

[0091] Optionally, after determining the alignment position, a horizontal offset is aligned by performing a shift operation to ensure that the x coordinate is aligned to a position that matches the cache line.

[0092] For example, the alignment can be performed using formula (1)

[0093] Formula (1)

[0094] First, divide the x coordinate by 32 to indicate alignment in units of 32 pixels. Then, multiply the result by 32 to restore the aligned x' value. The x' value is the target horizontal offset. In this embodiment, multiplying the result by 32 again is to calculate the coordinates of the first pixel in the row buffer, which is then converted into an address for data reading.

[0095] The aligned horizontal offset x′ determines the position of the data in the current row. The data reader then needs to combine this aligned coordinate with the other image coordinates to calculate the memory address. Combining the target horizontal offset with the other image coordinates yields the position (x′, y, z), which is the reference coordinate.

[0096] Next, the three-dimensional coordinates (x′, y, z) in the reference coordinates are combined with parameters such as the image height and line length to map the three-dimensional coordinates to the linear address in the memory.

[0097] In the above embodiment, after the target horizontal offset is obtained, it can be used to determine the reference coordinates of the pixel buffer object so as to perform subsequent coordinate conversion.

[0098] Furthermore, the reference coordinates include row offset, layer offset and target horizontal offset; coordinate mapping is performed according to the reference coordinates to obtain a first mapping logical address, including: calculating the vertical displacement according to the layer offset and the row offset; calculating the intra-row horizontal displacement according to the vertical displacement, the row length and the target horizontal offset; the row length is the number of bytes occupied by each row in the first target data; the first mapping logical address is obtained according to the intra-row offset, the number of pixel bytes corresponding to the first target data and the base address corresponding to the first target data.

[0099] The row offset represents the vertical position of the pixel in the image, that is, the row where the pixel is located, which is represented by the y coordinate.

[0100] The layer offset represents the layer position of the pixel in the three-dimensional data, and the layer offset is represented by the z coordinate.

[0101] Optionally, each layer of data may contain multiple rows, so the offset within the entire 3D data must be calculated based on layer number z. The height of each layer is determined by Image_Height. Within the current layer z, the row number of the pixel is calculated using y. The row offset, combined with the layer offset, determines the vertical position of the pixel.

[0102] For example, the vertical displacement can be calculated according to formula (2).

[0103] result1 = z*Image_Height + y formula (2)

[0104] Among them, result1 represents the vertical displacement.

[0105] Optionally, the horizontal displacement within a row is calculated by multiplying the vertical displacement of each row by the row length, and adding the target horizontal slice offset. The row length represents the total number of bytes occupied by each row in the image, which is an important parameter that determines the specific location of pixels in memory.

[0106] For example, the horizontal displacement within a row can be calculated according to formula (3).

[0107] result2 = result1*Row_Length + x' formula (3)

[0108] Among them, Row_Length indicates the row length.

[0109] Optionally, the first mapping logical address can be obtained by multiplying the horizontal shift within the row by the number of pixel bytes and adding the result to the base address. The number of pixel bytes represents the number of bytes occupied by each pixel. Each pixel may occupy multiple bytes, such as 32 or 128 bytes. To accurately calculate the pixel storage location, the byte size of each pixel must be considered. The base address represents the starting address of the first target data in memory.

[0110] Exemplarily, the first mapping logical address may be calculated according to formula (4).

[0111] Addr = result2*BytePerPixel + Base_Address formula (4)

[0112] In the above embodiment, the data reading device can calculate the position of each pixel in the memory through three-dimensional coordinates, thereby performing efficient data access operations.

[0113] In one embodiment, if the resource in the logical address corresponding to the data read request is not a pixel buffer object and the first target data does not exist in the target cache location, the logical address is converted into a second physical address, and the first target data is read according to the second physical address.

[0114] If the resource requested for data read is not a PBO, the data reading device will adopt a different reading process. In this case, there is no need to perform PBO-related alignment optimization.

[0115] First, it is checked whether the first target data already exists in the target cache. If the first target data does not exist in the target cache, that is, it is a cache miss, it is necessary to further read the first target data from the memory.

[0116] During the process of reading the first target data from the memory, the logical address is converted into a second physical address. The second physical address refers to the physical memory address corresponding to the non-PBO resource. The first target data in the memory can be correctly accessed through the second physical address.

[0117] Since PBO is an object used to process image or pixel data, it usually contains large blocks of continuous data. In order to improve the efficiency of PBO processing, PBO will be split into several data blocks.

[0118] Furthermore, in one embodiment, before aligning the horizontal offset in the logical address with the target cache, it also includes: splitting the pixel buffer object to obtain a plurality of data blocks; aligning the horizontal offset of the pixel buffer object in the logical address with the target cache position, including: aligning the horizontal offset corresponding to each data block with the target cache position.

[0119] Optionally, the PBO data is split into several small data blocks, and the size of each data block is usually consistent with the cache line size of the target cache for efficient storage and reading.

[0120] Optionally, each split data block is aligned with a horizontal offset to ensure that the storage location of each data block in the cache is aligned with the cache boundary. The specific alignment operation can refer to the steps in the above embodiment and will not be repeated here.

[0121] For example, referring to Figure 2, the PBO data is split into 4KB granularity. The data size of each row (3840 bytes) is less than 4KB, so each row can be treated as a data block. Since the PBO is a 2D image, the PBO row length is 120 pixels, and each pixel is 32 bytes. Therefore, the total data size of each row is 120 × 32 = 3840 bytes. This length is smaller than the 4KB cache, so a row of data will be stored in one cache line.

[0122] Combined with Figure 4, the split results are:

[0123] The first block: coordinates from (0,0,0)(0, 0, 0)(0,0,0) to (119,0,0)(119, 0, 0)(119,0,0), representing the first row of 120 pixels;

[0124] The second block: coordinates from (0,1,0)(0, 1, 0)(0,1,0) to (119,1,0)(119, 1, 0)(119,1,0), representing 120 pixels in the second row;

[0125] The third block: coordinates from (0,2,0)(0, 2, 0)(0,2,0) to (119,2,0)(119, 2, 0)(119,2,0), representing 120 pixels in the third row;

[0126] Fourth block: coordinates from (0,3,0)(0, 3, 0)(0,3,0) to (119,3,0)(119, 3, 0)(119,3,0), representing 120 pixels in the fourth row;

[0127] The fifth block: coordinates from (0,4,0)(0, 4, 0)(0,4,0) to (119,4,0)(119, 4, 0)(119,4,0), representing 120 pixels in the fifth row;

[0128] Next, the horizontal offset corresponding to each data block is aligned with the target cache position, and the first target data is read into each cache line of the target cache.

[0129] For the first block: allocate line[0] in the cache

[0130] Update "Information Cache": StartByteAddr=Base_address; Valid_byte_range=[0,479];

[0131] Update the "data cache": read the first 480 bytes of the first 4Kb and write them into the "data cache". Specifically, refer to FIG5 , which is a schematic diagram of reading data from the memory and writing it into the "data cache" in one embodiment.

[0132] For the second block: allocate line[1] in the cache

[0133] Update "Information Cache": StartByteAddr=Base_address + 480; Valid_byte_range=[0,479];

[0134] Update the "data cache": read the last 32 bytes of the first 4Kb and the first 448 bytes of the second 4Kb and write them to the "data cache";

[0135] For the third block: allocate line[2] in the cache

[0136] Update "Information Cache": StartByteAddr=Base_address + 960; Valid_byte_range=[0,479];

[0137] Update the "data cache": read the last 64 bytes of the second 4Kb and the first 416 bytes of the third 4Kb and write them to the "data cache";

[0138] For the fourth block: allocate line[3] in the cache

[0139] Update "Information Cache": StartByteAddr=Base_address + 1440; Valid_byte_range=[0,479];

[0140] Update the "data cache": read the last 96 bytes of the third 4Kb and the first 384 bytes of the fourth 4Kb and write them to the "data cache";

[0141] For the fifth block: allocate line[4] in the cache

[0142] Update "Information Cache": StartByteAddr=Base_address + 1920; Valid_byte_range=[0,479];

[0143] Update the data cache: read the last 128 bytes of the fourth 4Kb and the first 352 bytes of the fifth 4Kb and write them to the data cache.

[0144] The data cache is the memory used to store the actual data in the target cache, and the information cache is used to store the metadata of the data, including the storage location of the data, the valid data range, the status (whether it has been modified), etc.

[0145] In the above embodiment, by splitting the PBO, the PBO data can be read in batches, avoiding reading too large a data block at one time.

[0146] For example, referring to FIG6 , FIG6 is a structural diagram of a data reading device in one embodiment, which includes a splitting unit, a cache, and a read / write control unit.

[0147] Among them, the split unit is used to split the PBO resource. Since PBO usually contains large-scale images or pixel data, the split unit needs to split these large blocks of data into unit caches.

[0148] The cache consists of multiple word units that work together to manage and optimize data access. The cache includes a data cache, an information cache, a read memory unit, a write memory unit, an address calculation unit, and a command detection unit. The data cache is used to store the first target data read from the PBO, which is the target cache mentioned in the above embodiment; the information cache is used to store metadata related to the data in the data cache, such as the starting address and valid range of the data block; the read memory unit is used to load the corresponding data block from other storage units into the cache when the data block in the data cache is missing; the write memory unit is used to write the data block in the cache back to other storage units after modifying the data in the cache to ensure data consistency; the address calculation unit is used to convert the three-dimensional coordinates (x, y, z) of the pixel in the PBO into the first mapping logical address; the command detection unit is responsible for detecting read and write request commands from the system or application and coordinating the data flow between the cache and the memory.

[0149] The read / write control unit is responsible for the interaction between the cache, main memory, and data. Specifically, it determines when to read data from main memory, when to write modified data back to main memory, and how to coordinate these operations.

[0150] In one embodiment, an implementation for writing data in a cache to a PBO is provided.

[0151] First, each row in the PBO is still allocated to a separate cache.

[0152] After the data to be written to the PBO is ready in the cache, the process of writing them to the memory is as follows:

[0153] Step 1: Write data to line[0]

[0154] Data in the cache: line[0] contains 480 bytes of data.

[0155] Write to memory: These 480 bytes of data will be written to the first 480 bytes of the first 4KB in PBO.

[0156] In the PBO resource, the first 480 bytes will be overwritten by the data extracted from the cache.

[0157] Step 2: Write the data of line[1]

[0158] Data in the cache: line[1] contains 480 bytes of data.

[0159] The process of writing to memory:

[0160] Part 1: The first 32 bytes in the cache are written to the last 32 bytes in the first 4KB of the PBO.

[0161] Part 2: The last 448 bytes in the cache are written to the first 448 bytes of the second 4KB of the PBO.

[0162] Step 3: Write the data for line[2]

[0163] Data in the cache: line[2] contains 480 bytes of data.

[0164] The process of writing to memory:

[0165] Part 1: The first 64 bytes in the cache are written to the last 64 bytes of the second 4KB of the PBO.

[0166] Part 2: The last 416 bytes in the cache are written to the first 416 bytes of the third 4KB of the PBO.

[0167] Step 4: Write the data of line[3]

[0168] Data in the cache: line[3] contains 480 bytes of data.

[0169] The process of writing to memory:

[0170] Part 1: The first 96 bytes in the cache are written to the last 96 bytes of the third 4KB of the PBO.

[0171] Part 2: The last 384 bytes in the cache are written to the first 384 bytes of the fourth 4KB of the PBO.

[0172] Step 5: Write the data of line[4]

[0173] Data in the cache: line[4] contains 480 bytes of data.

[0174] The process of writing to memory:

[0175] Part 1: The first 128 bytes in the cache are written to the last 128 bytes of the fourth 4KB of the PBO.

[0176] Part 2: The last 352 bytes in the cache are written to the first 352 bytes of the fifth 4KB of the PBO.

[0177] In the above embodiment, the problem of mismatch between the PBO data row length and the cache row is effectively solved, and the efficiency and correctness of the writing process are ensured by splitting the data into small blocks for cross-page writing.

[0178] In one embodiment, Figure 7 As shown, a data reading method is provided. In this embodiment, the method is applied to a data reading device. The method includes the following steps:

[0179] Step S702: receiving a data write request.

[0180] A write request is a request from the CPU or other processing unit to access a logical address in memory to store data. Similar to a read request, a write request involves translating the logical address into a physical address to ensure the data is correctly written to the specific memory location.

[0181] Step S704 : If the resource type corresponding to the data write request is a pixel buffer object, align the horizontal offset of the pixel buffer object with the target cache position to obtain a second mapping logical address.

[0182] Align the horizontal offset of the pixel buffer object with the target cache location. This ensures that write operations are aligned with cache lines, avoiding straddling multiple cache lines and improving write efficiency. The aligned address is called the second-mapped logical address.

[0183] The specific alignment process can be referred to the description in the above embodiment and will not be described in detail here.

[0184] Step S706 : convert the second mapped logical address into a third physical address, and write the second target data in the target cache into the pixel buffer object according to the third physical address.

[0185] The calculated second mapping logical address is converted into a third physical address, which corresponds to the storage location of the PBO in the memory.

[0186] According to the third physical address, second target data to be written is read from the target cache, and the data is written to a specified memory location of the pixel buffer object (PBO).

[0187] In one embodiment, as shown in FIG8 .

[0188] First, each row in the PBO is still allocated to a separate cache;

[0189] Secondly, after the data to be written to the PBO is ready in the cache, the process of writing them to the memory is as follows:

[0190] For the data in line[0], take the first 480 bytes and write them to the first 480 bytes of the first 4KB in PBO;

[0191] For the data in line[1], write it into memory in two parts: the first part is the first 32 bytes, which is written to the last 32 bytes of the first 4Kb in PBO; the second part is the last 448 bytes, which is written to the first 448 bytes of the second 4Kb in PBO;

[0192] For the data in line[2], it is also written into the memory in two parts: the first 64 bytes are written into the last 64 bytes of the second 4Kb in PBO; the last 416 bytes are written into the first 416 bytes of the third 4Kb in PBO;

[0193] For the data in line[3], it is written into memory in two parts: the first 96 bytes are written into the last 96 bytes of the third 4Kb in PBO; the last 384 bytes are written into the first 384 bytes of the fourth 4Kb in PBO;

[0194] For the data in line[4], it is written into the memory in two parts: the first 128 bytes are written into the last 128 bytes of the fourth 4Kb in PBO; the last 352 bytes are written into the first 352 bytes of the fifth 4Kb in PBO.

[0195] Based on the same inventive concept, embodiments of the present application further provide a data reading device for implementing the aforementioned data reading method. The implementation solution provided by this device is similar to the implementation solution described in the aforementioned method. Therefore, the specific limitations of one or more data reading device embodiments provided below can be found in the above-described limitations of the data reading method and will not be further elaborated here.

[0196] In an exemplary embodiment, as shown in FIG9 , a data reading device is provided, including: a first request receiving module 100 , a first alignment module 200 , and a reading module 300 , wherein:

[0197] The first request receiving module 100 is configured to receive a data read request.

[0198] The first alignment module 200 is configured to align a horizontal offset of the pixel buffer object with a target cache to obtain a first mapping logical address if the resource type corresponding to the data read request is a pixel buffer object.

[0199] The first reading module 300 is configured to convert the first mapped logical address into a first physical address, read first target data from the pixel buffer object according to the first physical address, and read the first target data into a target cache.

[0200] In one embodiment, the first alignment module 200 includes:

[0201] The unit acquisition unit is used to acquire the unit cache of the target cache.

[0202] The alignment position unit is used to determine the alignment position according to the number of pixel bytes corresponding to the first target data and the unit buffer.

[0203] The alignment unit is configured to perform an alignment operation on the horizontal offset based on the alignment position to obtain a first mapping logical address.

[0204] In one embodiment, the alignment unit includes:

[0205] The horizontal offset calculation subunit is used to perform a shift operation on the horizontal offset according to the alignment position to obtain a target horizontal offset.

[0206] The reference coordinate calculation subunit is used to obtain the reference coordinate corresponding to the pixel buffer object according to the target horizontal offset.

[0207] The coordinate mapping subunit is used to coordinate map the reference coordinates to obtain a first mapping logical address.

[0208] In one embodiment, the coordinate mapping subunit includes:

[0209] The vertical displacement calculation unit is used to calculate the vertical displacement according to the layer offset and the row offset.

[0210] The intra-row horizontal displacement calculation subunit is used to calculate the intra-row horizontal displacement according to the vertical displacement, the row length and the target horizontal offset; the row length is the number of bytes occupied by each row in the first target data.

[0211] The first mapping logic address calculation subunit is used to obtain the first mapping logic address according to the intra-row offset, the number of pixel bytes corresponding to the first target data, and the base address corresponding to the first target data.

[0212] In one embodiment, the apparatus further comprises:

[0213] The second reading module is used to convert the logical address into a second physical address and read the first target data according to the second physical address if the resource in the logical address corresponding to the data read request is not a pixel buffer object and the first target data does not exist in the target cache location.

[0214] In one embodiment, the apparatus further comprises:

[0215] The splitting module is used to split the pixel buffer object to obtain several data blocks.

[0216] In one embodiment, the first alignment module 200 further includes:

[0217] The data block alignment unit is used to align the horizontal offset corresponding to each data block with the target cache position.

[0218] In an exemplary embodiment, as shown in FIG10 , a data writing device is provided, including: a second request receiving module 400 , a second alignment module 500 , and a writing module 600 , wherein:

[0219] The second request receiving module 400 is configured to receive a data writing request.

[0220] The second alignment module 500 is configured to align the horizontal offset of the pixel buffer object with the target cache position to obtain a second mapping logical address if the resource type corresponding to the data write request is a pixel buffer object.

[0221] The writing module 600 is configured to convert the second mapped logical address into a third physical address, and write the second target data in the target cache into the pixel buffer object according to the third physical address.

[0222] Each module in the above-mentioned data reading device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0223] In an exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in Figure 9. The computer device includes a processor, a memory, an input / output interface (I / O), and a communication interface. The processor, memory, and I / O interface are connected via a system bus, and the communication interface is connected to the system bus via the I / O interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The I / O interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it implements a data reading method.

[0224] Those skilled in the art will understand that the structure shown in Figure 9 is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0225] In an exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps of any one of the above embodiments when executing the computer program.

[0226] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in any one of the above embodiments are implemented.

[0227] In one embodiment, a computer program product is provided, comprising a computer program, which implements the steps in any one of the above embodiments when executed by a processor.

[0228] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0229] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0230] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A data reading method, characterized in that: The method comprises: Receive a data read request; If the resource type corresponding to the data read request is a pixel buffer object, aligning the horizontal offset of the pixel buffer object with the target cache position to obtain a first mapping logical address; The first mapped logical address is converted into a first physical address, first target data is read from the pixel buffer object according to the first physical address, and the first target data is stored in the target cache.

2. The method according to claim 1, characterized in that The step of aligning the horizontal offset of the pixel buffer object with the target cache position to obtain a first mapping logical address includes: Get the unit cache of the target cache; Determine an alignment position according to the number of pixel bytes corresponding to the first target data and the unit buffer; An alignment operation is performed on the horizontal offset based on the alignment position to obtain the first mapping logical address.

3. The method according to claim 2, characterized in that The performing an alignment operation on the horizontal offset according to the alignment position to obtain the first mapping logical address includes: Performing a shift operation on the horizontal offset according to the alignment position to obtain a target horizontal offset; Obtaining reference coordinates corresponding to the pixel buffer object according to the target horizontal offset; The reference coordinates are coordinate mapped to obtain the first mapping logical address.

4. The method according to claim 3, characterized in that The reference coordinates include a row offset, a layer offset, and a target horizontal offset; The coordinate mapping the reference coordinate to obtain the first mapping logical address includes: Calculating a vertical displacement according to the layer offset and the row offset; Calculating the horizontal displacement within the row according to the vertical displacement, the row length and the target horizontal offset; the row length is the number of bytes occupied by each row in the first target data; The first mapping logical address is obtained according to the intra-row offset, the number of pixel bytes corresponding to the first target data, and the base address corresponding to the first target data.

5. The method according to claim 1, characterized in that The method further comprises: If the resource type corresponding to the data read request is not the pixel buffer object, the logical address is converted into a second physical address, and the first target data is read according to the second physical address.

6. The method according to claim 1, characterized in that Before aligning the horizontal offset in the logical address with the target cache, the method further includes: Splitting the pixel buffer object to obtain a plurality of data blocks; Aligning a horizontal offset of a pixel buffer object in the logical address with a target cache location includes: The horizontal offset corresponding to each of the data blocks is aligned with the target cache position.

7. A data writing method, characterized in that: The method comprises: Receive data writing request; If the resource type corresponding to the data write request is a pixel buffer object, aligning the horizontal offset of the pixel buffer object with the target cache position to obtain a second mapping logical address; The second mapped logical address is converted into a third physical address, and the second target data in the target cache is written into the pixel buffer object according to the third physical address.

8. A data reading device, characterized in that: The device comprises: A first request receiving module, used for receiving a data reading request; A first alignment module, configured to align a horizontal offset of the pixel buffer object with a target cache to obtain a first mapping logical address if the resource type corresponding to the data read request is a pixel buffer object; A reading module is used to convert the first mapping logical address into a first physical address, read first target data from the pixel buffer object according to the first physical address, and read the first target data into the target cache.

9. A data writing device, characterized in that: The device comprises: A second request receiving module, used for receiving a data writing request; A second alignment module, configured to align a horizontal offset of the pixel buffer object with a target cache position to obtain a second mapping logical address if the resource type corresponding to the data write request is a pixel buffer object; A writing module is used to convert the second mapping logical address into a third physical address, and write the second target data in the target cache into the pixel buffer object according to the third physical address.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 or 7 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 or 7 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 or 7 are implemented.

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