Implementation method of high-performance atomic counter under multi-core architecture

Abstract

The invention discloses an implementation method of a high-performance atomic counter under a multi-core architecture, and belongs to the field of computer systems, the high-performance atomic counter comprises an Array and a core, and the Array comprises N atomic counters. An Array counter is arranged, each core is responsible for independently having an atomic counter, when access is needed, all counters of an array are accumulated, and an independent atomic counter variable is allocated to each CPU core in a system, so that when a certain thread needs to update the count, only the counter of the CPU corresponding to the thread where the thread is located needs to be updated, and the count of the thread needs to be updated. Therefore, conflicts and mutual exclusion among the threads are avoided, when the total value of the counter needs to be obtained, the counter values of all CPUs are accumulated, the process can be completed without locking, the reading efficiency is remarkably improved, the implementation mode of the invention not only reduces the frequency of mutual exclusion operation, but also improves the reading efficiency. And the performance loss caused by a memory barrier is reduced, and the performance of the atomic counter in a high-concurrency scene is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of computer systems, and in particular to a method for implementing a high-performance atomic counter in a multi-core architecture. Background Art

[0002] A computer system is a complex electronic system consisting of two major parts: hardware and software, which is used to perform various computing and processing tasks. Software is the program and data that guides the computer hardware to perform tasks. In modern computer systems, especially domestic servers, the application of multi-core architecture is becoming more and more widespread.

[0003] However, existing atomic counters usually use global shared variables for counting, and multiple CPU cores correspond to the same atomic counter. This design will lead to mutual exclusion operations between multiple threads when there is high concurrent access, and then generate memory barriers, which will seriously affect the performance of the system.

[0004] In a concurrent environment, threads accessing shared variables in traditional atomic counters will cause lock contention, leading to performance bottlenecks. Every time a thread tries to update the counter, it must first acquire the lock, which not only increases the context switching overhead, but also prevents the thread from fully utilizing CPU resources under high load conditions.

[0005] The present invention is used for a distributed counting module of a Sudis distributed high-speed cache database system product. Summary of the invention

[0006] The main purpose of the present invention is to provide a method for implementing a high-performance atomic counter in a multi-core architecture, which can effectively solve the problems in the background technology.

[0007] To achieve the above object, the technical solution adopted by the present invention is: A method for implementing a high-performance atomic counter in a multi-core architecture includes:

[0008] Preferably, the Array and the core, the Array includes N atomic counters, the number of the cores is the same as the number of the atomic counters, and the cores are independently set.

[0009] Preferably, N atomic counters are arranged in parallel, and the atomic counters are arranged independently, and each core is responsible for independently owning an atomic counter, and all atomic counters of the array are accumulated when access is required.

[0010] Preferably, the core belongs to the CPU core, and the core corresponds to the atomic counter one by one. When a thread needs to update the count, it only needs to update the atomic counter of the CPU corresponding to the thread, which can avoid conflicts and mutual exclusion between threads.

[0011] Preferably, the atomic counters corresponding to the CPU cores are accumulated to obtain the total counter value. This process can be completed without locking, which significantly improves the reading efficiency.

[0012] Compared with the prior art, the present invention has the following beneficial effects: the implementation method of high-performance atomic atomic counter under the multi-core architecture, by setting and maintaining a global Array counter, each core is responsible for independently owning an atomic counter, and all counters of the array are accumulated when access is needed. An independent atomic counter variable is allocated to each CPU core in the system, so that when a thread needs to update the count, it only needs to update the counter of the CPU corresponding to its thread, thereby avoiding conflicts and mutual exclusion between threads. When it is necessary to obtain the total value of the counter, the counter values ​​of all CPUs are accumulated. This process can be completed without locking, significantly improving the reading efficiency. This implementation method of the present invention not only reduces the frequency of mutually exclusive operations, but also reduces the performance loss caused by memory barriers, greatly improving the performance of atomic counters in high concurrency scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The schematic diagram is a method for realizing a high-performance atomic counter in a multi-core architecture according to the present invention. DETAILED DESCRIPTION

[0014] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below in conjunction with specific implementation methods.

[0015] like Figure 1 As shown, a method for implementing a high-performance atomic counter in a multi-core architecture includes an array and a core. The array includes N atomic counters. The number of cores is the same as the number of atomic counters, and the cores are independently set.

[0016] Through the above embodiment, N atomic counters are set in parallel, and the atomic counters are set independently. Each core is responsible for owning an atomic counter independently, and all atomic counters of the array are accumulated when access is needed. The core belongs to the CPU core, and the core corresponds to the atomic counter one by one. When a thread needs to update the count, it only needs to update the atomic counter of the CPU corresponding to its thread, which can avoid conflicts and mutual exclusion between threads. The atomic counter corresponding to the CPU core is accumulated to obtain the total value of the counter. This process can be completed without locking, which significantly improves the reading efficiency.

[0017] When using a computer system, each CPU core corresponds to an atomic counter. When access is required, data can be obtained through the atomic counter corresponding to the core. For high-concurrency access, since each core corresponds to an atomic counter, local variables are used for counting when accessed, and global shared variables will not be used for counting, thus avoiding lock competition caused by access to thread shared variables, preventing high-concurrency access from causing mutual exclusion operations between multiple threads, and preventing memory barriers, thereby ensuring the performance of the computer system. When the total value of the counter needs to be obtained, all atomic counter values ​​in the global Array are maintained and accumulated, and the accumulated result is the total value of the counter. This process can be completed without locking, thus improving the reading efficiency. If thread counts need to be updated, for the update process of all threads, the independent atomic counters corresponding to the CPU cores corresponding to all threads are updated. The atomic counters are set independently of each other, so there is no impact when updating. When a thread needs to update the count, it only needs to update the atomic counter of the CPU corresponding to its thread, and other atomic counters are not affected, thereby avoiding conflicts and mutual exclusion between threads.

[0018] It should be noted that by setting and maintaining a global Array counter, each core is responsible for independently owning an atomic counter, and all counters of the array are accumulated when access is needed. An independent atomic counter variable is assigned to each CPU core in the system, so that when a thread needs to update the count, it only needs to update the counter of the CPU corresponding to its thread, thereby avoiding conflicts and mutual exclusion between threads. When it is necessary to obtain the total value of the counter, the counter values ​​of all CPUs are accumulated. This process can be completed without locking, significantly improving reading efficiency. This implementation method of the present invention not only reduces the frequency of mutually exclusive operations, but also reduces the performance loss caused by memory barriers, greatly improving the performance of atomic counters in high concurrency scenarios.

[0019] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for implementing a high-performance atomic counter in a multi-core architecture, characterized in that: It includes an Array and a core. The Array includes N atomic counters. The number of the cores is the same as the number of the atomic counters. The cores are independently set.

2. The method for implementing a high-performance atomic counter in a multi-core architecture according to claim 1, characterized in that: N atomic counters are arranged in parallel, and the atomic counters are arranged independently. Each core is responsible for independently owning an atomic counter, and all atomic counters of the array are accumulated when access is required.

3. The method for implementing a high-performance atomic counter in a multi-core architecture according to claim 2, characterized in that: The core belongs to the CPU core, and the core corresponds to the atomic counter one by one. When a thread needs to update the count, it only needs to update the atomic counter of the CPU corresponding to its thread, which can avoid conflicts and mutual exclusion between threads.

4. The method for implementing a high-performance atomic counter in a multi-core architecture according to claim 3, characterized in that: The atomic counters corresponding to the CPU cores are accumulated to obtain the total counter value. This process can be completed without locking, which significantly improves the reading efficiency.

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