Interrupt scheduling method, apparatus and device, and computer readable storage medium

Abstract

The invention discloses an interrupt scheduling method, device and equipment and a computer readable storage medium, and is applied to the technical field of non-uniform memory access, and the method comprises the following steps: obtaining system load prediction data corresponding to a non-uniform memory access system; dynamically adjusting the interrupt scheduling strategy based on the system load prediction data to obtain a target interrupt scheduling strategy; and determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy, and processing each interrupt based on the target interrupt processing device. Compared with a traditional method for scheduling the interrupt based on a static scheduling strategy, the method has the advantages that the target interrupt scheduling strategy is obtained by obtaining the system load prediction data and dynamically adjusting the interrupt scheduling strategy based on the system load prediction data, so that the interrupt is scheduled based on the adjusted interrupt scheduling strategy; intelligent and dynamic interrupt scheduling is realized, and the accuracy of interrupt scheduling is improved.

Description

Technical Field

[0001] The present invention relates to the field of non-uniform memory access technology, and in particular to an interrupt scheduling method, device, equipment and computer-readable storage medium. Background Art

[0002] In modern computer systems, especially multi-processor systems using non-uniform memory access (NUMA) architecture, efficient scheduling of hardware interrupts is crucial to optimizing system performance. Interrupt scheduling refers to distributing interrupt requests to appropriate CPU cores for processing. Traditional interrupt scheduling methods are usually based on static strategies, which makes interrupt scheduling less effective.

[0003] It can be seen that how to improve the effect of interrupt scheduling is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In view of this, an object of the present invention is to provide an interrupt scheduling method, device, equipment and computer-readable storage medium, which solve the technical problem of poor interrupt scheduling effect in the prior art.

[0005] In order to solve the above technical problems, the present invention provides an interrupt scheduling method, comprising:

[0006] Obtain system load prediction data corresponding to the non-uniform memory access system;

[0007] Dynamically adjusting the interruption scheduling strategy based on the system load prediction data to obtain a target interruption scheduling strategy;

[0008] A target interrupt processing device corresponding to each interrupt is determined based on the target interrupt scheduling policy, and each interrupt is processed based on the target interrupt processing device.

[0009] On the one hand, before determining the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy and processing each interrupt based on the target interrupt processing device, the method further includes:

[0010] Prioritize interrupts according to their type and historical interrupt processing time to obtain the priority of each interrupt;

[0011] Adjusting the target interrupt scheduling strategy based on the priority of each interrupt to obtain an adjusted target interrupt scheduling strategy;

[0012] Accordingly, determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy, and processing each interrupt based on the target interrupt processing device includes:

[0013] A target interrupt processing device corresponding to each interrupt is determined based on the adjusted target interrupt scheduling policy, and each interrupt is processed based on the target interrupt processing device.

[0014] On the one hand, the priority of each interrupt is obtained by grading the interrupts according to the interrupt type and the historical interrupt processing time, including:

[0015] When the interrupt types are inconsistent, priority classification is performed on the interrupts based on the interrupt types to obtain the priority of each interrupt;

[0016] When the interrupt types are consistent, the interrupts are prioritized based on the historical interrupt processing time to obtain the priority level of each interrupt; wherein, the greater the historical interrupt processing time, the higher the priority level.

[0017] On the one hand, before dynamically adjusting the interruption scheduling strategy based on the system load prediction data to obtain the target interruption scheduling strategy, it also includes:

[0018] Predict target disruptions and target disruption time points based on historical disruption data;

[0019] Based on the interruption time point before the target interruption occurs, data corresponding to the target interruption is loaded into a cache to obtain a target cache.

[0020] On the one hand, before the target interruption occurs based on the interruption time point, the data corresponding to the target interruption is loaded into the cache, and after the target cache is obtained, the method further includes:

[0021] When it is determined that the data size in the target cache is greater than the set data threshold, determining whether the interrupt processing frequency corresponding to each data in the target cache is greater than the set processing frequency threshold;

[0022] When the interrupt processing frequency is not greater than the set processing frequency threshold, determining to clear the data from the target cache;

[0023] When the interrupt processing frequency is greater than the set processing frequency threshold, it is determined not to process the data.

[0024] On the one hand, the process of interrupt scheduling also includes:

[0025] Filter the system load prediction data based on the access control list to obtain the target collection data;

[0026] The target collection data and interrupt scheduling results are encrypted using a data encryption mechanism to obtain target encrypted data.

[0027] On the one hand, before obtaining the system load prediction data corresponding to the non-uniform memory access system, the method further includes:

[0028] Obtaining current system performance status and historical system performance data corresponding to the non-uniform memory access system;

[0029] The system load prediction data is determined by performing a prediction based on the current system performance state and the historical system performance data.

[0030] On the one hand, performing prediction based on the current system performance state and the historical system performance data to determine the system load prediction data includes:

[0031] Based on the current system performance state, the parameters of the prediction model are updated to obtain an updated target prediction model;

[0032] The target prediction model is used to perform prediction according to the historical system performance data to determine the system load prediction data.

[0033] On the one hand, the parameters of the prediction model are updated based on the current system performance state to obtain an updated target prediction model, including:

[0034] Based on the current system performance state, the parameters of the long short-term memory network model are updated to obtain the updated target prediction model; wherein the current system performance state is the system performance after the interruption is executed based on the interruption scheduling strategy; the training process of the long short-term memory network model includes data segmentation, model initialization, parameter optimization and model verification;

[0035] Wherein, the data segmentation refers to segmenting the data according to the data type;

[0036] The model initialization refers to initializing the parameters of the long short-term memory network model;

[0037] The parameter optimization refers to adjusting the parameters of the model to minimize the loss function;

[0038] The model validation refers to determining the predictive performance of the trained long short-term memory network model.

[0039] On the one hand, dynamically adjusting the interrupt scheduling strategy based on the system load prediction data to obtain a target interrupt scheduling strategy includes:

[0040] The interrupt scheduling strategy is dynamically adjusted based on the system load prediction data and the current system performance status to obtain the target interrupt scheduling strategy; wherein the dynamically adjusted parameters include an interrupt affinity threshold, and the interrupt affinity includes interrupt priority scheduling to the memory.

[0041] On the one hand, before predicting based on the current system performance state and the historical system performance data to determine the system load prediction data, the method further includes:

[0042] Using principal component analysis, extract key feature data from historical system performance data; wherein the key feature data includes the number of interruptions, memory utilization, number of devices, terminal frequency, and central processing unit load;

[0043] Performing scale unification processing on the key characteristic data to obtain scale-unified performance data;

[0044] Accordingly, performing prediction based on the current system performance state and the historical system performance data to determine the system load prediction data includes:

[0045] A prediction is performed based on the current system performance state and the scale-unified performance data to determine system load prediction data.

[0046] On the one hand, after determining the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy and processing each interrupt based on the target interrupt processing device, the method further includes:

[0047] Obtaining system performance feedback data after processing the interrupt based on the target interrupt scheduling strategy; wherein the system performance feedback data includes at least one of central processing unit utilization, memory access latency, input and output operation frequency, network traffic, waiting time, resource utilization and interrupt response time;

[0048] Analyze the system performance feedback data to determine the target performance parameters corresponding to the current system;

[0049] comparing the target performance parameter to a performance parameter threshold;

[0050] When it is determined that the target performance parameter is less than the performance parameter threshold, no processing is performed;

[0051] When it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, determine to send prompt information so that the client adjusts the interrupt scheduling strategy based on the prompt information;

[0052] The system load feedback data corresponding to the system load prediction data in the system performance feedback data;

[0053] Comparing the system load feedback data with the system load prediction data to determine a system load prediction difference;

[0054] The corresponding system load prediction model is adjusted based on the system load prediction difference to obtain an adjusted system load prediction model.

[0055] The embodiment of the present invention further provides an interrupt scheduling device, comprising:

[0056] A data acquisition module, used to acquire system load prediction data corresponding to the non-uniform memory access system;

[0057] A dynamic adjustment module, used to dynamically adjust the interruption scheduling strategy based on the system load prediction data to obtain a target interruption scheduling strategy;

[0058] The interrupt scheduling module is used to determine the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy, and process each interrupt based on the target interrupt processing device.

[0059] The embodiment of the present invention further provides an interrupt scheduling device, including:

[0060] Memory for storing computer programs;

[0061] A processor is used to execute the computer program to implement the steps of the above interrupt scheduling method.

[0062] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above interrupt scheduling method are implemented.

[0063] An embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the above interrupt scheduling method when executed by a processor.

[0064] To solve the above technical problems, an embodiment of the present invention provides an interrupt scheduling method, which may include: obtaining system load prediction data corresponding to a non-uniform memory access system; dynamically adjusting the interrupt scheduling strategy based on the system load prediction data to obtain a target interrupt scheduling strategy; determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy, and processing each interrupt based on the target interrupt processing device.

[0065] It can be seen from the above technical scheme that the beneficial effect of the present invention is that compared with the traditional interrupt scheduling based on an unchanging interrupt scheduling strategy, the present invention dynamically adjusts the interrupt scheduling strategy based on the system load prediction data to obtain the target interrupt scheduling strategy, so that when the interrupt is scheduled, the interrupt can be scheduled in real time to a more accurate interrupt processing device, and the interrupt can be scheduled based on the dynamically adjusted target interrupt scheduling strategy, thereby realizing the intelligent and dynamic interrupt scheduling and the accuracy of interrupt scheduling. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0067] Figure 1 A flowchart of an interrupt scheduling method provided by an embodiment of the present invention;

[0068] Figure 2 A flowchart of another interrupt scheduling method provided by an embodiment of the present invention;

[0069] Figure 3 A process implementation example of an interrupt scheduling method provided by an embodiment of the present invention;

[0070] Figure 4 A structural framework diagram of an interrupt scheduling method provided by an embodiment of the present invention;

[0071] Figure 5 A schematic diagram of the structure of an interrupt scheduling device provided by an embodiment of the present invention;

[0072] Figure 6 A schematic diagram of the structure of an interrupt scheduling device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0074] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0075] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0076] Next, an interrupt scheduling method provided by an embodiment of the present invention is described in detail. Figure 1 A flowchart of an interrupt scheduling method provided by an embodiment of the present invention, the method comprising:

[0077] S101, obtaining system load prediction data corresponding to a non-uniform memory access system.

[0078] This embodiment does not limit the specific execution subject. For example, the execution subject of this embodiment can be a computer; or the execution subject in this embodiment can also be a mobile phone, etc.; the execution subject of this embodiment can also be a node in the system. The non-uniform memory access (NUMA) system in this embodiment, the NUMA (Non-Uniform Memory Access) system is a computer architecture used in a multi-processor or multi-core system. This embodiment does not limit the specific way to obtain the system load prediction data. For example, this embodiment can be performed by analyzing historical load data, applying machine learning models and adjusting resource allocation strategies. The following is a detailed introduction to the system load prediction data: It is necessary to collect the historical load data of the system, which includes indicators such as CPU (central processing unit) usage, memory usage, disk I / O (input / output) and network traffic. The collected data is cleaned and preprocessed to ensure the accuracy of the analysis. This may include operations such as removing outliers and filling missing values. Through a detailed analysis of historical load data, the periodicity, trend and other characteristics of the load can be understood. Time series analysis is an important step, which helps to reveal the trend and periodicity of data changes over time. Choose an appropriate machine learning algorithm to build a prediction model. Common algorithms include linear regression, decision tree, random forest, and neural network. Use historical load data as a training set to train the model. During the training process, you need to adjust the model parameters to optimize the prediction performance. Use a validation set or a test set to evaluate the prediction performance of the model. Common evaluation indicators include mean square error (MSE), mean absolute error (MAE), etc.

[0079] S102, dynamically adjusting the interrupt scheduling strategy based on the system load prediction data to obtain a target interrupt scheduling strategy.

[0080] The interrupt scheduling in this embodiment refers to the process of how the operating system determines which task or process should be given priority when receiving an interrupt signal, and by reasonably arranging the order of interrupt processing, the response time of the system is reduced and the performance of the system is improved. This embodiment does not limit the original interrupt scheduling strategy. For example, the interrupt scheduling strategy in this embodiment can be the device corresponding to each interrupt, or the interrupt scheduling strategy in this embodiment can also be the priority of each interrupt processing. This embodiment does not limit the specific way to dynamically adjust the interrupt scheduling strategy based on the system load prediction data. For example, this embodiment can determine the load of each interrupt processing device based on the system load prediction data, determine the interrupt processing capacity according to the load, and give priority to allocating interrupts to interrupt processing devices with strong interrupt processing capacity, ensuring that interrupts are preferentially allocated to processing devices with lower loads and stronger processing capacity.

[0081] It should be further explained that, in order to improve the security of interrupt processing, before dynamically adjusting the interrupt scheduling strategy based on the system load prediction data to obtain the target interrupt scheduling strategy, it may also include: predicting the target interrupt and the target interrupt time point based on the historical interrupt data; before the target interrupt occurs based on the interrupt time point, the data corresponding to the target interrupt is loaded into the cache to obtain the target cache. The target cache in this embodiment is used to store the data corresponding to each interrupt. After the interrupt is processed, the data in the target cache can be deleted to improve the cache capacity of the target cache. This embodiment predicts the target interrupt based on the historical interrupt data, as well as the target interrupt time point corresponding to the target interrupt, so that based on the target interrupt time point, the data corresponding to the target interrupt is stored in the cache in a timely manner, thereby reducing the data loading time during interrupt processing.

[0082] It should be further explained that, before the target interrupt occurs based on the interrupt time point, the data corresponding to the target interrupt is loaded into the cache, and after the target cache is obtained, it can also include: when it is determined that the data size in the target cache is greater than the set data threshold, judging whether the interrupt processing frequency corresponding to each data in the target cache is greater than the set processing frequency threshold; when the interrupt processing frequency is not greater than the set processing frequency threshold, determining to clear the data from the target cache; when the interrupt processing frequency is greater than the set processing frequency threshold, determining not to process the data. This embodiment will consider the interrupt processing frequency of the interrupt when processing the data in the target cache, and will give priority to clearing the data corresponding to the interrupt with a low interrupt processing frequency from the target cache to improve the storage capacity of the target cache. The reason why this embodiment generally does not delete the data corresponding to the interrupt with a high interrupt processing frequency is to reduce the frequency of writing the data corresponding to the interrupt into the target cache and improve the processing capacity. For the data corresponding to the interrupt with a high interrupt processing frequency, the data in the target cache can be updated in time according to the latest data corresponding to the interrupt after the interrupt is processed.

[0083] S103, determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy, and processing each interrupt based on the target interrupt processing device.

[0084] The target interrupt processing device in this embodiment refers to a device that can process interrupts. This embodiment does not limit the specific type of the target interrupt processing device; for example, the target interrupt processing device in this embodiment may be a CPU; or the target interrupt processing device in this embodiment may also be a DMA controller, and the DMA (Direct Memory Access) controller allows peripheral devices to directly exchange data with the system memory without the intervention of the CPU. The target interrupt scheduling policy in this embodiment may include at least one of the corresponding relationship between the interrupt and the interrupt processing device, the interrupt processing device closest to the interrupt, and the processing capability of the interrupt processing device corresponding to the interrupt, wherein the closest specifically refers to belonging to the same NUMA. It can be understood that each interrupt has a corresponding device at the beginning, and the device corresponds to a NUMA. There are other interrupt processing devices under the NUMA, and the interrupt can be preferentially assigned to the device under the same NUMA. The capability of the interrupt processing device in this embodiment refers to the specification and architecture of the interrupt processing device itself. This embodiment can schedule each interrupt to a target interrupt processing device with a low load based on a target interrupt scheduling strategy, where a low load refers to a device with a load value lower than a set value; or the load of each target interrupt processing device can be sorted from small to large according to system load prediction data, the number of interrupts can be determined, and from the sorted loads, the number of devices corresponding to the number of interrupts can be selected from the front to process the interrupts.

[0085] It should be further explained that in order to improve the effect of interrupt processing, the above-mentioned target interrupt processing device corresponding to each interrupt is determined based on the target interrupt scheduling strategy, and before each interrupt is processed based on the target interrupt processing device, it can also include: prioritizing the interrupts according to the interrupt type and the historical interrupt processing time to obtain the priority of each interrupt; adjusting the target interrupt scheduling strategy based on the priority of each interrupt to obtain the adjusted target interrupt scheduling strategy; accordingly, determining the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy, and processing each interrupt based on the target interrupt processing device, including: determining the target interrupt processing device corresponding to each interrupt based on the adjusted target interrupt scheduling strategy, and processing each interrupt based on the target interrupt processing device. The specific interrupt type is not limited in this embodiment. For example, the interrupt type in this embodiment can be a hardware interrupt and a software interrupt, and the priority of the hardware interrupt is generally higher than that of the software interrupt, because the hardware interrupt may involve a device failure or a hardware error and needs to be processed as soon as possible. For example, machine check interrupts (such as power failures, main memory errors, etc.) usually have higher priorities because they are related to system stability and data security; or the interrupt type in this embodiment can also be a NUMA (Non-Uniform Memory Access) disk, keyboard, mouse, etc. The historical interrupt processing time in this embodiment refers to the time for processing each interrupt. The relationship between the historical interrupt processing time and the priority in this embodiment can be determined according to demand. For example, in this embodiment, the longer the historical interrupt processing time, the lower the priority, and it can be processed later, or in this embodiment, the longer the historical interrupt processing time, the higher the priority, because the longer the time, the earlier it is processed, ensuring that the interrupt can be processed within the set time. In this embodiment, the target interrupt scheduling policy is adjusted based on the priority of each interrupt, and the adjusted target interrupt scheduling policy means that according to the priority of the interrupt, the target device can be assigned to the interrupt with a high priority for processing.

[0086] It should be further explained that the above-mentioned priority grading of interrupts according to the interrupt type and the historical interrupt processing time to obtain the priority of each interrupt may include: when the interrupt types are inconsistent, the interrupts are prioritized based on the interrupt type to obtain the priority of each interrupt; when the interrupt types are consistent, the interrupts are prioritized based on the historical interrupt processing time to obtain the priority of each interrupt; wherein, the greater the historical interrupt processing time, the higher the priority level. In this embodiment, the interrupt type is more important than the historical interrupt processing time in determining the priority of the interrupt.

[0087] It should be further explained that in order to improve the security of interrupt scheduling, the process of interrupt scheduling may also include: filtering the system load prediction data based on the access control list to obtain the target collection data; encrypting the target collection data and the interrupt scheduling result by using the data encryption mechanism to obtain the target encrypted data. The access control list (ACL) in this embodiment is a security mechanism for defining and restricting access rights to system resources. The data encryption mechanism is a technical means for converting plaintext data into ciphertext through algorithms and keys to ensure the security of data transmission or storage. This embodiment does not limit the specific data encryption mechanism. For example, the data encryption mechanism in this embodiment may be symmetric encryption; or the data encryption mechanism in this embodiment may also be asymmetric encryption. This embodiment prevents malicious interrupt attacks and data leakage through access control lists (ACLs) and data encryption technology.

[0088] An interrupt scheduling method provided by an embodiment of the present invention may include: S101, obtaining system load prediction data corresponding to a non-uniform memory access system; S102, dynamically adjusting the interrupt scheduling strategy based on the system load prediction data to obtain a target interrupt scheduling strategy; S103, determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy, and processing each interrupt based on the target interrupt processing device. Compared with the traditional static scheduling, the present invention dynamically adjusts the interrupt scheduling strategy based on the system load prediction data to obtain the target interrupt scheduling strategy, and can schedule the interrupt based on the dynamically adjusted target interrupt scheduling strategy, thereby realizing the intelligentization and dynamism of interrupt scheduling.

[0089] In order to make the present invention easier to understand, please refer to Figure 2 , Figure 2 A flowchart of another interrupt scheduling method provided by an embodiment of the present invention may specifically include:

[0090] S201, obtaining current system performance status and historical system performance data.

[0091] The current system performance state in this embodiment refers to the performance of computer hardware and software during operation, including key indicators such as response speed, processing power and stability. This embodiment does not limit the specific method for determining the system performance state. For example, this embodiment can determine the system performance based on the CPU usage rate: the CPU is the brain of the computer, and its usage rate reflects the current system load. High usage may mean that a program has occupied too many computing resources, resulting in slow system response. Or this embodiment can be determined based on memory usage: memory is where the computer temporarily stores running programs and data. If the available memory is insufficient, the system may need to read data from the hard disk frequently, which will significantly reduce performance. This embodiment can also be based on disk read and write speed: the disk read and write speed directly affects the access efficiency of data. If the disk is in a high-load state for a long time, it may be due to a large amount of data exchange in the background service or application. This embodiment can also be based on network bandwidth utilization: for applications that rely on the network, the utilization of network bandwidth is an important indicator. Network congestion may cause data transmission delays, affecting user experience. This embodiment can also be based on the system stability index: the reliability monitor can view the system stability index and various events that occur in the system (such as software installation, system updates, application crashes, etc.). This information helps to analyze whether the system performance is stable. This embodiment can also comprehensively evaluate the performance level of the system based on a third-party performance testing tool. Or in this embodiment, the system performance can also be determined based on at least two of the above parameters. The system performance state in this embodiment is used to determine the level of current system performance, so as to determine whether the performance is reduced after processing the interrupt based on the target interrupt scheduling strategy. If it is reduced, it indicates that the current interrupt scheduling strategy needs to be adjusted to ensure that the performance remains unchanged or even improved. This embodiment does not limit specific historical system performance data. For example, the historical system performance data in this embodiment can be at least one of CPU load, memory usage, interrupt frequency, and network traffic.

[0092] S202: Perform prediction based on the current system performance status and historical system performance data to determine system load prediction data.

[0093] This embodiment does not limit the specific method of predicting based on the current system performance state and historical system performance data to determine the system load prediction data. For example, this embodiment can predict based on the current system performance state and historical system performance data based on a machine learning method to determine the system load prediction data; or this embodiment can also perform a prediction analysis based on the current system performance state and historical system performance data to obtain the law of load changes, and determine the system load prediction data based on the law of load changes.

[0094] It should be further explained that, in order to improve the accuracy of determining the system load prediction data, the above prediction based on the current system performance state and historical system performance data to determine the system load prediction data may include:

[0095] S2021, updating the parameters of the prediction model based on the current system performance status to obtain an updated target prediction model;

[0096] S2022: Determine system load forecast data by using a target forecast model based on historical system performance data.

[0097] In this embodiment, the parameters of the prediction model can be updated based on the current system performance status. When the prediction model is a long-short term memory model, the parameters that can be adjusted are memory depth and memory length. It is understandable that if the target interrupt scheduling strategy is adjusted based on the system load prediction data predicted last time compared with the previous one, the performance of the system is reduced, which means that there is a problem with the previous prediction, so it is necessary to adjust the parameters of the prediction model that affects a certain prediction data. This embodiment can predict future system loads and interrupt requirements in real time. The prediction model in this embodiment can adjust the parameters of the model in a timely manner according to feedback (current system performance status), thereby improving the effect of the model in making predictions.

[0098] It should be further explained that the above-mentioned updating of the parameters of the prediction model based on the current system performance state to obtain the updated target prediction model may include: updating the parameters of the long short-term memory network model based on the current system performance state to obtain the updated target prediction model; wherein the current system performance state is the system performance after the interruption is executed based on the interruption scheduling strategy; the training process of the long short-term memory network model includes data segmentation, model initialization, parameter optimization and model verification; wherein data segmentation refers to segmenting data according to data type; model initialization refers to initializing the parameters of the long short-term memory network model; parameter optimization refers to adjusting the parameters of the model to minimize the loss function; model verification refers to determining the prediction performance of the trained long short-term memory network model. In this embodiment, LSTM (Long Short-Term Memory Model) is sensitive to time, can learn patterns and features in time series data, and is suitable for tasks such as time series prediction and signal processing. This embodiment uses the long short-term memory network (LSTM) as the core prediction model, which can accurately capture the time series changes and complex patterns of system load. The LSTM model can effectively handle long-term dependencies through its memory unit and gating mechanism, and is suitable for dynamic prediction of system load. The innovation lies in combining the LSTM model with real-time data streams to form a closed-loop prediction system that can update prediction results within milliseconds, thereby achieving accurate prediction of system load.

[0099] It should be further explained that, in order to improve the accuracy of the data, before the prediction based on the current system performance state and the historical system performance data is made and the system load prediction data is determined, it may also include: extracting key feature data from the historical system performance data using the principal component analysis method; wherein the key feature data includes the number of interruptions, memory utilization, number of devices, terminal frequency and central processing unit load; performing scale unification processing on the key feature data to obtain scale-unified performance data; accordingly, predicting based on the current system performance state and the historical system performance data and determining the system load prediction data may include: predicting based on the current system performance state and the scale-unified performance data to determine the system load prediction data. This embodiment uses the principal component analysis (PCA) method to extract key feature data from the historical system performance data. PCA is a statistical method for transforming the original data into a set of new coordinate systems through linear transformation, so that the basis vectors of the new coordinate system are the main components of the original data. This can help us identify the most important features in the data and remove redundant information. This embodiment performs scale unification processing on the key feature data to eliminate the dimensional influence between different features, so that the data is more suitable for subsequent analysis and prediction.

[0100] S203: dynamically adjust the interruption scheduling strategy based on the system load prediction data to obtain a target interruption scheduling strategy.

[0101] This embodiment can determine the performance of each target interrupt processing device based on the system load prediction data, so as to give priority to adjusting the target interrupt processing device corresponding to each interrupt in the interrupt scheduling strategy. In this embodiment, the mapping of the same network card in the target interrupt scheduling strategy is given to the same CPU as much as possible. Mapping to the same CPU means that in a multi-core processor system, in order to improve processing efficiency and system performance, the interrupt request generated by a specific hardware (such as a network card) is preferentially assigned to a fixed one or several CPU cores for processing. Specifically, this strategy has the following key aspects: Interrupt affinity: By setting interrupt affinity (IRQ Affinity), a specific interrupt request can be bound to a specific CPU. The purpose of this is to avoid the processing of all interrupts being concentrated on a few CPUs, thereby causing these CPUs to be overloaded, while other CPUs are relatively idle. For network cards that support multiple queues, interrupts can be evenly distributed to different CPUs through hardware queues; for network cards that do not support multiple queues, similar effects can be achieved through software queues. In this way, each CPU can handle a part of the interrupts, thereby improving the overall processing efficiency. Binding the network card interrupt to a fixed CPU can reduce the overhead of interrupt processing, improve the throughput of network data and reduce latency. This is because when multiple CPUs handle interrupts from the same network card simultaneously, additional context switches and cache coherence issues may occur, thus affecting performance.

[0102] It should be further explained that, in order to improve the accuracy of the interruption policy, the above-mentioned dynamic adjustment of the interruption scheduling policy based on the system load prediction data to obtain the target interruption scheduling policy may include: dynamically adjusting the interruption scheduling policy based on the system load prediction data and the current system performance status to obtain the target interruption scheduling policy; wherein, the dynamically adjusted parameters include the interruption affinity threshold, and the interruption affinity includes the interruption priority scheduling to the memory. The interruption affinity threshold in this embodiment includes the interruption priority scheduling to the memory. When the memory is insufficient, the maximum CPU threshold is determined when each interrupt is processed on each CPU. If the current threshold of this CPU is greater than the maximum CPU threshold, the CPU will not be scheduled at this time. This embodiment can give priority to allocating interrupts to CPUs with lower loads based on the interruption affinity threshold, thereby improving the efficiency of interrupt processing.

[0103] S204, determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy, and processing each interrupt based on the target interrupt processing device.

[0104] This embodiment does not limit the specific target interrupt processing device, and the target interrupt processing device in this embodiment can be a CPU. This embodiment can adopt the Q-learning method to learn and optimize through real-time feedback of the scheduling strategy. Q-learning is a value-based model-free reinforcement learning algorithm.

[0105] It should be further explained that the above-mentioned process of processing interrupts based on the interrupt scheduling strategy may also include: determining whether the current interrupt processing device is processing other interrupts, and when processing, judging the priority of the current interrupt and other interrupts, giving priority to interrupt requests with higher priority, shielding interrupt requests of the same level or lower level, and forming interrupt nesting. Or under the condition of multi-core CPU (interrupt processing device), if a large number of hardware interrupts are assigned to different CPU cores for processing. Performance can be well balanced. For example, there will be multiple CPU cores, multiple network cards, and multiple hard disks on the server. If the network card interrupt can occupy one CPU core and the disk IO interrupt can occupy one CPU core, it will greatly reduce the load of a single CPU and improve the overall processing efficiency.

[0106] It should be further explained that, based on any of the above embodiments, in order to improve the stability of system operation and the accuracy of prediction, after determining the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy and processing each interrupt based on the target interrupt processing device, it can also include: obtaining system performance feedback data after processing the interrupt based on the target interrupt scheduling strategy; wherein the system performance feedback data includes at least one of central processing unit utilization rate, memory access delay, input and output operation frequency, network traffic, waiting time, resource utilization rate and interrupt response time; analyzing the system performance feedback data to determine the target performance parameter corresponding to the current system; comparing the target performance parameter with the performance parameter threshold; when it is determined that the target performance parameter is less than the performance parameter threshold, no processing is performed; when it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, determining to send a prompt information so that the client adjusts the interrupt scheduling strategy based on the prompt information; the system load feedback data corresponding to the system load prediction data in the system performance feedback data; comparing the system load feedback data with the system load prediction data to determine the system load prediction difference; adjusting the corresponding system load prediction model based on the system load prediction difference to obtain the adjusted system load prediction model. In this embodiment, analyzing the system performance feedback data and determining the target performance parameters corresponding to the current system means that all system performance feedback data are integrated to determine more certain target performance parameters, so that the target performance parameters can accurately reflect the state of the current system. In this embodiment, when it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, the system will send a prompt message to the client. These prompt messages may include performance warnings, recommended optimization measures or adjustment suggestions for interrupt scheduling strategies, so that the client can understand the system status in time and make corresponding adjustments. Based on the calculated system load prediction difference, this embodiment adjusts the original system load prediction model. This can include modifying model parameters, introducing new influencing factors or replacing more suitable prediction algorithms. The adjusted model should be able to more accurately predict future system load conditions, thereby providing strong support for the optimization of interrupt scheduling strategies.

[0107] An interrupt scheduling method provided by an embodiment of the present invention dynamically adjusts the interrupt affinity and mapping strategy by calculating the load and interrupt processing capability of each CPU in real time. The innovation lies in the introduction of an adaptive threshold adjustment mechanism, which dynamically adjusts the parameters of the scheduling strategy according to the current state of the system to ensure that interrupts are preferentially allocated to CPUs with lower loads and stronger processing capabilities. Specific beneficial effects include:

[0108] First: Improve system performance: In high-load network request scenarios, interrupt processing time is reduced by 30% and overall throughput is increased by 25%.

[0109] Second: Enhance resource utilization: By dynamically adjusting the interrupt strategy, the waste of CPU and memory resources is reduced.

[0110] Third: Improve system stability: Through adaptive optimization and fault-tolerant mechanisms, ensure that the system can still run stably under abnormal circumstances.

[0111] For easier understanding, please refer to Figure 3 , Figure 3 A process embodiment of an interrupt scheduling method provided by an embodiment of the present invention may specifically include:

[0112] S301, collecting system performance data; wherein the system performance data includes multi-dimensional data such as CPU load, memory usage, interrupt frequency, and network traffic.

[0113] For easier understanding, please refer to Figure 4 , Figure 4 A structural framework diagram of an interrupt scheduling method provided by an embodiment of the present invention. Figure 4 It can be seen that the whole method includes an acquisition module, a data processing module, a prediction module, a machine learning module, a scheduling strategy, and an enhanced feedback module. The data acquisition module of this embodiment: Design principle: The data acquisition module is responsible for real-time monitoring of the operating status of the system, and collects multi-dimensional data including CPU load, memory usage, interrupt frequency, network traffic, etc. In order to ensure the accuracy and real-time performance of the data, the module uses high-precision sensors and data acquisition cards. Specific implementation: Deploy sensors at key nodes of the system to obtain various performance indicators in real time. The data is transmitted to the central processing unit via a high-speed bus and stored in a distributed database for subsequent processing and analysis.

[0114] S302, performing data cleaning, normalization and dimension reduction techniques on the system performance data to obtain target system performance data.

[0115] The design principle of the data processing module of this embodiment: After data collection, the system needs to perform feature extraction and preprocessing on the data to identify the key factors affecting interrupt scheduling. Data cleaning, normalization and dimensionality reduction techniques are used to remove noise and redundant information and improve data quality. Specific implementation: The principal component analysis (PCA) technique is used to extract the main features in the data (the main features mainly refer to the number of interrupts, memory utilization, number of devices, overall interrupt load and CPU load), and the data is converted into a unified scale through standardization. The data after feature extraction is stored in the feature database for use by the prediction model. The data processing in this embodiment can also include classifying the data, for example, classifying to determine whether it belongs to the CPU, memory, network card, which NUMA and hardware layout.

[0116] S303, calling the prediction model at regular time intervals, making predictions based on the system performance data, and determining system load prediction data.

[0117] The design principle of the machine learning module in this embodiment: The prediction model is constructed using a long short-term memory network (LSTM), which can capture the time series changes and complex patterns of the system load. The model is trained using historical data, and the generalization ability of the model is improved through cross-validation and hyperparameter optimization. Specific implementation: Model training is performed in a GPU acceleration environment to improve training efficiency. The training process includes data segmentation, model initialization, parameter optimization, and model verification. The trained model is finally deployed on the prediction server to provide load prediction results in real time. Prediction-scheduling closed-loop system: Design a closed-loop system to feed back the load prediction results to the scheduling strategy in real time. By predicting future load changes, adjust the interrupt allocation strategy in advance to avoid performance bottlenecks during peak load periods. Dynamic parameter adjustment: According to the predicted load trend, dynamically adjust the key parameters of the scheduling algorithm, such as interrupt affinity threshold, load balancing strategy, etc. The design principle of the prediction module in this embodiment: Deploy the trained LSTM model to predict the future system load and interrupt demand in real time (interrupt demand refers to the demand to complete the interrupt). Based on the prediction results, dynamically adjust the affinity and mapping strategy of the interrupt, and give priority to allocating interrupts to CPUs with lower loads. Specific implementation: The system calls the prediction model at fixed time intervals and makes predictions based on the current system status (feedback) and historical data. The prediction results are used to update the interrupt scheduling table, which is stored in shared memory for real-time access by the scheduler. Priority classification: Interrupts are divided into multiple priority levels (such as high, medium, and low), and are graded according to the source, type, and historical processing time of the interrupts. Priority scheduling strategy: When designing the scheduling strategy, high-priority interrupts are given priority to ensure timely response to critical tasks. At the same time, the processing time of low-priority interrupts is dynamically adjusted to avoid affecting the overall performance of the system. Cache prefetch mechanism: When it is predicted that certain interrupts are about to occur, the relevant data is loaded into the cache in advance to reduce the data loading time during interrupt processing. Cache replacement strategy optimization: According to the frequency of interrupt processing and data access mode, the cache replacement strategy is dynamically adjusted to give priority to retaining high-frequency access data.

[0118] S304, adjusting the interrupt scheduling strategy according to the system load prediction data to obtain an adjusted interrupt scheduling strategy.

[0119] S305, adjusting the adjusted interrupt scheduling policy according to the interrupt type and the historical processing time to obtain a priority-based interrupt scheduling policy.

[0120] S306: Allocate the interrupt to the corresponding CPU using a priority-based interrupt scheduling policy.

[0121] S307, continuously updating the prediction model and interruption scheduling strategy through the interruption scheduling execution effect.

[0122] Adaptive optimization module in this embodiment: Design principle: The machine learning model is continuously updated through the feedback mechanism to adapt to changes in the system environment. The Q-learning algorithm is introduced to adjust the policy parameters according to the scheduling effect to achieve adaptive optimization. Specific implementation: The system records the scheduling effect after each scheduling, including indicators such as interrupt processing time and CPU utilization. Through the Q-learning algorithm, the system updates the policy parameters according to these feedbacks to optimize the scheduling performance. Strategy exploration and optimization: Through the exploration mechanism in reinforcement learning, different scheduling strategy combinations are continuously tried and their impact on system performance is recorded. Reward mechanism design: A reasonable reward mechanism is designed, and interrupt processing efficiency, system load balancing, etc. are used as reward indicators to guide the direction of strategy optimization. Security and fault-tolerant mechanism: Design principle: Design a security strategy to prevent malicious interrupt attacks and data leakage. Introduce a fault-tolerant mechanism to ensure that the system can still run stably in the event of hardware failure or abnormality. Specific implementation: By setting the access control list (ACL) and data encryption mechanism, the security of system data is protected. The system performs fault detection regularly and automatically switches to the backup plan when an abnormality is detected to ensure the stability of the system.

[0123] The interrupt scheduling device provided by the embodiment of the present invention is introduced below. The interrupt scheduling device described below and the interrupt scheduling method described above can be referred to each other.

[0124] Figure 5 A schematic diagram of the structure of an interrupt scheduling device provided by an embodiment of the present invention may include:

[0125] A data acquisition module 100 is used to acquire system load prediction data corresponding to the non-uniform memory access system;

[0126] A dynamic adjustment module 200, configured to dynamically adjust the interruption scheduling strategy based on the system load prediction data to obtain a target interruption scheduling strategy;

[0127] The interrupt scheduling module 300 is used to determine the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling policy, and process each interrupt based on the target interrupt processing device.

[0128] Further, based on the above embodiment, the above interrupt scheduling device may further include:

[0129] A priority determination module is used to prioritize interrupts according to interrupt types and historical interrupt processing times to obtain the priority of each interrupt;

[0130] A priority-based interrupt scheduling strategy adjustment module, used to adjust the target interrupt scheduling strategy based on the priority of each interrupt to obtain an adjusted target interrupt scheduling strategy;

[0131] Accordingly, the interruption scheduling module 300 includes:

[0132] The interrupt processing unit is used to determine the target interrupt processing device corresponding to each interrupt based on the adjusted target interrupt scheduling strategy, and process each interrupt based on the target interrupt processing device.

[0133] Further, based on any of the above embodiments, the priority determination module may include:

[0134] A priority grading unit, used for grading the priority of the interrupts based on the interrupt types when the interrupt types are inconsistent, to obtain the priority of each interrupt;

[0135] The priority determination unit is used to classify the interrupts based on the historical interrupt processing time when the interrupt types are consistent, so as to obtain the priority level of each interrupt; wherein, the greater the historical interrupt processing time, the higher the priority level.

[0136] Further, based on any of the above embodiments, the above interrupt scheduling device may further include:

[0137] A target interruption and target interruption time point prediction module, used to predict the target interruption and the target interruption time point based on historical interruption data;

[0138] The target cache determining unit is used to load the data corresponding to the target interrupt into the cache based on the interrupt time point before the target interrupt occurs, so as to obtain the target cache.

[0139] Further, based on the above embodiment, the above interrupt scheduling device may further include:

[0140] A judging module, configured to judge whether the interrupt processing frequency corresponding to each data in the target cache is greater than a set processing frequency threshold when it is determined that the data size in the target cache is greater than a set data threshold;

[0141] A data clearing module, used for determining to clear the data from the target cache when the interrupt processing frequency is not greater than the set processing frequency threshold;

[0142] The non-processing module is used to determine not to process the data when the interrupt processing frequency is greater than the set processing frequency threshold.

[0143] Further, based on any of the above embodiments, the above interrupt scheduling device may further include:

[0144] A data filtering module is used to filter the system load prediction data based on the access control list to obtain the target collection data;

[0145] The data encryption module is used to encrypt the target collection data and interrupt scheduling results using a data encryption mechanism to obtain target encrypted data.

[0146] Further, based on any of the above embodiments, the above interrupt scheduling device may further include:

[0147] A performance data acquisition module, used to acquire the current system performance status and historical system performance data corresponding to the non-consistent memory access system;

[0148] The system load prediction data determination module is used to make predictions based on the current system performance status and the historical system performance data to determine the system load prediction data.

[0149] Further, based on the above embodiment, the system load prediction data determination module may include:

[0150] A parameter updating unit, used to update the parameters of the prediction model based on the current system performance state to obtain an updated target prediction model;

[0151] The target prediction model-based prediction unit is used to perform prediction based on the historical system performance data using the target prediction model to determine the system load prediction data.

[0152] Further, based on the above embodiment, the parameter updating unit may include:

[0153] A parameter updating subunit, configured to update the parameters of the long short-term memory network model based on the current system performance state to obtain the updated target prediction model; wherein the current system performance state is the system performance after the interruption is executed based on the interruption scheduling strategy; the training process of the long short-term memory network model includes data segmentation, model initialization, parameter optimization and model verification;

[0154] Wherein, the data segmentation refers to segmenting the data according to the data type;

[0155] The model initialization refers to initializing the parameters of the long short-term memory network model;

[0156] The parameter optimization refers to adjusting the parameters of the model to minimize the loss function;

[0157] The model validation refers to determining the predictive performance of the trained long short-term memory network model.

[0158] Further, based on the above embodiment, the above dynamic adjustment module 200 may include:

[0159] A dynamic adjustment unit is used to dynamically adjust the interrupt scheduling strategy based on the system load prediction data and the current system performance status to obtain the target interrupt scheduling strategy; wherein the dynamically adjusted parameters include the interrupt affinity threshold, and the interrupt affinity includes interrupt priority scheduling to the memory.

[0160] Furthermore, the above interrupt scheduling device may also include:

[0161] A feature extraction module is used to extract key feature data from historical system performance data using a principal component analysis method; wherein the key feature data includes the number of interruptions, memory utilization, number of devices, terminal frequency, and central processing unit load;

[0162] A scale unification module, used for performing scale unification processing on the key feature data to obtain scale-unified performance data;

[0163] Accordingly, the system load prediction data determination module may include:

[0164] The system load prediction data determining unit is used to make predictions based on the current system performance state and the scale-unified performance data to determine the system load prediction data.

[0165] Further, based on any of the above embodiments, the above interrupt scheduling device may further include:

[0166] A system performance feedback data acquisition module, used to acquire system performance feedback data after processing the interrupt based on the target interrupt scheduling strategy; wherein the system performance feedback data includes at least one of central processing unit utilization rate, memory access latency, input and output operation frequency, network traffic, waiting time, resource utilization rate and interrupt response time;

[0167] A target performance parameter determination module is used to analyze the system performance feedback data to determine the target performance parameters corresponding to the current system;

[0168] A comparison module, configured to compare the target performance parameter with a performance parameter threshold;

[0169] A non-processing module, configured to not process when it is determined that the target performance parameter is less than the performance parameter threshold;

[0170] A prompt information sending module, used for determining to send prompt information when it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, so that the client adjusts the interrupt scheduling strategy based on the prompt information;

[0171] A system load feedback data determination module, used for determining the system load feedback data corresponding to the system load prediction data in the system performance feedback data;

[0172] A difference determination module, used for comparing the system load feedback data with the system load prediction data to determine a system load prediction difference;

[0173] The adjustment module is used to adjust the corresponding system load prediction model based on the system load prediction difference to obtain an adjusted system load prediction model.

[0174] It should be noted that the order of the modules and units in the above interrupt scheduling device can be changed without affecting the logic.

[0175] Figure 5 The description of the features in the corresponding embodiments can be found in Figure 5 The relevant descriptions of the corresponding embodiments will not be repeated here one by one.

[0176] The interrupt scheduling device provided by the embodiment of the present invention may include: a data acquisition module 100, which is used to obtain system load prediction data corresponding to the non-uniform memory access system; a dynamic adjustment module 200, which is used to dynamically adjust the interrupt scheduling strategy based on the system load prediction data to obtain a target interrupt scheduling strategy; an interrupt scheduling module 300, which is used to determine the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy, and process each interrupt based on the target interrupt processing device. Compared with the traditional static scheduling of interrupts, the present invention dynamically adjusts the interrupt scheduling strategy based on the system load prediction data to obtain the target interrupt scheduling strategy, and can schedule interrupts based on the dynamically adjusted target interrupt scheduling strategy, thereby realizing the intelligent and dynamic interrupt scheduling and improving the accuracy of interrupt scheduling.

[0177] An interrupt scheduling device provided by an embodiment of the present invention is introduced below. The interrupt scheduling device described below and the interrupt scheduling method described above can be referred to each other.

[0178] Figure 6 A schematic diagram of the structure of an interrupt scheduling device provided by an embodiment of the present invention, such as Figure 6 As shown, the interrupt scheduling device includes: a memory 60 for storing a computer program;

[0179] The processor 61 is used to implement the steps of the interrupt scheduling method in the above embodiment when executing a computer program.

[0180] The interrupt scheduling device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer, or a desktop computer.

[0181] Among them, the processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 61 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0182] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used to store the following computer program 601, wherein, after the computer program is loaded and executed by the processor 61, the relevant steps of the interrupt scheduling method disclosed in any of the aforementioned embodiments can be implemented. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 602 may include Windows, Unix, Linux, etc. Data 603 may include, but is not limited to, data required for interrupt scheduling, etc.

[0183] In some embodiments, the interrupt scheduling device may further include a display screen 62 , an input / output interface 63 , a communication interface 64 , a power supply 65 , and a communication bus 66 .

[0184] Those skilled in the art will understand that Figure 6 The structure shown in the figure does not constitute a limitation on the interrupt scheduling device, and may include more or less components than those shown in the figure.

[0185] It is understandable that if the interrupt scheduling method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the current technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk and other media that can store program code.

[0186] Based on this, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned interrupt scheduling method are implemented.

[0187] Based on this, an embodiment of the present invention further provides a computer program product, including a computer program / instruction, which implements the steps of the above interrupt scheduling method when executed by a processor.

[0188] The above is a detailed introduction to an interrupt scheduling device provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0189] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0190] The above is a detailed introduction to an interrupt scheduling method, device, equipment and computer-readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. An interrupt scheduling method, characterized in that: include: Obtain system load prediction data corresponding to the non-uniform memory access system; Dynamically adjusting the interruption scheduling strategy based on the system load prediction data to obtain a target interruption scheduling strategy; A target interrupt processing device corresponding to each interrupt is determined based on the target interrupt scheduling policy, and each interrupt is processed based on the target interrupt processing device.

2. The interrupt scheduling method according to claim 1, characterized in that: Before determining the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy and processing each interrupt based on the target interrupt processing device, the method further includes: Prioritize interrupts according to their type and historical interrupt processing time to obtain the priority of each interrupt; Adjusting the target interrupt scheduling strategy based on the priority of each interrupt to obtain an adjusted target interrupt scheduling strategy; Accordingly, determining a target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy, and processing each interrupt based on the target interrupt processing device includes: A target interrupt processing device corresponding to each interrupt is determined based on the adjusted target interrupt scheduling policy, and each interrupt is processed based on the target interrupt processing device.

3. The interrupt scheduling method according to claim 2, characterized in that: The priority of each interrupt is obtained by grading the interrupts according to the interrupt type and the historical interrupt processing time, including: When the interrupt types are inconsistent, priority classification is performed on the interrupts based on the interrupt types to obtain the priority of each interrupt; When the interrupt types are consistent, the interrupts are prioritized based on the historical interrupt processing time to obtain the priority level of each interrupt; wherein, the greater the historical interrupt processing time, the higher the priority level.

4. The interrupt scheduling method according to claim 1, characterized in that: Before dynamically adjusting the interrupt scheduling strategy based on the system load prediction data to obtain the target interrupt scheduling strategy, the method further includes: Predict target disruptions and target disruption time points based on historical disruption data; Based on the interruption time point before the target interruption occurs, data corresponding to the target interruption is loaded into a cache to obtain a target cache.

5. The interrupt scheduling method according to claim 4, characterized in that: Before the target interruption occurs based on the interruption time point, data corresponding to the target interruption is loaded into a cache to obtain the target cache, and further comprising: When it is determined that the data size in the target cache is greater than the set data threshold, determining whether the interrupt processing frequency corresponding to each data in the target cache is greater than the set processing frequency threshold; When the interrupt processing frequency is not greater than the set processing frequency threshold, determining to clear the data from the target cache; When the interrupt processing frequency is greater than the set processing frequency threshold, it is determined not to process the data.

6. The interrupt scheduling method according to claim 1, characterized in that: The process of interrupt scheduling also includes: Filter the system load prediction data based on the access control list to obtain the target collection data; The target collection data and interrupt scheduling results are encrypted using a data encryption mechanism to obtain target encrypted data.

7. The interrupt scheduling method according to any one of claims 1 to 6, characterized in that: Before obtaining the system load prediction data corresponding to the non-uniform memory access system, the method further includes: Obtaining current system performance status and historical system performance data corresponding to the non-uniform memory access system; The system load prediction data is determined by performing a prediction based on the current system performance state and the historical system performance data.

8. The interrupt scheduling method according to claim 7, characterized in that: Predicting based on the current system performance state and the historical system performance data to determine the system load prediction data includes: Based on the current system performance state, the parameters of the prediction model are updated to obtain an updated target prediction model; The target prediction model is used to perform prediction according to the historical system performance data to determine the system load prediction data.

9. The interrupt scheduling method according to claim 8, characterized in that: The parameters of the prediction model are updated based on the current system performance state to obtain an updated target prediction model, including: Based on the current system performance state, the parameters of the long short-term memory network model are updated to obtain the updated target prediction model; wherein the current system performance state is the system performance after the interruption is executed based on the interruption scheduling strategy; the training process of the long short-term memory network model includes data segmentation, model initialization, parameter optimization and model verification; Wherein, the data segmentation refers to segmenting the data according to the data type; The model initialization refers to initializing the parameters of the long short-term memory network model; The parameter optimization refers to adjusting the parameters of the model to minimize the loss function; The model validation refers to determining the predictive performance of the trained long short-term memory network model.

10. The interrupt scheduling method according to claim 7, characterized in that: Dynamically adjusting the interrupt scheduling strategy based on the system load prediction data to obtain a target interrupt scheduling strategy includes: The interrupt scheduling strategy is dynamically adjusted based on the system load prediction data and the current system performance status to obtain the target interrupt scheduling strategy; wherein the dynamically adjusted parameters include an interrupt affinity threshold, and the interrupt affinity includes interrupt priority scheduling to the memory.

11. The interrupt scheduling method according to claim 7, characterized in that: Before performing prediction based on the current system performance state and the historical system performance data to determine the system load prediction data, the method further includes: Using principal component analysis method, extract key characteristic data from the historical system performance data; wherein the key characteristic data includes the number of interruptions, memory utilization, number of devices, terminal frequency and central processing unit load; Performing scale unification processing on the key characteristic data to obtain scale-unified performance data; Accordingly, performing prediction based on the current system performance state and the historical system performance data to determine the system load prediction data includes: A prediction is performed based on the current system performance state and the scale-unified performance data to determine system load prediction data.

12. The interrupt scheduling method according to claim 1, characterized in that: After determining the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy and processing each interrupt based on the target interrupt processing device, the method further includes: Obtaining system performance feedback data after processing the interrupt based on the target interrupt scheduling strategy; wherein the system performance feedback data includes at least one of a central processing unit utilization rate, a memory access delay, an input and output operation frequency, a network flow, a waiting time, a resource utilization rate, and an interrupt response time; Analyze the system performance feedback data to determine the target performance parameters corresponding to the current system; comparing the target performance parameter to a performance parameter threshold; When it is determined that the target performance parameter is less than the performance parameter threshold, no processing is performed; When it is determined that the target performance parameter is greater than or equal to the performance parameter threshold, determine to send prompt information so that the client adjusts the interrupt scheduling strategy based on the prompt information; The system load feedback data corresponding to the system load prediction data in the system performance feedback data; Comparing the system load feedback data with the system load prediction data to determine a system load prediction difference; The corresponding system load prediction model is adjusted based on the system load prediction difference to obtain an adjusted system load prediction model.

13. An interrupt scheduling device, characterized in that: include: A data acquisition module, used to acquire system load prediction data corresponding to the non-uniform memory access system; A dynamic adjustment module, used to dynamically adjust the interruption scheduling strategy based on the system load prediction data to obtain a target interruption scheduling strategy; The interrupt scheduling module is used to determine the target interrupt processing device corresponding to each interrupt based on the target interrupt scheduling strategy, and process each interrupt based on the target interrupt processing device.

14. An interrupt scheduling device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the interrupt scheduling method according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the interrupt scheduling method according to any one of claims 1 to 12 are implemented.

16. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the interrupt scheduling method according to any one of claims 1 to 12 are implemented.

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