A physically unclonable function circuit and non-volatile magnetic random access memory

Abstract

This specification provides a physically non-cloning function (PUF) circuit and a non-volatile magnetic random access memory (Magnetic Random Access Memory). The PUF circuit includes multiple in-memory circuits, each with three magnetic tunnel junctions (MTJs). Two MTJs are used for input, and one MTJ is used for output. The two MTJs for input are connected in parallel and then connected in series with the one MTJ for output. The technical solution provided in this application addresses the problem that existing strong PUF circuits often require a large area overhead.

Description

Technical Field

[0001] This document relates to the field of memory technology, and in particular to a physically non-clonable function circuit and a non-volatile magnetic random access memory. Background Technology

[0002] Physically unclonable function (PUF) circuits are an emerging type of hardware security module. They primarily work by capturing and amplifying inter-chip mismatches in semiconductor manufacturing processes, thereby assigning a unique "fingerprint" to each chip. This allows for wide applications in anti-counterfeiting, authentication, and key generation.

[0003] The stimulus-response pair (CRP) is the unique mapping relationship between the input and output signals of a PUF circuit. PUF circuits can be classified into strong PUFs and weak PUFs based on the number of stimulus-response pairs, with the number of CRPs in strong PUFs increasing exponentially with area.

[0004] Although strong PUF circuits have excellent performance, they often require a large area overhead. Summary of the Invention

[0005] In view of the above analysis, this application aims to propose a physically non-clonable function circuit and a non-volatile magnetic random access memory to solve at least one of the above-mentioned technical problems.

[0006] Firstly, one or more embodiments of this specification provide a physically unclonable function circuit, including multiple in-memory circuits, each of which includes three magnetic tunnel junctions, wherein two magnetic tunnel junctions are used for input and one magnetic tunnel junction is used for output.

[0007] The two magnetic tunnel junctions used for input are connected in parallel and then connected in series with the one magnetic tunnel junction used for output.

[0008] Furthermore, the two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT.

[0009] When IN1 = 0 and IN2 = 0, OUT = 0;

[0010] When IN1 = 1 and IN2 = 0, OUT = 1;

[0011] When IN1 = 0 and IN2 = 1, OUT = 1; and

[0012] When IN1 = 1 and IN2 = 1, OUT = 1.

[0013] Furthermore, the two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT.

[0014] When IN1 = 0 and IN2 = 0, OUT = 0;

[0015] When IN1 = 1 and IN2 = 0, OUT = 0;

[0016] When IN1 = 0 and IN2 = 1, OUT = 1; and

[0017] When IN1 = 1 and IN2 = 1, OUT = 1.

[0018] Furthermore, the two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT.

[0019] When IN1 = 0 and IN2 = 0, OUT = 0;

[0020] When IN1 = 1 and IN2 = 0, OUT = 1;

[0021] When IN1 = 0 and IN2 = 1, OUT = 0; and

[0022] When IN1 = 1 and IN2 = 1, OUT = 1.

[0023] Furthermore, the two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT.

[0024] When IN1 = 0 and IN2 = 0, OUT = 0;

[0025] When IN1 = 1 and IN2 = 0, OUT = 0;

[0026] When IN1 = 0 and IN2 = 1, OUT = 0; and

[0027] When IN1 = 1 and IN2 = 1, OUT = 1.

[0028] Furthermore, the two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT.

[0029] When IN1 = 0 and IN2 = 0, OUT = 0;

[0030] When IN1 = 1 and IN2 = 0, OUT = 0;

[0031] When IN1 = 0 and IN2 = 1, OUT = 0; and

[0032] When IN1 = 1 and IN2 = 1, OUT = 0.

[0033] Furthermore, the two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT.

[0034] When IN1 = 0 and IN2 = 0, OUT = 1;

[0035] When IN1 = 1 and IN2 = 0, OUT = 1;

[0036] When IN1 = 0 and IN2 = 1, OUT = 1; and

[0037] When IN1 = 1 and IN2 = 1, OUT = 1.

[0038] Secondly, one or more embodiments of this specification provide a non-volatile magnetic random access memory, including a trimming circuit and a physically non-cloning function circuit array, wherein the physically non-cloning function circuit array includes the physically non-cloning function circuit described in any of the first aspects; and

[0039] The tuning circuit is connected to the write end of the physically unclonable function circuit array.

[0040] Furthermore, the adjustment circuit is equipped with resistors for changing and recording the resistance value of the adjustment circuit.

[0041] Furthermore, it also includes write driver circuitry, column compiler, read amplifier, and row compiler;

[0042] The write driver circuit is connected to the write terminal of the physically unclonable function circuit array through the trimming circuit;

[0043] The column compiler connects the word lines of the physically unclonable function circuit array;

[0044] The read amplifier is connected to the output of the physically unclonable function circuit array;

[0045] The row compiler is connected to the write driver circuit, the column compiler, and the read amplifier, respectively; and

[0046] The tuning circuit is configured with resistors that are connected to the write drive circuit, the column compiler, and the read amplifier, respectively.

[0047] Compared with the prior art, this application achieves at least the following technical effects: It utilizes a 2-input-1-output magnetic tunnel junction to form a physically unclonable function circuit, replacing the prior art gate transistor-magnetic tunnel junction as the memory cell. The memory cell based on the 2-input-1-output magnetic tunnel junction increases the storage capacity and response time of a single memory cell, thereby reducing the number of magnetic tunnel junctions used during read / write operations, and consequently reducing the area overhead of the PUF circuit. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A circuit diagram of a memory computing circuit provided for one or more embodiments of this specification;

[0050] Figure 2 A schematic diagram of the structure of a non-volatile magnetic random access memory provided for one or more embodiments of this specification;

[0051] Figure 3 A circuit diagram of a TRIM circuit provided for one or more embodiments of this specification;

[0052] Figure 4 A circuit diagram of a physically unclonable function circuit provided for one or more embodiments of this specification;

[0053] Figure 5 This is a schematic diagram of the structure of a prior art non-volatile magnetic random access memory provided for one or more embodiments of this specification. Detailed Implementation

[0054] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0055] Existing strong PUF circuits use gate-magnetic tunnel junctions (MTJs) as their memory cells, and generate corresponding signals by comparing the resistances of the two MTTs using a read amplifier. This approach suffers from the problems of large circuit area requirements and long processing times.

[0056] To address the aforementioned problems, embodiments of this application provide a physically unclonable function circuit, comprising multiple memory-based circuits, each of which, as follows: Figure 1 As shown, it includes three magnetic tunnel junctions (MTJs): two MTJs are used for input (MTJ_IN1, MTJ_IN2), and one MTJ is used for output (MTJ_OUT). The two MTJs used for input are connected in parallel and then connected in series with the one MTJ used for output.

[0057] In the embodiments of this application, Figure 1 This structure constitutes the basic architecture of CRAM (computational random-access memory) in-memory circuitry. When a certain operating voltage is applied to a CRAM cell, different amounts of current will flow through the OUTPUT MTJ depending on the resistance state of the INPUT MTJ.

[0058] CRAM logical operation steps:

[0059] Step 1: Write the computation data into INPUT MTJs.

[0060] Step 2: Set OUTPUT MTJ to high impedance state.

[0061] Step 3 applies a working voltage to the CRAM cell to perform logical operations, and the results will be directly stored in OUTPUTMTJ.

[0062] Depending on the operating voltage and the resistance value of the tunnel junction at the input, physically non-clonable function circuits can implement six different logic types, i.e., reconfigurable in-memory logic. By configuring different operating voltages, in-memory logic circuits gain greater flexibility in applications such as artificial intelligence chips. Specifically,

[0063] The first type is the logical OR function, which can be used for digital logical calculations.

[0064] When IN1 = 0 and IN2 = 0, OUT = 0;

[0065] When IN1 = 1 and IN2 = 0, OUT = 1;

[0066] When IN1 = 0 and IN2 = 1, OUT = 1; and

[0067] When IN1 = 1 and IN2 = 1, OUT = 1.

[0068] The second method is the IN2 copy function, which can be used for data copying.

[0069] When IN1 = 0 and IN2 = 0, OUT = 0;

[0070] When IN1 = 1 and IN2 = 0, OUT = 0;

[0071] When IN1 = 0 and IN2 = 1, OUT = 1; and

[0072] When IN1 = 1 and IN2 = 1, OUT = 1.

[0073] The third type is the IN1 copy function, which can be used for data copying.

[0074] When IN1 = 0 and IN2 = 0, OUT = 0;

[0075] When IN1 = 1 and IN2 = 0, OUT = 1;

[0076] When IN1 = 0 and IN2 = 1, OUT = 0; and

[0077] When IN1 = 1 and IN2 = 1, OUT = 1.

[0078] The fourth type is logical AND, which can be used for digital logical calculations.

[0079] When IN1 = 0 and IN2 = 0, OUT = 0;

[0080] When IN1 = 1 and IN2 = 0, OUT = 0;

[0081] When IN1 = 0 and IN2 = 1, OUT = 0; and

[0082] When IN1 = 1 and IN2 = 1, OUT = 1.

[0083] The fifth function, setting a bit to 0, can be used for data initialization.

[0084] When IN1 = 0 and IN2 = 0, OUT = 0;

[0085] When IN1 = 1 and IN2 = 0, OUT = 0;

[0086] When IN1 = 0 and IN2 = 1, OUT = 0; and

[0087] When IN1 = 1 and IN2 = 1, OUT = 0.

[0088] The sixth type is the set-to-1 function, which can be used for data initialization.

[0089] When IN1 = 0 and IN2 = 0, OUT = 1;

[0090] When IN1 = 1 and IN2 = 0, OUT = 1;

[0091] When IN1 = 0 and IN2 = 1, OUT = 1; and

[0092] When IN1 = 1 and IN2 = 1, OUT = 1.

[0093] Therefore, for a given CRAM cell, its logic function can be reconfigured by configuring different operating voltages, making it a basic unit for reconfigurable logic circuits. In the embodiments of this application, the physically unclonable function circuit is composed of several CRAM cells. Due to the inherent randomness of chip manufacturing processes, each CRAM cell exhibits different logic functions under a given operating voltage, thereby generating different logic outputs. This output is the fingerprint of the circuit, which can be used for key generation or identity recognition.

[0094] In this embodiment, the 2-input-1-output magnetic tunnel junction improves the storage capacity and response capacity of a single storage cell. Specifically, the scenario is set as follows: achieving 2^64 CRPs, with a single generation of at least 8 bits of response.

[0095] Existing strong PUF technologies require 1024 storage units to achieve the above scenario. In contrast, the PUF proposed in this application requires only 96 storage units to achieve the above scenario, and can generate a maximum of 32 bits at a time.

[0096] This application provides a non-volatile magnetic random access memory, such as... Figure 2 As shown, it includes: write driver circuit, column compiler, read amplifier, row compiler, trimming circuit, trimming circuit configuration resistor, and physical non-clonable function circuit array.

[0097] In this embodiment, the physically unclonable function circuit array includes multiple PUF units, each PUF unit containing a Figure 1 Physically unclonable function circuits.

[0098] In this embodiment, while physically non-cloning function circuits can improve read / write efficiency and reduce circuit area, they also increase operational inconsistencies during the read / write process. That is, the results of each read / write operation differ when reading and writing the same content. Furthermore, in existing technologies, drastic changes in environmental conditions such as temperature and voltage can cause changes in the stimulus-response pair, leading to operational inconsistencies. To address these issues, a trimming circuit (TRIM circuit) and a trimming circuit configuration resistor (TRIM configuration) are introduced into the non-volatile magnetic random access memory. The trimming circuit, for example... Figure 3 As shown, R0-R6 are resistors, and N and P are the input-output terminals of the TRIM module. The trimming circuit sets the input terminals (SL source line, BL bit line) of the physically unclonable function circuit array. By adjusting the configuration resistors of the trimming circuit, the resistance value of the trimming circuit can be adjusted in real time, thus ensuring that the results of each read and write are the same. Simultaneously, when environmental conditions such as temperature and voltage change drastically, the resistance value of the trimming circuit under the current conditions can be recorded through the configuration resistors of the trimming circuit, so that the corresponding resistance value can be recalled when the same conditions recur.

[0099] For example, when signal A was written last time, the resistance of the trimming circuit was 100 ohms, and the resistance value corresponding to signal A was recorded. Therefore, when writing signal A this time, the resistance value of the trimming circuit is directly adjusted to 100 ohms. The next time, due to an increase in chip temperature, when writing signal A, the resistance value of the trimming circuit is adjusted to 150 ohms by configuring the resistor in the trimming circuit, and the resistance value corresponding to signal A under this condition is recorded. If the chip temperature increases again subsequently, the resistance value of the trimming circuit is adjusted to 150 ohms.

[0100] In this embodiment, the write driver circuit is connected to the write terminal of the physically non-cloning function circuit array via a trimming circuit; the column compiler is connected to the word line (WL) of the physically non-cloning function circuit array; the read amplifier is connected to the output terminal of the physically non-cloning function circuit array; the row compiler is connected to the write driver circuit, the column compiler, and the read amplifier respectively; and the trimming circuit configures resistors to be connected to the write driver circuit, the column compiler, and the read amplifier respectively.

[0101] Specific response generation schemes are as follows Figure 4 As shown. Figure 4In the diagram, WD represents the write driver circuit, Data is the input signal of the write driver circuit, WE is the write enable signal, LWE is the PUF enable signal of the write driver circuit, WL, BL, and SL are the word line, bit line, and source line, respectively, LWL is the enable signal generated in response, M1 to M4 are four magnetic tunnel junctions, T1 to T4 are the gate transistors of conventional MRAM (Magnetoresistive Random Access Memory), PT1 and PT2 (red) are the enable transistors generated in response to the PUF, and m and n represent the number of rows and columns, respectively.

[0102] When generating a physically non-cloning function response, the excitation signal is first written to M1 and M2, using the same method as a regular MRAM. Then, an appropriate RO<0:6> is configured as needed, and WE and LWE are set to high potentials. <m>Data<m+1> Set WL to low and high potentials respectively. <n>WL<n+1> Set them to high and low potentials respectively, and finally set LWL <n 2>Set to high potential, at which point M1, M2, and M3 together form... Figure 1 The CRAM logic circuit shown is illustrated, where M1 and M2 are input terminals, M3 is the output terminal, and BL... <m>and SL<m+1> They are at high and low potentials respectively, while SL <m>and BL<m+1> It is in a floating state, therefore there is a current I. PUF The current flows through the CRAM circuit composed of M1, M2, and M3. This state is maintained for approximately 30ns, completing the generation of a 1-bit response. The generated response is directly stored in M3. Finally, all the signals are set to a low potential to end one cycle. In this way, the generation of a 1-bit response can be implemented in parallel across the entire array.

[0103] based on Figure 1 The array of physically non-clonable function circuits shown can significantly reduce the circuit area occupied. Specifically, as... Figure 5 As shown, to achieve the same effect, the prior art requires a total of 2*m*n*m*n MTJs, while this application only requires 3*m*n MTJs. Therefore, the technical solution of this application can greatly reduce the circuit area occupied. Figure 5 In the diagram, M represents a magnetic tunnel junction, W, C, and D represent gating transistors, E represents the word line terminal of even-numbered rows, B represents the word line terminal of odd-numbered rows, S represents the source line terminal, A represents the row selected when generating the response, and X and Y represent the gating transistors for the response generation row.

[0104] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0105] One or more embodiments of this specification can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a particular task or implement a particular abstract data type. One or more embodiments of this specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0106] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0107] The above description is merely an embodiment of this document and is not intended to limit the scope of this document. Various modifications and variations can be made to this document by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this document should be included within the scope of the claims of this document.< / m> < / m> < / n> < / n> < / m>

Claims

1. A non-volatile magnetic random access memory, characterized in that, include: Write driver circuit, column compiler, read amplifier, row compiler, trimming circuit, trimming circuit configuration resistors and magnetic tunnel junction array; The magnetic tunnel junction array is based on a multi-PUF unit array. Each PUF unit includes a 2*2 arrangement of magnetic tunnel junctions, a selector transistor T1 to T4 connected in series with the output terminal of each magnetic tunnel junction, and enable transistors PT1 and PT2. The two magnetic tunnel junctions in the first row are used as input tunnel junctions, and the first magnetic tunnel junction in the second row is used as the output tunnel junction. The drain of enable transistor PT1 is connected to the output terminal of the first input tunnel junction, and the drain of enable transistor PT2 is connected to the output terminal of the second input tunnel junction. The sources of PT1 and PT2 are both connected to the input terminal of the output tunnel junction, and the gates of PT1 and PT2 are both connected to the PUF enable signal. When a physically non-cloning function response needs to be generated, the column decoder generates a write enable signal and a PUF enable signal, sets the input tunnel junction to a low-impedance state, sets the output tunnel junction to a high-impedance state, and turns on the enable transistor to input a PUF current to the input terminal of the input tunnel junction. The generated response is stored in the output tunnel junction. The adjustment circuit includes resistors R0 to R6 connected in series, and a switching transistor connected in parallel across each resistor. One end of the resistor series is grounded, and the other end is connected to the source of the selector of the output tunnel junction. The adjustment circuit is configured with resistors to adjust the resistance value of the adjustment circuit by controlling the switching transistors to turn them on and off.

2. The non-volatile magnetic random access memory according to claim 1, characterized in that, The two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT. When IN1=0 and IN2=0, OUT=0; When IN1=1 and IN2=0, OUT=1; When IN1=0 and IN2=1, OUT=1; as well as When IN1=1 and IN2=1, OUT=1.

3. The non-volatile magnetic random access memory according to claim 1, characterized in that, The two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT. When IN1=0 and IN2=0, OUT=0; When IN1=1 and IN2=0, OUT=0; When IN1=0 and IN2=1, OUT=1; as well as When IN1=1 and IN2=1, OUT=1.

4. The non-volatile magnetic random access memory according to claim 1, characterized in that, The two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT. When IN1=0 and IN2=0, OUT=0; When IN1=1 and IN2=0, OUT=1; When IN1=0 and IN2=1, OUT=0; as well as When IN1=1 and IN2=1, OUT=1.

5. The non-volatile magnetic random access memory according to claim 1, characterized in that, The two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT. When IN1=0 and IN2=0, OUT=0; When IN1=1 and IN2=0, OUT=0; When IN1=0 and IN2=1, OUT=0; as well as When IN1=1 and IN2=1, OUT=1.

6. The non-volatile magnetic random access memory according to claim 1, characterized in that, The two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT. When IN1=0 and IN2=0, OUT=0; When IN1=1 and IN2=0, OUT=0; When IN1=0 and IN2=1, OUT=0; as well as When IN1=1 and IN2=1, OUT=0.

7. The non-volatile magnetic random access memory according to claim 1, characterized in that, The two magnetic tunnel junctions used for input correspond to input signals IN1 and IN2, respectively, and the one magnetic tunnel junction used for output corresponds to the output signal OUT. When IN1=0 and IN2=0, OUT=1; When IN1=1 and IN2=0, OUT=1; When IN1=0 and IN2=1, OUT=1; as well as When IN1=1 and IN2=1, OUT=1.

8. The non-volatile magnetic random access memory according to claim 1, characterized in that, Also includes: The adjustment circuit is equipped with resistors for changing and recording the resistance value of the adjustment circuit.

9. The non-volatile magnetic random access memory according to claim 8, characterized in that, It also includes write driver circuitry, column compiler, read amplifier, and row compiler; The write drive circuit is connected to the write end of the magnetic tunnel junction array through the trimming circuit; The column compiler connects the word lines of the magnetic tunnel junction array; The read amplifier is connected to the output of the magnetic tunnel junction array; The row compiler is connected to the write driver circuit, the column compiler, and the read amplifier, respectively. and The tuning circuit is configured with resistors that are connected to the write drive circuit, the column compiler, and the read amplifier, respectively.

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