Multi-DIE low-power-consumption management system and method based on core particle architecture

Abstract

The invention discloses a multi-DIE low power consumption management system and method based on a core particle architecture, the system comprises a master control MCU DIE, a controlled ASICMAIN DIE and a plurality of controlled ASICSLV DIEs, the master control MCU DIE and the controlled ASICMAIN DIE are communicated through a signal TX and a signal RX, and the controlled ASICMAIN DIE and the plurality of controlled ASICSLV DIEs are communicated through a signal TX32 and a signal RX32. According to the invention, aiming at the expansion of a plurality of DIEs, the power supply and the clock of each DIE can be managed from the system level, and the working scene requirements of different DIEs can be met.

Description

Technical Field

[0001] The present invention relates to a multi-DIE low power consumption management system and method, in particular to a multi-DIE low power consumption management system and method based on a core particle architecture, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Semiconductor technology is developing rapidly, and chip complexity and integration are also growing exponentially. Traditional single DIE SOC (system on chip) has become increasingly difficult to meet diverse needs. Chiplet architecture is a new packaging technology that packages small chips with different functions and different manufacturing processes together to form a heterogeneous chip. Chiplet can achieve different process nodes for cores with different functions, which can reduce costs and improve yield. However, while Chiplet has many advantages, it also faces some challenges. The integration of multiple cores will inevitably pose a greater challenge to heat dissipation, so how to control the power consumption of chiplet chips has become a very important issue. Automotive chips require low standby power consumption to reduce battery power consumption. Multiple different cores often have different power consumption requirements due to different working scenarios. How to balance the performance and power consumption of the entire system has become a very important issue.

[0003] For the power management of multi-chiplet chips, there are mainly the following issues: 1. Different chips often work in different working modes and have different power and clock requirements. If each chip has built-in power and clock and performs low-power circuit design, then at the system level, there will be a lot of redundant circuits, which is also a waste of area, that is, an increase in cost. 2. The traditional single-chip chip low-power design process usually requires the foundry to provide specific low-power design-related devices to support the design flow, and a single chip can usually only use one process, but chiplet chips often have different processes for different chips. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a multi-DIE low-power management system and method based on a chiplet architecture, so as to systematically manage the power supply and clock of each chiplet.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A multi-DIE low-power management system based on a core particle architecture includes a master MCU DIE, a controlled ASIC_MAIN DIE and several controlled ASIC_SLV DIEs. The master MCU DIE communicates with the controlled ASIC_MAIN DIE through signals TX and RX, and the controlled ASIC_MAIN DIE communicates with several controlled ASIC_SLV DIEs through signals TX32 and RX32.

[0006] Furthermore, the controlled ASIC_MAIN DIE includes an analog top-level module ANALOG_top and a digital top-level module DIGITAL_top.

[0007] Furthermore, the analog top-level module ANALOG_top includes a power module LDO, a clock generation module OSC and an off-chip LIN bus interaction module LINphy. The power module LDO provides a power signal to each DIE, the clock generation module OSC provides a clock signal to each DIE, and the off-chip LIN bus interaction module LINphy converts the LIN frame of the off-chip host into a signal LIN_RXD and transmits it to the main control MCU DIE.

[0008] Furthermore, the digital top-level module DIGITAL_top includes a power management module PMU, a communication module COMU and a digital core module DIG_core. The communication module COMU parses the instruction of the main control MCU DIE and determines whether the instruction of the main control MCU DIE is for the digital core module DIG_core, the controlled ASIC_SLV DIE or the power management module PMU; when the communication module COMU parses out that the device address in the instruction of the main control MCU DIE corresponds to the controlled ASIC_MAIN DIE, the communication line is switched to the digital core module DIG_core; when the communication module COMU parses out that the device address in the instruction of the main control MCU DIE corresponds to the controlled ASIC_SLV DIE, the communication line is switched to the controlled ASIC_SLV DIE; when the communication module COMU parses out that the instruction of the main control MCU DIE is for the power management module PMU, a corresponding request signal pd_req for DIE to enter the low power consumption mode is generated.

[0009] Furthermore, the digital core module DIG_core is a power-down voltage domain, and the power management module PMU and the communication module COMU are always on voltage domains.

[0010] A management method for a multi-DIE low power management system based on a core-grain architecture comprises the following steps: When the digital core module DIG_core does not need to work, the main control MCU DIE sends an instruction to the communication module COMU, and the communication module COMU generates a power-off request signal pulse to the power management module PMU. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the digital core module DIG_core, and then generates an iso signal to the isolation device ISOCELL, and forces the signal output from the digital core module DIG_core voltage domain to the always on voltage domain to a fixed value 1; then the power management module PMU generates a power switch control signal sw to cut off the power supply of the digital core module DIG_core, thereby putting the controlled ASIC_MAIN DIE into a low-power state, and the entire chip is in semi-sleep mode 1; when the digital core module DIG_core needs to be woken up from the power-off state, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy. The power management module PMU parses the wake-up frame and turns on the power of the digital core module DIG_core, and then turns on the isolation device ISO The iso signal of CELL is released, and finally the clock gating enable signal CG is released to turn on the clock of the digital core module DIG_core, and the digital core module DIG_core enters the normal working mode; When the controlled ASIC_SLV DIE does not need to work, the main control MCU DIE sends an instruction to the communication module COMU, and the communication module COMU generates a power-off request signal pulse to the power management module PMU module. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the controlled ASIC_SLV DIE, and then generates an iso signal to the isolation device ISO CELL, and forces the signal output by the controlled ASIC_SLV DIE to the controlled ASIC_MAIN DIE to a fixed value 1; then the power management module PMU generates a power switch control signal sw to cut off the power supply of the controlled ASIC_SLV DIE, thereby putting the controlled ASIC_SLV DIE into a low-power state, and the entire chip is in a semi-sleep mode 2; when the controlled ASIC_SLV DIE needs to be awakened from the power-off state, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy. The power management module PMU parses the wake-up frame and turns on the power of the controlled ASIC_SLV DIE, and then turns on the isolation device ISO The iso signal of CELL is released, and finally the clock gating enable signal CG is released to turn on the clock of the controlled ASIC_SLV DIE, and the controlled ASIC_SLV DIE enters the normal working mode; When the controlled ASIC_SLV DIE is powered off and the controlled ASIC_MAIN DIE is in normal working mode, the master MCU DIE is also in normal working mode; if the controlled ASIC_MAIN DIE does not need to work at this time, the master MCU DIE sends a power-off request instruction to the communication module COMU, and the communication module COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the digital core module DIG_core in the controlled ASIC_MAIN DIE and the master MCU DIE, and the whole chip enters deep sleep mode; if it is necessary to wake up from deep sleep, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the master MCU DIE, and the whole chip returns to normal working mode; When the digital core module DIG_core of the controlled ASIC_MAIN DIE is powered off and the controlled ASIC_SLV DIE is in normal working mode, the main control MCU DIE is also in normal working mode; if the controlled ASIC_SLV DIE does not need to work at this time, the main control MCU DIE sends a power-off request instruction to the communication module COMU, and the communication COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the controlled ASIC_SLV DIE and the main control MCU DIE, and the whole chip enters deep sleep mode; if it is necessary to wake up from deep sleep, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the whole chip returns to normal working mode.

[0011] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a multi-DIE low-power management system and method based on a core-grain architecture. For the expansion of multiple DIEs, the power supply and clock of each DIE can be managed from the system level, which can meet the working scenario requirements of different DIEs. Compared with the traditional core-grain integrated low-power management solution, the present invention only needs one DIE to provide power, clock, power management module and wake-up logic, avoiding the redundancy of the circuit at the entire chip level and saving area costs; the single-core low-power design involves front-end RTL plus UPF to back-end power planning, layout and wiring, and verification. The process is cumbersome and time-consuming. Compared with each DIE independently performing low-power design, the present invention only has one DIE to perform a low-power design process and other DIEs only need to perform conventional design, so it can also greatly save development time and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of a multi-DIE low power management system based on a core-grain architecture of the present invention.

[0013] Figure 2 It is a protocol timing diagram of instruction operation based on the core grain architecture multi-DIE low power management method of the present invention.

[0014] Figure 3 It is a state machine transition diagram of the PMU on the controlled ASIC_MAIN DIE side of the present invention.

[0015] Figure 4 It is a timing diagram of related signals of the power management module PMU of the present invention for entering the semi-sleep mode 1 and recovering from the semi-sleep mode 1 to the normal working mode.

[0016] Figure 5 It is a timing diagram of the power management module PMU related signals for entering the semi-sleep mode 2 and recovering from the semi-sleep mode 2 to the normal working mode of the present invention.

[0017] Figure 6 It is a timing diagram of the power management module PMU related signals for entering the deep sleep mode and recovering from the deep sleep mode to the normal working mode of the present invention.

[0018] Figure 7 It is a timing diagram of related signals of the power management module PMU of the present invention when entering the deep sleep mode from the semi-sleep mode 1 and then recovering from the deep sleep mode to the normal working mode. DETAILED DESCRIPTION

[0019] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0020] like Figure 1As shown, a multi-DIE low-power management system based on a core particle architecture of the present invention includes a master MCUDIE, a controlled ASIC_MAIN DIE and several controlled ASIC_SLV DIEs. The master MCU DIE communicates with the controlled ASIC_MAINDIE through signals TX and RX, and the controlled ASIC_MAIN DIE communicates with several controlled ASIC_SLV DIEs through signals TX32 and RX32.

[0021] The signal TX, the signal RX, the signal TX32 and the signal RX32 only represent the signal and the transmission direction, including but not limited to transmission via a single wire.

[0022] The controlled ASIC_MAIN DIE includes an analog top-level module ANALOG_top and a digital top-level module DIGITAL_top.

[0023] The analog top-level module ANALOG_top includes a power module LDO, a clock generation module OSC and an off-chip LIN bus interaction module LINphy. The power module LDO provides power signals to each DIE, the clock generation module OSC provides clock signals to each DIE, and the off-chip LIN bus interaction module LINphy converts the LIN frame of the off-chip host into a signal LIN_RXD and transmits it to the main control MCU DIE.

[0024] The digital top-level module DIGITAL_top includes a power management module PMU, a communication module COMU and a digital core module DIG_core. The communication module COMU parses the instructions of the main control MCU DIE and determines whether the instructions of the main control MCU DIE are for the digital core module DIG_core, the controlled ASIC_SLV DIE or the power management module PMU; when the communication module COMU parses out that the device address in the instruction of the main control MCU DIE corresponds to the controlled ASIC_MAIN DIE, the communication line is switched to the digital core module DIG_core; when the communication module COMU module parses out that the device address in the instruction of the main control MCU DIE corresponds to the controlled ASIC_SLV DIE, the communication line is switched to the controlled ASIC_SLV DIE; when the communication module COMU module parses out that the instruction of the main control MCU DIE is for the power management module PMU, a corresponding request signal pd_req for DIE to enter the low power mode is generated.

[0025] The digital core module DIG_core is a power-down voltage domain, and the power management module PMU and the communication module COMU are always on voltage domains.

[0026] A management method for a multi-DIE low power management system based on a core-grain architecture comprises the following steps: When the digital core module DIG_core does not need to work, the main control MCU DIE sends an instruction to the communication module COMU, and the communication module COMU generates a power-off request signal pulse to the power management module PMU. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the digital core module DIG_core, and then generates an iso signal to the isolation device ISOCELL, and forces the signal output from the digital core module DIG_core voltage domain to the always on voltage domain to a fixed value 1; then the power management module PMU generates a power switch control signal sw to cut off the power supply of the digital core module DIG_core, thereby putting the controlled ASIC_MAIN DIE into a low-power state, and the entire chip is in semi-sleep mode 1; when the digital core module DIG_core needs to be woken up from the power-off state, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy. The power management module PMU parses the wake-up frame and turns on the power of the digital core module DIG_core, and then turns on the isolation device ISO The iso signal of CELL is released, and finally the clock gating enable signal CG is released to turn on the clock of the digital core module DIG_core, and the digital core module DIG_core enters the normal working mode.

[0027] The power supply and clock of the controlled ASIC_SLV DIE are provided by the controlled ASIC_MAIN DIE and can be completely cut off. When the controlled ASIC_SLV DIE does not need to work, the main control MCU DIE sends an instruction to the communication module COMU, and the communication module COMU generates a power-off request signal pulse to the power management module PMU module. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the controlled ASIC_SLV DIE, and then generates an iso signal to the isolation device ISO CELL, and forces the signal output by the controlled ASIC_SLV DIE to the controlled ASIC_MAIN DIE to a fixed value 1; then the power management module PMU generates a power switch control signal sw to cut off the power supply of the controlled ASIC_SLV DIE, thereby putting the controlled ASIC_SLV DIE into a low-power state, and the entire chip is in a semi-sleep mode 2; when the controlled ASIC_SLV DIE needs to be awakened from the power-off state, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy. The power management module PMU parses the wake-up frame and turns on the power of the controlled ASIC_SLV DIE, and then turns on the isolation device ISO The iso signal of CELL is released, and finally the clock gating enable signal CG is released to turn on the clock of the controlled ASIC_SLV DIE, and the controlled ASIC_SLV DIE enters the normal working mode.

[0028] When the controlled ASIC_SLV DIE is powered off and the controlled ASIC_MAIN DIE is in normal working mode, the master MCU DIE is also in normal working mode; if the controlled ASIC_MAIN DIE does not need to work at this time, the master MCU DIE sends a power-off request instruction to the communication module COMU, and the communication module COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the digital core module DIG_core in the controlled ASIC_MAIN DIE and the master MCU DIE, and the whole chip enters deep sleep mode; if it is necessary to wake up from deep sleep, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the master MCU DIE, and the whole chip returns to normal working mode.

[0029] When the digital core module DIG_core of the controlled ASIC_MAIN DIE is powered off and the controlled ASIC_SLV DIE is in normal working mode, the main control MCU DIE is also in normal working mode; if the controlled ASIC_SLV DIE does not need to work at this time, the main control MCU DIE sends a power-off request instruction to the communication module COMU, and the communication COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the controlled ASIC_SLV DIE and the main control MCU DIE, and the whole chip enters deep sleep mode; if it is necessary to wake up from deep sleep, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the whole chip returns to normal working mode.

[0030] During the working mode conversion, there is no instruction to directly switch between semi-sleep mode 1 and semi-sleep mode 2.

[0031] The present invention will be further described below by means of specific examples.

[0032] like Figure 2 As shown, the DEVID byte represents the device address of the ASIC DIE, so the bit width of the DEVID determines the number of ASIC DIEs interconnected with the main control MCU DIE, including but not limited to more than two ASIC DIEs. The analog top-level module ANALOG_top in the controlled ASIC_MAIN DIE provides the power module LDO and the clock generation module OSC, and the output power VDD_AO is a normally open power supply, and CK is a normally open clock; the power VDD1 and clock CK1 for the digital core module DIG_core can be controlled and cut off by the power management module PMU; the power VDD2 and clock CK2 for the controlled ASIC_SLV DIE can be controlled and cut off by the power management module PMU; the power VDD3 and clock CK3 for the main control MCU DIE can be controlled and cut off by the power management module PMU.

[0033] The protocol for the master MCU DIE to send instructions to the ASIC DIE only represents the byte order, including but not limited to various serial buses or parallel buses. The MODE byte represents the operation mode of the master MCU DIE to the ASIC DIE. For example, when MODE=0x7A, it means entering the sleep mode; DEVID represents the device to be operated. For example, when DEVID is equal to 0x01, it means that the object to be operated is the controlled ASIC_MAIN DIE; DEVID is equal to 0x02, it means that the object to be operated is the controlled ASIC_SLV DIE. When MODE=0x7A, and DEVID=0x01, and data WDATA=0x55 is written to the register address 0xFF at the same time, and the CRC check value is also correct, it means that the controlled ASIC_MAIN DIE enters the sleep mode, that is, the semi-sleep mode 1. When MODE=0x7A, and DEVID=0x02, and data WDATA=0x55 is written to register address 0xFF, and the CRC check value is also correct, it means that the controlled ASIC_SLV DIE enters sleep mode, that is, semi-sleep mode 2. When MODE=0x7A, and device address DEVID=0xBF, and data WDATA=0x55 is written to register address 0xFF, and the CRC check value is also correct, it means that both the controlled ASIC_MAIN DIE and the controlled ASIC_SLV DIE enter sleep mode, that is, deep sleep mode.

[0034] Figure 3 The state machine transition of the power management module PMU of the controlled ASIC_MAIN DIE, that is, the working mode switching of the entire system, is described. Figures 4 to 7 It is a timing diagram of various control signals of the power management module PMU when each working mode is switched.

[0035] For example, when the chip is powered on normally, the entire chip is in a normal working mode, that is, each DIE works normally. When the digital core module DIG_core of the controlled ASIC_MAIN DIE has no data collection and transmission tasks, in order to save power consumption, the main control MCU DIE can send instructions, the byte order is MODE=0x7A, DEVID=0x01, REGADDR=0xFF, WDATA=0x55, CRC is automatically calculated and generated, when the communication module COMU of the controlled ASIC_MAIN DIE receives and parses the correct bytes and checks CRC, it will generate a sleep request signal pd_req1 high pulse, and then the power management module PMU will first pull the clock gating enable signal CG1 low, and the clock CK1 of the digital core module DIG_core will be turned off; then the enable signal iso1 of the isolation device ISO CELL will be pulled high, and the signal output by the digital core module DIG_core to the Always on voltage domain will be clamped to a fixed value; finally, the control signal sw1 of the power switch PSW will be pulled high, and the power supply VDD1 of the digital core module DIG_core will be cut off, and the system will enter semi-sleep mode 1. After a period of time, if you want the digital core module DIG_core controlled by ASIC_MAIN DIE to continue working, that is, to recover from semi-sleep mode to normal working mode, the off-chip host only needs to send a low-level wake-up signal LIN_WK lasting 200us to the LIN bus. When the power management module PMU parses the correct wake-up frame, it first pulls down the control signal sw1 of the power switch PSW, turns on the power supply VDD1 of the digital core module DIG_core, and then releases the enable signal iso1 of the isolation device ISO CELL, no longer clamps the output of the digital core module DIG_core, and finally restores the clock CK1 of the digital core module DIG_core, and the system enters normal working mode.

[0036] When the whole chip is in normal working mode, when the controlled ASIC_SLV DIE has no data collection and transmission tasks from a certain moment on, in order to save power consumption, the main control MCU DIE can send instructions, the byte order is MODE=0x7A, DEVID=0x02, REGADDR=0xFF, WDATA=0x55, CRC is automatically calculated and generated, when the communication module COMU of the controlled ASIC_MAIN DIE receives and parses the correct bytes and checks CRC, it will generate a sleep request signal pd_req2 high pulse, and then the power management module PMU will first pull the clock gating enable signal CG2 low, and the clock CK2 of the controlled ASIC_SLV DIE will be turned off; then the enable signal iso2 of the isolation device ISO CELL will be pulled high, and the signal output from the controlled ASIC_SLV DIE to the controlled ASIC_MAIN DIE will be clamped to a fixed value; finally, the control signal sw2 of the power switch PSW will be pulled high, and the power supply VDD2 of the controlled ASIC_SLV DIE will be cut off, and the system will enter semi-sleep mode 2. After a period of time, if you want the controlled ASIC_SLV DIE to continue working, that is, to recover from semi-sleep mode 2 to normal working mode, the off-chip host only needs to send a low-level wake-up signal LIN_WK lasting 200us to the LIN bus. When the power management module PMU parses the correct wake-up frame, it first pulls down the control signal sw2 of the power switch PSW, turns on the power supply VDD2 of the controlled ASIC_SLV DIE, and then releases the enable signal iso2 of the isolation device ISO CELL, no longer clamps the output of the controlled ASIC_SLV DIE, and finally restores the clock CK2 of the controlled ASIC_SLV DIE, and the system enters normal working mode.

[0037] When the entire chip is in normal working mode, starting from a certain moment, when the digital core modules DIG_core of the controlled ASIC_SLV DIE and the controlled ASIC_MAIN DIE have no data collection and transmission tasks, in order to save power consumption, the power supplies of the digital core module DIG_core, the controlled ASIC_SLV DIE and the main control MCU DIE can be cut off. The command can be sent through the master MCU DIE, the byte order is MODE=0x7A, DEVID=0xBF, REGADDR=0xFF, WDATA=0x55, CRC is automatically calculated and generated, when the communication module COMU of the controlled ASIC_MAIN DIE receives and parses the correct bytes and checks the CRC correctly, it will generate sleep request signals pd_req1, pd_req2 high pulses, then the power management module PMU will first pull the control clock gating enable signal CG1~3 low, then the clock CK1~3 of the controlled ASIC_MAIN DIE, the controlled ASIC_SLV DIE, and the master MCU DIE will be turned off; then the enable signal iso1~3 of the isolation device ISO CELL will be pulled high, and finally the control signal sw1~3 of the power switch PSW will be pulled high, and the power supply VDD1~3 of the controlled ASIC_MAIN DIE, the controlled ASIC_SLV DIE, and the master MCU DIE will be cut off, and the system will enter deep sleep mode. After a period of time, if you want to recover from deep sleep mode to normal working mode, the off-chip host only needs to send a low-level wake-up signal LIN_WK lasting 200us to the LIN bus. When the power management module PMU parses the correct wake-up frame, it first pulls down the control signal sw1~3 of the power switch PSW, turns on the power supply VDD1~3 of the controlled ASIC_MAIN DIE, the controlled ASIC_SLV DIE, and the master MCU DIE, and then releases the enable signal iso1~3 of the isolation device ISO CELL, and finally restores the clock CK1~3 of the controlled ASIC_MAIN DIE, the controlled ASIC_SLV DIE, and the master MCU DIE, and the system enters normal working mode.

[0038] When the system is in semi-sleep mode 1, if the controlled ASIC_SLV DIE does not have data collection and transmission tasks, and you want to further reduce power consumption, you can send instructions through the main control MCU DIE, the byte order is MODE=0x7A, DEVID=0xBF, REGADDR=0xFF, WDATA=0x55, CRC is automatically calculated and generated, when the communication module COMU of the controlled ASIC_MAIN DIE receives and parses the correct bytes and checks CRC, it will generate sleep request signals pd_req1, pd_req2 high pulses, and the power management module PMU will switch CG2~3, iso2~3, sw2~3 to further shut down the clock and power of the controlled ASIC_SLV DIE and the main control MCU DIE, thereby entering deep sleep mode. Figure 7 The figure shows the PMU timing transition diagram from semi-sleep mode 1 to deep sleep mode and then recovering from deep sleep mode to normal working mode.

[0039] Similarly, the conversion process from the semi-sleep mode 2 to the deep sleep mode can be obtained.

[0040] The present invention provides a multi-DIE low-power management system and method based on a core-grain architecture. For the expansion of multiple DIEs, the power supply and clock of each DIE can be managed from the system level, which can meet the working scenario requirements of different DIEs. Compared with the traditional core-grain integrated low-power management solution, the present invention only needs one DIE to provide power, clock, power management module and wake-up logic, avoiding the redundancy of the circuit at the entire chip level and saving area costs; the single-core low-power design involves front-end RTL plus UPF to back-end power planning, layout and wiring, and verification. The process is cumbersome and time-consuming. Compared with each DIE independently performing low-power design, the present invention only has one DIE to perform the low-power design process and other DIEs only need to perform conventional design, so it can also greatly save development time and cost.

[0041] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A multi-DIE low power management system based on a core-grain architecture, characterized by: It includes a master MCU DIE, a controlled ASIC_MAIN DIE and several controlled ASIC_SLV DIEs. The master MCU DIE communicates with the controlled ASIC_MAIN DIE through signals TX and RX, and the controlled ASIC_MAIN DIE communicates with several controlled ASIC_SLV DIEs through signals TX32 and RX32.

2. According to claim 1, a multi-DIE low power management system based on a core-grain architecture is characterized by: The controlled ASIC_MAIN DIE includes an analog top-level module ANALOG_top and a digital top-level module DIGITAL_top.

3. According to claim 2, a multi-DIE low power management system based on a core-grain architecture is characterized by: The analog top-level module ANALOG_top includes a power module LDO, a clock generation module OSC and an off-chip LIN bus interaction module LINphy. The power module LDO provides a power signal to each DIE, the clock generation module OSC provides a clock signal to each DIE, and the off-chip LIN bus interaction module LINphy converts the LIN frame of the off-chip host into a signal LIN_RXD and transmits it to the main control MCUDIE.

4. According to claim 2, a multi-DIE low power management system based on a core-grain architecture is characterized by: The digital top-level module DIGITAL_top includes a power management module PMU, a communication module COMU and a digital core module DIG_core. The communication module COMU parses the instruction of the main control MCU DIE and determines whether the instruction of the main control MCU DIE is for the digital core module DIG_core, the controlled ASIC_SLV DIE or the power management module PMU; when the communication module COMU parses that the device address in the instruction of the main control MCU DIE corresponds to the controlled ASIC_MAIN DIE, the communication line is switched to the digital core module DIG_core; when the communication module COMU parses that the device address in the instruction of the main control MCU DIE corresponds to the controlled ASIC_SLVDIE, the communication line is switched to the controlled ASIC_SLV DIE; when the communication module COMU parses that the instruction of the main control MCU DIE acts on the power management module PMU, a corresponding request signal pd_req for DIE to enter a low power consumption mode is generated.

5. The multi-DIE low power management system based on core-grain architecture according to claim 4, characterized in that: The digital core module DIG_core is a power-down voltage domain, and the power management module PMU and the communication module COMU are always on voltage domains.

6. A management method for a multi-DIE low power management system based on a core-grain architecture as claimed in any one of claims 1 to 5, characterized in that The following steps are involved: When the digital core module DIG_core does not need to work, the main control MCU DIE sends an instruction to the communication module COMU, and the communication module COMU generates a power-off request signal pulse to the power management module PMU. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the digital core module DIG_core, and then generates an iso signal to the isolation device ISO CELL, and forces the signal output from the digital core module DIG_core voltage domain to the always on voltage domain to a fixed value 1; then the power management module PMU generates a power switch control signal sw to cut off the power supply of the digital core module DIG_core, thereby making the controlled ASIC_MAIN DIE enter a low-power state, and the entire chip is in semi-sleep mode 1; when the digital core module DIG_core needs to be awakened from the power-off state, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy. The power management module PMU parses the wake-up frame and turns on the power of the digital core module DIG_core, and then turns on the isolation device ISO The iso signal of CELL is released, and finally the clock gating enable signal CG is released to turn on the clock of the digital core module DIG_core, and the digital core module DIG_core enters the normal working mode; When the controlled ASIC_SLV DIE does not need to work, the main control MCU DIE sends an instruction to the communication module COMU, and the communication module COMU generates a power-off request signal pulse to the power management module PMU module. The power management module PMU first generates a clock gating enable signal CG to turn off the clock CK of the controlled ASIC_SLV DIE, and then generates an iso signal to the isolation device ISO CELL, and forces the signal output by the controlled ASIC_SLV DIE to the controlled ASIC_MAIN DIE to a fixed value 1; then the power management module PMU generates a power switch control signal sw to cut off the power supply of the controlled ASIC_SLV DIE, thereby putting the controlled ASIC_SLV DIE into a low-power state, and the entire chip is in a semi-sleep mode 2; when the controlled ASIC_SLV DIE needs to be awakened from the power-off state, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy. The power management module PMU parses the wake-up frame and turns on the power of the controlled ASIC_SLV DIE, and then turns on the isolation device ISO The iso signal of CELL is released, and finally the clock gating enable signal CG is released to turn on the clock of the controlled ASIC_SLV DIE, and the controlled ASIC_SLV DIE enters the normal working mode; When the controlled ASIC_SLV DIE is powered off and the controlled ASIC_MAIN DIE is in normal working mode, the master MCU DIE is also in normal working mode; if the controlled ASIC_MAIN DIE does not need to work at this time, the master MCU DIE sends a power-off request instruction to the communication module COMU, and the communication module COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the digital core module DIG_core in the controlled ASIC_MAIN DIE and the master MCU DIE, and the whole chip enters deep sleep mode; if it is necessary to wake up from deep sleep, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the master MCU DIE, and the whole chip returns to normal working mode; When the digital core module DIG_core of the controlled ASIC_MAIN DIE is powered off and the controlled ASIC_SLV DIE is in normal working mode, the main control MCU DIE is also in normal working mode; if the controlled ASIC_SLV DIE does not need to work at this time, the main control MCU DIE sends a power-off request instruction to the communication module COMU, and the communication COMU generates a power-off request pulse to the power management module PMU to turn off the power and clock of the controlled ASIC_SLV DIE and the main control MCU DIE, and the whole chip enters deep sleep mode; if it is necessary to wake up from deep sleep, the off-chip host uses the LIN bus to send a low-level wake-up frame of a specific duration to the off-chip LIN bus interaction module LINphy, and the power management module PMU turns on the power and clock of the digital core module DIG_core, the controlled ASIC_SLV DIE, and the main control MCU DIE, and the whole chip returns to normal working mode.

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