Fibonacci coding-based memory-computing integrated neural network acceleration method and accelerator

Abstract

The application provides a memory-compute integrated neural network acceleration method and accelerator based on Fibonacci coding, which comprises the following steps: a Fibonacci encoder of a memory-compute integrated neural network accelerator converts activation values and weight values participating in a neural network operation task from binary coding to Fibonacci coding to obtain Fibonacci activation and Fibonacci weight; a DAC of a memory-compute integrated unit in the memory-compute integrated neural network accelerator converts the Fibonacci activation into multiple analog voltages and applies the analog voltages to word lines of each row of an SRAM array in the memory-compute integrated unit; each unit of the SRAM array multiplies the input analog voltage by the corresponding Fibonacci weight to obtain an intermediate operation result; an adder of each column of the SRAM array reallocates the charge of the intermediate operation result to complete the accumulation operation of the inner product, and converts the accumulation operation result into a digital format of Fibonacci coding through an ADC of the memory-compute integrated unit as an operation result of the neural network operation task.

Description

Technical Field

[0001] This invention relates to the field of charge-domain in-memory computing neural network accelerator technology, and in particular to a Fibonacci-coded in-memory computing unit and a Fibonacci-coded sparse computing in-memory computing architecture. Background Technology

[0002] Currently, the most common in-memory computing (CIM) neural network accelerators use charge-domain static random access memory (SRAM) arrays for computation, such as... Figure 1 As shown, the structure mainly includes a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and an SRAM array for computation. The SRAM array represents data as voltage amplitudes and performs one-bit inner products. Each row in the SRAM array is connected to a DAC for digital-to-analog conversion, while several columns share a single ADC for reading the computation results. Each cell in the SRAM array integrates a digital AND / XNOR gate or a transmission gate for one-bit multiplication. In the SRAM array, a column of capacitors is connected together via bit lines (BLs) to redistribute charge and complete the accumulation operation of the inner product. Furthermore, the weights of the neural network are typically stored in the SRAM for reuse. Because storing analog values ​​can cause accuracy loss in the neural network due to non-ideal analog circuitry, the CIM accelerator stores the weights in the digital domain and performs computations in the analog domain. The computation flow of this SRAM array is as follows: multiple binary inputs are converted into multiple analog voltages by the DAC and applied to the word lines (WLs) of each row of the SRAM array. Then, each cell in the SRAM array multiplies the input analog voltage by a corresponding 1-bit weight, which can be achieved using logic gates within the SRAM cell. Next, the capacitors in each column of the SRAM undergo charge redistribution to obtain the output voltage. Finally, the output voltage is converted into a digital output by an ADC.

[0003] To support multi-bit activation values ​​and weights, existing CIM neural network accelerators employ a bit-serial-bit-parallel (BSBP) scheme. BSBP involves splitting the inner product of an n-bit activation vector and an n-bit weight vector into multiple one-bit inner products. Assuming the activation values ​​are p bits, the original activation vector is split into p n one-bit vectors; assuming the weights are q bits, the original weight vector is split into q n one-bit vectors. After splitting, the p one-bit activation vectors are serially input into an SRAM array, while the q one-bit weight vectors are stored in parallel in the SRAM and their inner products are performed in parallel with each input one-bit activation vector. After the inner product operations are complete, the results of these one-bit inner products are left-shifted and added to obtain the original multi-bit inner product result. The left shift is the sum of the bit positions of the one-bit activation vector and the one-bit weight vector in the original one-bit inner product.

[0004] The CIM neural network accelerator integrates several of the aforementioned SRAM arrays for computation. The latest CIM neural network accelerator organizes these SRAM arrays into four layers: chip, computation block, local multiply-accumulate unit, and SRAM array. The chip contains multiple computation blocks connected via a two-dimensional on-chip network. Each computation block is directly connected to an on-chip router, and each router can send received data to other adjacent routers. Thus, a computation block can send data to any other computation block via one or more routers, and can also perform unicast and multicast communication. A computation block typically contains multiple local multiply-accumulate units, local caches, pooling units, quantization units, and element-wise computation units. These units are few in number and can be connected via a shared bus. The local cache is used to cache a certain number of activation values ​​for data reuse and to reduce access to external storage. The pooling unit can perform max pooling or average pooling operations. The quantization unit performs low-bit conversion of the output activation values. The element-wise computation units sum the calculation results of multiple local multiply-accumulate units. Each local multiply-accumulate unit contains multiple SRAM arrays capable of performing computations, and these SRAM arrays are organized according to a fixed data path to complete a fixed-shape vector-matrix multiplication operation. The SRAM array is the charge-domain SRAM in-memory computation unit described above.

[0005] Existing charge-domain CIM neural network accelerators face the problem of high ADC power consumption. First, the inference accuracy of the neural network is highly sensitive to the ADC resolution. Experiments show that the inference accuracy of the neural network drops sharply as the ADC resolution decreases. In CIM neural network accelerators integrated with SRAM of shape Row×Column, the ADC resolution must be maintained at log2(Row) to avoid output overflow (i.e., large values ​​are truncated to an upper bound). Although signed CIMs can mitigate the overflow problem caused by low-resolution ADCs by limiting the output voltage to a narrow range through saturation computation, they only show advantages on impractical small neural networks or uncommon binary neural networks (BNNs). In contrast, when testing several representative DNNs (e.g., ResNet50) on SRAM arrays of shape 288×256, we found that designs with saturation computation can only reduce the ADC resolution from 8 bits to 6 bits; otherwise, unless expensive neural network retraining is performed, the neural network inference accuracy drops significantly (e.g., a 5-bit ADC reduces DNN accuracy by an average of 4.0%). However, high-resolution ADCs limit energy efficiency. Even with compliant CIM and saturation calculations that could reduce the ADC resolution to 6 bits, the ADC still accounts for the largest share of power consumption (64%) in charge-domain SRAM-based CIM architectures. Previous designs mitigated ADC power consumption at the cost of area overhead and performance loss. For example, timing offset calibration reduced ADC power consumption by 34.3%, but increased area overhead by 25 times. Therefore, to achieve a peak throughput of 256 TOPS using this interleaved SAR ADC in a CIM architecture, the chip area would explode to approximately 1000 mm². 2 This is unacceptable; while pipelined and data parallelism can be used to address the energy efficiency issue of ADCs, this leads to increased ADC latency and consequently performance loss. In conclusion, a low-resolution ADC without area overhead and performance loss is urgently needed to improve the energy efficiency of high-performance charge-domain SRAM-CIM neural network accelerators without sacrificing accuracy. Summary of the Invention

[0006] The purpose of this invention is to solve the energy consumption bottleneck problem of existing ADCs, and to propose a Fibonacci-encoded in-memory computing unit and a Fibonacci-encoded sparse computing in-memory computing architecture. This Fibonacci-encoded in-memory computing unit can reduce the range of computation results to lower ADC resolution, and is combined with sparse computing, integrated into a high-throughput in-memory computing neural network accelerator to reduce accumulated energy consumption and improve energy efficiency.

[0007] To address the shortcomings of existing technologies, such as Figure 10As shown, this invention proposes a method for accelerating in-memory computing neural networks based on Fibonacci coding, including:

[0008] The initial step is to build an in-memory neural network accelerator that includes a Fibonacci encoder and obtain the neural network computation task to be executed.

[0009] The computational steps are as follows: The Fibonacci encoder of the in-memory computing neural network accelerator encodes the activation and weight values ​​participating in the neural network computation task from binary to Fibonacci code, obtaining Fibonacci activation and Fibonacci weight. The DAC of the in-memory computing unit in the in-memory computing neural network accelerator converts the Fibonacci activation into multiple analog voltages, which are then applied to the word lines of each row of the SRAM array in the in-memory computing unit. Each cell of the SRAM array multiplies the input analog voltage by the corresponding Fibonacci weight to obtain an intermediate computation result. The adder of each column of the SRAM array redistributes the charge of the intermediate computation result to complete the inner product accumulation operation, and converts the accumulation operation result into a Fibonacci encoded digital format through the ADC of the in-memory computing unit, which serves as the computation result of the neural network computation task.

[0010] The in-memory computing neural network acceleration method based on Fibonacci encoding, wherein the in-memory computing unit includes an SRAM absolute value unit, an SRAM sign unit, a DAC, an ADC, the Fibonacci encoder, and a Fibonacci encoded adder.

[0011] The SRAM symbol cell and the SRAM absolute value cell store the weight values ​​of the Fibonacci encoding format; the Fibonacci encoder uses a hardware lookup table to convert binary numbers into the Fibonacci encoding format; and the adder adds the intermediate calculation results of multiple SRAM columns into a multi-bit inner product result.

[0012] The aforementioned in-memory computing neural network acceleration method based on Fibonacci coding, wherein...

[0013] Multiple absolute value cells and SRAM symbol cells form a Fibonacci-coded weight array; the bit line outputs of multiple columns of absolute value cells share the same ADC; the word lines of each row of SRAM absolute value cells and SRAM symbol cells share a DAC.

[0014] The Fibonacci encoder contains multiple lookup tables and a multi-selector. Each lookup table converts the input binary number into a Fibonacci encoding format multiplied by a fixed number. The encoder activates only one lookup table each time it operates. The output of the activated lookup table is selected by the MUX as the output of the Fibonacci encoder.

[0015] The in-memory computing neural network acceleration method based on Fibonacci coding, wherein the in-memory computing neural network accelerator includes: a chip, a computing block, and an in-memory computing unit composed of an accumulator and an SRAM array;

[0016] Each chip contains at least one computation block and at least one Fibonacci-coded cache, and the computation blocks are interconnected via an on-chip network; each computation block contains at least one local multiply-accumulate unit, a computation block local cache, a pooling unit, a compressor, and a decompressor; each local multiply-accumulate unit contains at least one input shift register, a zero detector, at least one element-wise arithmetic unit, at least one accumulator, and at least one SRAM array;

[0017] Furthermore, multiple SRAM arrays share one accumulator. The outputs of multiple SRAM arrays are first added in the binary field, and then the addition result is input into the Fibonacci encoder. The output of the encoder is then input into the subsequent Fibonacci encoded adder.

[0018] The zero-detection component for activation values ​​performs a multi-input OR-NOT operation on the absolute value bits of a column of multiple activation values ​​to calculate the AZERO signal indication, which indicates whether all bits in the current column are zero, and broadcasts the AZERO signal indication to the adjacent SRAM array for input sharing; the ADC output zero-detection component is equipped in the SRAM array and consists of a row of OR gates and a row of 1-bit registers. The number of OR gates and registers is the same as the number of columns of the SRAM, and each register bit indicates whether the weight of a column is all zero; when the AZERO signal indication represents that all activation value input bits are zero, the ADC conversion process is skipped, and the output value of that column is directly determined to be zero.

[0019] like Figure 11 As shown, this invention also proposes a memory-based neural network accelerator based on Fibonacci coding, which includes:

[0020] The initial module constructs a memory-based neural network accelerator containing a Fibonacci encoder and obtains the neural network computation tasks to be executed.

[0021] The computation module of this in-memory computing neural network accelerator uses a Fibonacci encoder to encode the activation and weight values ​​involved in the neural network computation task from binary to Fibonacci code, obtaining Fibonacci activation and Fibonacci weight. The DAC of the in-memory computing unit in this in-memory computing neural network accelerator converts the Fibonacci activation into multiple analog voltages, which are then applied to the word lines of each row of the SRAM array in the in-memory computing unit. Each cell of the SRAM array multiplies the input analog voltage by the corresponding Fibonacci weight to obtain an intermediate computation result. The adder of each column of the SRAM array redistributes the charge of the intermediate computation result to complete the inner product accumulation operation, and converts the accumulation operation result into a Fibonacci encoded digital format through the ADC of the in-memory computing unit, which serves as the computation result of the neural network computation task.

[0022] The in-memory computing neural network accelerator based on Fibonacci encoding includes an SRAM absolute value unit, an SRAM sign unit, a DAC, an ADC, the Fibonacci encoder, and a Fibonacci encoded adder.

[0023] The SRAM symbol cell and the SRAM absolute value cell store the weight values ​​of the Fibonacci encoding format; the Fibonacci encoder uses a hardware lookup table to convert binary numbers into the Fibonacci encoding format; and the adder adds the intermediate calculation results of multiple SRAM columns into a multi-bit inner product result.

[0024] The aforementioned in-memory neural network accelerator based on Fibonacci coding, wherein

[0025] Multiple absolute value cells and SRAM symbol cells form a Fibonacci-coded weight array; the bit line outputs of multiple columns of absolute value cells share the same ADC; the word lines of each row of SRAM absolute value cells and SRAM symbol cells share a DAC.

[0026] The Fibonacci encoder contains multiple lookup tables and a multi-selector. Each lookup table converts the input binary number into a Fibonacci encoding format multiplied by a fixed number. The encoder activates only one lookup table each time it operates. The output of the activated lookup table is selected by the MUX as the output of the Fibonacci encoder.

[0027] The in-memory computing neural network accelerator includes: a chip, a computing block, and an in-memory computing unit consisting of an accumulator and an SRAM array;

[0028] Each chip contains at least one computation block and at least one Fibonacci-coded cache, and the computation blocks are interconnected via an on-chip network; each computation block contains at least one local multiply-accumulate unit, a computation block local cache, a pooling unit, a compressor, and a decompressor; each local multiply-accumulate unit contains at least one input shift register, a zero detector, at least one element-wise arithmetic unit, at least one accumulator, and at least one SRAM array;

[0029] Furthermore, multiple SRAM arrays share one accumulator. The outputs of multiple SRAM arrays are first added in the binary field, and then the addition result is input into the Fibonacci encoder. The output of the encoder is then input into the subsequent Fibonacci encoded adder.

[0030] The zero-detection component for activation values ​​performs a multi-input OR-NOT operation on the absolute value bits of a column of multiple activation values ​​to calculate the AZERO signal indication, which indicates whether all bits in the current column are zero, and broadcasts the AZERO signal indication to the adjacent SRAM array for input sharing; the ADC output zero-detection component is equipped in the SRAM array and consists of a row of OR gates and a row of 1-bit registers. The number of OR gates and registers is the same as the number of columns of the SRAM, and each register bit indicates whether the weight of a column is all zero; when the AZERO signal indication represents that all activation value input bits are zero, the ADC conversion process is skipped, and the output value of that column is directly determined to be zero.

[0031] The present invention also proposes an electronic device, including the aforementioned in-memory computing neural network accelerator, which may be connected to an information display device for displaying the evaluation results using user-set display parameters, attributes, or through an artificial intelligence model.

[0032] The present invention also proposes a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the in-memory computing neural network acceleration methods described herein.

[0033] The present invention also proposes a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the in-memory computing neural network acceleration methods described herein.

[0034] As can be seen from the above solutions, the advantages of the present invention are:

[0035] The energy efficiency of this invention is 1.62 times that of the prior art. This energy efficiency improvement stems from Fibonacci encoding and sparsity support. First, Fibonacci encoding centralizes the range of the ADC input, avoiding data overflow errors, thus enabling the use of a low-resolution ADC. Second, sparsity support skips redundant zero calculations, correcting the defects caused by more "0"s. Conversely, the prior art uses a high-resolution ADC to avoid data overflow errors in binary encoding, resulting in significant energy consumption. Attached Figure Description

[0036] Figure 1 Diagram of existing technical solution;

[0037] Figure 2 Diagram of a Fibonacci-coded in-memory computing unit;

[0038] Figure 3 Here is a structural diagram of the DAC;

[0039] Figure 4 This is a structural diagram of a Fibonacci encoder;

[0040] Figure 5 Adders encoded in Fibonacci sequence and skull diagram;

[0041] Figure 6 Diagram of a sparse computing in-memory architecture for Fibonacci encoding;

[0042] Figure 7 The zero-output skip structure diagram for the ADC;

[0043] Figure 8 Zero-input skips the structure graph for addition;

[0044] Figure 9 A diagram of data compression methods;

[0045] Figure 10 This is a flowchart of the method of the present invention;

[0046] Figure 11 This is a block diagram of the device of the present invention;

[0047] Figure 12 This is a schematic diagram of the structure of the first electronic device of the present invention;

[0048] Figure 13 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0049] Figure 14 This is a schematic diagram of the structure of the second electronic device of the present invention.

[0050] Figure label:

[0051] A - First electronic device;

[0052] B-In-memory neural network accelerator based on Fibonacci coding;

[0053] C-Data acquisition equipment;

[0054] D-Information display device;

[0055] 1000 - Second electronic device;

[0056] Ⅰ-Computational Unit;

[0057] II-ROM;

[0058] III-RAM;

[0059] N-bus;

[0060] V-Interface;

[0061] VI - Input Unit;

[0062] VII - Output Unit;

[0063] VIII - Storage medium;

[0064] IX - Communication Unit. Detailed Implementation

[0065] It should be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0066] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0067] The processor described in this invention is the control center of an electronic device. It can be a single processor or a collective term for multiple processing elements. For example, it can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of this invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0068] Alternatively, the processor can perform various functions of the electronic device by running or executing software programs stored in memory and by calling data stored in memory.

[0069] In a specific implementation, as one example, the processor may include one or more CPUs. Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Electronic devices may include servers, desktop computers, laptops, smartphones, tablets, embedded computers, etc., where the embedded computer includes vehicles and robots, etc.

[0070] The memory is used to store the software program that executes the solution of the present invention, and the execution is controlled by the processor. For specific implementation methods, please refer to the above method embodiments, which will not be repeated here.

[0071] It should be noted that the structure of the electronic device shown in the accompanying drawings of this invention does not constitute a limitation thereof. The actual knowledge structure recognition device may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0072] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0073] It should also be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0074] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0075] It should also be understood that, in various embodiments of the present invention, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0076] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0077] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0078] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0079] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0080] In its research on charge-domain in-memory neural network accelerators, this invention discovered that the high energy consumption of existing ADCs is due to their excessively high resolution. Current solutions focus on optimizing the design and implementation of the ADC itself at a given resolution, neglecting to reduce the ADC's resolution through overall system design, thereby reducing its energy consumption. The high resolution of the ADC is caused by the high density of "1"s in existing binary encoding methods, resulting in a large range of variation in the output voltage of each column (i.e., the ADC's input voltage), thus requiring a high-resolution ADC to perform analog-to-digital conversion. Finding an innovative encoding method that reduces the density of "1"s in each number is the technical challenge of this invention.

[0081] This invention, through research on digital encoding methods, discovered that this deficiency can be resolved using Fibonacci encoding. Fibonacci encoding, unlike binary encoding, eliminates the possibility of two consecutive "1"s, thus reducing the density of "1"s. A lower density of "1"s helps to reduce the input voltage range of the ADC, thereby reducing the ADC's resolution and power consumption.

[0082] This invention utilizes Fibonacci encoding to propose a Fibonacci-encoded in-memory computation unit. This Fibonacci-encoded in-memory computation unit transforms the activation values ​​and weights involved in the computation from binary encoding to Fibonacci encoding. Furthermore, the ADC output is also converted from binary format to Fibonacci-encoded format by the encoder and then accumulated by a subsequent Fibonacci-encoded adder.

[0083] This invention combines Fibonacci-encoded in-memory computing units with sparsity support to create a Fibonacci-encoded sparse computing in-memory architecture. Because Fibonacci encoding increases the density of "0", it is more suitable for using sparsity techniques to further reduce energy consumption. Specifically, this architecture further reduces ADC overhead by skipping columns of all-zero activation values ​​or all-zero weights, reduces the overhead of the Fibonacci-encoded adder by zero-skipping, and reduces storage and communication bandwidth through bit-slice-level compression.

[0084] To make the above-mentioned features and effects of the present invention clearer and easier to understand, specific embodiments are described below in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are merely illustrative. The scope of protection of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.

[0085] Figure 2The diagram illustrates the architecture of a Fibonacci-encoded in-memory computing unit according to Embodiment 1 of the present invention. This Fibonacci-encoded in-memory computing unit can calculate the activation values ​​and weights of Fibonacci codes to improve energy efficiency. The specific structure of this Fibonacci-encoded in-memory computing unit is as follows:

[0086] An SRAM in-memory computing unit includes multiple SRAM absolute value units, multiple SRAM symbol units, multiple digital-to-analog converters (DACs), at least one analog-to-digital converter (ADC), at least one Fibonacci encoder, and at least one Fibonacci-encoded adder. Each column of multiple SRAM symbol units and multiple columns of SRAM absolute value units store multiple weights in a Fibonacci-encoded format represented in original code. The key difference between Fibonacci encoding and binary encoding is that the absolute value of a number does not contain two consecutive "1"s at any position. The Fibonacci encoder uses a hardware lookup table to convert the binary format number read from the ADC into a Fibonacci-encoded format multiplied by a fixed number. The Fibonacci-encoded adder adds the results of multiple one-bit inner products into the result corresponding to a multi-bit inner product.

[0087] Further reference Figure 2 As shown in this embodiment, multiple SRAM absolute value units and SRAM symbol units form a Fibonacci encoded weight array. For example, each weight contains 10 absolute values ​​and 1 weight, so each column of symbol units will be accompanied by 10 columns of absolute value units. The bit line outputs of multiple columns of absolute value units can share the same ADC. The word lines of each row of SRAM absolute value units and SRAM symbol units share a DAC.

[0088] In this embodiment, the DAC structure is as follows: Figure 3 As shown. The DAC input is 1 bit, representing 1 bit of the absolute value of the activation value. The DAC outputs two voltages, Vx and Vdd-Vx. If the DAC input bit is '0', then Vx is Vdd / 2, and Vdd-Vx is also Vdd / 2; if the DAC input bit is '1', then Vx is Vdd, and Vdd-Vx is GND.

[0089] In this embodiment, the structure of the Fibonacci encoder is as follows: Figure 4 As shown, it contains multiple lookup tables and a multiplexer (MUX). Each lookup table converts the input binary number into a Fibonacci encoding format multiplied by a fixed number; the encoder activates only one lookup table each time it works; the output of the activated lookup table is selected by the MUX as the output of the Fibonacci encoder.

[0090] In this embodiment, as Figure 5As shown, the Fibonacci-coded adder is designed based on the signed addition algorithm of the original Fibonacci-coded data (i.e., sign and absolute value). This algorithm mainly utilizes a bit-by-bit addition and subtraction and four passes of the sliding window algorithm to calculate the addition result. Based on this algorithm, the bit-by-bit adder consists of several 1-bit adders and subtractors, each with 2 bits of input and 2 bits of output; subsequently, there are four stages, each corresponding to the four stages of the sliding window algorithm. Since the Fibonacci-coded data is in original code format, the Fibonacci-coded adder first needs to determine whether to perform addition or subtraction based on the sign and magnitude of the input. Then, if subtraction is chosen, stage 0 executes the first pass of the sliding window; otherwise, stage 0 is skipped, and the input is directly forwarded to stage 1. Each stage consists of multiple window adders (WA), each window adder converting several bits of the input into an output of the same number of bits according to a certain rule. In each stage, except for the first window adder, each window adder takes one bit of the output from the previous stage and several bits of the output from the previous window adder in the current stage as input, producing one bit of output and some intermediate bits as part of the input to the next window adder. Note that, according to the literature, the output of the last window adder in stage 1 requires a cleanup operation. All transformation rules for each window adder follow the algorithm described in [reference needed].

[0091] In this embodiment, the Fibonacci-encoded in-memory computing unit performs calculations in a serial-to-parallel manner using activation value bits and weight bits. One calculation by the Fibonacci-encoded in-memory computing unit includes four steps: activation value input, SRAM cell calculation, analog domain charge redistribution, and ADC analog-to-digital conversion. Specifically, each bit of the absolute value of a column of activation values ​​is serially calculated with all bits of the weights. Each input consists of one bit of each activation value and one sign bit of each activation value. The absolute value bits are converted into two voltages by the DAC and injected into the SRAM array along with the sign bits for charge domain analog calculation. The SRAM cell calculation includes the sign unit calculating the sign of each multiplication result and selecting the appropriate voltage (Vx for a positive result, Vdd-Vx for a negative result, and Vdd / 2 for a result of 0). Analog domain charge redistribution involves averaging the selected voltages across each column using the physical laws of charge redistribution. Finally, the ADC converts the calculated voltages of each column into a digital domain representation.

[0092] Furthermore, this embodiment can also be applied to in-memory computing units in the current domain.

[0093] In summary, the Fibonacci-encoded in-memory computing unit provided in this embodiment can perform calculations on the activation values ​​and weights of Fibonacci codes to improve the energy efficiency of neural network inference accelerators.

[0094] Furthermore, based on the aforementioned Fibonacci-encoded in-memory computing unit, this second embodiment further provides a Fibonacci-encoded sparse computing in-memory computing architecture, such as... Figure 6 As shown in the diagram. Overall, the architecture comprises four layers: chip, computation block, local multiply-accumulate unit, and SRAM array. Each chip contains at least one computation block and at least one Fibonacci-encoded cache, with the computation blocks interconnected via an on-chip network. Each computation block contains at least one local multiply-accumulate unit, a computation block local cache, a pooling unit, a compressor, and a decompressor. Each local multiply-accumulate unit contains at least one input shift register, a zero detector, at least one element-wise arithmetic unit, at least one accumulator, and at least one SRAM array. The combination of the accumulator (containing at least one Fibonacci encoder and at least one Fibonacci-encoded adder) and the SRAM array constitutes the aforementioned Fibonacci-encoded in-memory computation unit.

[0095] It should be noted that, in order to reduce the overhead of the accumulator, in this embodiment, every two SRAM arrays share one accumulator. Specifically, the outputs of the two SRAM arrays are first added in the binary field, and then the addition result is input into a Fibonacci encoder. The output of the encoder is then input into a subsequent Fibonacci-encoded adder.

[0096] To skip the zero-output ADC conversion process, this embodiment implements two components responsible for zero detection of the activation value and zero detection of the ADC output, such as... Figure 7 As shown. The zero-detection component for activation values ​​performs a multi-input NOR operation on the absolute value bits of a column of multiple activation values ​​to calculate AZERO. This signal indicates whether all bits in that column are zero and broadcasts AZERO to the adjacent SRAM array for input sharing. The ADC output zero-detection component is equipped in the SRAM array and consists of one row of OR gates and one row of 1-bit registers. The number of OR gates and registers is the same as the number of columns in the SRAM. Each register bit indicates whether all weights in a column are zero. When all activation value input bits are zero (i.e., AZERO is 1) or a column of weight bits is zero (WZERO is 1), the output value of that column can be determined to be zero in advance, thus avoiding one ADC conversion process. Since the weights are fixed, all WZEROs can be pre-calculated before the overall execution begins. Each column of SRAM has one WZERO value; if all bits in that column of SRAM are 0, then WZERO is 1; otherwise, WZERO is 0.

[0097] Zero-input skipping Fibonacci code adders equip Fibonacci code adders with zero-input skipping logic, such as... Figure 8As shown. To support zero-input skipping, the Fibonacci-coded adder takes inputs from two registers, whose values ​​are only updated when both inputs are non-zero. When there is a zero input, the values ​​in both registers remain unchanged, thus keeping the inputs to the Fibonacci-coded adder constant. Since the Fibonacci-coded adder is a combinational circuit, it consumes no dynamic energy. According to the addition rule, when one input is zero, the addition result equals the other input. Therefore, a 3-to-1 MUX circuit is used to select the addition result from the two inputs and the output of the Fibonacci-coded adder.

[0098] To compensate for the additional storage capacity and interconnect bandwidth requirements caused by the large bit width of Fibonacci encoded data, we utilize a bit-slicing-based compression method to reduce external cache capacity and interconnect bandwidth requirements. For example... Figure 9 As shown, this compression method comprises two stages: a slice length reduction stage (for reducing the length of each slice) and a hybrid compression stage (for reducing the length of multiple slices).

[0099] Bit slice length reduction stage: Since there are no consecutive '1's in Fibonacci encoding, a 4-bit slice, for example, can only be one of eight possibilities: "0000", "0001", "0010", "0100", "1000", "1010", "0101", and "1001". We can define a conversion rule to represent a 4-bit slice as a 3-bit index, such as "000" for code "0000" and "111" for code "1001". In this way, we compress the length of each slice from 4 bits to 3 bits during data transmission and storage, and decompress it during computation.

[0100] Hybrid Compression Stage: We categorize a set of slices into high-sparseness, medium-sparseness, and low-sparseness levels based on their compression ratio. The hybrid compression method utilizes three different strategies: run-length encoding compression, bitmap compression, and no compression, corresponding to the high-sparseness, medium-sparseness, and low-sparseness levels, respectively. For low-sparseness slices, we do not compress them to avoid overhead. For high-sparseness slices, we choose run-length encoding compression to maximize the compression ratio. For medium-sparseness slices, we use bitmap compression to balance overhead and compression ratio.

[0101] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0102] like Figure 11As shown, this invention also proposes a memory-based neural network accelerator based on Fibonacci coding, which includes:

[0103] The initial module constructs a memory-based neural network accelerator containing a Fibonacci encoder and obtains the neural network computation tasks to be executed.

[0104] The computation module of this in-memory computing neural network accelerator uses a Fibonacci encoder to encode the activation and weight values ​​involved in the neural network computation task from binary to Fibonacci code, obtaining Fibonacci activation and Fibonacci weight. The DAC of the in-memory computing unit in this in-memory computing neural network accelerator converts the Fibonacci activation into multiple analog voltages, which are then applied to the word lines of each row of the SRAM array in the in-memory computing unit. Each cell of the SRAM array multiplies the input analog voltage by the corresponding Fibonacci weight to obtain an intermediate computation result. The adder of each column of the SRAM array redistributes the charge of the intermediate computation result to complete the inner product accumulation operation, and converts the accumulation operation result into a Fibonacci encoded digital format through the ADC of the in-memory computing unit, which serves as the computation result of the neural network computation task.

[0105] The in-memory computing neural network accelerator based on Fibonacci encoding includes an SRAM absolute value unit, an SRAM sign unit, a DAC, an ADC, the Fibonacci encoder, and a Fibonacci encoded adder.

[0106] The SRAM symbol cell and the SRAM absolute value cell store the weight values ​​of the Fibonacci encoding format; the Fibonacci encoder uses a hardware lookup table to convert binary numbers into the Fibonacci encoding format; and the adder adds the intermediate calculation results of multiple SRAM columns into a multi-bit inner product result.

[0107] The aforementioned in-memory neural network accelerator based on Fibonacci coding, wherein

[0108] Multiple absolute value cells and SRAM symbol cells form a Fibonacci-coded weight array; the bit line outputs of multiple columns of absolute value cells share the same ADC; the word lines of each row of SRAM absolute value cells and SRAM symbol cells share a DAC.

[0109] The Fibonacci encoder contains multiple lookup tables and a multi-selector. Each lookup table converts the input binary number into a Fibonacci encoding format multiplied by a fixed number. The encoder activates only one lookup table each time it operates. The output of the activated lookup table is selected by the MUX as the output of the Fibonacci encoder.

[0110] The in-memory computing neural network accelerator includes: a chip, a computing block, and an in-memory computing unit consisting of an accumulator and an SRAM array;

[0111] Each chip contains at least one computation block and at least one Fibonacci-coded cache, and the computation blocks are interconnected via an on-chip network; each computation block contains at least one local multiply-accumulate unit, a computation block local cache, a pooling unit, a compressor, and a decompressor; each local multiply-accumulate unit contains at least one input shift register, a zero detector, at least one element-wise arithmetic unit, at least one accumulator, and at least one SRAM array;

[0112] Furthermore, multiple SRAM arrays share one accumulator. The outputs of multiple SRAM arrays are first added in the binary field, and then the addition result is input into the Fibonacci encoder. The output of the encoder is then input into the subsequent Fibonacci encoded adder.

[0113] The zero-detection component for activation values ​​performs a multi-input OR-NOT operation on the absolute value bits of a column of multiple activation values ​​to calculate the AZERO signal indication, which indicates whether all bits in the current column are zero, and broadcasts the AZERO signal indication to the adjacent SRAM array for input sharing; the ADC output zero-detection component is equipped in the SRAM array and consists of a row of OR gates and a row of 1-bit registers. The number of OR gates and registers is the same as the number of columns of the SRAM, and each register bit indicates whether the weight of a column is all zero; when the AZERO signal indication represents that all activation value input bits are zero, the ADC conversion process is skipped, and the output value of that column is directly determined to be zero.

[0114] like Figure 12 As shown, in another embodiment of the present invention, a first electronic device A is also proposed, which includes the aforementioned in-memory computing neural network accelerator.

[0115] like Figure 13 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through wired or wireless information transmission schemes. The data acquisition device C is used to collect neural network operation tasks, such as face recognition tasks, image classification tasks, and weather forecasting tasks based on neural network models. The information display device D is used to display the task reasoning results obtained by the present invention, i.e., the operation results.

[0116] The information display device D can process and organize the data output by the first electronic device A based on an information display mechanism to improve the readability of the data. This information display mechanism can be manually preset, for example, visualizing the data output by the first electronic device A. It can be based on user-defined display parameters and / or attributes, such as the data range to be displayed and font, color, and scrolling options. It can present the user with the key information specified by the user, such as image classification results or weather forecasts from calculations, allowing the user to access this information more quickly without having to access secondary pages or scroll through pages, thus saving user effort. Alternatively, this information display mechanism can be an artificial intelligence (AI) display model, which can learn the user's key information interests based on previous usage habits, such as viewing time, number of clicks, and number of edits, and then automatically present the user with rich and necessary key information.

[0117] The present invention also provides a computer program product, which includes a computer program that can be stored on a readable storage medium. When the computer program is executed by a processor, the computer can execute the in-memory computing neural network acceleration method provided by the above methods.

[0118] In another embodiment of the present invention, a storage medium VIII is provided for storing a computer program that executes the in-memory computing neural network acceleration method. It should be understood that the storage medium in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DRRAM).

[0119] Figure 14 A schematic block diagram of a second electronic device 1000 that can be used to implement embodiments of the present invention is shown. The second electronic device 1000 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein. The second electronic device 1000 may be the same as or different from the first electronic device A.

[0120] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from storage medium VIII into random access memory (RAM) III. The RAM III may also store various programs and data required for the operation of the device 1000. The computing unit I, ROM II, and RAM III are interconnected via bus IV. An input / output (I / O) interface V is also connected to bus IV.

[0121] Multiple components in the second electronic device 1000 are connected to I / O interface V, including: input unit VI, such as a keyboard, mouse, etc.; output unit VII, such as various types of displays, speakers, etc.; storage medium VIII, such as a disk, optical disk, etc.; and communication unit IX, such as a network card, modem, wireless transceiver, etc. Communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0122] The computing unit I can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit I performs the various methods and processes described above, such as method steps S1-S2. For example, in some embodiments, the methods can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage medium VIII. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM II and / or communication unit IX. When the computer program is loaded into RAM III and executed by computing unit I, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, computing unit I can be configured to perform methods by any other suitable means (e.g., by means of firmware).

[0123] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A method for accelerating in-memory computing neural networks based on Fibonacci coding, characterized in that, include: The initial step is to build an in-memory neural network accelerator that includes a Fibonacci encoder and obtain the neural network computation task to be executed. The computational steps are as follows: The Fibonacci encoder of the in-memory computing neural network accelerator encodes the activation and weight values ​​participating in the neural network computation task from binary to Fibonacci code, obtaining Fibonacci activation and Fibonacci weight. The DAC of the in-memory computing unit in the in-memory computing neural network accelerator converts the Fibonacci activation into multiple analog voltages, which are then applied to the word lines of each row of the SRAM array in the in-memory computing unit. Each cell of the SRAM array multiplies the input analog voltage by the corresponding Fibonacci weight to obtain an intermediate computation result. The adder of each column of the SRAM array redistributes the charge of the intermediate computation result to complete the inner product accumulation operation, and the accumulation result is converted into a Fibonacci encoded digital format by the ADC of the in-memory computing unit as the computation result of the neural network computation task. The in-memory computing unit includes an SRAM absolute value unit, an SRAM sign unit, a DAC, an ADC, a Fibonacci encoder, and a Fibonacci-encoded adder; The SRAM symbol cell and the SRAM absolute value cell store the weight values ​​of the Fibonacci encoding format; the Fibonacci encoder uses a hardware lookup table to convert binary numbers into the Fibonacci encoding format; and the adder adds the intermediate calculation results of multiple SRAM columns into a multi-bit inner product result.

2. The in-memory computing neural network acceleration method based on Fibonacci coding as described in claim 1, characterized in that, Multiple absolute value cells and SRAM symbol cells form a Fibonacci-coded weight array; the bit line outputs of multiple columns of absolute value cells share the same ADC; the word lines of each row of SRAM absolute value cells and SRAM symbol cells share a DAC. The Fibonacci encoder contains multiple lookup tables and a multi-selector. Each lookup table converts the input binary number into a Fibonacci encoded format multiplied by a fixed number. The encoder activates only one lookup table each time it operates; the output of the activated lookup table is selected by the MUX as the output of that Fibonacci encoder.

3. The in-memory computing neural network acceleration method based on Fibonacci coding as described in claim 1, characterized in that, The in-memory computing neural network accelerator includes: a chip, a computing block, and an in-memory computing unit consisting of an accumulator and an SRAM array; Each chip contains at least one computation block and at least one Fibonacci-coded cache, and the computation blocks are interconnected via an on-chip network; each computation block contains at least one local multiply-accumulate unit, a computation block local cache, a pooling unit, a compressor, and a decompressor; each local multiply-accumulate unit contains at least one input shift register, a zero detector, at least one element-wise arithmetic unit, at least one accumulator, and at least one SRAM array; Furthermore, multiple SRAM arrays share one accumulator. The outputs of multiple SRAM arrays are first added in the binary field, and then the addition result is input into the Fibonacci encoder. The output of the encoder is then input into the subsequent Fibonacci encoded adder. The zero-detection component for activation values ​​performs a multi-input OR-NOT operation on the absolute value bits of a column of multiple activation values ​​to calculate the AZERO signal indication, which indicates whether all bits in the current column are zero, and broadcasts the AZERO signal indication to the adjacent SRAM array for input sharing; the ADC output zero-detection component is equipped in the SRAM array and consists of a row of OR gates and a row of 1-bit registers. The number of OR gates and registers is the same as the number of columns of the SRAM, and each register bit indicates whether the weight of a column is all zero; when the AZERO signal indication represents that all activation value input bits are zero, the ADC conversion process is skipped, and the output value of that column is directly determined to be zero.

4. A memory-based neural network accelerator based on Fibonacci coding, characterized in that, include: The initial module constructs a memory-based neural network accelerator containing a Fibonacci encoder and obtains the neural network computation tasks to be executed. The computation module of this in-memory computing neural network accelerator uses a Fibonacci encoder to encode the activation and weight values ​​involved in the neural network computation task from binary to Fibonacci code, obtaining Fibonacci activation and Fibonacci weight. The DAC of the in-memory computing unit in this in-memory computing neural network accelerator converts the Fibonacci activation into multiple analog voltages, which are then applied to the word lines of each row of the SRAM array in the in-memory computing unit. Each cell of the SRAM array multiplies the input analog voltage by the corresponding Fibonacci weight to obtain an intermediate computation result. The adder of each column of the SRAM array redistributes the charge of the intermediate computation result to complete the inner product accumulation operation, and converts the accumulation operation result into a Fibonacci encoded digital format through the ADC of the in-memory computing unit, which serves as the computation result of the neural network computation task. The in-memory computing unit includes an SRAM absolute value unit, an SRAM sign unit, a DAC, an ADC, a Fibonacci encoder, and a Fibonacci-encoded adder; The SRAM symbol cell and the SRAM absolute value cell store the weight values ​​of the Fibonacci encoding format; the Fibonacci encoder uses a hardware lookup table to convert binary numbers into the Fibonacci encoding format; and the adder adds the intermediate calculation results of multiple SRAM columns into a multi-bit inner product result.

5. The in-memory computing neural network accelerator based on Fibonacci coding as described in claim 4, characterized in that, Multiple absolute value cells and SRAM symbol cells form a Fibonacci-coded weight array; the bit line outputs of multiple columns of absolute value cells share the same ADC; the word lines of each row of SRAM absolute value cells and SRAM symbol cells share a DAC. The Fibonacci encoder contains multiple lookup tables and a multi-selector. Each lookup table converts the input binary number into a Fibonacci encoded format multiplied by a fixed number. The encoder activates only one lookup table per operation. The output of the activated lookup table is selected by the MUX as the output of the Fibonacci encoder; The in-memory computing neural network accelerator includes: a chip, a computing block, and an in-memory computing unit consisting of an accumulator and an SRAM array; Each chip contains at least one computation block and at least one Fibonacci-coded cache, and the computation blocks are interconnected via an on-chip network; each computation block contains at least one local multiply-accumulate unit, a computation block local cache, a pooling unit, a compressor, and a decompressor; each local multiply-accumulate unit contains at least one input shift register, a zero detector, at least one element-wise arithmetic unit, at least one accumulator, and at least one SRAM array; Furthermore, multiple SRAM arrays share one accumulator. The outputs of multiple SRAM arrays are first added in the binary field, and then the addition result is input into the Fibonacci encoder. The output of the encoder is then input into the subsequent Fibonacci encoded adder. The zero-detection component for activation values ​​performs a multi-input OR-NOT operation on the absolute value bits of a column of multiple activation values ​​to calculate the AZERO signal indication, which indicates whether all bits in the current column are zero, and broadcasts the AZERO signal indication to the adjacent SRAM array for input sharing; the ADC output zero-detection component is equipped in the SRAM array and consists of a row of OR gates and a row of 1-bit registers. The number of OR gates and registers is the same as the number of columns of the SRAM, and each register bit indicates whether the weight of a column is all zero; when the AZERO signal indication represents that all activation value input bits are zero, the ADC conversion process is skipped, and the output value of that column is directly determined to be zero.

6. An electronic device, characterized in that, The device includes the in-memory neural network accelerator as described in claim 4 or 5, and the electronic device is connected to an information display device, which is used to display the computation results of the neural network computation task using user-set display parameters, attributes, or through an artificial intelligence model.

7. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the in-memory computing neural network acceleration method according to any one of claims 1-3.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the in-memory computing neural network acceleration method according to any one of claims 1-3.

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