Display module, binding impedance detection method thereof and display device

Abstract

The embodiment of the invention provides a display module, a binding impedance detection method thereof and a display device, relates to the technical field of display, and can save the detection cost and improve the detection efficiency. The display module comprises a display assembly, the display assembly comprises a display panel and a driving chip, the display panel comprises a sub-pixel and a data line which are electrically connected, and the driving chip comprises a first pin used for outputting a high level; the circuit board is bound with the display assembly; the display assembly further comprises a test switch, a first test pin and a second test pin, the first test pin is electrically connected with the first pin, and the test switch is electrically connected between the second test pin and the data line. The circuit board comprises a first resistor, a third test pin and a fourth test pin, the third test pin is electrically connected with the first test pin, the fourth test pin is electrically connected with the second test pin, and the first resistor is electrically connected between the third test pin and the fourth test pin.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display module and a binding impedance detection method thereof, and a display device. Background Art

[0002] The display module includes a display component and a circuit board bound to the display component.

[0003] Currently, before the display module is put into the subsequent production line, the bonding impedance of the circuit board will be tested to determine whether the bonding impedance of the circuit board exceeds the specification, thereby preventing unqualified products from flowing into the subsequent process and causing process waste. However, the existing testing methods are relatively complicated and costly, which is not conducive to improving testing efficiency. Summary of the invention

[0004] The embodiments of the present invention provide a display module and a binding impedance detection method and a display device, which can save detection costs and improve detection efficiency.

[0005] In a first aspect, an embodiment of the present invention provides a display module, including:

[0006] A display component, comprising a display panel and a driving chip, wherein the display panel comprises sub-pixels and data lines that are electrically connected, and the driving chip comprises a first pin for outputting a high level;

[0007] a circuit board bound to the display assembly;

[0008] Wherein, the display component further includes a test switch, a first test pin and a second test pin, the first test pin is electrically connected to the first pin, and the test switch is electrically connected between the second test pin and the data line;

[0009] The circuit board includes a first resistor, a third test pin and a fourth test pin, the third test pin is electrically connected to the first test pin, the fourth test pin is electrically connected to the second test pin, and the first resistor is electrically connected between the third test pin and the fourth test pin.

[0010] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a method for detecting a binding impedance of a display module, the display module comprising:

[0011] A display component, comprising a display panel and a driving chip, wherein the display panel comprises sub-pixels and data lines that are electrically connected, and the driving chip comprises a first pin;

[0012] a circuit board bound to the display assembly;

[0013] Wherein, the display component further includes a test switch, a first test pin and a second test pin, the first test pin is electrically connected to the first pin, and the test switch is electrically connected between the second test pin and the data line;

[0014] The circuit board comprises a first resistor, a third test pin and a fourth test pin, the third test pin is electrically connected to the first test pin, the fourth test pin is electrically connected to the second test pin, and the first resistor is electrically connected between the third test pin and the fourth test pin;

[0015] The bonding impedance detection method includes: during the detection process, controlling the test switch to be turned on, and controlling the first pin to output a high level, and judging whether the bonding impedance of the circuit board exceeds the specification according to the luminous state of the sub-pixel coupled to the test switch.

[0016] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the above-mentioned display module.

[0017] The technical solution provided by the embodiment of the present invention has the following beneficial effects:

[0018] Based on the above structure, after the circuit board is bound to the display component, whether the binding impedance of the circuit board exceeds the specification will be reflected in the binding impedance between the first test pin and the third test pin, and the binding impedance between the second test pin and the fourth test pin. When detecting the binding condition of the circuit board, the test switch is controlled to be turned on, and the first pin is controlled to output a high level. If the binding impedance between the first test pin and the third test pin, and the binding impedance between the second test pin and the fourth test pin exceed the specification, the binding impedance at the two binding positions is large, which will affect the voltage size finally transmitted to the data line connected to the test switch, such as causing the data line to transmit a low level or be in a floating state, thereby affecting the size of the data voltage written by the pixel circuit in the pixel column coupled to the test switch. Because the size of the data voltage written by the pixel circuit will affect the conduction state of the driving transistor, and thus affect the luminous brightness of the sub-pixel, therefore, it can be judged whether the binding impedance of the circuit board exceeds the specification according to the luminous condition of the pixel column coupled to the test switch.

[0019] This structure only needs to add a test screen at the electrical test site after the circuit board binding process. By checking whether the pixel columns coupled to the test switch in the display area emit light or not, the human eye can directly determine whether the binding impedance of the circuit board in the display module exceeds the specification. This can save the time of accurate alignment, testing, recording and then judging of the test equipment in the related technology, effectively reducing the manpower and equipment costs during the test, thereby greatly saving production costs and production time, and improving the detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 A structural schematic diagram of a display module in the related art;

[0022] Figure 2 for Figure 1 A structural schematic diagram of a corresponding display component and circuit board;

[0023] Figure 3 A schematic diagram of the structure of a display module provided by an embodiment of the present invention;

[0024] Figure 4 for Figure 3 A structural schematic diagram of a corresponding display component and circuit board;

[0025] Figure 5 A schematic diagram of a structure of a pixel circuit provided by an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of a detection circuit provided by an embodiment of the present invention;

[0027] Figure 7 A schematic diagram of the structure of a display component provided by an embodiment of the present invention;

[0028] Figure 8 Another schematic diagram of the structure of a display assembly provided by an embodiment of the present invention;

[0029] Fig. 9 Another structural schematic diagram of a display assembly provided by an embodiment of the present invention

[0030] Fig.10 for Figure 3 Another structural schematic diagram of the corresponding display assembly and circuit board;

[0031] Fig.11 A schematic diagram of the structure of a display device provided by an embodiment of the present invention;

[0032] Fig.12 Another schematic diagram of the structure of the display device provided by the embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0036] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0037] like Figure 1 and Figure 2 As shown, Figure 1 It is a structural schematic diagram of a display module in the related technology. Figure 2 for Figure 1 A structural schematic diagram of a corresponding display component and circuit board, the display module includes a display component 01 and a circuit board 02 bound to the display component 01, and the display component 01 includes a display panel 03 and a driving chip 04.

[0038] See also Figure 2 , the display component 01 further includes a first test pin 05 and a second test pin 06, and the circuit board 02 includes a third test pin 07 and a fourth test pin 08. After the circuit board 02 is bound to the display component 01, the third test pin 07 is electrically connected to the first test pin 05, and the fourth test pin 08 is electrically connected to the second test pin 06.

[0039] The first test pin 05 and the second test pin 06 are connected together, the third test pin 07 is led to the first test point 09 in the circuit board 02 , and the fourth test pin 08 is led to the second test point 010 in the circuit board 02 .

[0040] In the related art, when testing the binding condition of the circuit board 02, it is first necessary to import the bound display module into the test equipment, and make the test equipment accurately align with the first test point 09 and the second test point 010. Then, the test equipment is controlled to apply a detection voltage to the first test point 09, detect the voltage of the second test point 010 and record it, and by comparing the detected data with the target specification data, it is determined whether the binding impedance between the first test pin 05 and the third test pin 07 and between the second test pin 06 and the fourth test pin 08 exceeds the specification, and then it is known whether the binding impedance of the circuit board 02 exceeds the specification.

[0041] However, this detection method requires professional testing equipment and equipment operators, which increases production costs. In addition, the precise alignment of the testing equipment and the test points will increase the production time, resulting in low detection efficiency. If you want to improve efficiency and reduce costs, you can only use random inspections, but this will result in missed inspections, resulting in a greater risk of unqualified products flowing into subsequent processes.

[0042] In this regard, an embodiment of the present invention provides a display module. Based on the structure of the display module, the operation process and cost of display module binding detection can be greatly simplified, thereby effectively improving the detection efficiency.

[0043] like Figure 3 and Figure 4 As shown, Figure 3 A schematic diagram of the structure of a display module provided by an embodiment of the present invention, Figure 4 for Figure 3 A structural schematic diagram of a corresponding display component and circuit board, the display module includes a display component 1, and the display component 1 includes a display panel 2 and a driver chip 3. Among them, the display panel 2 can be a display panel 2 of various types such as an organic light emitting diode (OLED), a light emitting diode (LED), etc., for example, it can be an active-matrix organic light emitting diode (AMOLED) display panel 2. The display panel 2 includes electrically connected sub-pixels 4 and data lines Data. The driver chip 3 includes a first pin 5 for outputting a high level.

[0044] The display module further includes a circuit board 6, which is bound to the display assembly 1. The circuit board 6 can be a main flexible printed circuit (MFPC).

[0045] See also Figure 4The display component 1 further includes a test switch 7, a first test pin 8 and a second test pin 9, the first test pin 8 is electrically connected to the first pin 5, and the test switch 7 is electrically connected between the second test pin 9 and the data line Data.

[0046] The circuit board 6 includes a first resistor 10, a third test pin 11 and a fourth test pin 12. The third test pin 11 is electrically connected to the first test pin 8, the fourth test pin 12 is electrically connected to the second test pin 9, and the first resistor 10 is electrically connected between the third test pin 11 and the fourth test pin 12.

[0047] Based on the above structure, after the circuit board 6 is bound to the display component 1, whether the binding impedance of the circuit board 6 exceeds the specification will be reflected in the binding impedance between the first test pin 8 and the third test pin 11, and the binding impedance between the second test pin 9 and the fourth test pin 12. When the binding condition of the circuit board 6 is detected, the test switch 7 is controlled to be turned on, and the first pin 5 is controlled to output a high level. If the binding impedance between the first test pin 8 and the third test pin 11, and the binding impedance between the second test pin 9 and the fourth test pin 12 exceed the specification, the binding impedance at the two binding positions is very large, which will affect the voltage size finally transmitted to the data line Data connected to the test switch 7, for example, it will cause the data line Data to transmit a low level or be in a floating state, thereby affecting the size of the data voltage written by the pixel circuit in the pixel column coupled to the test switch 7. Because the size of the data voltage written by the pixel circuit will affect the conduction state of the driving transistor, and then affect the luminous brightness of the sub-pixel 4, therefore, it can be judged whether the binding impedance of the circuit board 6 exceeds the specification according to the luminous condition of the pixel column coupled to the test switch 7.

[0048] This structure only needs to add a test screen at the electrical detection site after the circuit board 6 binding process. The human eye can directly judge whether the binding impedance of the circuit board 6 in the display module exceeds the specification by the pixel column coupled to the test switch 7 in the display area emitting light or not. This can save the time of accurate positioning, testing, recording and then judging of the test equipment in the related technology, effectively reduce the manpower and equipment costs during the detection, and thus greatly save production costs and production time, and improve the detection efficiency.

[0049] Regarding the first resistor 10, the embodiment of the present invention may follow the following logic when designing the resistance value of the first resistor 10:

[0050] The sub-pixel 4 includes a pixel circuit 13 and a light-emitting element 14. Figure 5 As shown, Figure 5A structural schematic diagram of a pixel circuit provided in an embodiment of the present invention, the pixel circuit 13 includes a driving transistor M0, a gate reset transistor M1, a data writing transistor M2, a threshold compensation transistor M3, a first light-emitting control transistor M4, a second light-emitting control transistor M5, an anode reset transistor M6 and a storage capacitor Cst.

[0051] The gate of the gate reset transistor M1 is electrically connected to the first scan line Scan1 , the first electrode is electrically connected to the first reset line Ref1 , and the second electrode is electrically connected to the gate of the driving transistor M0 .

[0052] The data writing transistor M2 has a gate electrically connected to the second scan line Scan2 , a first electrode electrically connected to the data line Data, and a second electrode electrically connected to the first electrode of the driving transistor M0 .

[0053] The gate of the threshold compensation transistor M3 is electrically connected to the second scan line Scan2 , the first electrode is electrically connected to the second electrode of the driving transistor M0 , and the second electrode is electrically connected to the gate of the driving transistor M0 .

[0054] The first light emission control transistor M4 has a gate electrically connected to the light emission control line Emit, a first electrode electrically connected to the power line PVDD, and a second electrode electrically connected to the first electrode of the driving transistor M0 .

[0055] The second light emitting control transistor M5 has a gate electrically connected to the light emitting control line Emit, a first electrode electrically connected to the second electrode of the driving transistor M0 , and a second electrode electrically connected to the light emitting element 14 .

[0056] The anode reset transistor M6 has a gate electrically connected to the second scan line Scan2 , a first electrode electrically connected to the second reset line Ref2 , and a second electrode electrically connected to the light emitting element 14 .

[0057] A first plate of the storage capacitor Cst is electrically connected to the power line PVDD, and a second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor M0.

[0058] The first scan line Scan1, the second scan line Scan2, and the light emitting control line Emit can all be connected to the driving chip 3. When the circuit board 6 is subjected to binding detection, these signal lines can normally provide signals so that the pixel circuit can work normally.

[0059] According to the working principle of the pixel circuit, the magnitude of the data voltage written into the pixel circuit will affect the conduction degree of the driving transistor M0, thereby affecting the magnitude of the light-emitting current flowing into the light-emitting element 14, that is, affecting the light-emitting brightness of the light-emitting element 14.

[0060] The test switch 7 is a transistor. When designing the first resistor 10, Figure 6 As shown, Figure 6 A detection circuit diagram provided by an embodiment of the present invention, V = V1-V bonding1 -V R -V bonding2 -V sd Wherein, V1 is the high level voltage output by the first pin 5, V bonding1 is the binding voltage between the first test pin 8 and the third test pin 11 when the circuit board 6 is binding compliant, V bonding2 is the binding voltage between the second test pin 9 and the fourth test pin 12 when the circuit board 6 is binding compliant, V sd is the source-drain voltage when the test switch 7 is turned on.

[0061] Let V equal the threshold voltage V of the driving transistor M0 th , calculate V according to the formula R , and then the resistance value of the first resistor 10 is calculated according to the loop current.

[0062] After designing the first resistor 10 with this resistance value, if the bonding impedance of the circuit board 6 exceeds the specification, then V bonding1 and V bonding2 will become larger, resulting in the voltage V transmitted to the data line Data being smaller than V th After the voltage is written into the pixel circuit, the driving transistor M0 is turned on, thereby making the light-emitting element emit light. In this way, it is possible to determine whether the bonding impedance of the circuit board 6 exceeds the specification according to the light-emitting state of the pixel column coupled to the test switch 7.

[0063] In one possible implementation, see again Figure 3 and Figure 4 The display panel 2 has a first binding area 15 and a second binding area 16. The driving chip 3 is electrically connected to the first binding area 15, and the circuit board 6 is electrically connected to the second binding area 16.

[0064] The test switch 7 is located on the display panel 2 , and the first test pin 8 and the second test pin 9 are both located in the second binding area 16 .

[0065] In this structure, the driving chip 3 and the circuit board 6 are respectively bound to the display panel 2, that is, a COP (chip on Panel) and FOP (FPC on Panel) structure, and what is detected is the binding impedance between the COP and the FOP.

[0066] This structure will make it easier to connect the test switch 7 to the data line Data. For example, the test switch 7 can be located between the display area 17 and the first binding area 15. The first end of the test switch 7 is led downward to the second test pin 9 and connected to the second test pin 9, and the second end of the test switch 7 is led upward to the data line Data and connected to the data line Data.

[0067] In a possible implementation, Figure 7 to Figure 9 Show, Figure 7 A schematic diagram of the structure of a display assembly 1 provided in an embodiment of the present invention. Figure 8 Another structural schematic diagram of the display assembly 1 provided in an embodiment of the present invention is shown in FIG. Fig. 9 Another structural schematic diagram of the display assembly 1 provided in an embodiment of the present invention, the display panel 2 further includes a crack detection line 18 and a crack detection circuit 19. The crack detection line 18 can be arranged around the display area 17 at the periphery of the display area 17. The crack detection circuit 19 can be located between the display area 17 and the first binding area 15.

[0068] The crack detection circuit 19 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 and the gate of the second transistor T2 are both electrically connected to the first control line SW1, the first electrode of the first transistor T1 is electrically connected to the first constant voltage signal line VGH, the second electrode of the first transistor T1 is electrically connected to the data line Data, the first electrode of the second transistor T2 is electrically connected to the test line PCD-test, and the second electrode of the second transistor T2 is electrically connected to the data line Data. In addition, the data lines Data connected to the first transistor T1 and the second transistor T2 are different.

[0069] One end of the crack detection line 18 is electrically connected to the first constant voltage signal line VGH, and the other end of the crack detection line 18 is electrically connected to the test line PCD-test.

[0070] The test line PCD-test may also be electrically connected to the second test pin 9 , and the test switch 7 is a second transistor T2 .

[0071] When the motherboard is cut to form the display panel 2, cracks may be generated at the edge of the display panel 2, which may affect the internal structure of the display panel 2 and cause problems such as poor display. Therefore, after the display panel 2 and the driver chip 3 are bound to form the display component 1, the display panel 2 is generally first tested for cracks to prevent unqualified display components 1 from being subsequently bound to the circuit board 6, resulting in a waste of resources.

[0072] The above-mentioned crack detection line 18 and crack detection circuit 19 are structures for performing crack detection on the display panel 2. The related first control line SW1, first constant voltage signal line VGH and test line PCD-test are all electrically connected to the driver chip 3 (not shown in the figure). When crack detection is performed, the driver chip 3 outputs related signals.

[0073] During the crack detection process, the driver chip 3 outputs an enable level to the first control line SW1 (when the first transistor T1 and the second transistor T2 are P-type transistors, the enable level is low; when the first transistor T1 and the second transistor T2 are N-type transistors, the enable level is high) to control the first transistor T1 and the second transistor T2 to be turned on, and the driver chip 3 outputs a high level to the first constant voltage signal line VGH. If there is no crack, the crack detection line 18 is in good condition, and the high level in the first constant voltage signal line VGH can be transmitted to the test line PCD-test via the crack detection line 18, and then transmitted to the data line Data connected to the second transistor T2, so that the pixel circuit connected to this part of the data line Data is written with a high level, and the driving transistor is controlled to be cut off, so that the pixel column corresponding to this part of the data line Data does not emit light. If it is detected that the pixel column corresponding to this part of the data line Data emits light, it means that the crack detection line 18 has been broken to a certain extent, and the display panel 2 has cracks.

[0074] In the embodiment of the present invention, based on the original crack detection circuit 19, the connection method of the test line PCD-test is further adjusted so that the test line PCD-test is also connected to the second test pin 9. Figure 4 , and then the circuit board 6 is subsequently bound, so that the second test pin 9 is electrically connected to the fourth test pin 12, a signal transmission path is established between the circuit board 6 and the test line PCD-test. Then, when the binding condition of the circuit board 6 is detected, the first control line SW1 outputs an enable level to control the second transistor T2 to be turned on, so that the binding impedance of the circuit board 6 can be judged whether it is compliant according to the light-emitting state of the pixel column coupled to the second transistor T2.

[0075] This setting method can further reuse the second transistor T2 originally used for crack detection as a test switch 7, without adding other transistor structures for binding detection, simplifying the structural design of the panel. In addition, the crack detection is performed before the circuit board 6 is bound, which means that the first test pin 8 is in a floating state during crack detection. Therefore, even if the test line PCD-test is connected to the first test pin 8, the first test pin 8 will not output a signal to it during crack detection, so it will not affect the crack detection process.

[0076] Further, see again Fig. 9, the first constant voltage signal line VGH is also electrically connected to the first pin 5 .

[0077] When detecting the binding status of the circuit board 6, the first control line SW1 needs to be controlled to output an enable level, and the corresponding first transistor T1 will also be turned on. The first constant voltage signal line VGH is also electrically connected to the first pin 5. When the first pin 5 outputs a high level, the high level can be written into the pixel circuit coupled to the first transistor T1, thereby controlling the pixel column coupled to the first transistor T1 not to emit light, thereby avoiding interference with the detection of the light-emitting state of the pixel column coupled to the second transistor T2.

[0078] In one possible implementation, see again Fig. 9 , the sub-pixel 4 includes a first sub-pixel 4-1, a second sub-pixel 4-2 and a third sub-pixel 4-3. Exemplarily, the first sub-pixel 4-1 is a red sub-pixel, the second sub-pixel 4-2 is a green sub-pixel, and the third sub-pixel 4-3 is a blue sub-pixel. For ease of understanding, Fig. 9 In the figure, R is marked in the first sub-pixel 4-1, G is marked in the second sub-pixel 4-2, and B is marked in the third sub-pixel 4-3.

[0079] The data lines Data include a first data line Data1, and the first data line Data1 is electrically connected to the second sub-pixel 4-2. The first transistor T1 and the second transistor T2 are electrically connected to the first data line Data1, respectively.

[0080] That is to say, the embodiment of the present invention uses the luminous state of the green pixel column to judge the crack condition and the binding condition of the circuit board 6. The luminous brightness of the green sub-pixel is higher and easier to be recognized by the human eye. Therefore, by using the green pixel column to perform the above two tests, the human eye can more intuitively and clearly identify the luminous state of this part of the pixel column.

[0081] Furthermore, at least two first data lines Data1 electrically connected to the second transistor T2 are not separated by the first data line Data1 electrically connected to the first transistor T1. That is, at least two green pixel columns coupled to the second transistor T2 are adjacent to each other and are not separated by the green pixel column coupled to the first transistor T1. It is easier to identify whether the green pixel column coupled to the second transistor T2 emits light or not, and the detection result can be judged more accurately.

[0082] In one possible implementation, see again Fig. 9 , the sub-pixel 4 includes a first sub-pixel 4-1, a second sub-pixel 4-2 and a third sub-pixel 4-3.

[0083] The data lines Data include a first data line Data1, and the first data line Data1 is electrically connected to the second sub-pixel 4-2. The first transistor T1 and the second transistor T2 are electrically connected to the first data line Data1, respectively.

[0084] The display panel 2 also includes a dot screen test circuit 20. The dot screen test circuit 20 includes a plurality of third transistors T3, the gates of the plurality of third transistors T3 are electrically connected to the second control line SW2, the first electrodes of the plurality of third transistors T3 are electrically connected to the first source signal line GL, and the second electrodes of the plurality of third transistors T3 are electrically connected to different first data lines Data1, respectively.

[0085] The third transistor T3 includes a first type third transistor T31 and a second type third transistor T32. The first type third transistor T31 and the first transistor T1 are electrically connected to the same first data line Data1. The second type third transistor T32 and the second transistor T2 are electrically connected to the same first data line Data1.

[0086] The second control line SW2 and the first source signal line GL are both electrically connected to the driving chip 3 (not shown in the figure). When the dot screen test is performed, the driving chip 3 outputs relevant signals.

[0087] After the display panel 2 and the driver chip 3 are bound to form the display component 1, a dot screen test is generally performed on the display panel 2 to detect whether the sub-pixels 4 in the display panel 2 can emit light normally, so as to prevent unqualified display components 1 from being subsequently bound to the circuit board 6, causing a waste of resources.

[0088] In one test method, the process of the dot screen test may include forming a green test screen. During the test process, the first source signal line GL provides a first test signal, the second control line SW2 provides an enable level, and the first test signal is written into the pixel circuit of the second sub-pixel 4-2 via the turned-on third transistor T3, and then the green sub-pixel is tested to see whether it can emit light normally according to the displayed test screen.

[0089] In one structure, each first data line Data1 is electrically connected to a third transistor T3, wherein part of the first data line Data1 is also electrically connected to the first transistor T1, and the remaining part of the first data line Data1 is also electrically connected to the second transistor T2, so that each green pixel column can be detected during the dot screen test.

[0090] Furthermore, when performing the bonding test on the circuit board 6, the second control line SW2 may be controlled to provide a non-enable level, thereby controlling the third transistor T3 to be turned off to prevent the first source signal line GL from writing a voltage to the first data line Data1 to interfere with the detection of the bonding impedance.

[0091] Further, see again Fig. 9 The data line Data further includes a second data line Data2 and a third data line Data3, the second data line Data2 is electrically connected to the first sub-pixel 4-1 and the third sub-pixel 4-3, and the third data line Data3 is electrically connected to the first sub-pixel 4-1 and the third sub-pixel 4-3. The first sub-pixel 4-1 connected to the second data line Data2 and the third sub-pixel 4-3 connected to the third data line Data3 are arranged along a first direction, and the first direction intersects with the extension direction of the data line Data.

[0092] That is, the second data line Data2 and the third data line Data3 are electrically connected to the red and blue pixel columns respectively, and the first sub-pixel 4-1 in the red and blue pixel column connected to the second data line Data2 and the third sub-pixel 4-3 in the red and blue pixel column connected to the third data line Data3 are aligned.

[0093] The dot screen test circuit 20 also includes a first gating module 21. The first gating module 21 includes a fourth transistor T4 and a fifth transistor T5, the gate of the fourth transistor T4 is electrically connected to the third control line SW3, the gate of the fifth transistor T5 is electrically connected to the fourth control line SW4, the first electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5 are both electrically connected to the second source signal line RL, the second electrode of the fourth transistor T4 is electrically connected to the second data line Data2, and the second electrode of the fifth transistor T5 is electrically connected to the third data line Data3.

[0094] The dot screen test circuit 20 also includes a second gating module 22. The second gating module 22 includes a sixth transistor T6 and a seventh transistor T7, the gate of the sixth transistor T6 is electrically connected to the third control line SW3, the gate of the seventh transistor T7 is electrically connected to the fourth control line SW4, the first electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 are both electrically connected to the third source signal line BL, the second electrode of the sixth transistor T6 is electrically connected to the third data line Data3, and the second electrode of the seventh transistor T7 is electrically connected to the second data line Data2.

[0095] The second source signal line RL and the third source signal line BL are also electrically connected to the first pin 5 .

[0096] Among them, the third control line SW3, the fourth control line SW4, the second source signal line RL and the third source signal line BL are all electrically connected to the driving chip 3 (not shown in the figure), and when performing the dot screen test, the driving chip 3 outputs relevant signals.

[0097] The dot screen test process may also include forming a red detection screen. During the detection process, the second source signal line RL is controlled to output a second test signal. When the odd pixel rows are turned on, the third control line SW3 provides an enable level, and the second test signal is written into the first sub-pixel 4-1 in the odd pixel rows via the turned-on fourth transistor T4. When the even pixel rows are turned on, the fourth control line SW4 provides an enable level, and the second test signal is written into the first sub-pixel 4-1 in the even pixel rows via the turned-on fifth transistor T5, and then the red sub-pixel is detected according to the displayed detection screen to see whether it can emit light normally.

[0098] The dot screen test process may also include forming a blue detection screen. During the detection process, the third source signal line BL is controlled to output a third test signal. When the odd pixel row is turned on, the third control line SW3 provides an enable level, and the third test signal is written into the third sub-pixel 4-3 in the odd pixel row via the turned-on sixth transistor T6. When the even pixel row is turned on, the fourth control line SW4 provides an enable level, and the third test signal is written into the third sub-pixel 4-3 in the even pixel row via the turned-on seventh transistor T7, and then the blue sub-pixel is detected according to the displayed detection screen. Whether it can emit light normally.

[0099] The above structure is equivalent to integrating the dot screen test circuit 20, the crack detection circuit 19 and the test switch 7 to form a shorting bar circuit structure.

[0100] In the embodiment of the present invention, the second source signal line RL and the third source signal line BL are also electrically connected to the first pin 5. When the binding condition of the circuit board 6 is detected, the third control line SW3 and the fourth control line SW4 can be controlled to output an enable level to control the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to be turned on. At this time, the high level output by the first pin 5 can be written into the first sub-pixel 4-1 and the third sub-pixel 4-3, thereby controlling the first sub-pixel 4-1 and the third sub-pixel 4-3 not to emit light, avoiding interference with the judgment of the light-emitting state of the second sub-pixel 4-2 coupled to the second transistor T2 (test switch 7).

[0101] In the embodiment of the present invention, Fig.10 As shown, Fig.10 for Figure 3 Another structural schematic diagram of the corresponding display assembly and circuit board, the display panel 2 includes a test unit 24, and the test unit 24 includes a first test pin 8, a second test pin 9, a third test pin 11, a fourth test pin 12 and a first resistor 10. One test unit 24 can be set in the display panel 2, or at least two test units 24 can be set, so that the bonding impedance of the circuit board 6 can be more accurately detected by using multiple test units 24.

[0102] In a feasible implementation, the sub-pixel 4 connected to the data line Data corresponding to the test switch 7 emits green light. For example, in the above structure, the test switch 7 (the second transistor T2) is electrically connected to the first data line Data1, and the first data line Data1 is only electrically connected to the second sub-pixel 4-2 (green sub-pixel).

[0103] The green sub-pixel has a higher luminance and is easier for the human eye to recognize. Therefore, the green pixel column is used for the above two tests, and the human eye can more intuitively and clearly identify the luminous state of this part of the pixel column.

[0104] Based on the same inventive concept, the embodiment of the present invention also provides a method for detecting the binding impedance of a display module. Figure 3 and Figure 4 The display module used in the detection method includes a display component 1 and a circuit board 6 bound to the display component 1.

[0105] The display assembly 1 includes a display panel 2 and a driving chip 3. The display panel 2 includes sub-pixels 4 and data lines Data that are electrically connected. The driving chip 3 includes a first pin 5 for outputting a high level.

[0106] The display assembly 1 further includes a test switch 7, a first test pin 8 and a second test pin 9, the first test pin 8 is electrically connected to the first pin 5, and the test switch 7 is electrically connected between the second test pin 9 and the data line Data. The circuit board 6 includes a first resistor 10, a third test pin 11 and a fourth test pin 12, the third test pin 11 is electrically connected to the first test pin 8, the fourth test pin 12 is electrically connected to the second test pin 9, and the first resistor 10 is electrically connected between the third test pin 11 and the fourth test pin 12.

[0107] The bonding impedance detection method includes: during the detection process, controlling the test switch 7 to be turned on, and controlling the first pin 5 to output a high level, and judging whether the bonding impedance of the circuit board 6 exceeds the specification according to the luminous state of the sub-pixel 4 coupled to the test switch 7.

[0108] When the binding condition of the circuit board 6 is detected, the test switch 7 is controlled to be turned on, and the first pin 5 is controlled to output a high level. If the binding impedance between the first test pin 8 and the third test pin 11, and the binding impedance between the second test pin 9 and the fourth test pin 12 exceed the specification, the binding impedance at the two binding positions is very large, which will affect the voltage size finally transmitted to the data line Data connected to the test switch 7, for example, it will cause the data line Data to transmit a low level or be in a floating state, thereby affecting the size of the data voltage written by the pixel circuit in the pixel column coupled to the test switch 7. Because the size of the data voltage written by the pixel circuit will affect the conduction state of the driving transistor, and thus affect the luminous brightness of the sub-pixel 4, therefore, it can be judged whether the binding impedance of the circuit board 6 exceeds the specification according to the luminous condition of the pixel column coupled to the test switch 7.

[0109] This detection method only needs to add a detection screen at the electrical detection site after the circuit board 6 binding process. The human eye can directly judge whether the binding impedance of the circuit board 6 in the display module exceeds the specification by the pixel column coupled to the test switch 7 in the display area 17 emitting light or not. Compared with the detection method in the related art, it greatly saves production cost and production time and improves detection efficiency.

[0110] In one possible implementation, see Figure 7 to Figure 9 The display panel 2 also includes a crack detection line 18 and a crack detection circuit 19 .

[0111] The crack detection circuit 19 includes a first transistor T1 and a second transistor T2, the gate of the first transistor T1 and the gate of the second transistor T2 are both electrically connected to the first control line SW1, the first electrode of the first transistor T1 is electrically connected to the first constant voltage signal line VGH, the second electrode of the first transistor T1 is electrically connected to the data line Data, the first electrode of the second transistor T2 is electrically connected to the test line PCD-test, and the second electrode of the second transistor T2 is electrically connected to the data line Data; the data lines Data connected to the first transistor T1 and the second transistor T2 are different.

[0112] One end of the crack detection line 18 is electrically connected to the first constant voltage signal line VGH, and the other end of the crack detection line 18 is electrically connected to the test line PCD-test.

[0113] The test line PCD-test is also electrically connected to the second test pin 9, and the test switch 7 is a second transistor T2. During the detection process, the first control line SW1 is controlled to provide an enable level.

[0114] The embodiment of the present invention is based on the original crack detection circuit 19, and further adjusts the connection method of the test line PCD-test so that the test line PCD-test is also connected to the second test pin 9. Figure 4 , and then the circuit board 6 is subsequently bound, so that the second test pin 9 is electrically connected to the fourth test pin 12, a signal transmission path is established between the circuit board 6 and the test line PCD-test. Then, when the binding condition of the circuit board 6 is detected, the first control line SW1 outputs an enable level to control the second transistor T2 to be turned on, so that the binding impedance of the circuit board 6 can be judged whether it is compliant according to the light-emitting state of the pixel column coupled to the second transistor T2.

[0115] This configuration can further reuse the second transistor T2 originally used for crack detection as the test switch 7, eliminating the need to add other transistor structures for binding detection, thereby simplifying the structural design of the panel.

[0116] In one possible implementation, see Fig. 9 The sub-pixel 4 includes a first sub-pixel 4-1, a second sub-pixel 4-2 and a third sub-pixel 4-3. Exemplarily, the first sub-pixel 4-1 is a red sub-pixel, the second sub-pixel 4-2 is a green sub-pixel, and the third sub-pixel 4-3 is a blue sub-pixel.

[0117] The data lines Data include a first data line Data1 , which is electrically connected to the second sub-pixel 4 - 2 ; and the first transistor T1 and the second transistor T2 are electrically connected to the first data line Data1 , respectively.

[0118] The display panel 2 also includes a dot screen test circuit 20, which includes multiple third transistors T3, the gates of the multiple third transistors T3 are all electrically connected to the second control line SW2, the first electrodes of the multiple third transistors T3 are all electrically connected to the first source signal line GL, and the second electrodes of the multiple third transistors T3 are respectively electrically connected to different first data lines Data1.

[0119] The third transistor T3 includes a first type third transistor T31 and a second type third transistor T32. The first type third transistor T31 and the first transistor T1 are electrically connected to the same first data line Data1. The second type third transistor T32 and the second transistor T2 are electrically connected to the same first data line Data1.

[0120] During the detection process, the second control line SW2 is controlled to provide a non-enable level, thereby controlling the third transistor T3 to be turned off, to prevent the first source signal line GL from writing a voltage to the first data line Data1 to interfere with the detection of the bonding impedance.

[0121] In one possible implementation, see Fig. 9The data line Data further includes a second data line Data2 and a third data line Data3, the second data line Data2 is electrically connected to the first sub-pixel 4-1 and the third sub-pixel 4-3, and the third data line Data3 is electrically connected to the first sub-pixel 4-1 and the third sub-pixel 4-3. The first sub-pixel 4-1 connected to the second data line Data2 and the third sub-pixel 4-3 connected to the third data line Data3 are arranged along a first direction, and the first direction intersects with the extension direction of the data line Data.

[0122] The dot screen test circuit 20 also includes a first gating module 21. The first gating module 21 includes a fourth transistor T4 and a fifth transistor T5, the gate of the fourth transistor T4 is electrically connected to the third control line SW3, the gate of the fifth transistor T5 is electrically connected to the fourth control line SW4, the first electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5 are both electrically connected to the second source signal line RL, the second electrode of the fourth transistor T4 is electrically connected to the second data line Data2, and the second electrode of the fifth transistor T5 is electrically connected to the third data line Data3.

[0123] The dot screen test circuit 20 also includes a second gating module 22. The second gating module 22 includes a sixth transistor T6 and a seventh transistor T7, the gate of the sixth transistor T6 is electrically connected to the third control line SW3, the gate of the seventh transistor T7 is electrically connected to the fourth control line SW4, the first electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 are both electrically connected to the third source signal line BL, the second electrode of the sixth transistor T6 is electrically connected to the third data line Data3, and the second electrode of the seventh transistor T7 is electrically connected to the second data line Data2.

[0124] The second source signal line RL and the third source signal line BL are also electrically connected to the first pin 5. During the binding impedance detection process, the third control line SW3 and the fourth control line SW4 are controlled to provide an enable level, thereby controlling the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 to be turned on. At this time, the high level output by the first pin 5 can be written into the first sub-pixel 4-1 and the third sub-pixel 4-3, thereby controlling the first sub-pixel 4-1 and the third sub-pixel 4-3 not to emit light, thereby avoiding interference with the judgment of the light-emitting state of the second sub-pixel 4-2 coupled to the second transistor T2 (test switch 7).

[0125] In one possible implementation, see Fig. 9 The driving chip 3 includes a second pin 23, which is electrically connected to the data line Data and is used to output a data voltage to the data line Data when the display panel 2 is displaying.

[0126] During the detection process, the second pin 23 is also controlled to be in a high impedance state (HIZ) to prevent the driver chip 3 from outputting an interference signal to the data line Data and affecting the normal detection of the bonding impedance.

[0127] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.11 and Fig.12 As shown, Fig.11 A schematic diagram of the structure of a display device provided by an embodiment of the present invention is shown in FIG. Fig.12 Another structural diagram of a display device provided by an embodiment of the present invention is shown, and the display device includes the above-mentioned display module 100. Of course, Fig.11 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0128] In one structure, see Fig.12 The display panel 2 includes a planar portion and a bent portion, the bent portion is bent to the backlight side of the planar portion, the driving chip 3 is bound to the bent portion of the display panel 2, and the circuit board 6 is bound to the bent portion of the display panel 2.

[0129] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display module, characterized in that: include: A display component, comprising a display panel and a driving chip, wherein the display panel comprises sub-pixels and data lines that are electrically connected, and the driving chip comprises a first pin for outputting a high level; a circuit board bound to the display assembly; Wherein, the display component further includes a test switch, a first test pin and a second test pin, the first test pin is electrically connected to the first pin, and the test switch is electrically connected between the second test pin and the data line; The circuit board includes a first resistor, a third test pin and a fourth test pin, the third test pin is electrically connected to the first test pin, the fourth test pin is electrically connected to the second test pin, and the first resistor is electrically connected between the third test pin and the fourth test pin.

2. The display module according to claim 1, characterized in that: The display panel has a first binding area and a second binding area, the driving chip is electrically connected to the first binding area, and the circuit board is electrically connected to the second binding area; Wherein, the test switch is located on the display panel, and the first test pin and the second test pin are located in the second binding area.

3. The display module according to claim 1, characterized in that: The display panel also includes a crack detection line and a crack detection circuit; The crack detection circuit comprises a first transistor and a second transistor, wherein the gate of the first transistor and the gate of the second transistor are both electrically connected to a first control line, a first electrode of the first transistor is electrically connected to a first constant voltage signal line, a second electrode of the first transistor is electrically connected to the data line, a first electrode of the second transistor is electrically connected to a test line, a second electrode of the second transistor is electrically connected to the data line, and the first transistor and the second transistor are connected to different data lines; One end of the crack detection line is electrically connected to the first constant voltage signal line, and the other end of the crack detection line is electrically connected to the test line; The test line is also electrically connected to the second test pin, and the test switch is the second transistor.

4. The display module according to claim 3, characterized in that: The first constant voltage signal line is also electrically connected to the first pin.

5. The display module according to claim 3, characterized in that: The sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel; The data line comprises a first data line, the first data line is electrically connected to the second sub-pixel, and the first transistor and the second transistor are electrically connected to the first data line respectively; Among them, there is no first data line electrically connected to the first transistor between at least two of the first data lines electrically connected to the second transistor.

6. The display module according to claim 3, characterized in that: The sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel; The data line comprises a first data line, the first data line is electrically connected to the second sub-pixel; the first transistor and the second transistor are electrically connected to the first data line respectively; The display panel further includes a dot screen test circuit, the dot screen test circuit includes a plurality of third transistors, the gates of the plurality of third transistors are electrically connected to the second control line, the first electrodes of the plurality of third transistors are electrically connected to the first source signal line, and the second electrodes of the plurality of third transistors are electrically connected to different first data lines respectively; The third transistor includes a first type third transistor and a second type third transistor, the first type third transistor and the first transistor are electrically connected to the same first data line, and the second type third transistor and the second transistor are electrically connected to the same first data line.

7. The display module according to claim 6, characterized in that: The data lines further include a second data line and a third data line, the second data line is electrically connected to the first sub-pixel and the third sub-pixel, the third data line is electrically connected to the first sub-pixel and the third sub-pixel, wherein the first sub-pixel connected to the second data line and the third sub-pixel connected to the third data line are arranged along a first direction, and the first direction intersects with an extension direction of the data lines; The point screen test circuit also includes: a first gating module, comprising a fourth transistor and a fifth transistor, wherein a gate of the fourth transistor is electrically connected to a third control line, a gate of the fifth transistor is electrically connected to a fourth control line, a first electrode of the fourth transistor and a first electrode of the fifth transistor are both electrically connected to a second source signal line, a second electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fifth transistor is electrically connected to the third data line; a second gating module, comprising a sixth transistor and a seventh transistor, wherein a gate of the sixth transistor is electrically connected to the third control line, a gate of the seventh transistor is electrically connected to the fourth control line, a first electrode of the sixth transistor and a first electrode of the seventh transistor are both electrically connected to a third source signal line, a second electrode of the sixth transistor is electrically connected to the third data line, and a second electrode of the seventh transistor is electrically connected to the second data line; The second source signal line and the third source signal line are also electrically connected to the first pin.

8. The display module according to claim 1, characterized in that: The sub-pixel connected to the data line corresponding to the test switch emits green light.

9. A method for detecting the binding impedance of a display module, characterized in that: The display module comprises: A display component, comprising a display panel and a driving chip, wherein the display panel comprises sub-pixels and data lines that are electrically connected, and the driving chip comprises a first pin; a circuit board bound to the display assembly; Wherein, the display component further includes a test switch, a first test pin and a second test pin, the first test pin is electrically connected to the first pin, and the test switch is electrically connected between the second test pin and the data line; The circuit board comprises a first resistor, a third test pin and a fourth test pin, the third test pin is electrically connected to the first test pin, the fourth test pin is electrically connected to the second test pin, and the first resistor is electrically connected between the third test pin and the fourth test pin; The bonding impedance detection method includes: during the detection process, controlling the test switch to be turned on, and controlling the first pin to output a high level, and judging whether the bonding impedance of the circuit board exceeds the specification according to the luminous state of the sub-pixel coupled to the test switch.

10. The bonding impedance detection method according to claim 9, characterized in that: The display panel also includes a crack detection line and a crack detection circuit; The crack detection circuit comprises a first transistor and a second transistor, wherein the gate of the first transistor and the gate of the second transistor are both electrically connected to a first control line, a first electrode of the first transistor is electrically connected to a first constant voltage signal line, a second electrode of the first transistor is electrically connected to the data line, a first electrode of the second transistor is electrically connected to a test line, and a second electrode of the second transistor is electrically connected to the data line; the first transistor and the second transistor are connected to different data lines; One end of the crack detection line is electrically connected to the first constant voltage signal line, and the other end of the crack detection line is electrically connected to the test line; Wherein, the test line is also electrically connected to the second test pin, and the test switch is the second transistor; During the detection process, the first control line is controlled to provide an enable level.

11. The bonding impedance detection method according to claim 10, characterized in that: The sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel; The data line comprises a first data line, the first data line is electrically connected to the second sub-pixel; the first transistor and the second transistor are electrically connected to the first data line respectively; The display panel further includes a dot screen test circuit, the dot screen test circuit includes a plurality of third transistors, the gates of the plurality of third transistors are electrically connected to the second control line, the first electrodes of the plurality of third transistors are electrically connected to the first source signal line, and the second electrodes of the plurality of third transistors are electrically connected to different first data lines respectively; The third transistor includes a first-type third transistor and a second-type third transistor, the first-type third transistor and the first transistor are electrically connected to the same first data line, and the second-type third transistor and the second transistor are electrically connected to the same first data line; During the detection process, the second control line is controlled to provide a non-enable level.

12. The bonding impedance detection method according to claim 11, characterized in that: The data lines further include a second data line and a third data line, the second data line is electrically connected to the first sub-pixel and the third sub-pixel, the third data line is electrically connected to the first sub-pixel and the third sub-pixel, wherein the first sub-pixel connected to the second data line and the third sub-pixel connected to the third data line are arranged along a first direction, and the first direction intersects with an extension direction of the data lines; The point screen test circuit also includes: a first gating module, comprising a fourth transistor and a fifth transistor, wherein a gate of the fourth transistor is electrically connected to a third control line, a gate of the fifth transistor is electrically connected to a fourth control line, a first electrode of the fourth transistor and a first electrode of the fifth transistor are both electrically connected to a second source signal line, a second electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fifth transistor is electrically connected to the third data line; a second gating module, comprising a sixth transistor and a seventh transistor, wherein a gate of the sixth transistor is electrically connected to the third control line, a gate of the seventh transistor is electrically connected to the fourth control line, a first electrode of the sixth transistor and a first electrode of the seventh transistor are both electrically connected to a third source signal line, a second electrode of the sixth transistor is electrically connected to the third data line, and a second electrode of the seventh transistor is electrically connected to the second data line; Wherein, the second source signal line and the third source signal line are also electrically connected to the first pin; During the bonding impedance detection process, the third control line and the fourth control line are controlled to provide an enable level.

13. The bonding impedance detection method according to claim 10, characterized in that: The driving chip comprises a second pin, and the second pin is electrically connected to the data line; During the detection process, the second pin is also controlled to be in a high impedance state.

14. A display device, characterized in that: It comprises the display module as claimed in any one of claims 1 to 9.

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