Gate drive circuit and display panel

Abstract

The invention provides a gate drive circuit and a display panel. The gate drive circuit comprises a signal input module, a first control module, a secondary low potential blocking module, a second control module and a signal output module. Wherein the first control module is used for controlling the potential of the first node, the second control module is used for controlling the potential of the third node, and the signal output module controls the potential of the signal output end of the level under the control of the potential of the second node and the potential of the third node. According to the gate drive circuit and the display panel provided by the invention, transistor threshold voltage in the gate drive circuit is eliminated, the size of an output step is dynamically adjusted, and the service life performance and uniformity of the display panel are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Art

[0002] Gate Driver On Array (GOA) is a technology that integrates the gate driver circuit on the array substrate of the display panel to achieve line-by-line scanning drive. Figure 1 As shown, the threshold voltage (Vth) of the P-type transistor in the gate drive circuit will shift due to factors such as temperature changes, process differences, and aging of the transistor, which will cause the falling edge step of the drive signal output by the gate drive circuit to change due to the offset of the threshold voltage, affecting the output stability of the gate drive circuit. Summary of the invention

[0003] Embodiments of the present application provide a gate driving circuit and a display panel to solve the problem of poor output stability of the gate driving circuit in the related art.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] In a first aspect, the present application provides a gate driving circuit, comprising a plurality of gate driving units arranged in cascade, wherein the gate driving unit comprises:

[0006] A signal input module is used to receive the output signal of the previous level;

[0007] a first control module, electrically connected to the signal input module and to the first node, the first control module being used to control the potential of the first node;

[0008] A sub-low potential blocking module, electrically connected to the first node and to the second node, the low potential blocking module being used to block the sub-low voltage of the first node from passing through;

[0009] a second control module, electrically connected to the third node and to the first control module, the second control module being used to control the potential of the third node;

[0010] A signal output module is electrically connected to the signal output terminal of this stage and to the second node and the third node. The signal output module is used to control the potential of the signal output terminal of this stage under the control of the potential of the second node and the potential of the third node.

[0011] In one embodiment, the signal input module includes:

[0012] A first transistor, wherein a gate of the first transistor is connected to a first clock signal, a source of the first transistor is connected to the previous stage output signal, and a drain of the first transistor is electrically connected to the first control module.

[0013] In one embodiment, the first control module includes:

[0014] a second transistor, wherein a gate of the second transistor is connected to a constant low potential signal, a source of the second transistor is electrically connected to a drain of the first transistor, and a drain of the second transistor is electrically connected to the first node;

[0015] a third transistor, wherein a gate of the third transistor is connected to the first node, and a source of the third transistor is connected to a second clock signal;

[0016] a fourth transistor, wherein a gate of the fourth transistor is connected to the second control module, a source of the fourth transistor is connected to a constant high potential signal, and a drain of the fourth transistor is electrically connected to a drain of the third transistor;

[0017] a first capacitor, wherein a first end of the first capacitor is electrically connected to the gate of the third transistor, and a second end of the first capacitor is electrically connected to the drain of the third transistor; and

[0018] A fifth transistor, wherein a gate of the fifth transistor is connected to a reset control signal, a source of the fifth transistor is connected to the constant high potential signal, and a drain of the fifth transistor is electrically connected to a drain of the first transistor.

[0019] In one embodiment, the sub-low potential blocking module includes:

[0020] A sixth transistor, wherein a gate of the sixth transistor is electrically connected to a drain of the first transistor, a source of the sixth transistor is electrically connected to the first node, and a drain of the sixth transistor is electrically connected to the second node.

[0021] In one embodiment, the sub-low potential blocking module includes:

[0022] A sixth transistor, wherein a gate of the sixth transistor is connected to the constant high potential signal, a source of the sixth transistor is electrically connected to the first node, and a drain of the sixth transistor is electrically connected to the second node.

[0023] In one embodiment, the sub-low potential blocking module further includes:

[0024] A second capacitor, wherein a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is connected to the constant high potential signal.

[0025] In one embodiment, the sub-low potential blocking module further includes:

[0026] A seventh transistor, wherein a gate of the seventh transistor is electrically connected to the first node, a source of the seventh transistor is connected to the constant high potential signal, and a drain of the seventh transistor is electrically connected to the second node.

[0027] In one embodiment, the seventh transistor is an N-type transistor.

[0028] In one embodiment, the sixth transistor is an N-type transistor.

[0029] In one embodiment, the second control module includes:

[0030] an eighth transistor, wherein a gate of the eighth transistor is connected to the first clock signal, a source of the eighth transistor is connected to the constant low potential signal, and a drain of the eighth transistor is electrically connected to the gate of the fourth transistor;

[0031] a ninth transistor, wherein a gate of the ninth transistor is connected to the constant low potential signal, and a source of the ninth transistor is electrically connected to a drain of the eighth transistor;

[0032] a tenth transistor, wherein a gate of the tenth transistor is electrically connected to a drain of the ninth transistor, and a source of the tenth transistor is connected to the second clock signal;

[0033] an eleventh transistor, a gate of the eleventh transistor being connected to the second clock signal, a source of the eleventh transistor being electrically connected to a drain of the tenth transistor, and a drain of the eleventh transistor being electrically connected to the third node;

[0034] a twelfth transistor, wherein a gate of the twelfth transistor is electrically connected to a drain of the first transistor, a source of the twelfth transistor is connected to the first clock signal, and a drain of the twelfth transistor is electrically connected to a drain of the eighth transistor;

[0035] a thirteenth transistor, wherein a gate of the thirteenth transistor is electrically connected to a source of the second transistor, a source of the thirteenth transistor is connected to the constant high potential signal, and a drain of the thirteenth transistor is electrically connected to the third node; and

[0036] A third capacitor, wherein a first end of the third capacitor is electrically connected to the gate of the tenth transistor, and a second end of the third capacitor is electrically connected to the drain of the tenth transistor.

[0037] In one embodiment, the signal output module includes:

[0038] a fourteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to the second node, a source of the fourteenth transistor is connected to the constant low potential signal, and a drain of the fourteenth transistor is electrically connected to the current-stage signal output terminal;

[0039] a fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to the third node, a source of the fifteenth transistor is connected to the constant high potential signal, and a drain of the fifteenth transistor is electrically connected to the current-stage signal output terminal; and

[0040] A fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to the third node, and a second end of the fourth capacitor is electrically connected to the source of the fifteenth transistor.

[0041] In one embodiment, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are all P-type transistors.

[0042] In one embodiment, the first clock signal and the second clock signal are signals with the same period and opposite phases.

[0043] In a second aspect, the present application provides a display panel comprising the aforementioned gate driving circuit.

[0044] The embodiment of the present application provides a gate drive circuit and a display panel, wherein the gate drive circuit includes a signal input module, a first control module, a sub-low potential blocking module, a second control module, and a signal output module. The first control module is used to control the potential of the first node, the second control module is used to control the potential of the third node, and the signal output module controls the potential of the signal output terminal of this level under the control of the potentials of the second node and the third node. The present application sets a sub-low potential blocking module to block the sub-low voltage of the first node from passing through, thereby eliminating the transistor threshold voltage in the gate drive circuit, dynamically adjusting the output step size, and improving the life performance and uniformity of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0046] Attached Figure 1 Schematic diagram of the output steps of the gate driving circuit in the embodiment of the present application;

[0047] Attached Figure 2 This is a schematic diagram of a module of an optional gate driving unit in an embodiment of the present application;

[0048] Attached Figure 3 This is a circuit diagram of an optional gate driving unit in an embodiment of the present application;

[0049] Attached Figure 4 A circuit diagram of another optional gate driving unit in an embodiment of the present application;

[0050] Attached Figure 5 A circuit diagram of another optional gate driving unit in an embodiment of the present application;

[0051] Attached Figure 6 A circuit diagram of another optional gate driving unit in an embodiment of the present application;

[0052] Attached Figure 7 This is a working timing diagram of the gate driving unit in the embodiment of the present application;

[0053] Attached Figure 8 Another working timing diagram of the gate driving unit in the embodiment of the present application;

[0054] Attached Fig. 9 This is a schematic diagram of the effect of eliminating output steps of the gate driving unit in the embodiment of the present application;

[0055] Attached Fig.10 A schematic diagram of a module of an optional display panel in an embodiment of the present application.

[0056] Description of reference numerals in the figures:

[0057] 1. Display panel; 10. Gate driving circuit; 100. Gate driving unit; 110. Signal input module; 120. First control module; 130. Secondary low potential blocking module; 140. Second control module; 150. Signal output module. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0059] According to the first aspect of this application, referring to Figure 2As shown, a gate driving circuit 10 is provided, including a plurality of cascaded gate driving units 100 , wherein the gate driving unit 100 includes a signal input module 110 , a first control module 120 , a sub-low potential blocking module 130 , a second control module 140 and a signal output module 150 .

[0060] The signal input module 110 is used to receive the output signal of the previous stage. It should be noted that when the gate driving unit 100 is a first-stage driving unit, the signal input module 110 receives the frame start signal STV.

[0061] The first control module 120 is electrically connected to the signal input module 110 and to the first node Q1 . The first control module 120 is used to control the potential of the first node Q1 .

[0062] The sub-low potential blocking module 130 is electrically connected to the first node Q1 and the second node Q, and the low potential blocking module is used to block the sub-low voltage of the first node Q1 from passing through;

[0063] The second control module 140 is electrically connected to the third node P and to the first control module 120, and the second control module 140 is used to control the potential of the third node P;

[0064] The signal output module 150 is electrically connected to the signal output terminal EM_out of this stage, and is electrically connected to the second node Q and the third node P. The signal output module 150 is used to control the potential of the signal output terminal EM_out of this stage under the control of the potential of the second node Q and the potential of the third node P.

[0065] Compared with the existing gate driving circuit 10, the gate driving circuit 10 of the embodiment of the present application uses a low potential blocking module to block the second lowest voltage passing through the first node Q1, eliminating the output step of the gate driving circuit 10, which is beneficial to improving the life performance and uniformity of the display panel.

[0066] In some specific embodiments of the present application, refer to Figure 3 As shown, the signal input module 110 includes: a first transistor T1, a gate of the first transistor T1 is connected to the first clock signal, a source of the first transistor T1 is electrically connected to the previous stage signal output terminal, and a drain of the first transistor T1 is electrically connected to the first control module 120.

[0067] In some specific embodiments of the present application, the first control module 120 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1 and a fifth transistor T5.

[0068] The gate of the second transistor T2 is connected to a constant low potential signal, the source of the second transistor T2 is electrically connected to the drain of the first transistor T1, the drain of the second transistor T2 is electrically connected to the first node Q1, and the second transistor T2 is used to block the ultra-low potential. It should be noted that in some embodiments of the present application, the constant low potential signal can be a gate turn-off voltage VGL.

[0069] The gate of the third transistor T3 is connected to the first node Q1 , and the source of the third transistor T3 is connected to the second clock signal.

[0070] The gate of the fourth transistor T4 is connected to the second control module 140, the source of the fourth transistor T4 is connected to the constant high potential signal, and the drain of the fourth transistor T4 is electrically connected to the drain of the third transistor T3. It should be noted that in some embodiments of the present application, the constant high potential signal can be a gate-on voltage VGH.

[0071] A first end of the first capacitor C1 is electrically connected to the gate of the third transistor T3 , and a second end of the first capacitor C1 is electrically connected to the drain of the third transistor T3 .

[0072] The gate of the fifth transistor T5 is connected to the reset control signal, the source of the fifth transistor T5 is connected to the constant high potential signal, and the drain of the fifth transistor T5 is electrically connected to the drain of the first transistor T1.

[0073] In this embodiment, the third transistor T3, the fourth transistor T4 and the first capacitor C1 together form a coupling pull-down module. The coupling pull-down module can pull down the potential of the first node Q1. Figure 7 As shown, when the potential of the first node Q1 is already -4.2744788 V, the potential of the first node Q1 can be pulled to a lower potential through the coupling pull-down module.

[0074] In some specific embodiments of the present application, refer to Figure 3 As shown, the sub-low potential blocking module 130 includes a sixth transistor T6, a gate of the sixth transistor T6 is electrically connected to the drain of the first transistor T1, a source of the sixth transistor T6 is electrically connected to the first node Q1, and a drain of the sixth transistor T6 is electrically connected to the second node Q.

[0075] In some specific embodiments of the present application, refer to Figure 4 As shown, Figure 4 The sub-low potential blocking module 130 is shown with Figure 3 The difference of the sub-low potential blocking module 130 shown is: Figure 4The sub-low potential blocking module 130 shown further includes a second capacitor C2, a first end of the second capacitor C2 is electrically connected to the second node Q, a second end of the second capacitor C2 is connected to a constant high potential signal, and the second capacitor C2 is used to stabilize the voltage of the second node Q.

[0076] In this embodiment, the second control module 140 includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13 and a third capacitor C3.

[0077] The gate of the eighth transistor T8 is connected to the first clock signal, the source of the eighth transistor T8 is connected to the constant low potential signal, and the drain of the eighth transistor T8 is electrically connected to the gate of the fourth transistor T4.

[0078] The gate of the ninth transistor T9 is connected to a constant low potential signal, and the source of the ninth transistor T9 is electrically connected to the drain of the eighth transistor T8.

[0079] The gate of the tenth transistor T10 is electrically connected to the drain of the ninth transistor T9 , and the source of the tenth transistor T10 is connected to the second clock signal.

[0080] The gate of the eleventh transistor T11 is connected to the second clock signal, the source of the eleventh transistor T11 is electrically connected to the drain of the tenth transistor T10 , and the drain of the eleventh transistor T11 is electrically connected to the third node P.

[0081] The gate of the twelfth transistor T12 is electrically connected to the drain of the first transistor T1 , the source of the twelfth transistor T12 is connected to the first clock signal, and the drain of the twelfth transistor T12 is electrically connected to the drain of the eighth transistor T8 .

[0082] The gate of the thirteenth transistor T13 is electrically connected to the source of the second transistor T2 , the source of the thirteenth transistor T13 is connected to the constant high potential signal, and the drain of the thirteenth transistor T13 is electrically connected to the third node P.

[0083] A first end of the third capacitor C3 is electrically connected to the gate of the tenth transistor T10 , and a second end of the third capacitor C3 is electrically connected to the drain of the tenth transistor T10 .

[0084] In this embodiment, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 constitute a high potential output maintaining module. The third capacitor C3 is used to pull down the coupling. The ninth transistor T9 is used to block the ultra-low potential. The thirteenth transistor T13 is used to prevent the output short circuit.

[0085] In some specific embodiments of the present application, refer to Figure 3 to Figure 4As shown, the signal output module 150 includes: a fourteenth transistor T14, a fifteenth transistor T15 and a fourth capacitor C4.

[0086] The gate of the fourteenth transistor T14 is electrically connected to the second node Q, the source of the fourteenth transistor T14 is connected to the constant low potential signal, and the drain of the fourteenth transistor T14 is electrically connected to the signal output terminal EM_out of this stage.

[0087] The gate of the fifteenth transistor T15 is electrically connected to the third node P, the source of the fifteenth transistor T15 is connected to the constant high potential signal, and the drain of the fifteenth transistor T15 is electrically connected to the signal output terminal EM_out of this stage.

[0088] The first end of the fourth capacitor C4 is electrically connected to the third node P, and the second end of the fourth capacitor C4 is electrically connected to the source of the fifteenth transistor T15, that is, a constant high potential signal is connected to achieve voltage stabilization of the third node P.

[0089] Reference Figure 5 As shown, the present application also provides a gate driving circuit 10, including a plurality of cascaded gate driving units 100, wherein the gate driving unit 100 includes a signal input module 110, a first control module 120, a sub-low potential blocking module 130, a second control module 140 and a signal output module 150.

[0090] The signal input module 110 is used to receive the output signal of the previous stage. It should be noted that when the gate driving unit 100 is a first-stage driving unit, the signal input module 110 receives the frame start signal STV.

[0091] The first control module 120 is electrically connected to the signal input module 110 and to the first node Q1 . The first control module 120 is used to control the potential of the first node Q1 .

[0092] The sub-low potential blocking module 130 is electrically connected to the first node Q1 and to the second node Q. The low potential blocking module is used to block the sub-low voltage of the first node Q1 from passing through.

[0093] The second control module 140 is electrically connected to the third node P and to the first control module 120 . The second control module 140 is used to control the potential of the third node P.

[0094] The signal output module 150 is electrically connected to the signal output terminal EM_outEM_out of this stage, and is electrically connected to the second node Q and the third node P. The signal output module 150 is used to control the potential of the signal output terminal EM_out of this stage under the control of the potential of the second node Q and the potential of the third node P.

[0095] Compared with the existing gate driving circuit 10, the gate driving circuit 10 of the embodiment of the present application utilizes a low potential blocking module to block the second lowest voltage passing through the first node Q1, thereby eliminating the output step of the gate driving circuit 10, which is beneficial to improving the life performance and uniformity of the display panel 1.

[0096] In some specific embodiments of the present application, refer to Figure 5 As shown, the signal input module 110 includes: a first transistor T1, a gate of the first transistor T1 is connected to the first clock signal, a source of the first transistor T1 is electrically connected to the previous stage signal output terminal, and a drain of the first transistor T1 is electrically connected to the first control module 120.

[0097] In some specific embodiments of the present application, the first control module 120 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1 and a fifth transistor T5.

[0098] The gate of the second transistor T2 is connected to a constant low potential signal, the source of the second transistor T2 is electrically connected to the drain of the first transistor T1, the drain of the second transistor T2 is electrically connected to the first node Q1, and the second transistor T2T12 is used to block the ultra-low potential.

[0099] The gate of the third transistor T3 is connected to the first node Q1 , and the source of the third transistor T3 is connected to the second clock signal.

[0100] The gate of the fourth transistor T4 is connected to the second control module 140 , the source of the fourth transistor T4 is connected to a constant high potential signal, and the drain of the fourth transistor T4 is electrically connected to the drain of the third transistor T3 .

[0101] A first end of the first capacitor C1 is electrically connected to the gate of the third transistor T3 , and a second end of the first capacitor C1 is electrically connected to the drain of the third transistor T3 .

[0102] The gate of the fifth transistor T5 is connected to the reset control signal, the source of the fifth transistor T5 is connected to the constant high potential signal, and the drain of the fifth transistor T5 is electrically connected to the drain of the first transistor T1.

[0103] In this embodiment, the third transistor T3, the fourth transistor T4, and the first capacitor C1 together constitute a coupling pull-down module, and the potential of the first node Q1 can be pulled down by the coupling pull-down module. Figure 8 As shown, when the potential of the first node Q1 is already -4.2744788 V, the potential of the first node Q1 can be pulled to a lower potential through the coupling pull-down module.

[0104] In some specific embodiments of the present application, refer to Figure 5As shown, the sub-low potential blocking module 130 includes: a sixth transistor T6, a gate of the sixth transistor T6 is connected to a constant low potential signal, a source of the sixth transistor T6 is electrically connected to the first node Q1, and a drain of the sixth transistor T6 is electrically connected to the second node Q. Figure 5 The sub-low potential blocking module 130 is shown with Figure 3 The difference of the sub-low potential blocking module 130 shown is: Figure 5 In the sub-low potential blocking module 130 shown, the gate voltage of the sixth transistor T6 can be set according to specific needs. For example, assuming that the threshold voltage of the sixth transistor T6 is 0V, the gate voltage of the sixth transistor T6 is set to -4V, then the sub-low potential blocking module 130 can block the voltage of -4V and above from passing through, and the gate voltage of the sixth transistor T6 is set to -7V, then the sub-low potential blocking module 130 can block the voltage of -7V and above from passing through. It should be noted that if the gate voltage of the sixth transistor T6 is set to 10V, the sixth transistor T6 is approximately a normally open tube, and a step will be generated, so it is necessary to ensure that the set voltage of the gate of the sixth transistor T6 does not exceed the threshold voltage of the sixth transistor T6.

[0105] In this embodiment, refer to Figure 5 As shown, the second low potential blocking module 130 further includes a seventh transistor T7, the gate of the seventh transistor T7 is electrically connected to the first node Q1, the source of the seventh transistor T7 is connected to the constant high potential signal, and the drain of the seventh transistor T7 is electrically connected to the second node Q. A constant high potential signal can be written to the second node Q through the seventh transistor T7, so that the fourteenth transistor T14 can be turned off.

[0106] In this embodiment, refer to Figure 6 As shown, the sub-low potential blocking module 130 may also include a second capacitor C2, a first end of the second capacitor C2 is electrically connected to the second node Q, and a second end of the second capacitor C2 is connected to a constant high potential signal to achieve voltage stabilization of the second node Q.

[0107] In this embodiment, the second control module 140 includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13 and a third capacitor C3.

[0108] The gate of the eighth transistor T8 is connected to the first clock signal, the source of the eighth transistor T8 is connected to the constant low potential signal, and the drain of the eighth transistor T8 is electrically connected to the gate of the fourth transistor T4.

[0109] The gate of the ninth transistor T9 is connected to a constant low potential signal, and the source of the ninth transistor T9 is electrically connected to the drain of the eighth transistor T8.

[0110] The gate of the tenth transistor T10 is electrically connected to the drain of the ninth transistor T9 , and the source of the tenth transistor T10 is connected to the second clock signal.

[0111] The gate of the eleventh transistor T11 is connected to the second clock signal, the source of the eleventh transistor T11 is electrically connected to the drain of the tenth transistor T10 , and the drain of the eleventh transistor T11 is electrically connected to the third node P.

[0112] The gate of the twelfth transistor T12 is electrically connected to the drain of the first transistor T1 , the source of the twelfth transistor T12 is connected to the first clock signal, and the drain of the twelfth transistor T12 is electrically connected to the drain of the eighth transistor T8 .

[0113] The gate of the thirteenth transistor T13 is electrically connected to the source of the second transistor T2 , the source of the thirteenth transistor T13 is connected to the constant high potential signal, and the drain of the thirteenth transistor T13 is electrically connected to the third node P.

[0114] A first end of the third capacitor C3 is electrically connected to the gate of the tenth transistor T10 , and a second end of the third capacitor C3 is electrically connected to the drain of the tenth transistor T10 .

[0115] In this embodiment, the eighth transistor T8, the tenth transistor T10, the eleventh transistor T11 and the twelfth transistor T12 constitute a high potential output maintaining module. The third capacitor C3 is used to pull down the coupling. The ninth transistor T9 is used to block the ultra-low potential. The thirteenth transistor T13 is used to prevent the output short circuit.

[0116] In some specific embodiments of the present application, refer to Figures 4 to 5 As shown, the signal output module 150 includes: a fourteenth transistor T14, a fifteenth transistor T15 and a fourth capacitor C4.

[0117] The gate of the fourteenth transistor T14 is electrically connected to the second node Q, the source of the fourteenth transistor T14 is connected to the constant low potential signal, and the drain of the fourteenth transistor T14 is electrically connected to the signal output terminal EM_out of this stage.

[0118] The gate of the fifteenth transistor T15 is electrically connected to the third node P, the source of the fifteenth transistor T15 is connected to the constant high potential signal, and the drain of the fifteenth transistor T15 is electrically connected to the signal output terminal EM_out of this stage.

[0119] The first end of the fourth capacitor C4 is electrically connected to the third node P, and the second end of the fourth capacitor C4 is electrically connected to the source of the fifteenth transistor T15, that is, a constant high potential signal is connected to achieve voltage stabilization of the third node P.

[0120] It should be noted that, in the aforementioned embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14 and the fifteenth transistor T15 are all P-type transistors, and the sixth transistor T6 and the seventh transistor T7 are all N-type transistors.

[0121] It should be noted that in the above-mentioned embodiment, the first clock signal and the second clock signal are signals with the same period and opposite phases. Figure 7 As shown, Figure 3 A timing diagram of the gate driving unit 100 is shown.

[0122] Specifically, before the time t0 shown in the figure, the gate drive unit 100 receives the previous level output signal in as a low level, the first clock signal XCK is a low level, and the second clock signal CK is a high level. At this time, T5, T6, T11, T14 and T15 are in a closed state, and the other transistors are all in an open state. Specifically, T1 and T8 are turned on under the control of the first clock signal XCK, T2 and T9 are turned on under the control of the constant low potential signal, the low level of the constant low potential signal is output to the node C, the node B and the first end of the third capacitor C3, and the low level output of the previous level output signal in is output to the node D, the node Q1 and the first end of C1; because the node D is a low level, T12 and T13 are turned on, the low level of the first clock signal XCK is output to the node C, and the high level of the constant high potential voltage is output to the third node P. At this time, T10 is turned on, and the high level of the second clock signal CK is output to the second end of C3 (i.e., node A). Since node C is at a low level, the first node Q1 is at a low level, so that T3 and T4 are turned on, and the high level of the second clock signal CK and the high level of the constant high potential voltage are output to the second end of C1 (i.e., node F). At this time, since T6 is closed, the second node Q does not receive any signal.

[0123] Then, at the time t0 shown in the figure, the gate drive unit 100 receives the previous level output signal in as a low level, the first clock signal XCK is a high level, and the second clock signal CK is a low level. At this moment, T3, T6, T9, T11, T12, T13 and T14 are in an open state, and the other transistors are in a closed state. Specifically, the first node Q1 maintains a low level due to the existence of C1, at which time T12 and T13 are opened, the high level of the first clock signal XCK is output to the node C and the node B and the first end of the capacitor C3, the high level of the constant high potential signal is output to the third node P and the second end of the capacitor C3, and T15 is closed. Since the first node Q1 is a low level, T3 is opened, and the low level of the second clock signal CK is output to the first end of C1. At this time, the second end of C1 jumps from a high level to a low level, and C1 bootstraps to pull the potential of the first node Q1 down. At the same time, T6 is turned on, so that the level of the second node Q is equal to the level of the first node Q1 at this time, and the low level of the constant low potential signal is output to the signal output terminal EM_out of this stage.

[0124] Then, at the moment t1 shown in the figure, the gate drive unit 100 receives the previous level output signal in as a high level, the first clock signal XCK is a low level, and the second clock signal CK is a high level. At this moment, T1, T2, T4, T6, T8, T9 and T10 are in an open state, and the other transistors are in a closed state. Specifically, T8 and T1 are opened under the control of the first clock signal XCK, T9 is opened under the control of the constant low potential signal, and the low level of the constant low potential signal is output to the node C, the node B and the first end of the capacitor C3, and the high level of the previous level output signal in is output to the node D, the node Q1 and the first end of C1; because the node D is a high level, T12 and T13 are closed. Because the second clock signal CK is a high level, T11 is closed, and the third node P maintains a high level. Because the node B is a low level, T10 is opened, and the high level of the second clock signal CK is output to the second end of the capacitor C3. Since node C is at a low level and the first node Q1 is at a high level, T3 is closed and T4 is opened, and the high level of the constant high potential signal is output to the second end of capacitor C1. At this time, since T6 is opened, the second node Q is connected to the first node Q1, the voltage gradually rises, and the signal output terminal EM_out of T14 remains at a low level.

[0125] Then, at the moment t2 shown in the figure, when the gate drive unit 100 receives the output signal of the previous stage and maintains a high level, the first clock signal XCK is a high level, and the second clock signal CK is a low level, at this moment, T2, T4, T6, T10, T11 and T15 are all in an open state, and the other transistors are all in a closed state. Specifically, the first node Q1 maintains a high level due to the presence of the capacitor C1, and at this time, T12 and T13 are closed. Since the second clock signal CK is a low level, T11 is turned on. Since the node B is a low level, T10 is turned on, and the low level of the second clock signal CK is output to the second end of the capacitor C3 and the third node P, T15 is turned on, and at this time, the capacitor C3 bootstraps to pull down the potential of the node B. Since the node C is a low level, the first node Q1 is a high level, so that T3 is closed, T4 is opened, and the high level of the constant high potential signal is output to the second end of the capacitor C1. At this time, since T2 is turned on, Q1 is at a high level, T6 is turned on, the second node Q remains at a high level, T14 is turned off, and the high level of the constant high potential signal is output to the signal output terminal EM_out of this stage.

[0126] Then, at the time t3 shown in the figure, the gate driving unit 100 receives the output signal of the previous stage from high level to low level, the first clock signal is low level, and the second clock signal is high level, that is, T1 and T8 are turned on, and the low level of the constant low potential signal VGL is output to the node C, the node B and the first end of the capacitor C3, and the low level of the output signal of the previous stage is output to the node D, the first node Q1 and the first end of the capacitor C1. At this time, T6 is turned off, that is, the first node Q1 is disconnected from the second node Q, so that the capacitor C1 can be charged at this time. After the first node Q1 reaches a stable state, the potential of the first node Q1 is output to the second node Q, so that the output will not have a falling delay. The low level of the first node Q1 is output to the first end of the capacitor C1. The high level of the second clock signal CK and the high level of the constant high potential signal VGH are output to the second end of the capacitor C1.

[0127] Finally, when the gate drive circuit 10 receives the previous stage output signal in as a low level, the first clock signal XCK as a high level, and the second clock signal CK as a low level, that is, at moment t4 shown in the figure, at this moment, the on or off status of each transistor is the same as at moment t0, which will not be repeated here.

[0128] It should be noted that in reference Figure 5 In the embodiment of the present invention, the on-off status of each transistor at each moment is Figure 3 The on-off conditions of the transistors in the illustrated embodiment at each moment are substantially the same, except that: Figure 5The seventh transistor T7 is in the off state at time t1 and time t2, and is in the on state at time t3 and time t4; and the sixth transistor T6 can be controlled by the constant low potential voltage connected to it.

[0129] Reference Figure 8 As shown, in an example of the present application, the potential of the first node Q1 is -4V, and the potential of the second node Q is 13V. The second-lowest potential blocking module 130 of the present application is used to disconnect the first node Q1 from the second node Q. When Q1 is coupled lower by the capacitor C1, T14 is turned on, thereby pulling down the potential of the second node Q and starting to output a low potential.

[0130] Reference Fig. 9 As shown, out1 is the output step of the gate driving circuit 10 in the related art, and out2 is the output step of the gate driving circuit 10 of the present application. The present application eliminates the output step of the gate driving circuit 10 by adding a sub-low potential blocking module 130, thereby improving the life performance and uniformity of the display panel 1.

[0131] According to the second aspect of the present application, referring to Fig.10 As shown, a display panel 1 is provided, which includes the aforementioned gate driving circuit 10 and can achieve all the effects of the aforementioned gate driving circuit 10, which will not be described in detail here.

[0132] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a plurality of gate driving units arranged in cascade, wherein the gate driving unit comprises: A signal input module is used to receive the output signal of the previous level; a first control module, electrically connected to the signal input module and to the first node, the first control module being used to control the potential of the first node; A sub-low potential blocking module, electrically connected to the first node and to the second node, the low potential blocking module being used to block the sub-low voltage of the first node from passing through; a second control module, electrically connected to the third node and to the first control module, the second control module being used to control the potential of the third node; A signal output module is electrically connected to the signal output terminal of this stage and to the second node and the third node. The signal output module is used to control the potential of the signal output terminal of this stage under the control of the potential of the second node and the potential of the third node.

2. The gate driving circuit according to claim 1, characterized in that: The signal input module comprises: A first transistor, wherein a gate of the first transistor is connected to a first clock signal, a source of the first transistor is connected to the previous stage output signal, and a drain of the first transistor is electrically connected to the first control module.

3. The gate driving circuit according to claim 2, characterized in that: The first control module comprises: a second transistor, wherein a gate of the second transistor is connected to a constant low potential signal, a source of the second transistor is electrically connected to a drain of the first transistor, and a drain of the second transistor is electrically connected to the first node; a third transistor, wherein a gate of the third transistor is connected to the first node, and a source of the third transistor is connected to a second clock signal; a fourth transistor, wherein a gate of the fourth transistor is connected to the second control module, a source of the fourth transistor is connected to a constant high potential signal, and a drain of the fourth transistor is electrically connected to a drain of the third transistor; a first capacitor, wherein a first end of the first capacitor is electrically connected to the gate of the third transistor, and a second end of the first capacitor is electrically connected to the drain of the third transistor; and A fifth transistor, wherein a gate of the fifth transistor is connected to a reset control signal, a source of the fifth transistor is connected to the constant high potential signal, and a drain of the fifth transistor is electrically connected to a drain of the first transistor.

4. The gate driving circuit according to claim 3, characterized in that: The sub-low potential blocking module comprises: A sixth transistor, wherein a gate of the sixth transistor is electrically connected to a drain of the first transistor, a source of the sixth transistor is electrically connected to the first node, and a drain of the sixth transistor is electrically connected to the second node.

5. The gate driving circuit according to claim 3, characterized in that: The sub-low potential blocking module comprises: A sixth transistor, wherein a gate of the sixth transistor is connected to the constant low potential signal, a source of the sixth transistor is electrically connected to the first node, and a drain of the sixth transistor is electrically connected to the second node.

6. The gate drive circuit according to claim 4 or 5, characterized in that: The sub-low potential blocking module also includes: A second capacitor, wherein a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is connected to the constant high potential signal.

7. The gate drive circuit according to claim 4 or 5, characterized in that: The sub-low potential blocking module also includes: A seventh transistor, wherein a gate of the seventh transistor is electrically connected to the first node, a source of the seventh transistor is connected to the constant high potential signal, and a drain of the seventh transistor is electrically connected to the second node.

8. The gate driving circuit according to claim 7, characterized in that: The seventh transistor is an N-type transistor.

9. The gate drive circuit according to claim 4 or 5, characterized in that: The sixth transistor is an N-type transistor.

10. The gate driving circuit according to claim 4 or 5, characterized in that: The second control module includes: an eighth transistor, wherein a gate of the eighth transistor is connected to the first clock signal, a source of the eighth transistor is connected to the constant low potential signal, and a drain of the eighth transistor is electrically connected to the gate of the fourth transistor; a ninth transistor, wherein a gate of the ninth transistor is connected to the constant low potential signal, and a source of the ninth transistor is electrically connected to a drain of the eighth transistor; a tenth transistor, wherein a gate of the tenth transistor is electrically connected to a drain of the ninth transistor, and a source of the tenth transistor is connected to the second clock signal; an eleventh transistor, a gate of the eleventh transistor being connected to the second clock signal, a source of the eleventh transistor being electrically connected to a drain of the tenth transistor, and a drain of the eleventh transistor being electrically connected to the third node; a twelfth transistor, wherein a gate of the twelfth transistor is electrically connected to a drain of the first transistor, a source of the twelfth transistor is connected to the first clock signal, and a drain of the twelfth transistor is electrically connected to a drain of the eighth transistor; a thirteenth transistor, wherein a gate of the thirteenth transistor is electrically connected to a source of the second transistor, a source of the thirteenth transistor is connected to the constant high potential signal, and a drain of the thirteenth transistor is electrically connected to the third node; and A third capacitor, wherein a first end of the third capacitor is electrically connected to the gate of the tenth transistor, and a second end of the third capacitor is electrically connected to the drain of the tenth transistor.

11. The gate driving circuit according to claim 10, characterized in that: The signal output module comprises: a fourteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to the second node, a source of the fourteenth transistor is connected to the constant low potential signal, and a drain of the fourteenth transistor is electrically connected to the current-stage signal output terminal; a fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to the third node, a source of the fifteenth transistor is connected to the constant high potential signal, and a drain of the fifteenth transistor is electrically connected to the current-stage signal output terminal; and A fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to the third node, and a second end of the fourth capacitor is electrically connected to the source of the fifteenth transistor.

12. The gate driving circuit according to claim 11, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are all P-type transistors.

13. The gate driving circuit according to claim 12, characterized in that: The first clock signal and the second clock signal are signals with the same period and opposite phases.

14. A display panel, characterized in that: The gate driving circuit comprises the gate driving circuit as claimed in any one of claims 1 to 13.

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