Staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channel

Abstract

The invention relates to the technical field of IPM packaging, in particular to a staggered distribution type double-face heat dissipation high-power IPM packaging structure with a cooling channel, which comprises an upper copper-clad ceramic substrate and a lower copper-clad ceramic substrate, and is characterized in that the upper copper-clad ceramic substrate is connected with the lower copper-clad ceramic substrate through an IPM module; the IPM module comprises a first phase IPM unit, a second phase IPM unit and a third phase IPM unit, the two sides of the first phase IPM unit, the two sides of the second phase IPM unit and the two sides of the third phase IPM unit are connected with the upper copper-clad ceramic substrate and the lower copper-clad ceramic substrate respectively, and the two ends of the first phase IPM unit, the two ends of the second phase IPM unit and the two ends of the third phase IPM unit are connected with the driving chip unit and the driving protection PCB unit respectively; the upper copper-clad ceramic substrate is provided with an upper cooling channel, and the lower copper-clad ceramic substrate is provided with a lower cooling channel. According to the invention, the length of a power loop is shortened, parasitic inductance in the module power loop is greatly reduced, the size of the module can be reduced, and the power density of the module can be improved.

Description

Technical Field

[0001] The invention relates to the technical field of IPM packaging, in particular to a staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels. Background Art

[0002] Intelligent Power IPM (Intelligent Power Module) is a power drive product that combines power electronics and integrated circuit technology. It integrates power semiconductor chips with control circuits, drive circuits, overcurrent (OC), short circuit (SC), undervoltage (UV), overheat (OH) protection circuits and self-diagnosis circuits, and seals them in the same insulating shell. IPM is small in size and highly integrated, and can provide excellent electrical performance, such as fast switching speed, low switching loss, and strong driving ability. In addition, compared with ordinary single modules, the internal intelligent protection function and module integration form have improved the reliability of the system and the self-protection ability of the module under fault conditions, which is conducive to system maintenance and debugging. IPM is generally used in three-phase inverter applications and is widely used in inverters, motor drives, power conversion and other fields. For example, in electric vehicles and hybrid vehicles, IPM modules are used to drive motors; in wind power generation and solar power generation systems, IPM modules are used to convert variable frequency electric energy into stable grid electric energy.

[0003] With the high-power requirements for higher voltage and larger current in the system, the voltage level of the chip integrated inside the IPM is also constantly increasing, and SiC MOSFET chips can also be selected as the main chip. However, compared with conventional modules, the IPM module is smaller in size and more compact in structure. The three-phase inverter output will cause six bridge arms and multiple power devices inside the module, and the module heating phenomenon is very serious. In addition, in the existing IPM internal structure, the chip bodies of the upper and lower bridge arm units of each phase are distributed in the same direction, and the upper and lower bridge arms are connected in series through copper sheets. Such a same-direction series structure makes the parasitic inductance of the power circuit larger, and the further miniaturization and power density of the IPM module are limited. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels to solve the above problems.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels, comprising an upper copper-clad ceramic substrate and a lower copper-clad ceramic substrate, wherein the upper copper-clad ceramic substrate is connected to the lower copper-clad ceramic substrate through an IPM module; The IPM module includes a first-phase IPM unit, a second-phase IPM unit and a third-phase IPM unit, the two sides of the first-phase IPM unit, the second-phase IPM unit and the third-phase IPM unit are respectively connected to the upper copper-clad ceramic substrate and the lower copper-clad ceramic substrate, and the two ends of the first-phase IPM unit, the second-phase IPM unit and the third-phase IPM unit are respectively connected to the driving chip unit and the driving protection PCB board unit; An upper cooling channel is provided on the upper copper-clad ceramic substrate, and a lower cooling channel is provided on the lower copper-clad ceramic substrate.

[0006] As a further solution of the present invention, the upper copper-clad ceramic substrate comprises an upper copper layer of the upper copper-clad ceramic substrate, the inner side of the upper copper layer of the upper copper-clad ceramic substrate is connected to a ceramic layer of the upper copper-clad ceramic substrate, and the inner sides of the ceramic layer of the upper copper-clad ceramic substrate are respectively connected to a first lower copper layer of the upper copper-clad ceramic substrate and a second lower copper layer of the upper copper-clad ceramic substrate; The lower copper-clad ceramic substrate comprises a lower copper-clad ceramic substrate lower copper layer, the inner side of the lower copper-clad ceramic substrate lower copper layer is connected to a lower copper-clad ceramic substrate ceramic layer, and the inner side of the lower copper-clad ceramic substrate ceramic layer is provided with a lower copper-clad ceramic substrate first upper copper layer, a lower copper-clad ceramic substrate second upper copper layer, and a lower copper-clad ceramic substrate third upper copper layer; The bottom side of the first phase IPM unit is connected to the first upper copper layer of the lower copper-clad ceramic substrate, and the top of the first phase IPM unit is respectively connected to the first lower copper layer of the upper copper-clad ceramic substrate and the second lower copper layer of the upper copper-clad ceramic substrate; The bottom side of the second phase IPM unit is connected to the second upper copper layer of the lower copper-clad ceramic substrate, and the top of the second phase IPM unit is respectively connected to the first lower copper layer of the upper copper-clad ceramic substrate and the second lower copper layer of the upper copper-clad ceramic substrate; The bottom side of the third-phase IPM unit is connected to the third upper copper layer of the lower copper-clad ceramic substrate, and the top of the third-phase IPM unit is respectively connected to the first lower copper layer of the upper copper-clad ceramic substrate and the second lower copper layer of the upper copper-clad ceramic substrate; Radiators are arranged on the outer sides of the upper cooling channel and the lower cooling channel.

[0007] As a further solution of the present invention, the first-phase IPM unit includes a first upper bridge arm unit and a first lower bridge arm unit; The first upper bridge arm unit includes a first high-voltage SiC MOSFET chip and a first fast recovery diode chip, the drain electrode on the lower surface of the first high-voltage SiC MOSFET chip is connected to the first upper copper layer of the lower copper-clad ceramic substrate through the first-phase first solder layer, the source electrode on the upper surface of the first high-voltage SiC MOSFET chip is connected to the first buffer layer of the first phase through the first-phase second solder layer, and the first buffer layer of the first phase is connected to the first lower copper layer of the upper copper-clad ceramic substrate through the first-phase third solder layer; The cathode on the lower surface of the first fast recovery diode chip is connected to the first upper copper layer of the lower copper-clad ceramic substrate through the first phase fourth solder layer, the anode on the upper surface of the first fast recovery diode chip is connected to the first phase second buffer layer through the first phase fifth solder layer, and the first phase second buffer layer is connected to the first lower copper layer of the upper copper-clad ceramic substrate through the first phase sixth solder layer; The first lower bridge arm unit includes a second high-voltage SiC MOSFET chip and a second fast recovery diode chip, the drain electrode on the upper surface of the second high-voltage SiC MOSFET chip is connected to the second lower copper layer of the upper copper-clad ceramic substrate through the seventh solder layer of the first phase, the source electrode on the lower surface of the second high-voltage SiC MOSFET chip is connected to the third buffer layer of the first phase through the eighth solder layer of the first phase, and the third buffer layer of the first phase is connected to the first upper copper layer of the lower copper-clad ceramic substrate through the ninth solder layer of the first phase; The cathode on the upper surface of the second fast recovery diode chip is connected to the second lower copper layer of the upper copper-clad ceramic substrate through the tenth solder layer of the first phase, the anode on the lower surface of the second fast recovery diode chip is connected to the fourth buffer layer of the first phase through the eleventh solder layer of the first phase, and the fourth buffer layer of the first phase is connected to the first upper copper layer of the lower copper-clad ceramic substrate through the twelfth solder layer of the first phase.

[0008] As a further solution of the present invention, the second phase IPM unit includes a second upper bridge arm unit and a second lower bridge arm unit; The second upper bridge arm unit includes a third high-voltage SiC MOSFET chip and a third fast recovery diode chip, the drain electrode on the lower surface of the third high-voltage SiC MOSFET chip is connected to the second upper copper layer of the lower copper-clad ceramic substrate through the second-phase first solder layer, the source electrode on the upper surface of the third high-voltage SiC MOSFET chip is connected to the second-phase first buffer layer through the second-phase second solder layer, and the second-phase first buffer layer is connected to the first lower copper layer of the upper copper-clad ceramic substrate through the second-phase third solder layer; The cathode on the lower surface of the third fast recovery diode chip is connected to the second upper copper layer of the lower copper-clad ceramic substrate through the second-phase fourth solder layer, the anode on the upper surface of the third fast recovery diode chip is connected to the second-phase second buffer layer through the second-phase fifth solder layer, and the second-phase second buffer layer is connected to the first lower copper layer of the upper copper-clad ceramic substrate through the second-phase sixth solder layer; The second lower bridge arm unit includes a fourth high-voltage SiC MOSFET chip and a fourth fast recovery diode chip, the drain electrode on the upper surface of the fourth high-voltage SiC MOSFET chip is connected to the second lower copper layer of the upper copper-clad ceramic substrate through the seventh solder layer of the second phase, the source electrode on the lower surface of the fourth high-voltage SiC MOSFET chip is connected to the third buffer layer of the second phase through the eighth solder layer of the second phase, and the third buffer layer of the second phase is connected to the second upper copper layer of the lower copper-clad ceramic substrate through the ninth solder layer of the second phase; The cathode on the upper surface of the fourth fast recovery diode chip is connected to the second lower copper layer of the upper copper-clad ceramic substrate through the second phase tenth solder layer, the anode on the lower surface of the fourth fast recovery diode chip is connected to the second phase fourth buffer layer through the second phase eleventh solder layer, and the second phase fourth buffer layer is connected to the second upper copper layer of the lower copper-clad ceramic substrate through the second phase twelfth solder layer.

[0009] As a further solution of the present invention, the third-phase IPM unit includes a third upper bridge arm unit and a first lower bridge arm unit; The third upper bridge arm unit includes a fifth high-voltage SiC MOSFET chip and a fifth fast recovery diode chip, the drain electrode on the lower surface of the fifth high-voltage SiC MOSFET chip is connected to the third upper copper layer of the lower copper-clad ceramic substrate through the third-phase first solder layer, the source electrode on the upper surface of the fifth high-voltage SiC MOSFET chip is connected to the third-phase first buffer layer through the third-phase second solder layer, and the third-phase first buffer layer is connected to the first lower copper layer of the upper copper-clad ceramic substrate through the third-phase third solder layer; The cathode on the lower surface of the fifth fast recovery diode chip is connected to the third upper copper layer of the lower copper-clad ceramic substrate through the third phase fourth solder layer, the anode on the upper surface of the fifth fast recovery diode chip is connected to the third phase second buffer layer through the third phase fifth solder layer, and the third phase second buffer layer is connected to the first lower copper layer of the upper copper-clad ceramic substrate through the third phase sixth solder layer; The third lower bridge arm unit includes a sixth high-voltage SiC MOSFET chip and a sixth fast recovery diode chip, the drain electrode on the upper surface of the sixth high-voltage SiC MOSFET chip is connected to the second lower copper layer of the upper copper-clad ceramic substrate through the seventh solder layer of the third phase, the source electrode on the lower surface of the sixth high-voltage SiC MOSFET chip is connected to the third buffer layer of the third phase through the eighth solder layer of the third phase, and the third buffer layer of the third phase is connected to the third upper copper layer of the lower copper-clad ceramic substrate through the ninth solder layer of the third phase; The cathode on the upper surface of the sixth fast recovery diode chip is connected to the second lower copper layer of the upper copper-clad ceramic substrate through the tenth solder layer of the third phase, the anode on the lower surface of the sixth fast recovery diode chip is connected to the fourth buffer layer of the third phase through the eleventh solder layer of the third phase, and the fourth buffer layer of the third phase is connected to the third upper copper layer of the lower copper-clad ceramic substrate through the twelfth solder layer of the third phase.

[0010] As a further solution of the present invention, the upper surface gate of the first high-voltage SiC MOSFET chip is connected to the first copper sheet through the first phase thirteenth solder layer, the first copper sheet is connected to the upper bridge arm driver chip through the upper bridge arm PCB board, the lower surface gate of the second high-voltage SiC MOSFET chip is connected to the fourth copper sheet through the first phase fourteenth solder layer, and the fourth copper sheet is connected to the lower bridge arm driver chip through the lower bridge arm PCB board.

[0011] As a further solution of the present invention, the upper surface gate of the third high-voltage SiC MOSFET chip is connected to the second copper sheet through the second-phase thirteenth solder layer, the second copper sheet is connected to the upper bridge arm driver chip through the upper bridge arm PCB board, and the lower surface gate of the third high-voltage SiC MOSFET chip is connected to the fifth copper sheet through the second-phase fourteenth solder layer, and the fifth copper sheet is connected to the lower bridge arm driver chip through the lower bridge arm PCB board.

[0012] As a further solution of the present invention, the upper surface gate of the fifth high-voltage SiC MOSFET chip is connected to the third copper sheet through the thirteenth solder layer of the third phase, and the third copper sheet is connected to the upper bridge arm driver chip through the upper bridge arm PCB board. The lower surface gate of the sixth high-voltage SiC MOSFET chip is connected to the sixth copper sheet through the fourteenth solder layer of the third phase, and the sixth copper sheet is connected to the lower bridge arm driver chip through the lower bridge arm PCB board.

[0013] As a further solution of the present invention, the ceramic layer of the upper copper-clad ceramic substrate and the ceramic layer of the lower copper-clad ceramic substrate are both made of aluminum nitride ceramic or aluminum oxide ceramic; the upper copper layer of the upper copper-clad ceramic substrate is embedded in the upper cooling channel, and the lower copper layer of the lower copper-clad ceramic substrate is embedded in the lower cooling channel.

[0014] As a further solution of the present invention, the radiator includes an upper radiator and a lower radiator, the upper radiator is connected to the upper copper layer of the upper copper-clad ceramic substrate through an upper thermal grease layer, and the lower radiator is connected to the lower copper layer of the lower copper-clad ceramic substrate through a lower thermal grease layer.

[0015] Since the present invention adopts the above technical solution, the present invention has the following advantages and positive effects: the staggered distributed structure of the IPM unit proposed by the present invention shortens the length of the power circuit, greatly reduces the parasitic inductance inside the module power circuit, and at the same time the module volume can be reduced, which can improve the module power density. The presence of the cooling channel and the radiator can achieve double-sided heat dissipation of the module, which can greatly improve the heat dissipation performance of the module, thereby increasing the service life of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a circuit schematic diagram of the IPM packaging structure of the present invention.

[0017] Figure 2 It is a structural schematic diagram of the IPM packaging structure of the present invention.

[0018] Figure 3 It is a complete three-phase structural schematic diagram of the IPM packaging structure of the present invention.

[0019] Figure 4 Schematic diagram of the second phase IPM unit of the IPM packaging structure of the present invention.

[0020] Figure 5 Schematic diagram of the third phase IPM unit of the IPM packaging structure of the present invention.

[0021] Figure 6 Schematic diagram of a three-phase IPM unit of the IPM packaging structure of the present invention.

[0022] Figure 7 The figure is a top view schematic diagram of the lower copper-clad ceramic substrate and the three-phase IPM module of the IPM packaging structure of the present invention.

[0023] Figure 8 This is a bottom-up schematic diagram of the copper-clad ceramic substrate and the three-phase IPM module of the IPM packaging structure of the present invention.

[0024] Fig. 9 Schematic diagram of the lower cooling channel of the IPM packaging structure of the present invention.

[0025] In the figure: 1 is a first high-voltage SiC MOSFET chip, 2 is a first fast recovery diode chip, 3 is a second high-voltage SiC MOSFET chip, 4 is a second fast recovery diode chip, 5 is a third high-voltage SiC MOSFET chip, 6 is a third fast recovery diode chip, 7 is a fourth high-voltage SiC MOSFET chip, 8 is a fourth fast recovery diode chip, 9 is a fifth high-voltage SiC MOSFET chip, 10 is a fifth fast recovery diode chip, 11 is a sixth high-voltage SiC MOSFET chip, 12 is the sixth fast recovery diode chip, 13 is the first solder layer of the first phase, 14 is the second solder layer of the first phase, 15 is the third solder layer of the first phase, 16 is the fourth solder layer of the first phase, 17 is the fifth solder layer of the first phase, 18 is the sixth solder layer of the first phase, 19 is the seventh solder layer of the first phase, 20 is the eighth solder layer of the first phase, 21 is the ninth solder layer of the first phase, 22 is the tenth solder layer of the first phase, 23 is the eleventh solder layer of the first phase, 24 is the twelfth solder layer of the first phase, 25 is the thirteenth solder layer of the first phase, 26 is the fourteenth solder layer of the first phase, 27 is the first phase Buffer layer, 28 is the second buffer layer of the first phase, 29 is the third buffer layer of the first phase, 30 is the fourth buffer layer of the first phase, 31 is the lower radiator, 32 is the upper radiator, 33 is the lower thermal grease layer, 34 is the upper thermal grease layer, 35 is the lower copper layer of the lower copper-clad ceramic substrate, 36 is the ceramic layer of the lower copper-clad ceramic substrate, 37 is the first upper copper layer of the lower copper-clad ceramic substrate, 38 is the second upper copper layer of the lower copper-clad ceramic substrate, 39 is the third upper copper layer of the lower copper-clad ceramic substrate, 40 is the upper copper layer of the upper copper-clad ceramic substrate, 41 is the ceramic layer of the upper copper-clad ceramic substrate, 42 is the first lower copper layer of the upper copper-clad ceramic substrate, 43 is the upper copper-clad ceramic The second lower copper layer of the substrate, 44 is the lower cooling channel, 45 is the upper cooling channel, 46 is the upper bridge arm PCB board, 47 is the upper bridge arm driver chip, 48 is the lower bridge arm PCB board, 49 is the lower bridge arm driver chip, 50 is the first copper sheet, 51 is the second copper sheet, 52 is the third copper sheet, 53 is the fourth copper sheet, 54 is the fifth copper sheet, 55 is the sixth copper sheet, 56 is the plastic package shell, 57 is the first phase IPM unit, 58 is the second phase IPM unit, 59 is the third phase IPM unit, 60 is the water inlet hole, 61 is the water outlet hole, 62 is the second phase first solder layer, 63 is the second phase second solder layer, 64 is The third solder layer of the second phase, 65 is the fourth solder layer of the second phase, 66 is the fifth solder layer of the second phase, 67 is the sixth solder layer of the second phase, 68 is the seventh solder layer of the second phase, 69 is the eighth solder layer of the second phase, 70 is the ninth solder layer of the second phase, 71 is the tenth solder layer of the second phase, 72 is the eleventh solder layer of the second phase, 73 is the twelfth solder layer of the second phase, 74 is the thirteenth solder layer of the second phase, 75 is the fourteenth solder layer of the second phase, 76 is the first buffer layer of the second phase, 77 is the second buffer layer of the second phase, 78 is the third buffer layer of the second phase, 79 is the fourth buffer layer of the second phase, 80 is the first solder layer of the third phase,81 is the second solder layer of the third phase, 82 is the third solder layer of the third phase, 83 is the fourth solder layer of the third phase, 84 is the fifth solder layer of the third phase, 85 is the sixth solder layer of the third phase, 86 is the seventh solder layer of the third phase, 87 is the eighth solder layer of the third phase, 88 is the ninth solder layer of the third phase, 89 is the tenth solder layer of the third phase, 90 is the eleventh solder layer of the third phase, 91 is the twelfth solder layer of the third phase, 92 is the thirteenth solder layer of the third phase, 93 is the fourteenth solder layer of the third phase, 94 is the first buffer layer of the third phase, 95 is the second buffer layer of the third phase, 96 is the third buffer layer of the third phase, and 97 is the fourth buffer layer of the third phase. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0027] like Figures 1 to 9 As shown, the present invention is a staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels, which is characterized by: comprising an upper copper-clad ceramic substrate and a lower copper-clad ceramic substrate, wherein the upper copper-clad ceramic substrate is connected to the lower copper-clad ceramic substrate through an IPM module; The IPM module includes a first-phase IPM unit 57, a second-phase IPM unit 58 and a third-phase IPM unit 59, the two sides of the first-phase IPM unit 57, the second-phase IPM unit 58 and the third-phase IPM unit 59 are respectively connected to the upper copper-clad ceramic substrate and the lower copper-clad ceramic substrate, and the two ends of the first-phase IPM unit 57, the second-phase IPM unit 58 and the third-phase IPM unit 59 are respectively connected to the driving chip unit and the driving protection PCB board unit; An upper cooling channel 45 is provided on the upper copper-clad ceramic substrate, and a lower cooling channel 44 is provided on the lower copper-clad ceramic substrate.

[0028] In a further embodiment of the present invention, the upper copper-clad ceramic substrate comprises an upper copper layer 40 of the upper copper-clad ceramic substrate, the inner side of the upper copper layer 40 of the upper copper-clad ceramic substrate is connected to an upper copper-clad ceramic substrate ceramic layer 41, and the inner sides of the upper copper-clad ceramic substrate ceramic layer 41 are respectively connected to an upper copper-clad ceramic substrate first lower copper layer 42 and an upper copper-clad ceramic substrate second lower copper layer 43; The lower copper-clad ceramic substrate comprises a lower copper-clad ceramic substrate lower copper layer 35, the inner side of which is connected to a lower copper-clad ceramic substrate ceramic layer 36, and the inner side of the lower copper-clad ceramic substrate ceramic layer 36 is provided with a lower copper-clad ceramic substrate first upper copper layer 37, a lower copper-clad ceramic substrate second upper copper layer 38, and a lower copper-clad ceramic substrate third upper copper layer 39; The bottom side of the first phase IPM unit 57 is connected to the first upper copper layer 37 of the lower copper-clad ceramic substrate, and the top of the first phase IPM unit 57 is connected to the first lower copper layer 42 of the upper copper-clad ceramic substrate and the second lower copper layer 43 of the upper copper-clad ceramic substrate respectively; The bottom side of the second phase IPM unit 58 is connected to the second upper copper layer 38 of the lower copper-clad ceramic substrate, and the top of the second phase IPM unit 58 is connected to the first lower copper layer 42 of the upper copper-clad ceramic substrate and the second lower copper layer 43 of the upper copper-clad ceramic substrate respectively; The bottom side of the third phase IPM unit 59 is connected to the third upper copper layer 39 of the lower copper-clad ceramic substrate, and the top of the third phase IPM unit 59 is respectively connected to the first lower copper layer 42 of the upper copper-clad ceramic substrate and the second lower copper layer 43 of the upper copper-clad ceramic substrate; Radiators are disposed on the outer sides of the upper cooling channel 45 and the lower cooling channel 44 .

[0029] In a further embodiment of the present invention, the first phase IPM unit 57 includes a first upper bridge arm unit and a first lower bridge arm unit; The first upper bridge arm unit includes a first high-voltage SiC MOSFET chip 1 and a first fast recovery diode chip 2, the drain electrode on the lower surface of the first high-voltage SiC MOSFET chip 1 is connected to the first upper copper layer 37 of the lower copper-clad ceramic substrate through the first-phase first solder layer 13, the source electrode on the upper surface of the first high-voltage SiC MOSFET chip 1 is connected to the first-phase first buffer layer 27 through the first-phase second solder layer 14, and the first-phase first buffer layer 27 is connected to the first lower copper layer 42 of the upper copper-clad ceramic substrate through the first-phase third solder layer 15; The cathode on the lower surface of the first fast recovery diode chip 2 is connected to the first upper copper layer 37 of the lower copper-clad ceramic substrate through the first phase fourth solder layer 16, the anode on the upper surface of the first fast recovery diode chip 2 is connected to the first phase second buffer layer 28 through the first phase fifth solder layer 17, and the first phase second buffer layer 28 is connected to the first lower copper layer 42 of the upper copper-clad ceramic substrate through the first phase sixth solder layer 18; The first lower bridge arm unit includes a second high-voltage SiC MOSFET chip 3 and a second fast recovery diode chip 4, the drain electrode on the upper surface of the second high-voltage SiC MOSFET chip 3 is connected to the second lower copper layer 43 of the upper copper-clad ceramic substrate through the first-phase seventh solder layer 19, the source electrode on the lower surface of the second high-voltage SiC MOSFET chip 3 is connected to the first-phase third buffer layer 29 through the first-phase eighth solder layer 20, and the first-phase third buffer layer 29 is connected to the first upper copper layer 37 of the lower copper-clad ceramic substrate through the first-phase ninth solder layer 21; The cathode on the upper surface of the second fast recovery diode chip 4 is connected to the second lower copper layer 43 of the upper copper-clad ceramic substrate through the first phase tenth solder layer 22, the anode on the lower surface of the second fast recovery diode chip 4 is connected to the first phase fourth buffer layer 30 through the first phase eleventh solder layer 23, and the first phase fourth buffer layer 30 is connected to the first upper copper layer 37 of the lower copper-clad ceramic substrate through the first phase twelfth solder layer 24.

[0030] In a further embodiment of the present invention, the second phase IPM unit 58 includes a second upper bridge arm unit and a second lower bridge arm unit; The second upper bridge arm unit includes a third high-voltage SiC MOSFET chip 5 and a third fast recovery diode chip 6, the drain electrode on the lower surface of the third high-voltage SiC MOSFET chip 5 is connected to the second upper copper layer 38 of the lower copper-clad ceramic substrate through the second-phase first solder layer 62, the source electrode on the upper surface of the third high-voltage SiC MOSFET chip 5 is connected to the second-phase first buffer layer 76 through the second-phase second solder layer 63, and the second-phase first buffer layer 76 is connected to the first lower copper layer 42 of the upper copper-clad ceramic substrate through the second-phase third solder layer 64; The cathode on the lower surface of the third fast recovery diode chip 6 is connected to the second upper copper layer 38 of the lower copper-clad ceramic substrate through the second-phase fourth solder layer 65, the anode on the upper surface of the third fast recovery diode chip 6 is connected to the second-phase second buffer layer 77 through the second-phase fifth solder layer 66, and the second-phase second buffer layer 77 is connected to the first lower copper layer 42 of the upper copper-clad ceramic substrate through the second-phase sixth solder layer 67; The second lower bridge arm unit includes a fourth high-voltage SiC MOSFET chip 7 and a fourth fast recovery diode chip 8, the drain electrode on the upper surface of the fourth high-voltage SiC MOSFET chip 7 is connected to the second lower copper layer 43 of the upper copper-clad ceramic substrate through the second-phase seventh solder layer 68, the source electrode on the lower surface of the fourth high-voltage SiC MOSFET chip 7 is connected to the second-phase third buffer layer 78 through the second-phase eighth solder layer 69, and the second-phase third buffer layer 78 is connected to the second upper copper layer 38 of the lower copper-clad ceramic substrate through the second-phase ninth solder layer 70; The cathode on the upper surface of the fourth fast recovery diode chip 8 is connected to the second lower copper layer 43 of the upper copper-clad ceramic substrate through the second phase tenth solder layer 71, and the anode on the lower surface of the fourth fast recovery diode chip 8 is connected to the second phase fourth buffer layer 79 through the second phase eleventh solder layer 72, and the second phase fourth buffer layer 79 is connected to the second upper copper layer 38 of the lower copper-clad ceramic substrate through the second phase twelfth solder layer 73.

[0031] According to a further solution of the present invention, the third-phase IPM unit 59 includes a third upper bridge arm unit and a first lower bridge arm unit; The third upper bridge arm unit includes a fifth high-voltage SiC MOSFET chip 9 and a fifth fast recovery diode chip 10, the drain electrode on the lower surface of the fifth high-voltage SiC MOSFET chip 9 is connected to the third upper copper layer 39 of the lower copper-clad ceramic substrate through the third-phase first solder layer 80, the source electrode on the upper surface of the fifth high-voltage SiC MOSFET chip 9 is connected to the third-phase first buffer layer 94 through the third-phase second solder layer 81, and the third-phase first buffer layer 94 is connected to the first lower copper layer 42 of the upper copper-clad ceramic substrate through the third-phase third solder layer 82; The cathode on the lower surface of the fifth fast recovery diode chip 10 is connected to the third upper copper layer 39 of the lower copper-clad ceramic substrate through the third phase fourth solder layer 83, the anode on the upper surface of the fifth fast recovery diode chip 10 is connected to the third phase second buffer layer 95 through the third phase fifth solder layer 84, and the third phase second buffer layer 95 is connected to the first lower copper layer 42 of the upper copper-clad ceramic substrate through the third phase sixth solder 85; The third lower bridge arm unit includes a sixth high-voltage SiC MOSFET chip 11 and a sixth fast recovery diode chip 12, the drain electrode on the upper surface of the sixth high-voltage SiC MOSFET chip 11 is connected to the second lower copper layer 43 of the upper copper-clad ceramic substrate through the third-phase seventh solder layer 86, the source electrode on the lower surface of the sixth high-voltage SiC MOSFET chip 11 is connected to the third-phase third buffer layer 96 through the third-phase eighth solder layer 87, and the third-phase third buffer layer 96 is connected to the third upper copper layer 39 of the lower copper-clad ceramic substrate through the third-phase ninth solder layer 88; The cathode on the upper surface of the sixth fast recovery diode chip 12 is connected to the second lower copper layer 43 of the upper copper-clad ceramic substrate through the third-phase tenth solder layer 89, and the anode on the lower surface of the sixth fast recovery diode chip 12 is connected to the third-phase fourth buffer layer 97 through the third-phase eleventh solder layer 90, and the third-phase fourth buffer layer 97 is connected to the third upper copper layer 39 of the lower copper-clad ceramic substrate through the third-phase twelfth solder layer 91.

[0032] According to a further solution of the present invention, the upper surface gate of the first high-voltage SiC MOSFET chip 1 is connected to the first copper sheet 50 through the first phase thirteenth solder layer 25, and the first copper sheet 50 is connected to the upper bridge arm driver chip 47 through the upper bridge arm PCB board 46; the lower surface gate of the second high-voltage SiC MOSFET chip 3 is connected to the fourth copper sheet 53 through the first phase fourteenth solder layer 26, and the fourth copper sheet 53 is connected to the lower bridge arm driver chip 49 through the lower bridge arm PCB board 48.

[0033] According to a further solution of the present invention, the upper surface gate of the third high-voltage SiC MOSFET chip 5 is connected to the second copper sheet 51 through the second-phase thirteenth solder layer 74, and the second copper sheet 51 is connected to the upper bridge arm driver chip 47 through the upper bridge arm PCB board 46. The lower surface gate of the third high-voltage SiC MOSFET chip 7 is connected to the fifth copper sheet 54 through the second-phase fourteenth solder layer 75, and the fifth copper sheet 54 is connected to the lower bridge arm driver chip 49 through the lower bridge arm PCB board 48.

[0034] According to a further solution of the present invention, the upper surface gate of the fifth high-voltage SiC MOSFET chip 9 is connected to the third copper sheet 52 through the third phase thirteenth solder layer 92, and the third copper sheet 52 is connected to the upper bridge arm driver chip 47 through the upper bridge arm PCB board 46. The lower surface gate of the sixth high-voltage SiC MOSFET chip 11 is connected to the sixth copper sheet 55 through the third phase fourteenth solder layer 93, and the sixth copper sheet 55 is connected to the lower bridge arm driver chip 49 through the lower bridge arm PCB board 48.

[0035] In a further solution of the present invention, the ceramic layer 41 of the upper copper-clad ceramic substrate and the ceramic layer 36 of the lower copper-clad ceramic substrate are made of aluminum nitride ceramic or aluminum oxide ceramic; the upper copper layer 40 of the upper copper-clad ceramic substrate is embedded in the upper cooling channel 45, and the lower copper layer 35 of the lower copper-clad ceramic substrate is embedded in the lower cooling channel 44. The upper cooling channel 45 and the lower cooling channel 44 are respectively provided with a water inlet hole 60 and a water outlet hole 61. The cooling channel can achieve cooling by circulating a cooling medium (such as water) through the small holes at both ends.

[0036] According to a further solution of the present invention, the heat sink comprises an upper heat sink 32 and a lower heat sink 31, wherein the upper heat sink 32 is connected to the upper copper layer 40 of the upper copper-clad ceramic substrate via an upper thermal grease layer 34, and the lower heat sink 31 is connected to the lower copper layer 35 of the lower copper-clad ceramic substrate via a lower thermal grease layer 33.

[0037] In a further solution of the present invention, a plastic shell 56 is provided outside the entire IPM to encapsulate the module. The height of the plastic shell 56 is from the upper copper-clad ceramic substrate ceramic layer 41 to the lower copper-clad ceramic substrate ceramic layer 36, and epoxy resin is injected into the plastic shell 56 to encapsulate the internal structure.

[0038] Although specific embodiments of the present invention are described above, those skilled in the art should understand that these are merely examples and that various changes or modifications may be made to the embodiments without departing from the principles and essence of the present invention. The scope of protection of the present invention is limited only by the appended claims.

Claims

1. A staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels, characterized by: It comprises an upper copper-clad ceramic substrate and a lower copper-clad ceramic substrate, wherein the upper copper-clad ceramic substrate is connected to the lower copper-clad ceramic substrate via an IPM module; The IPM module comprises a first-phase IPM unit (57), a second-phase IPM unit (58) and a third-phase IPM unit (59); two sides of the first-phase IPM unit (57), the second-phase IPM unit (58) and the third-phase IPM unit (59) are respectively connected to an upper copper-clad ceramic substrate and a lower copper-clad ceramic substrate; and two ends of the first-phase IPM unit (57), the second-phase IPM unit (58) and the third-phase IPM unit (59) are respectively connected to a driver chip unit and a driver protection PCB board unit; An upper cooling channel (45) is provided on the upper copper-clad ceramic substrate, and a lower cooling channel (44) is provided on the lower copper-clad ceramic substrate.

2. According to claim 1, a staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels is characterized by: The upper copper-clad ceramic substrate comprises an upper copper-clad ceramic substrate upper copper layer (40), the inner side of the upper copper-clad ceramic substrate upper copper layer (40) is connected to an upper copper-clad ceramic substrate ceramic layer (41), and the inner sides of the upper copper-clad ceramic substrate ceramic layer (41) are respectively connected to an upper copper-clad ceramic substrate first lower copper layer (42) and an upper copper-clad ceramic substrate second lower copper layer (43); The lower copper-clad ceramic substrate comprises a lower copper-clad ceramic substrate lower copper layer (35), the inner side of the lower copper-clad ceramic substrate lower copper layer (35) is connected to a lower copper-clad ceramic substrate ceramic layer (36), and the inner side of the lower copper-clad ceramic substrate ceramic layer (36) is provided with a lower copper-clad ceramic substrate first upper copper layer (37), a lower copper-clad ceramic substrate second upper copper layer (38), and a lower copper-clad ceramic substrate third upper copper layer (39); The bottom side of the first-phase IPM unit (57) is connected to the first upper copper layer (37) of the lower copper-clad ceramic substrate, and the top of the first-phase IPM unit (57) is respectively connected to the first lower copper layer (42) of the upper copper-clad ceramic substrate and the second lower copper layer (43) of the upper copper-clad ceramic substrate; The bottom side of the second phase IPM unit (58) is connected to the second upper copper layer (38) of the lower copper-clad ceramic substrate, and the top of the second phase IPM unit (58) is respectively connected to the first lower copper layer (42) of the upper copper-clad ceramic substrate and the second lower copper layer (43) of the upper copper-clad ceramic substrate; The bottom side of the third-phase IPM unit (59) is connected to the third upper copper layer (39) of the lower copper-clad ceramic substrate, and the top of the third-phase IPM unit (59) is respectively connected to the first lower copper layer (42) of the upper copper-clad ceramic substrate and the second lower copper layer (43) of the upper copper-clad ceramic substrate; Radiators are provided on the outer sides of the upper cooling channel (45) and the lower cooling channel (44).

3. The staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels according to claim 2 is characterized by: The first-phase IPM unit (57) comprises a first upper bridge arm unit and a first lower bridge arm unit; The first upper bridge arm unit comprises a first high-voltage SiC MOSFET chip (1) and a first fast recovery diode chip (2); the drain electrode on the lower surface of the first high-voltage SiC MOSFET chip (1) is connected to the first upper copper layer (37) of the lower copper-clad ceramic substrate via a first-phase first solder layer (13); the source electrode on the upper surface of the first high-voltage SiC MOSFET chip (1) is connected to the first-phase first buffer layer (27) via a first-phase second solder layer (14); and the first-phase first buffer layer (27) is connected to the first lower copper layer (42) of the upper copper-clad ceramic substrate via a first-phase third solder layer (15); The cathode on the lower surface of the first fast recovery diode chip (2) is connected to the first upper copper layer (37) of the lower copper-clad ceramic substrate via the first phase fourth solder layer (16), the anode on the upper surface of the first fast recovery diode chip (2) is connected to the first phase second buffer layer (28) via the first phase fifth solder layer (17), and the first phase second buffer layer (28) is connected to the first lower copper layer (42) of the upper copper-clad ceramic substrate via the first phase sixth solder layer (18); The first lower bridge arm unit comprises a second high-voltage SiC MOSFET chip (3) and a second fast recovery diode chip (4); the upper surface drain of the second high-voltage SiC MOSFET chip (3) is connected to the second lower copper layer (43) of the upper copper-clad ceramic substrate via the first-phase seventh solder layer (19); the lower surface source of the second high-voltage SiC MOSFET chip (3) is connected to the first-phase third buffer layer (29) via the first-phase eighth solder layer (20); and the first-phase third buffer layer (29) is connected to the first upper copper layer (37) of the lower copper-clad ceramic substrate via the first-phase ninth solder layer (21); The cathode on the upper surface of the second fast recovery diode chip (4) is connected to the second lower copper layer (43) of the upper copper-clad ceramic substrate through the tenth solder layer (22) of the first phase, the anode on the lower surface of the second fast recovery diode chip (4) is connected to the fourth buffer layer (30) of the first phase through the eleventh solder layer (23) of the first phase, and the fourth buffer layer (30) of the first phase is connected to the first upper copper layer (37) of the lower copper-clad ceramic substrate through the twelfth solder layer (24) of the first phase.

4. The staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels according to claim 2 is characterized by: The second phase IPM unit (58) comprises a second upper bridge arm unit and a second lower bridge arm unit; The second upper bridge arm unit comprises a third high-voltage SiC MOSFET chip (5) and a third fast recovery diode chip (6); the drain electrode on the lower surface of the third high-voltage SiC MOSFET chip (5) is connected to the second upper copper layer (38) of the lower copper-clad ceramic substrate via the second-phase first solder layer (62); the source electrode on the upper surface of the third high-voltage SiC MOSFET chip (5) is connected to the second-phase first buffer layer (76) via the second-phase second solder layer (63); and the second-phase first buffer layer (76) is connected to the first lower copper layer (42) of the upper copper-clad ceramic substrate via the second-phase third solder layer (64); The cathode on the lower surface of the third fast recovery diode chip (6) is connected to the second upper copper layer (38) of the lower copper-clad ceramic substrate via the second phase fourth solder layer (65), the anode on the upper surface of the third fast recovery diode chip (6) is connected to the second phase second buffer layer (77) via the second phase fifth solder layer (66), and the second phase second buffer layer (77) is connected to the first lower copper layer (42) of the upper copper-clad ceramic substrate via the second phase sixth solder layer (67); The second lower bridge arm unit comprises a fourth high-voltage SiC MOSFET chip (7) and a fourth fast recovery diode chip (8); the drain electrode on the upper surface of the fourth high-voltage SiC MOSFET chip (7) is connected to the second lower copper layer (43) of the upper copper-clad ceramic substrate via the seventh solder layer (68) of the second phase; the source electrode on the lower surface of the fourth high-voltage SiC MOSFET chip (7) is connected to the third buffer layer (78) of the second phase via the eighth solder layer (69) of the second phase; and the third buffer layer (78) of the second phase is connected to the second upper copper layer (38) of the lower copper-clad ceramic substrate via the ninth solder layer (70) of the second phase; The cathode on the upper surface of the fourth fast recovery diode chip (8) is connected to the second lower copper layer (43) of the upper copper-clad ceramic substrate through the second phase tenth solder layer (71), the anode on the lower surface of the fourth fast recovery diode chip (8) is connected to the second phase fourth buffer layer (79) through the second phase eleventh solder layer (72), and the second phase fourth buffer layer (79) is connected to the second upper copper layer (38) of the lower copper-clad ceramic substrate through the second phase twelfth solder layer (73).

5. The staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels according to claim 1 is characterized by: The third-phase IPM unit (59) comprises a third upper bridge arm unit and a first lower bridge arm unit; The third upper bridge arm unit comprises a fifth high-voltage SiC MOSFET chip (9) and a fifth fast recovery diode chip (10); the drain electrode on the lower surface of the fifth high-voltage SiC MOSFET chip (9) is connected to the third upper copper layer (39) of the lower copper-clad ceramic substrate via a third-phase first solder layer (80); the source electrode on the upper surface of the fifth high-voltage SiC MOSFET chip (9) is connected to the third-phase first buffer layer (94) via a third-phase second solder layer (81); and the third-phase first buffer layer (94) is connected to the first lower copper layer (42) of the upper copper-clad ceramic substrate via a third-phase third solder layer (82); The cathode on the lower surface of the fifth fast recovery diode chip (10) is connected to the third upper copper layer (39) of the lower copper-clad ceramic substrate via the third phase fourth solder layer (83), the anode on the upper surface of the fifth fast recovery diode chip (10) is connected to the third phase second buffer layer (95) via the third phase fifth solder layer (84), and the third phase second buffer layer (95) is connected to the first lower copper layer (42) of the upper copper-clad ceramic substrate via the third phase sixth solder layer (85); The third lower bridge arm unit comprises a sixth high-voltage SiC MOSFET chip (11) and a sixth fast recovery diode chip (12); the drain electrode on the upper surface of the sixth high-voltage SiC MOSFET chip (11) is connected to the second lower copper layer (43) of the upper copper-clad ceramic substrate via a third-phase seventh solder layer (86); the source electrode on the lower surface of the sixth high-voltage SiC MOSFET chip (11) is connected to the third-phase third buffer layer (96) via a third-phase eighth solder layer (87); and the third-phase third buffer layer (96) is connected to the third upper copper layer (39) of the lower copper-clad ceramic substrate via a third-phase ninth solder layer (88); The cathode on the upper surface of the sixth fast recovery diode chip (12) is connected to the second lower copper layer (43) of the upper copper-clad ceramic substrate through the third phase tenth solder layer (89), the anode on the lower surface of the sixth fast recovery diode chip (12) is connected to the third phase fourth buffer layer (97) through the third phase eleventh solder layer (90), and the third phase fourth buffer layer (97) is connected to the third upper copper layer (39) of the lower copper-clad ceramic substrate through the third phase twelfth solder layer (91).

6. The staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels according to claim 3 is characterized by: The gate on the upper surface of the first high-voltage SiC MOSFET chip (1) is connected to the first copper sheet (50) via the first phase thirteenth solder layer (25), the first copper sheet (50) is connected to the upper bridge arm driver chip (47) via the upper bridge arm PCB board (46), the gate on the lower surface of the second high-voltage SiC MOSFET chip (3) is connected to the fourth copper sheet (53) via the first phase fourteenth solder layer (26), the fourth copper sheet (53) is connected to the lower bridge arm driver chip (49) via the lower bridge arm PCB board (48).

7. The staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels according to claim 4 is characterized by: The gate on the upper surface of the third high-voltage SiC MOSFET chip (5) is connected to the second copper sheet (51) via the second phase thirteenth solder layer (74); the second copper sheet (51) is connected to the upper bridge arm drive chip (47) via the upper bridge arm PCB board (46); the gate on the lower surface of the third high-voltage SiC MOSFET chip (7) is connected to the fifth copper sheet (54) via the second phase fourteenth solder layer (75); the fifth copper sheet (54) is connected to the lower bridge arm drive chip (49) via the lower bridge arm PCB board (48).

8. The staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels according to claim 5 is characterized by: The gate on the upper surface of the fifth high-voltage SiC MOSFET chip (9) is connected to the third copper sheet (52) via the third phase thirteenth solder layer (92), and the third copper sheet (52) is connected to the upper bridge arm drive chip (47) via the upper bridge arm PCB board (46); the gate on the lower surface of the sixth high-voltage SiC MOSFET chip (11) is connected to the sixth copper sheet (55) via the third phase fourteenth solder layer (93), and the sixth copper sheet (55) is connected to the lower bridge arm drive chip (49) via the lower bridge arm PCB board (48).

9. The staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels according to claim 2 is characterized by: The ceramic layer (41) of the upper copper-clad ceramic substrate and the ceramic layer (36) of the lower copper-clad ceramic substrate are both made of aluminum nitride ceramic or aluminum oxide ceramic; the upper copper layer (40) of the upper copper-clad ceramic substrate is embedded in the upper cooling channel (45), and the lower copper layer (35) of the lower copper-clad ceramic substrate is embedded in the lower cooling channel (44).

10. The staggered distributed double-sided heat dissipation high-power IPM packaging structure with cooling channels according to claim 2 is characterized by: The heat sink comprises an upper heat sink (32) and a lower heat sink (31); the upper heat sink (32) is connected to an upper copper layer (40) of the upper copper-clad ceramic substrate via an upper thermally conductive silicone grease layer (34); and the lower heat sink (31) is connected to a lower copper layer (35) of the lower copper-clad ceramic substrate via a lower thermally conductive silicone grease layer (33).

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