Method for suppressing transient noise of double-step-down symmetrical half-bridge power converter switch

Abstract

The invention discloses a method for suppressing switching transient noise of a double-step-down symmetrical half-bridge power converter, and relates to the technical field of power motor driving. Four PCB layout optimization schemes are provided. According to the first scheme, a double-step-down symmetrical half-bridge power converter, four driving loops and four additional auxiliary sources form a vertical layout. In the second scheme, distributed filter capacitors are arranged on the basis of the first scheme; according to the third scheme, a double-step-down symmetrical half-bridge power converter, four driving loops, four additional auxiliary sources and a distributed filter capacitor form a horizontal staggered layout. According to the fourth scheme, two separation grooves are formed on the basis of the third scheme. Based on a circuit-level switch analysis model, a layout method for reducing mutual coupling of parasitic inductors of a power loop is provided, parasitic parameters of a PCB are optimized, transient oscillation of a switch can be suppressed, the precision of output current is improved, and the application requirement under a high-precision occasion is better met.

Description

Technical Field

[0001] The invention relates to the technical field of power motor drive, and in particular to a method for suppressing switching transient noise of a dual-buck symmetrical half-bridge power converter. Background Art

[0002] The output current distortion of high-precision power converters can cause unnecessary positioning fluctuations in ultra-precision motors, which has a serious impact on precision control systems. The inventors have previously developed a dual-buck symmetrical half-bridge power converter in a composite current-driven hybrid power converter. The patent name is composite current-driven hybrid power amplifier, application number: CN202310051995.3, which has greater interleaving flexibility and faster current dynamic response, and can suppress the different voltage drops at the midpoint of the bridge arm during switch on and off, and has the ability to output high-precision current. However, GaN HEMT will cause serious switching oscillations, which can easily cause the device to mis-convert or even break down the device, especially at high frequencies. It is one of the main sources of distortion in dual-buck symmetrical half-bridge power converters based on GaN HEMTs.

[0003] There are few studies on the existing GaN HEMT switch characteristic analysis model, and few studies analyze the switch behavior from the power converter level. The circuit-level switch analysis model for the dual-buck symmetrical half-bridge power converter is still relatively lacking. Therefore, it is necessary to establish a dual-buck symmetrical half-bridge power converter switch analysis model and deeply analyze the influence of different parasitic parameters on the switching transient characteristics from the circuit perspective. However, the traditional piecewise linear model, which is widely used in the switch analysis model, can simply and quickly estimate the switch waveform, but simplifies the influence of parasitic parameters and nonlinear terms. In high-frequency conditions, the calculated results do not match the experimental results. Summary of the invention

[0004] In order to overcome the shortcomings of the background technology, the present invention provides a method for suppressing the transient noise of the switch of a dual-buck symmetrical half-bridge power converter. Based on a circuit-level switch analysis model, the present invention proposes a layout method for reducing the mutual coupling of parasitic inductances in the power loop, optimizes the PCB parasitic parameters, can suppress the transient oscillation of the switch, improves the output current accuracy, and better meets the application requirements in high-precision occasions.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A method for suppressing switching transient noise of a dual-step-down symmetrical half-bridge power converter, wherein the dual-step-down symmetrical half-bridge power converter comprises switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2 , load inductance L and load resistance R, parasitic inductance L of the drain lineD1 , L D2 , L D3 , L D4 , the parasitic inductance L of the source line S1 , L S2 , L S3 , L S4 And dual voltage source U i1 , U i2 The inductor L is set on the corresponding PCB layout. o and L n ;

[0007] The L D1 One end is connected to the positive terminal of S1, and the negative terminal of S1 is connected to L S1 One end of the L S1 The other end is connected to the positive terminal of D1, the negative terminal of D1 is connected to the negative terminal of D2, and the positive terminal of D2 is connected to L D2 One end of the L D2 The other end is connected to the positive terminal of S2, and the negative terminal of S2 is connected to L S2 One end of L1 forms a first symmetrical bridge arm, the midpoint of which is connected to one end of L2; D3 One end is connected to the positive terminal of S3, and the negative terminal of S3 is connected to L S3 One end of the L S3 The other end is connected to the negative terminal of D3, the positive terminal of D3 is connected to the positive terminal of D4, and the negative terminal of D4 is connected to L D4 One end of the L D4 The other end is connected to the positive terminal of S4, and the negative terminal of S4 is connected to L S4 The other ends of L1 and L2 are connected to L and R and C f1 and C f2 The midpoint of the connection; f1 The other end is connected to L D3 The other end of the C f2 The other end is connected to L S4 The other end of L D1 and L D3 Through the L o Connect the L S2 and the L S4 Through the L n Connection; L D1 The other end is connected to U i1 The positive terminal of the U i1 The negative terminal is connected to U i2 The positive terminal, LS2 The other end is connected to the U i2 The negative end of

[0008] The dual-buck symmetrical half-bridge power converter is provided with four drive loops and four additional auxiliary source electrodes, forming a vertical layout of the dual-buck symmetrical half-bridge power converter;

[0009] A driving circuit is set in each of the four switches, and the driving circuit includes a driving power supply, a driving resistor and a gate parasitic inductance. The positive terminal of the driving power supply is connected to one end of the driving resistor, and the other end of the driving resistor is connected to the gate of the corresponding switch. The negative terminal of the driving power supply is connected to one end of the gate parasitic inductance, and the other end of the gate parasitic inductance is connected to the negative terminal of the corresponding switch through the additional auxiliary source and the parasitic inductance of the corresponding source line.

[0010] Furthermore, the dual-buck symmetrical half-bridge power converter is further provided with distributed filter capacitors, including capacitors C1 to C n+1 , capacitors C1~C n Connect in parallel with U i1 and U i2 The two ends of the capacitor C n Close to the first symmetrical bridge arm, capacitor C n+1 Connect in parallel between the first symmetrical bridge arm and the second symmetrical bridge arm, and o and L n Separated into two sections, the L o Separated into L o1 and L o2 , the L n Separated into L n1 and L n2 , capacitor C n+1 Connect one end to the L o1 and the L o2 The midpoint of the capacitor C n+1 The other end is connected to the L n1 and the L n2 The midpoint of .

[0011] A method for suppressing switching transient noise of a dual-step-down symmetrical half-bridge power converter, wherein the dual-step-down symmetrical half-bridge power converter comprises switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2 , load inductance L and load resistance R, parasitic inductance L of the drain line D1 , L D2 , L D3 , L D4 , the parasitic inductance L of the source line S1 , L S2 , LS3 , L S4 And dual voltage source U i1 , U i2 The inductor L is set on the corresponding PCB layout. o and L n ;

[0012] The positive terminal of D2 is connected to L D2 One end of the L D2 The other end is connected to the positive terminal of S2, and the negative terminal of S2 is connected to L S2 The negative terminal of D4 is connected to L D4 One end of the L D4 The other end is connected to the positive terminal of S4, and the negative terminal of S4 is connected to L S4 The positive terminal of D1 is connected to L S1 One end of the L S1 The other end is connected to the negative terminal of S1, and the positive terminal of S1 is connected to L D1 The negative terminal of D3 is connected to L S3 One end of the L S3 The other end is connected to the negative terminal of S3, and the positive terminal of S3 is connected to L D3 The negative end of D1 is connected to the negative end of D2, and at the same time, the negative end of D1 is connected to one end of L1; the positive end of D3 is connected to the positive end of D4, and at the same time, the positive end of D3 is connected to one end of L2; the other ends of L1 and L2 are connected to L and R and C f1 and C f2 The midpoint of the connection; f1 The other end is connected to L D3 The other end of the C f2 The other end is connected to L S4 The other end of L D1 and the L D3 Through the L o Connect the L S2 and the L S4 Through the L n Connection; L D1 The other end is connected to U i1 The positive terminal of the U i1 The negative terminal is connected to U i2 The positive terminal, L S2 The other end is connected to the U i2 The negative end of

[0013] The dual-buck symmetrical half-bridge power converter is provided with four drive loops, four additional auxiliary source electrodes and distributed filter capacitors, forming a horizontally staggered layout of the dual-buck symmetrical half-bridge power converter;

[0014] A driving circuit is respectively provided on the four switches, wherein the driving circuit includes a driving power supply, a driving resistor and a gate parasitic inductance, wherein the positive terminal of the driving power supply is connected to one end of the driving resistor, the other end of the driving resistor is connected to the gate of the corresponding switch, the negative terminal of the driving power supply is connected to one end of the gate parasitic inductance, and the other end of the gate parasitic inductance is connected to the negative terminal of the corresponding switch through an additional auxiliary source and the parasitic inductance of the corresponding source line;

[0015] The distributed filter capacitor includes capacitors C1 to C n+1 , capacitors C1~C n+1 Connect in parallel with U i1 and U i2 The two ends of the capacitor C n Close to the bridge arm where S1, S2 and D1, D2 are located, capacitor C n+1 Close to the bridge arms where S3, S4, D3 and D4 are located.

[0016] Furthermore, the L o and the L n The L is symmetrically divided into two sections by adding separation grooves under S2 and S4 and under S1 and S3. o Separated into L o1 and L o2 , L n Separated into L n1 and L n2 , where the capacitor C n+1 Connect U i2 Connect the negative terminal to the L n1 and the L n2 The midpoint of the capacitor C n+1 Connect U i1 Connect the positive end to the L o1 and the L o2 The midpoint of .

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention takes into account the nonlinear characteristics of circuit parasitic inductance, junction capacitance and transconductance of power devices, establishes a circuit-level switch analysis model of a dual-buck symmetrical half-bridge power converter based on GaN HEMT, solves the problems of inaccuracy of traditional piecewise linear models and lack of circuit-level switch analysis models of power amplifiers, and proposes a layout method for reducing mutual coupling of parasitic inductance of power loops based on the circuit-level switch analysis model, optimizes PCB parasitic parameters, solves the disadvantage of severe transient oscillation of GaN HEMT switches in a high-frequency state, improves the output waveform quality of the dual-buck symmetrical half-bridge power converter, can suppress transient oscillation of switches, improves output current accuracy, and better meets application requirements in high-precision occasions. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a topological diagram of the circuit structure of the existing dual-buck symmetrical half-bridge power converter;

[0019] Figure 2 yes Figure 1 Topological diagram of the circuit-level switch analysis model;

[0020] Figure 3 yes Figure 2 Modal analysis topology diagram during the S1 opening period;

[0021] Figure 4 yes Figure 2 Modal analysis topology diagram during S1 shutdown period;

[0022] Figure 5 yes Figure 2 Modal analysis topology diagram during the S4 opening period;

[0023] Figure 6 yes Figure 2 Modal analysis topology diagram during S4 shutdown period;

[0024] Figure 7 is a topological diagram of scheme 1 in a specific implementation mode;

[0025] Figure 8 is a topological diagram of scheme 2 in a specific implementation mode;

[0026] Fig. 9 It is a topological diagram of scheme 3 in a specific implementation mode;

[0027] Fig.10 It is a topological diagram of scheme 4 in the specific implementation method. DETAILED DESCRIPTION

[0028] The technical solution of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0029] The inventor previously submitted an invention patent application with application date of February 2, 2023, application number CN202310051995.3, and titled A Composite Current Driven Hybrid Power Amplifier, which discloses a dual-buck symmetrical half-bridge power converter circuit structure, and the topology diagram is combined with Figure 1 shown.

[0030] The switch analysis model is as follows:

[0031] Considering the nonlinear parasitic parameters of GaN HEMT and diode, driving loop and circuit routing parasitic parameters, the circuit-level switch analysis model is combined with Figure 2 As shown. Using U i1 and U i2 It is powered by a dual voltage source and consists of two Buck circuits, four drive loops, two LC filter links and a load, where:

[0032] The first Buck circuit consists of switches S1 and S2, drain-source parasitic capacitance C ds1 and C ds2 , diodes D1 and D2, diode nonlinear junction capacitance C D1 and C D2 , the parasitic inductance L of the drain line D1 and L D2 , the parasitic inductance L of the source line S1 and L S2 And line parasitic resistance R1 and R2. The positive terminal of S1 is connected to L D1 One end, L D1 The other end of S1 is connected to R1, and the negative end of S1 is connected to L S1 One end, L S1 The other end is connected to the positive terminal of D1, and the negative terminal of D1 is connected to L D2 One end, L D2 The other end is connected to the positive terminal of S2, and the negative terminal of S2 is connected to L S2 One end, L S2 The other end is connected to the negative terminal of D2, and the positive terminal of D2 is connected to R2. ds1 , C ds2 , C D1 , C D2Connected in parallel at both ends of S1, S2, D1, and D2 respectively, and the other end of R1 is connected to the voltage source U i1 The positive terminal of R2 is connected to the voltage source U i2 Negative terminal.

[0033] The second Buck circuit consists of switches S3 and S4, drain-source parasitic capacitance C ds3 and C ds4 , diodes D3 and D4, diode nonlinear junction capacitance C D3 and C D4 , the parasitic inductance L of the drain line D3 and L D4 , the parasitic inductance L of the source line S3 and L S4 And line parasitic resistance R3 and R4. The positive terminal of S3 is connected to L D3 One end, L D3 The other end is connected to the positive terminal of D3, the negative terminal of D3 is connected to R3, and the negative terminal of S3 is connected to L S3 One end, L S3 The other end is connected to the positive terminal of D4, and the negative terminal of D4 is connected to L D4 One end, L D4 The other end is connected to the positive terminal of S4, and the negative terminal of S4 is connected to L S4 One end, L S4 The other end is connected to one end of R4, C ds3 , C ds4 , C D3 , C D4 They are connected in parallel at both ends of S3, S4, D3, and D4 respectively, and the other end of R3 is connected to the voltage source U i1 The positive terminal of R4 is connected to the voltage source U i2 Negative terminal.

[0034] The first drive circuit consists of a drive power supply V G1 , driving resistance R G1 , gate parasitic inductance L G1 , gate-source parasitic capacitance C gs1 And the gate-drain parasitic capacitance C gd1 Composition. G1 The positive terminal is connected to L G1 One end, L G1 The other end is connected to R G1 One end, R G1 The other end is connected to C gd1 and C gs1 One end, C gs1 The other end is connected to V G1 The negative terminal, C gd1The other end of is connected to the positive terminal of S1.

[0035] The second drive circuit consists of a drive power supply V G2 , driving resistance R G2 , gate parasitic inductance L G2 , gate-source parasitic capacitance C gs2 And the gate-drain parasitic capacitance C gd2 Composition. G2 The positive terminal is connected to L G2 One end, L G2 The other end is connected to R G2 One end, R G2 The other end is connected to C gd2 and C gs2 One end, C gs2 The other end is connected to V G2 The negative terminal, C gd2 The other end is connected to the positive terminal of S2.

[0036] The third drive circuit consists of a drive power supply V G3 , driving resistance R G3 , gate parasitic inductance L G3 , gate-source parasitic capacitance C gs3 And the gate-drain parasitic capacitance C gd3 Composition. G3 The positive terminal is connected to L G3 One end, L G3 The other end is connected to R G3 One end, R G3 The other end is connected to C gd3 and C gs3 One end, C gs3 The other end is connected to V G3 The negative terminal, C gd3 The other end of is connected to the positive terminal of S3.

[0037] The fourth drive circuit is driven by the drive power supply V G4 , driving resistance R G4 , gate parasitic inductance L G4 , gate-source parasitic capacitance C gs4 And the gate-drain parasitic capacitance C gd4 Composition. G4 The positive terminal is connected to L G4 One end, L G4 The other end is connected to R G4 One end, R G4 The other end is connected to C gd4 and C gs4 One end, C gs4 The other end is connected to V G4The negative terminal of, C gd4 The other end is connected to the positive terminal of S4.

[0038] The first LC filtering section consists of the inductor L1, capacitor C f1 and the parasitic resistor R L1 It consists of. One end of L1 is connected to one end of R L1 of, R L1 The other end is connected to the negative terminal of D1, and the other end of L1 is connected to one end of C f1 of, C f1 The other end is connected to the positive terminal of the voltage source U i1 positive terminal.

[0039] The second LC filtering section consists of the inductor L2, capacitor C f2 and the parasitic resistor R L2 It consists of. One end of L2 is connected to one end of R L2 of, R L2 The other end is connected to the positive terminal of D4, and the other end of L2 is connected to one end of C f2 of, C f2 The other end is connected to the negative terminal of the voltage source U i2 negative terminal.

[0040] The load inductor L and load resistor R of the load part are equivalently replaced by the output current i L flowing through.

[0041] The modal analysis is as follows:

[0042] (1) The turn-on process of S1

[0043] The turn-on process of S1 in the GaN HEMT-based dual buck symmetric half-bridge power converter can be divided into four stages: the S1 conduction delay period, the drain-source voltage drop period, the diode turn-on oscillation period, and the S1 turn-on oscillation period. Combining Figure 3 shown, where (a) shows Mode1: the S1 conduction delay period, (b) shows Mode2: the drain-source voltage drop period, (c) to (f) show Mode3: the diode turn-on oscillation period, and (g) to (h) show Mode4: the S1 turn-on oscillation period.

[0044] Mode1[t0 < t < t1]: S1 conduction delay

[0045] At the moment t0, V G1 changes from low to high, and the drive current i g1 charges C gs1 and C gd1 The drain-source voltage v ds1 and the drain current i D1 remain unchanged. From Figure 3(a) The following equations can be derived:

[0046]

[0047] When the gate-source voltage v gs1 rises to the threshold voltage v th1 this mode ends.

[0048] Mode2[t1<t<t2]: Drain-source voltage drop period

[0049] At time t1, the channel current i ch1 is controlled by v gs1 C gd1 C ds1 and C D1 discharge and oscillate with the parasitic inductance in the circuit. During the Miller plateau stage of the device, i g1 mainly charges C gd1 and v ds1 rapidly drops. At the same time, the slow increase in v gs1 causes the slow rise of i ch1 and the Miller plateau delays the turn-on time of the device. From Figure 3 (b) The following equations can be derived, where R loop represents the high-frequency damping resistor and has an inhibitory effect on the oscillation:

[0050]

[0051] When v ds1 drops to 0, this mode ends.

[0052] Mode3[t2<t<t3]: Diode turn-on oscillation period

[0053] At time t2, S1 is basically turned on and i ch1 is not controlled by v gs1 and from Figure 3 (c) it can be seen that:

[0054]

[0055] C D1 continues to discharge. When the voltage v D1 across D1 reaches the turn-on voltage of D1, D1 conducts, as shown in Figure 3 (d). When the drain current i D2 drops to 0, C D2 participates in the resonance, as shown in Figure 3 (e). Specifically, which one arrives first is related to the circuit parameters. When the stray inductance in the circuit is large or the load current is large, the falling speed of i d2 is delayed. When C D1When it is larger, the capacitor discharge time is longer. Whenever i D1 When the oscillation is 0, D1 turns off. The loop inductor and capacitors C D1 、C D2 、C ds1 、C ds2 resonate, and i D2 charges C D1 , as shown in Figure 3 (f). When v D1 reaches the turn-on voltage of D1, D1 starts to conduct again, as shown in Figure 3 (e). D1 switches on and off repeatedly during the oscillation until the voltage across C D2 drops to a certain extent and no longer generates a discharge current greater than the inductor current i L1 to charge C D1 , and D1 is fully conducting, and this mode ends.

[0056] Mode4[t3<t<t4]: S1 turn-on oscillation period

[0057] At time t3, D1 is fully conducting, but the parasitic inductance and parasitic capacitance in the circuit form a second-order oscillation circuit, which is an underdamped system. From Figure 3 (g), the following oscillation equation can be derived:

[0058]

[0059] When the oscillation is completely attenuated, this process ends, and the S1 turn-on process ends, as shown in Figure 3 (h).

[0060] (2) S1 turn-off process

[0061] The S1 turn-off process of the dual buck symmetric half-bridge power converter based on GaN HEMT can be divided into three stages: S1 turn-off delay period, drain-source voltage rise period, and S1 turn-off oscillation period. Combining Figure 4 shown, where (a) shows Mode1: S1 turn-off delay period, (b) - (d) show Mode2: drain-source voltage rise period, and (e) - (f) show Mode3: S1 turn-off oscillation period.

[0062] Mode1[t0<t<t1]: S1 turn-off delay period

[0063] At time t0, V G1 changes from high to low level, C gs1 and C gd1 discharge, v ds1 and i D1 remain unchanged. From Figure 4 (a), the following equation can be derived:

[0064]

[0065] When the channel current i ch1 is controlled by the driving voltage v gs1 S1 starts to turn off and this mode ends.

[0066] Mode2[t1<t<t2]: Rising period of drain-source voltage

[0067] At time t1, the channel current i ch1 is controlled by v gs1 As v gs1 decreases, i ch1 also decreases accordingly. Since the falling speed of the channel current i ch1 is faster than that of the current i D1 the current difference charges C ds1 and C gd1 and v ds1 rises. The current difference between i D1 and i L1 discharges the capacitor C D2 and the voltage v D2 across D2 decreases. From Figure 4 (b), the following equation can be derived:

[0068]

[0069] When i ch1 drops to 0, the channel current of S1 turns off, as shown in Figure 4 (c). C D2 continues to discharge and v D2 continues to decrease. When v D2 reaches the turn-on voltage, D2 conducts, as shown in Figure 4 (d). i d1 continues to charge C ds1 until i d1 drops to 0 and D1 turns off, and this mode ends.

[0070] Mode3[t2<t<t3]: Oscillation period when S1 is off

[0071] At time t2, D1 turns off, and there is an underdamped parasitic oscillation between C D1 and the loop inductor, C ds1 and C ds2 From Figure 4 (e), the following equation can be derived:

[0072]

[0073] When the oscillation is completely attenuated, S1 is completely turned off, as shown in Figure 4As shown in (f), the turn-off process ends.

[0074] (3) Turn-on process of S4

[0075] The turn-on process of the double buck symmetric half-bridge power converter based on GaN HEMT can be divided into four stages: the S4 conduction delay period, the drain-source voltage drop period, the diode turn-on oscillation period, and the S4 turn-on oscillation period. As shown in Figure 5 , where (a) shows Mode1: S1 conduction delay period, (b) shows Mode2: drain-source voltage drop period, (c) - (f) show Mode3: diode turn-on oscillation period, and (g) - (h) show Mode4: S4 turn-on oscillation period.

[0076] Mode1 [t’0 < t < t’1]: S4 conduction delay

[0077] At time t’0, V G4 changes from low to high, and the drive current i g4 charges C gs4 and C gd4 . The drain-source voltage v ds4 and the drain current i D4 remain unchanged. From Figure 5 (a), the following equation can be deduced:

[0078]

[0079] When the gate-source voltage v gs4 rises to the threshold voltage v th4 , this mode ends.

[0080] Mode2 [t’1 < t < t’2]: Drain-source voltage drop period

[0081] At time t’1, the channel current i ch4 is controlled by v gs4 . C gd4 , C ds4 and C D4 discharge and oscillate with the parasitic inductance in the circuit. During the Miller plateau stage of the device, i g4 mainly charges C gd4 , and v ds4 rapidly drops. At the same time, the slow increase of v gs4 causes the slow rise of i ch4 . The Miller plateau delays the turn-on time of the device. From Figure 5 (b), the following equation can be deduced, where R’ loop represents the high-frequency damping resistance, which has an inhibitory effect on the oscillation:

[0082]

[0083] When v ds4 drops to 0, this mode ends.

[0084] Mode3[t’2 < t < t’3]: Diode conduction oscillation period

[0085] At t’2, S4 is basically conducting, and i ch4 is not controlled by v gs4 and is determined by Figure 5 (c) as follows:

[0086]

[0087] C D4 continues to discharge. When the voltage v D4 across D4 reaches the turn-on voltage of D4, D4 conducts, as shown in Figure 5 (d). When the drain current i D3 drops to 0, C D3 participates in resonance, as shown in Figure 5 (e). Specifically, which one reaches first is related to the circuit parameters. When the stray inductance of the loop is large or the load current is large, the decline rate of i d3 slows down. When C D4 is larger, the capacitor discharge time is longer. Whenever i D4 oscillates to 0, D4 turns off. The loop inductance resonates with capacitors C D4 、C D4 、C ds4 、C ds4 and i D3 charges C D4 , as shown in Figure 5 (f). When v D4 reaches the turn-on voltage of D4, D4 starts to conduct again, as shown in Figure 5 (e). D4 switches on and off repeatedly during the oscillation until the voltage across C D3 drops to a certain level and no longer generates a discharge current greater than the inductor current i L4 of L4 to charge C D4 , and D4 is fully conducting, and this mode ends.

[0088] Mode4[t’3 < t < t’4]: S4 conduction oscillation period

[0089] At t’3, D4 is fully conducting, but the parasitic inductance and parasitic capacitance in the circuit form a second-order oscillation circuit, which is an underdamped system. From Figure 5 (g), the following oscillation equation can be deduced:

[0090]

[0091] When the oscillation completely decays, this process ends, and the S4 turn-on process ends, as shown in Figure 5 (h).

[0092] (4) S4 turn-off process

[0093] The S4 turn-off process of the dual buck symmetric half-bridge power converter based on GaN HEMT can be divided into three stages: the S4 turn-off delay period, the drain-source voltage rise period, and the S4 turn-off oscillation period. Combining Figure 6 as shown, where (a) shows Mode1: the S4 turn-off delay period, (b) - (d) show Mode2: the drain-source voltage rise period, and (e) - (f) show Mode3: the S4 turn-off oscillation period.

[0094] Mode1[t’0 < t < t’1]: S4 turn-off delay period

[0095] At time t’0, V G4 changes from high to low level, C gs4 and C gd4 discharge, v ds4 and i D4 remain unchanged. From Figure 6 (a), the following equation can be deduced:

[0096]

[0097]

[0098] When the channel current i ch4 is controlled by the drive voltage v gs4 , S4 starts to turn off, and this mode ends.

[0099] Mode2[t’1 < t < t’2]: Drain-source voltage rise period

[0100] At time t’1, the channel current i ch4 is controlled by v gs4 . As v gs4 decreases, i ch4 will also decrease accordingly. Since the channel current i ch4 decreases faster than the current i D4 , the current difference between them charges C ds4 and C gd4 , and v ds4 increases. The current difference between i D4 and i L4 discharges the capacitor C D3 , and v D3 decreases. From Figure 6 (b), the following equation can be deduced:

[0101]

[0102] When i ch4 drops to 0, the S4 channel current turns off, as shown in Figure 6 (c). C D3 Continues to discharge, and v D3 continues to decrease. When v D3 reaches the turn-on voltage, D3 conducts, as shown in Figure 6 (d). i d4 Continues to charge C ds4 until i d4 drops to 0, at which time D4 turns off and this mode ends.

[0103] Mode3[t’2<t<t’3]: S4 turn-off oscillation period

[0104] At time t’2, D4 turns off, and C D4 has underdamped parasitic oscillations with the loop inductor, C ds4 , C ds3 . The following equation can be derived from Figure 6 (e):

[0105]

[0106] When the oscillation is completely damped, S4 is completely turned off, as shown in Figure 6 (f), and the turn-off process ends.

[0107] From the modal analysis of the circuit-level switch analysis model of the dual buck symmetric half-bridge power converter, it can be seen that the oscillation process of the power device is mainly affected by the junction capacitance of the power device and the stray inductance of the PCB loop. Combining with Figure 7 to Figure 10 shown, a method for suppressing the switching transient noise of the dual buck symmetric half-bridge power converter is proposed, including four PCB layout optimization schemes, which are specifically as follows:

[0108] Scheme 1

[0109] Combining with Figure 7 shown, it consists of a dual buck symmetric half-bridge power converter, four drive loops and four additional auxiliary sources, forming a vertical layout of the dual buck symmetric half-bridge power converter.

[0110] The dual buck symmetric half-bridge power converter consists of switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2 , load inductor L and load resistor R, parasitic inductances L D1 , L D2 , L D3 , L D4 of the source line, the parasitic inductance LS1 , L S2 , L S3 , L S4 And dual voltage source U i1 , U i2 The inductor L is set on the corresponding PCB layout. o and L n The parasitic inductance L of the drain line D1 One end is connected to the positive terminal of switch S1, and the negative terminal of switch S1 is connected to the parasitic inductance L of the source line. S1 At one end, the parasitic inductance L of the source line S1 The other end is connected to the positive terminal of the diode D1, the negative terminal of the diode D1 is connected to the negative terminal of the diode D2, and the positive terminal of the diode D2 is connected to the parasitic inductance L of the drain line. D2 At one end, the parasitic inductance L of the drain line D2 The other end is connected to the positive terminal of switch S2, and the negative terminal of switch S2 is connected to the parasitic inductance L of the source line. S2 The parasitic inductance L of the drain line is L D3 One end of the switch is connected to the positive terminal of the switch S3, and the negative terminal of the switch S3 is connected to the parasitic inductance L of the source line. S3 At one end, the parasitic inductance L of the source line S3 The other end is connected to the cathode end of the diode D3, the anode end of the diode D3 is connected to the anode end of the diode D4, and the cathode end of the diode D4 is connected to the parasitic inductance L of the drain line. D4 At one end, the parasitic inductance L of the drain line D4 The other end is connected to the positive terminal of switch S4, and the negative terminal of switch S4 is connected to the parasitic inductance L of the source line. S4 The other ends of inductors L1 and L2 are connected to the load inductor L, load resistor R and capacitor C. f1 and C f2 The midpoint of the connection. Capacitor C f1 The other end is connected to the parasitic inductance L of the drain line D3 The other end of the capacitor C f2 The other end is connected to the parasitic inductance L of the source line S4 The other end of the drain line. D1 and L D3 Through the inductor L o Connection, source line parasitic inductance L S2 and L S4 Through the inductor L n The parasitic inductance L of the drain line D1The other end is connected to the voltage source U i1 The positive terminal of the voltage source U i1 The negative terminal is connected to the voltage source U i2 The positive terminal of the source line has a parasitic inductance L S2 The other end is connected to the voltage source U i2 negative terminal.

[0111] Additional auxiliary sources are added between the gate parasitic inductance and source line parasitic inductance of the four drive loops to achieve decoupling of the gate loop and the power loop. G1 The positive terminal is connected to the driving resistor R G1 One end of the drive resistor R G1 The other end is connected to the gate of switch S1, driving power supply V G1 The negative terminal is connected to the gate parasitic inductance L G1 One end of the gate parasitic inductance L G1 The other end of the source is connected to the source line through the additional auxiliary source and the parasitic inductance L S1 Connected to the negative terminal of switch S1; the driving power supply V G2 The positive terminal is connected to the driving resistor R G2 One end of the drive resistor R G2 The other end is connected to the gate of switch S2, driving power supply V G2 The negative terminal is connected to the gate parasitic inductance L G2 One end of the gate parasitic inductance L G2 The other end of the source is connected to the source line through the additional auxiliary source and the parasitic inductance L S2 Connected to the negative terminal of switch S2. The driving power supply V G3 The positive terminal is connected to the driving resistor R G3 One end of the drive resistor R G3 The other end is connected to the gate of switch S3, driving power supply V G3 The negative terminal is connected to the gate parasitic inductance L G3 One end of the gate parasitic inductance L G3 The other end of the source is connected to the source line through the additional auxiliary source and the parasitic inductance L S3 Connected to the negative terminal of switch S3. The driving power supply V G4 The positive terminal is connected to the driving resistor R G4 One end of the drive resistor R G4 The other end is connected to the gate of switch S4, driving power supply V G4 The negative terminal is connected to the gate parasitic inductance L G4 One end of the gate parasitic inductance L G4 The other end of the source is connected to the source line through the additional auxiliary source and the parasitic inductance LS4 Connected together to the negative terminal of switch S4.

[0112] Solution 2

[0113] Combination Figure 8 As shown, it is composed of a dual-buck symmetrical half-bridge power converter, four driving loops, four additional auxiliary sources and distributed filter capacitors, forming a vertical layout of a dual-buck symmetrical half-bridge power converter with distributed filter capacitors.

[0114] Solution 2 adds distributed filter capacitors based on Solution 1, which consists of n+1 distributed small-capacitance capacitors C1~C n+1 Composition, capacitors C1~C n Connect in parallel to the voltage source U i1 and U i2 The two ends of the capacitor C n Close to the first symmetrical bridge arm, capacitor C n+1 Connect in parallel between the first symmetrical bridge arm and the second symmetrical bridge arm, and replace the inductor L in scheme 1 o and inductor L n Separated into two sections, inductor L o Separated into L o1 and L o2 , inductance L n Separated into L n1 and L n2 , capacitor C n+1 One end is connected to the inductor L o1 and L o2 The midpoint of the capacitor C n+1 The other end is connected to the inductor L n1 and L n2 This layout reduces the coupling between inductors and lowers the parasitic inductance of the power loop.

[0115] Option 3

[0116] Combination Fig. 9 As shown, it is composed of a dual-buck symmetrical half-bridge power converter, four driving loops, four additional auxiliary sources and distributed filter capacitors, forming a horizontally staggered layout of a dual-buck symmetrical half-bridge power converter with distributed filter capacitors.

[0117] The connection method of scheme three is the same as that of scheme two, but the two bridge arms of the dual-buck symmetrical half-bridge power converter are changed from a vertical layout to a horizontal staggered layout, so that the power circuit of each bridge arm maintains the current reverse direction.

[0118] The dual-buck symmetrical half-bridge power converter consists of switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2, load inductance L and load resistance R, parasitic inductance L of the drain line D1 , L D2 , L D3 , L D4 , the parasitic inductance L of the source line S1 , L S2 , L S3 , L S4 And dual voltage source U i1 , U i2 The inductor L is set on the corresponding PCB layout. o and L n The two bridge arms of the dual-buck symmetrical half-bridge power converter are arranged horizontally in an interlaced manner, from left to right: the positive terminal of the diode D2 is connected to the parasitic inductance L of the drain line D2 At one end, the parasitic inductance L of the drain line D2 The other end is connected to the positive terminal of switch S2, and the negative terminal of switch S2 is connected to the parasitic inductance L of the source line. S2 The negative terminal of diode D4 is connected to the parasitic inductance L of the drain line. D4 At one end, the parasitic inductance L of the drain line D4 The other end is connected to the positive terminal of switch S4, and the negative terminal of switch S4 is connected to the parasitic inductance L of the source line. S4 The positive terminal of diode D1 is connected to the parasitic inductance L of the source line. S1 At one end, the parasitic inductance L of the source line S1 The other end is connected to the negative terminal of switch S1, and the positive terminal of switch S1 is connected to the parasitic inductance L of the drain line. D1 The cathode end of diode D3 is connected to the parasitic inductance L of the source line. S3 At one end, the parasitic inductance L of the source line S3 The other end is connected to the negative terminal of switch S3, and the positive terminal of switch S3 is connected to the parasitic inductance L of the drain line. D3 The cathode end of diode D1 is connected to the cathode end of diode D2, and the cathode end of diode D1 is connected to one end of inductor L1. The anode end of diode D3 is connected to the anode end of diode D4, and the anode end of diode D3 is connected to one end of inductor L2. The other ends of inductors L1 and L2 are connected to load inductor L, load resistor R, and capacitor C. f1 and C f2 The midpoint of the connection. Capacitor C f1 The other end is connected to the parasitic inductance L of the drain line D3 The other end of the capacitor C f2 The other end is connected to the parasitic inductance L of the source line S4 The other end of the drain line.D1 and L D3 Through the inductor L o Connection, source line parasitic inductance L S2 and L S4 Through the inductor L n The parasitic inductance L of the drain line D1 The other end is connected to the voltage source U i1 The positive terminal of the voltage source U i1 The negative terminal is connected to the voltage source U i2 The positive terminal of the source line has a parasitic inductance L S2 The other end is connected to the voltage source U i2 negative terminal.

[0119] Additional auxiliary sources are added between the gate parasitic inductance and source line parasitic inductance of the four drive loops to achieve decoupling of the gate loop and the power loop, and the current flowing through the drive loop is also reversed through the horizontal staggered layout. The drive power supply V of the first drive loop G1 The positive terminal is connected to the driving resistor R G1 One end of the drive resistor R G1 The other end is connected to the gate of switch S1, driving power supply V G1 The negative terminal is connected to the gate parasitic inductance L G1 One end of the gate parasitic inductance L G1 The other end of the source is connected to the source line through the additional auxiliary source and the parasitic inductance L S1 Connected to the negative terminal of switch S1; the driving power supply V G2 The positive terminal is connected to the driving resistor R G2 One end of the drive resistor R G2 The other end is connected to the gate of switch S2, driving power supply V G2 The negative terminal is connected to the gate parasitic inductance L G2 One end of the gate parasitic inductance L G2 The other end of the source is connected to the source line through the additional auxiliary source and the parasitic inductance L S2 Connected to the negative terminal of switch S2. The driving power supply V G3 The positive terminal is connected to the driving resistor R G3 One end of the drive resistor R G3 The other end is connected to the gate of switch S3, driving power supply V G3 The negative terminal is connected to the gate parasitic inductance L G3 One end of the gate parasitic inductance L G3 The other end of the source is connected to the source line through the additional auxiliary source and the parasitic inductance L S3 Connected to the negative terminal of switch S3. The driving power supply V G4The positive terminal is connected to the driving resistor R G4 One end of the drive resistor R G4 The other end is connected to the gate of switch S4, driving power supply V G4 The negative terminal is connected to the gate parasitic inductance L G4 One end of the gate parasitic inductance L G4 The other end of the source is connected to the source line through the additional auxiliary source and the parasitic inductance L S4 The first drive loop and the third drive loop are adjacent to each other, and the drive currents of the two drive loops are opposite to each other; the second drive loop and the fourth drive loop are adjacent to each other, and the drive currents of the two drive loops are opposite to each other.

[0120] The distributed filter capacitor consists of n+1 distributed small capacitance capacitors C1~C n+1 Composition, capacitors C1~C n+1 Connect in parallel to the voltage source U i1 and U i2 The two ends of the capacitor C n Close to the bridge arm where switches S1, S2 and diodes D1, D2 are located, capacitor C n+1 Close to the bridge arm where switches S3, S4 and diodes D3, D4 are located.

[0121] Option 4

[0122] Combination Fig.10 As shown, it consists of a dual-buck symmetrical half-bridge power converter, four driving loops, four additional auxiliary sources, distributed filter capacitors and two separation slots.

[0123] Solution 4 is based on Solution 3. Two identical separation slots are added under switches S2 and S4 and switches S1 and S3 respectively, so that the inductor L is set on the PCB layout in Solution 3. o and L n Separated into two sections, inductor L o Separated into L o1 and L o2 , inductance L n Separated into L n1 and L n2 , symmetrical parasitic inductance can reduce the mutual coupling between inductors. Capacitors C1~C n+1 Connect in parallel to the voltage source U i1 and U i2 The two ends of the capacitor C n+1 Connect voltage source U i2 The negative terminal is connected to the inductor L n1 and L n2 The midpoint of the capacitor C n+1 Connect voltage source U i1The positive terminal is connected to the inductor L o1 and L o2 The midpoint of .

[0124] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other forms of assembly without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and range of equivalents of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0125] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for suppressing switching transient noise of a dual-buck symmetrical half-bridge power converter, characterized in that: The dual-buck symmetrical half-bridge power converter consists of switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2 , load inductance L and load resistance R, parasitic inductance L of the drain line D1 , L D2 , L D3 , L D4 , the parasitic inductance L of the source line S1 , L S2 , L S3 , L S4 And dual voltage source U i1 , U i2 The inductor L is set on the corresponding PCB layout. o and L n ; The L D1 One end is connected to the positive terminal of S1, and the negative terminal of S1 is connected to L S1 One end of the L S1 The other end is connected to the positive terminal of D1, the negative terminal of D1 is connected to the negative terminal of D2, and the positive terminal of D2 is connected to L D2 One end of the L D2 The other end is connected to the positive terminal of S2, and the negative terminal of S2 is connected to L S2 One end of L1 forms a first symmetrical bridge arm, the midpoint of which is connected to one end of L2; D3 One end is connected to the positive terminal of S3, and the negative terminal of S3 is connected to L S3 One end of the L S3 The other end is connected to the negative terminal of D3, the positive terminal of D3 is connected to the positive terminal of D4, and the negative terminal of D4 is connected to L D4 One end of the L D4 The other end is connected to the positive terminal of S4, and the negative terminal of S4 is connected to L S4 The other ends of L1 and L2 are connected to L and R and C f1 and C f2 The midpoint of the connection; f1 The other end is connected to L D3 The other end of the C f2 The other end is connected to L S4 The other end of L D1 and L D3 Through the L o Connect the L S2 and the L S4 Through the L n Connection; L D1 The other end is connected to U i1 The positive terminal of the U i1 The negative terminal is connected to U i2 The positive terminal, L S2 The other end is connected to the U i2 The negative end of The dual-buck symmetrical half-bridge power converter is provided with four drive loops and four additional auxiliary source electrodes, forming a vertical layout of the dual-buck symmetrical half-bridge power converter; A driving circuit is set in each of the four switches, and the driving circuit includes a driving power supply, a driving resistor and a gate parasitic inductance. The positive terminal of the driving power supply is connected to one end of the driving resistor, and the other end of the driving resistor is connected to the gate of the corresponding switch. The negative terminal of the driving power supply is connected to one end of the gate parasitic inductance, and the other end of the gate parasitic inductance is connected to the negative terminal of the corresponding switch through the additional auxiliary source and the parasitic inductance of the corresponding source line.

2. The method for suppressing switching transient noise of a dual-buck symmetrical half-bridge power converter according to claim 1, characterized in that: The dual-step-down symmetrical half-bridge power converter is also provided with distributed filter capacitors, including capacitors C1 to C n+1 , capacitors C1~C n Parallel connection in U i1 and U i2 The two ends of the capacitor C n Close to the first symmetrical bridge arm, capacitor C n+1 Connect in parallel between the first symmetrical bridge arm and the second symmetrical bridge arm, and o and L n Separated into two sections, the L o Separated into L o1 and L o2 , the L n Separated into L n1 and L n2 , capacitor C n+1 Connect one end to the L o1 and the L o2 The midpoint of the capacitor C n+1 The other end is connected to the L n1 and the L n2 The midpoint of .

3. A method for suppressing switching transient noise of a dual-buck symmetrical half-bridge power converter, characterized in that: The dual-buck symmetrical half-bridge power converter consists of switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2 , load inductance L and load resistance R, parasitic inductance L of the drain line D1 , L D2 , L D3 , L D4 , the parasitic inductance L of the source line S1 , L S2 , L S3 , L S4 And dual voltage source U i1 , U i2 The inductor L is set on the corresponding PCB layout. o and L n ; The positive terminal of D2 is connected to L D2 One end of the L D2 The other end is connected to the positive terminal of S2, and the negative terminal of S2 is connected to L S2 The negative terminal of D4 is connected to L D4 One end of the L D4 The other end is connected to the positive terminal of S4, and the negative terminal of S4 is connected to L S4 The positive terminal of D1 is connected to L S1 One end of the L S1 The other end is connected to the negative terminal of S1, and the positive terminal of S1 is connected to L D1 The negative terminal of D3 is connected to L S3 One end of the L S3 The other end is connected to the negative terminal of S3, and the positive terminal of S3 is connected to L D3 The negative end of D1 is connected to the negative end of D2, and at the same time, the negative end of D1 is connected to one end of L1; the positive end of D3 is connected to the positive end of D4, and at the same time, the positive end of D3 is connected to one end of L2; the other ends of L1 and L2 are connected to L and R and C f1 and C f2 The midpoint of the connection; f1 The other end is connected to L D3 The other end of the C f2 The other end is connected to L S4 The other end of L D1 and the L D3 Through the L o Connect the L S2 and the L S4 Through the L n Connection; L D1 The other end is connected to U i1 The positive terminal of the U i1 The negative terminal is connected to U i2 The positive terminal, L S2 The other end is connected to the U i2 The negative end of The dual-buck symmetrical half-bridge power converter is provided with four drive loops, four additional auxiliary source electrodes and distributed filter capacitors, forming a horizontally staggered layout of the dual-buck symmetrical half-bridge power converter; A driving circuit is respectively provided on the four switches, wherein the driving circuit includes a driving power supply, a driving resistor and a gate parasitic inductance, wherein the positive terminal of the driving power supply is connected to one end of the driving resistor, the other end of the driving resistor is connected to the gate of the corresponding switch, the negative terminal of the driving power supply is connected to one end of the gate parasitic inductance, and the other end of the gate parasitic inductance is connected to the negative terminal of the corresponding switch through an additional auxiliary source and the parasitic inductance of the corresponding source line; The distributed filter capacitor includes capacitors C1 to C n+1 , capacitors C1~C n+1 Parallel connection in U i1 and U i2 The two ends of the capacitor C n Close to the bridge arm where S1, S2 and D1, D2 are located, capacitor C n+1 Close to the bridge arms where S3, S4, D3 and D4 are located.

4. The method for suppressing switching transient noise of a dual-buck symmetrical half-bridge power converter according to claim 3, characterized in that: The L o and the L n The L is symmetrically divided into two sections by adding separation grooves under S2 and S4 and under S1 and S3. o Separated into L o1 and L o2 , L n Separated into L n1 and L n2 , where the capacitor C n+1 Connect U i2 Connect the negative terminal to the L n1 and the L n2 The midpoint of the capacitor C n+1 Connect U i1 Connect the positive end to the L o1 and the L o2 The midpoint of .

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