A Method for Suppressing Switching Transient Noise of a Dual-Buck Symmetrical Half-Bridge Power Converter

Abstract

A method for suppressing switching transient noise of a dual buck symmetric half-bridge power converter, which relates to the technical field of power supply motor drive. Four PCB layout optimization schemes are provided: Scheme 1 forms a vertical layout by a dual buck symmetric half-bridge power converter, four drive circuits and four additional auxiliary source electrodes; Scheme 2 sets distributed filter capacitors on the basis of Scheme 1; Scheme 3 forms a horizontal staggered layout by a dual buck symmetric half-bridge power converter, four drive circuits, four additional auxiliary source electrodes and distributed filter capacitors; Scheme 4 sets two separation slots on the basis of Scheme 3. Based on the circuit-level switching analysis model, a layout method for reducing the mutual coupling of parasitic inductances of power loops is proposed, optimizing the PCB parasitic parameters, which can suppress the transient oscillation of the switch, improve the output current accuracy, and better meet the application requirements in high-precision occasions.

Description

Technical Field

[0001] The invention relates to the technical field of power motor drive, and in particular to a method for suppressing switching transient noise of a dual-buck symmetrical half-bridge power converter. Background Art

[0002] The output current distortion of high-precision power converters can cause unnecessary positioning fluctuations in ultra-precision motors, which has a serious impact on precision control systems. The inventors have previously developed a dual-buck symmetrical half-bridge power converter in a composite current-driven hybrid power converter. The patent name is composite current-driven hybrid power amplifier, application number: CN202310051995.3, which has greater interleaving flexibility and faster current dynamic response, and can suppress the different voltage drops at the midpoint of the bridge arm during switch on and off, and has the ability to output high-precision current. However, GaN HEMT will cause serious switching oscillations, which can easily cause the device to mis-convert or even break down the device, especially at high frequencies. It is one of the main sources of distortion in dual-buck symmetrical half-bridge power converters based on GaN HEMTs.

[0003] There are few studies on the existing GaN HEMT switch characteristic analysis model, and few studies analyze the switch behavior from the power converter level. The circuit-level switch analysis model for the dual-buck symmetrical half-bridge power converter is still relatively lacking. Therefore, it is necessary to establish a dual-buck symmetrical half-bridge power converter switch analysis model and deeply analyze the influence of different parasitic parameters on the switching transient characteristics from the circuit perspective. However, the traditional piecewise linear model, which is widely used in the switch analysis model, can simply and quickly estimate the switch waveform, but simplifies the influence of parasitic parameters and nonlinear terms. In high-frequency conditions, the calculated results do not match the experimental results. Summary of the invention

[0004] In order to overcome the shortcomings of the background technology, the present invention provides a method for suppressing the transient noise of the switch of a dual-buck symmetrical half-bridge power converter. Based on a circuit-level switch analysis model, the present invention proposes a layout method for reducing the mutual coupling of parasitic inductances in the power loop, optimizes the PCB parasitic parameters, can suppress the transient oscillation of the switch, improves the output current accuracy, and better meets the application requirements in high-precision occasions.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A method for suppressing switching transient noise of a dual-step-down symmetrical half-bridge power converter, wherein the dual-step-down symmetrical half-bridge power converter comprises switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2 , load inductance L and load resistance R, parasitic inductance L of the drain lineD1 and L D2 and L D3 and L D4 , the parasitic inductance L of the source line S1 and L S2 and L S3 and L S4 and the dual voltage sources U i1 and U i2 are composed, and inductors L o and L n are set in the corresponding PCB layout and wiring;

[0007] One end of the said L D1 is connected to the positive terminal of S1, the negative terminal of S1 is connected to one end of L S1 , one end of the said L S1 is connected to the positive terminal of D1, the negative terminal of D1 is connected to the negative terminal of D2, the positive terminal of D2 is connected to one end of L D2 , one end of the said L D2 is connected to the positive terminal of S2, the negative terminal of S2 is connected to one end of L S2 , forming a first symmetric bridge arm, the midpoint of this bridge arm is connected to one end of L1; One end of the said L D3 is connected to the positive terminal of S3, the negative terminal of S3 is connected to one end of L S3 , one end of the said L S3 is connected to the negative terminal of D3, the positive terminal of D3 is connected to the positive terminal of D4, the negative terminal of D4 is connected to one end of L D4 , one end of the said L D4 is connected to the positive terminal of S4, the negative terminal of S4 is connected to one end of L S4 , forming a second symmetric bridge arm, the midpoint of this bridge arm is connected to one end of L2; The other ends of the said L1 and L2 are connected to the midpoint of the connection of L, R, C f1 and C f2 ; The other end of the said C f1 is connected to the other end of L D3 , the other end of the said C f2 is connected to the other end of L S4 ; L D1 and L D3 are connected through the said L o , the said L S2 and the said L S4 are connected through the said L n ; The other end of L D1 is connected to the positive terminal of U i1 , the negative terminal of the said U i1 is connected to the positive terminal of U i2 , LS2 The other end is connected to the U i2 negative terminal;

[0008] The dual buck symmetric half-bridge power converter is provided with four drive circuits and four additional auxiliary source electrodes, forming a vertical layout of the dual buck symmetric half-bridge power converter;

[0009] Drive circuits are respectively arranged for the four switches. The drive circuit includes a drive power supply, a drive resistor and a gate parasitic inductance. The positive terminal of the drive power supply is connected to one end of the drive resistor, the other end of the drive resistor is connected to the gate of the corresponding switch, the negative terminal of the drive power supply is connected to one end of the gate parasitic inductance, and the other end of the gate parasitic inductance is connected to the negative terminal of the corresponding switch through the additional auxiliary source electrode and the parasitic inductance of the corresponding source line.

[0010] Furthermore, the dual buck symmetric half-bridge power converter is also provided with distributed filter capacitors, including capacitors C1 to C n+1 , capacitors C1 to C n are connected in parallel across the two ends of U i1 and U i2 . Among them, capacitor C n is close to the first symmetric bridge arm, capacitor C n+1 is connected in parallel between the first symmetric bridge arm and the second symmetric bridge arm, and divides L o and L n into two segments respectively. The L o is divided into L o1 and L o2 . The L n is divided into L n1 and L n2 . One end of capacitor C n+1 is connected to the midpoint of the L o1 and the L o2 , and the other end of capacitor C n+1 is connected to the midpoint of the L n1 and the L n2 .

[0011] A method for suppressing the switching transient noise of a dual buck symmetric half-bridge power converter. The dual buck symmetric half-bridge power converter consists of switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2 , a load inductor L and a load resistor R, the parasitic inductances L D1 , L D2 , L D3 , L D4 of the drain line, the parasitic inductances L S1 , L S2 , LS3 , L S4 , and the dual voltage sources U i1 , U i2 to form, and inductors L o and L n are set in the corresponding PCB layout and wiring;

[0012] The positive terminal of the said D2 is connected to one end of L D2 , the other end of the said L D2 is connected to the positive terminal of S2, and the negative terminal of S2 is connected to one end of L S2 ; the negative terminal of the said D4 is connected to one end of L D4 , the other end of the said L D4 is connected to the positive terminal of S4, and the negative terminal of S4 is connected to one end of L S4 ; the positive terminal of the said D1 is connected to one end of L S1 , the other end of the said L S1 is connected to the negative terminal of S1, and the positive terminal of S1 is connected to one end of L D1 ; the negative terminal of the said D3 is connected to one end of L S3 , the other end of the said L S3 is connected to the negative terminal of S3, and the positive terminal of S3 is connected to one end of L D3 ; the negative terminal of D1 is connected to the negative terminal of D2, and at the same time, the negative terminal of D1 is connected to one end of L1; the positive terminal of D3 is connected to the positive terminal of D4, and at the same time, the positive terminal of D3 is connected to one end of L2; the other ends of the said L1 and the said L2 are connected to the midpoint of the connection of L, R, C f1 and C f2 ; the other end of the said C f1 is connected to the other end of L D3 , the other end of the said C f2 is connected to the other end of L S4 ; the said L D1 and the said L D3 are connected through the said L o , the said L S2 and the said L S4 are connected through the said L n ; the other end of L D1 is connected to the positive terminal of U i1 , the negative terminal of the said U i1 is connected to the positive terminal of U i2 , the other end of L S2 is connected to the negative terminal of the said U i2 ;

[0013] The dual-buck symmetric half-bridge power converter is provided with four drive circuits, four additional auxiliary sources, and distributed filter capacitors, forming a horizontal interleaved layout of the dual-buck symmetric half-bridge power converter;

[0014] Drive circuits are respectively arranged for the four switches. The drive circuit includes a drive power supply, a drive resistor, and a gate parasitic inductance. The positive terminal of the drive power supply is connected to one end of the drive resistor, the other end of the drive resistor is connected to the gate of the corresponding switch, the negative terminal of the drive power supply is connected to one end of the gate parasitic inductance, and the other end of the gate parasitic inductance is connected to the negative terminal of the corresponding switch through the additional auxiliary source and the parasitic inductance of the corresponding source line;

[0015] The distributed filter capacitors include capacitors C1 to C n+1 , and capacitors C1 to C n+1 are connected in parallel across the two ends of U i1 and U i2 . Among them, capacitor C n is close to the bridge arms where S1, S2, D1, and D2 are located, and capacitor C n+1 is close to the bridge arms where S3, S4, D3, and D4 are located.

[0016] Furthermore, the L o and the L n are symmetrically divided into two segments respectively by adding partition slots under S2 and S4, and under S1 and S3. L o is divided into L o1 and L o2 , and L n is divided into L n1 and L n2 . Among them, one end of the negative pole of capacitor C n+1 connected to U i2 is connected to the midpoint of the L n1 and the L n2 , and one end of the positive pole of capacitor C n+1 connected to U i1 is connected to the midpoint of the L o1 and the L o2 .

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention takes into account the parasitic inductance of the circuit, the junction capacitance of the power device, and the non-linear characteristics of the transconductance, establishes a circuit-level switching analysis model of the dual buck symmetric half-bridge power converter based on GaN HEMT, solves the problems of inaccurate traditional piecewise linear models and the lack of circuit-level switching analysis models for power amplifier circuits, and based on the circuit-level switching analysis model, proposes a layout method to reduce the mutual coupling of parasitic inductances in the power loop, optimizes the parasitic parameters of the PCB, solves the serious drawback of severe transient oscillation in the high-frequency state of GaN HEMT switches, improves the output waveform quality of the dual buck symmetric half-bridge power converter, can suppress the transient oscillation of the switches, improves the output current accuracy, and better meets the application requirements in high-precision occasions. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a topology diagram of the circuit structure of the existing dual buck symmetric half-bridge power converter;

[0019] Figure 2 is Figure 1 the topology diagram of the circuit-level switching analysis model of

[0020] Figure 3 is Figure 2 the modal analysis topology diagram during the turn-on period of S1;

[0021] Figure 4 is Figure 2 the modal analysis topology diagram during the turn-off period of S1;

[0022] Figure 5 is Figure 2 the modal analysis topology diagram during the turn-on period of S4;

[0023] Figure 6 is Figure 2 the modal analysis topology diagram during the turn-off period of S4;

[0024] Figure 7 is the topology diagram of Scheme 1 in the specific implementation manner;

[0025] Figure 8 is the topology diagram of Scheme 2 in the specific implementation manner;

[0026] Figure 9 is the topology diagram of Scheme 3 in the specific implementation manner;

[0027] Figure 10 is the topology diagram of Scheme 4 in the specific implementation manner. SPECIFIC IMPLEMENTATION MANNER

[0028] Next, the technical solutions in the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0029] The inventor previously submitted a patent application for an invention titled "A Composite Current-Driven Hybrid Power Amplifier" with an application date of February 2, 2023, an application number of CN202310051995.3, which discloses a dual buck symmetric half-bridge power converter circuit structure, and its topology is combined Figure 1 as shown.

[0030] The specific switch analysis model is as follows:

[0031] Considering the non-linear parasitic parameters of GaN HEMT and diodes, the driving loop, and the parasitic parameters of the circuit traces, its circuit-level switch analysis model is combined Figure 2 as shown. It is powered by U i1 and U i2 dual voltage sources, and consists of two Buck circuits, four driving loops, two LC filtering links, and a load, where:

[0032] The first Buck circuit consists of switches S1 and S2, drain-source parasitic capacitances C ds1 and C ds2 diodes D1 and D2, diode non-linear junction capacitances C D1 and C D2 parasitic inductances L D1 and L D2 of the drain line, parasitic inductances L S1 and L S2 of the source line, and line parasitic resistances R1 and R2. The positive end of S1 is connected to one end of L D1 the other end of L D1 is connected to R1, the negative end of S1 is connected to one end of L S1 the other end of L S1 is connected to the positive end of D1, the negative end of D1 is connected to one end of L D2 the other end of L D2 is connected to the positive end of S2, the negative end of S2 is connected to one end of L S2 the other end of L S2 is connected to the negative end of D2, the positive end of D2 is connected to R2, C ds1 C ds2 C D1 C D2They are respectively connected in parallel across both ends of S1, S2, D1, and D2. The other end of R1 is connected to the voltage source U i1 positive terminal, and the other end of R2 is connected to the voltage source U i2 negative terminal.

[0033] The second Buck circuit consists of switches S3 and S4, drain-source parasitic capacitances C ds3 and C ds4 , diodes D3 and D4, diode nonlinear junction capacitances C D3 and C D4 , parasitic inductances L D3 and L D4 of the drain line, parasitic inductances L S3 and L S4 of the source line, and line parasitic resistances R3 and R4. The positive terminal of S3 is connected to one end of L D3 , the other end of L D3 is connected to the positive terminal of D3, the negative terminal of D3 is connected to R3, and the negative terminal of S3 is connected to one end of L S3 , the other end of L S3 is connected to the positive terminal of D4, the negative terminal of D4 is connected to one end of L D4 , the other end of L D4 is connected to the positive terminal of S4, the negative terminal of S4 is connected to one end of L S4 , the other end of L S4 is connected to one end of R4, and C ds3 , C ds4 , C D3 , C D4 are respectively connected in parallel across both ends of S3, S4, D3, and D4. The other end of R3 is connected to the positive terminal of the voltage source U i1 , and the other end of R4 is connected to the negative terminal of the voltage source U i2 negative terminal.

[0034] The first drive circuit consists of a drive power supply V G1 , a drive resistance R G1 , a gate parasitic inductance L G1 , a gate-source parasitic capacitance C gs1 , and a gate-drain parasitic capacitance C gd1 . The positive terminal of V G1 is connected to one end of L G1 , the other end of L G1 is connected to one end of R G1 , the other end of R G1 is connected to one end of C gd1 and C gs1 , the other end of C gs1 is connected to the negative terminal of V G1 , and C gd1The other end is connected to the positive terminal of S1.

[0035] The second drive circuit consists of a drive power supply V G2 , a drive resistor R G2 , a gate parasitic inductance L G2 , a gate-source parasitic capacitance C gs2 and a gate-drain parasitic capacitance C gd2 . The positive terminal of V G2 is connected to one end of L G2 . The other end of L G2 is connected to one end of R G2 . The other end of R G2 is connected to one end of C gd2 and C gs2 . The other end of C gs2 is connected to the negative terminal of V G2 . The other end of C gd2 is connected to the positive terminal of S2.

[0036] The third drive circuit consists of a drive power supply V G3 , a drive resistor R G3 , a gate parasitic inductance L G3 , a gate-source parasitic capacitance C gs3 and a gate-drain parasitic capacitance C gd3 . The positive terminal of V G3 is connected to one end of L G3 . The other end of L G3 is connected to one end of R G3 . The other end of R G3 is connected to one end of C gd3 and C gs3 . The other end of C gs3 is connected to the negative terminal of V G3 . The other end of C gd3 is connected to the positive terminal of S3.

[0037] The fourth drive circuit consists of a drive power supply V G4 , a drive resistor R G4 , a gate parasitic inductance L G4 , a gate-source parasitic capacitance C gs4 and a gate-drain parasitic capacitance C gd4 . The positive terminal of V G4 is connected to one end of L G4 . The other end of L G4 is connected to one end of R G4 . The other end of R G4 is connected to one end of C gd4 and C gs4 . The other end of C gs4 is connected to the negative terminal of V G4The negative terminal of, C gd4 The other end is connected to the positive terminal of S4.

[0038] The first LC filter section consists of an inductor L1, a capacitor C f1 and a parasitic resistor R L1 One end of L1 is connected to one end of R L1 The other end of R L1 is connected to the negative terminal of D1, and the other end of L1 is connected to one end of C f1 One end of C f1 is connected to the positive terminal of the voltage source U i1 positive terminal.

[0039] The second LC filter section consists of an inductor L2, a capacitor C f2 and a parasitic resistor R L2 One end of L2 is connected to one end of R L2 The other end of R L2 is connected to the positive terminal of D4, and the other end of L2 is connected to one end of C f2 One end of C f2 is connected to the negative terminal of the voltage source U i2 negative terminal.

[0040] The load inductor L and the load resistor R in the load part are equivalently replaced by the output current i L flowing through.

[0041] The modal analysis is as follows:

[0042] (1) The turn-on process of S1

[0043] The turn-on process of S1 in the dual buck symmetric half-bridge power converter based on GaN HEMT can be divided into four stages: the S1 conduction delay period, the drain-source voltage drop period, the diode turn-on oscillation period, and the S1 turn-on oscillation period. Combining with Figure 3 shown, where (a) shows Mode1: the S1 conduction delay period, (b) shows Mode2: the drain-source voltage drop period, (c) to (f) show Mode3: the diode turn-on oscillation period, and (g) to (h) show Mode4: the S1 turn-on oscillation period.

[0044] Mode1[t0 < t < t1]: S1 conduction delay

[0045] At time t0, V G1 changes from low to high, and the drive current i g1 charges C gs1 and C gd1 The drain-source voltage v ds1 and the drain current i D1 remain unchanged. From Figure 3(a) The following equations can be derived:

[0046]

[0047] When the gate-source voltage v gs1 rises to the threshold voltage v th1 this mode ends.

[0048] Mode2[t1<t<t2]: The period when the drain-source voltage drops

[0049] At time t1, the channel current i ch1 is controlled by v gs1 C gd1 C ds1 and C D1 discharge and oscillate with the parasitic inductance in the loop. During the Miller plateau stage of the device, i g1 mainly charges C gd1 and v ds1 drops rapidly. At the same time, the slow increase in v gs1 causes the slow rise of i ch1 and the Miller plateau delays the turn-on time of the device. From Figure 3 (b) the following equations can be derived, where R loop represents the high-frequency damping resistor and has an inhibitory effect on the oscillation:

[0050]

[0051] When v ds1 drops to 0, this mode ends.

[0052] Mode3[t2<t<t3]: The period when the diode turns on and oscillates

[0053] At time t2, S1 is basically turned on and i ch1 is not controlled by v gs1 and from Figure 3 (c) it can be known that:

[0054]

[0055] C D1 continues to discharge. When the voltage v D1 across D1 reaches the turn-on voltage of D1, D1 conducts, as shown in Figure 3 (d). When the drain current i D2 drops to 0, C D2 participates in resonance, as shown in Figure 3 (e). Specifically, which one arrives first is related to the circuit parameters. When the stray inductance in the loop is large or the load current is large, the drop rate of i d2 is delayed. When C D1When it is larger, the capacitor discharge time is longer. Whenever i D1 When the oscillation is 0, D1 turns off. The loop inductor and capacitors C D1 、C D2 、C ds1 、C ds2 resonate, and i D2 charges C D1 , as shown in Figure 3 (f). When v D1 reaches the turn-on voltage of D1, D1 starts to conduct again, as shown in Figure 3 (e). D1 switches on and off repeatedly during the oscillation until the voltage across C D2 drops to a certain level and no longer generates a discharge current greater than the inductor current i L1 to charge C D1 , and D1 is fully conducting, and this mode ends.

[0056] Mode4[t3<t<t4]: S1 turn-on oscillation period

[0057] At time t3, D1 is fully conducting, but the parasitic inductance and parasitic capacitance in the circuit form a second-order oscillation circuit, which is an underdamped system. From Figure 3 (g), the following oscillation equation can be deduced:

[0058]

[0059] When the oscillation is completely damped, this process ends, and the S1 turn-on process ends, as shown in Figure 3 (h).

[0060] (2) S1 turn-off process

[0061] The S1 turn-off process of the dual buck symmetric half-bridge power converter based on GaN HEMT can be divided into three stages: the S1 turn-off delay period, the drain-source voltage rise period, and the S1 turn-off oscillation period. Combining Figure 4 shown, where (a) shows Mode1: S1 turn-off delay period, (b) - (d) show Mode2: drain-source voltage rise period, and (e) - (f) show Mode3: S1 turn-off oscillation period.

[0062] Mode1[t0<t<t1]: S1 turn-off delay period

[0063] At time t0, V G1 changes from high to low level, C gs1 and C gd1 discharge, v ds1 and i D1 remain unchanged. From Figure 4 (a), the following equation can be deduced:

[0064]

[0065] When the channel current i ch1 is controlled by the driving voltage v gs1 , S1 starts to turn off and this mode ends.

[0066] Mode2[t1<t<t2]: Rise period of drain-source voltage

[0067] At time t1, the channel current i ch1 is controlled by v gs1 . As v gs1 decreases, i ch1 also decreases accordingly. Since the channel current i ch1 decreases faster than the current i D1 , the current difference charges C ds1 and C gd1 , and v ds1 increases. The current difference between i D1 and i L1 discharges the capacitor C D2 , and the voltage v D2 across D2 decreases. From Figure 4 (b), the following equation can be derived:

[0068]

[0069] When i ch1 drops to 0, the channel current of S1 turns off, as shown in Figure 4 (c). C D2 continues to discharge, and v D2 continues to decrease. When v D2 reaches the turn-on voltage, D2 conducts, as shown in Figure 4 (d). i d1 continues to charge C ds1 until i d1 drops to 0 and D1 turns off, and this mode ends.

[0070] Mode3[t2<t<t3]: Oscillation period of S1 turn-off

[0071] At time t2, D1 turns off, and there is an underdamped parasitic oscillation between C D1 and the loop inductance, C ds1 , C ds2 . From Figure 4 (e), the following equation can be derived:

[0072]

[0073] When the oscillation completely decays, S1 is completely turned off, as shown in Figure 4As shown in (f), the turn-off process ends.

[0074] (3) Turn-on process of S4

[0075] The turn-on process of the S4 in the GaN HEMT-based dual buck symmetric half-bridge power converter can be divided into four stages: the S4 conduction delay period, the drain-source voltage drop period, the diode turn-on oscillation period, and the S4 turn-on oscillation period. As shown in Figure 5 , among which, (a) shows Mode1: S1 conduction delay period, (b) shows Mode2: drain-source voltage drop period, (c) to (f) show Mode3: diode turn-on oscillation period, and (g) to (h) show Mode4: S4 turn-on oscillation period.

[0076] Mode1 [t’0 < t < t’1]: S4 conduction delay

[0077] At the moment of t’0, V G4 changes from low to high, and the drive current i g4 charges C gs4 and C gd4 . The drain-source voltage v ds4 and the drain current i D4 remain unchanged. From Figure 5 (a), the following equation can be deduced:

[0078]

[0079] When the gate-source voltage v gs4 rises to the threshold voltage v th4 , this mode ends.

[0080] Mode2 [t’1 < t < t’2]: Drain-source voltage drop period

[0081] At the moment of t’1, the channel current i ch4 is controlled by v gs4 . C gd4 , C ds4 and C D4 discharge and oscillate with the parasitic inductance in the loop. During the Miller plateau stage of the device, i g4 mainly charges C gd4 , and v ds4 rapidly decreases. At the same time, the slow increase of v gs4 causes the slow rise of i ch4 . The Miller plateau delays the turn-on time of the device. From Figure 5 (b), the following equation can be deduced, where R’ loop represents the high-frequency damping resistance, which has an inhibitory effect on the oscillation:

[0082]

[0083] When v ds4 drops to 0, this mode ends.

[0084] Mode 3 [t’2 < t < t’3]: Diode turn-on oscillation period

[0085] At the moment t’2, S4 is basically conducting, and i ch4 is not controlled by v gs4 and, according to Figure 5 (c), it can be seen that:

[0086]

[0087] C D4 continues to discharge. When the voltage v D4 across D4 reaches the turn-on voltage of D4, D4 conducts, as shown in Figure 5 (d). When the drain current i D3 drops to 0, C D3 participates in resonance, as shown in Figure 5 (e). Specifically, which one arrives first is related to the circuit parameters. When the stray inductance of the loop is large or the load current is large, the falling speed of i d3 is delayed. When C D4 is larger, the capacitor discharge time is longer. Whenever i D4 oscillates to 0, D4 turns off. The loop inductance resonates with capacitors C D4 C D4 C ds4 C ds4 and i D3 charges C D4 , as shown in Figure 5 (f). When v D4 reaches the turn-on voltage of D4, D4 starts to conduct again, as shown in Figure 5 (e). D4 switches on and off repeatedly during the oscillation until the voltage across C D3 drops to a certain extent and no longer generates a discharge current greater than the inductor current i L4 of L4 to charge C D4 , and D4 is fully conducting, and this mode ends.

[0088] Mode 4 [t’3 < t < t’4]: S4 turn-on oscillation period

[0089] At the moment t’3, D4 is fully conducting, but the parasitic inductance and parasitic capacitance in the circuit form a second-order oscillation circuit, which is an underdamped system. From Figure 5 (g), the following oscillation equation can be deduced:

[0090]

[0091] When the oscillation completely decays, this process ends, and the S4 turn-on process ends, as shown in Figure 5 (h).

[0092] (4) S4 turn-off process

[0093] The S4 turn-off process of the dual buck symmetric half-bridge power converter based on GaN HEMT can be divided into three stages: the S4 turn-off delay period, the drain-source voltage rise period, and the S4 turn-off oscillation period. Combining with Figure 6 shown, where (a) shows Mode1: the S4 turn-off delay period, (b)–(d) show Mode2: the drain-source voltage rise period, and (e)–(f) show Mode3: the S4 turn-off oscillation period.

[0094] Mode1 [t’0 < t < t’1]: S4 turn-off delay period

[0095] At time t’0, V G4 changes from high to low level, C gs4 and C gd4 discharge, v ds4 and i D4 remain unchanged. From Figure 6 (a), the following equation can be deduced:

[0096]

[0097]

[0098] When the channel current i ch4 is controlled by the drive voltage v gs4 , S4 starts to turn off, and this mode ends.

[0099] Mode2 [t’1 < t < t’2]: Drain-source voltage rise period

[0100] At time t’1, the channel current i ch4 is controlled by v gs4 . As v gs4 decreases, i ch4 will also decrease accordingly. Since the channel current i ch4 decreases faster than the current i D4 , the current difference charges C ds4 and C gd4 , and v ds4 increases. The current difference between i D4 and i L4 discharges the capacitor C D3 , and v D3 decreases. From Figure 6 (b), the following equation can be deduced:

[0101]

[0102] When i ch4 drops to 0, the S4 channel current is turned off, as shown in Figure 6 (c). C D3 Continues to discharge, and v D3 continues to decrease. When v D3 reaches the turn-on voltage, D3 conducts, as shown in Figure 6 (d). i d4 Continues to charge C ds4 until i d4 drops to 0, at which point D4 is cut off and this mode ends.

[0103] Mode3[t’2<t<t’3]: S4 turn-off oscillation period

[0104] At time t’2, D4 is turned off, and C D4 has an underdamped parasitic oscillation with the loop inductor, C ds4 , C ds3 . From Figure 6 (e), the following equation can be derived:

[0105]

[0106] When the oscillation is completely damped, S4 is completely turned off, as shown in Figure 6 (f), and the turn-off process ends.

[0107] From the modal analysis of the circuit-level switching analysis model of the dual buck symmetric half-bridge power converter, it can be seen that the oscillation process of the power device is mainly affected by the junction capacitance of the power device and the stray inductance of the PCB board loop. Combining with Figures 7 to 10 shown, a method for suppressing the switching transient noise of the dual buck symmetric half-bridge power converter is proposed, including four PCB layout optimization schemes, specifically as follows:

[0108] Scheme 1

[0109] Combining with Figure 7 shown, it consists of a dual buck symmetric half-bridge power converter, four drive loops, and four additional auxiliary sources, forming a vertical layout of the dual buck symmetric half-bridge power converter.

[0110] The dual buck symmetric half-bridge power converter consists of switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2 , load inductor L and load resistor R, parasitic inductances L D1 , L D2 , L D3 , L D4 , parasitic inductance L of the source lineS1 , L S2 , L S3 , L S4 and the dual voltage sources U i1 , U i2 are composed, and inductors L o and L n are set in the corresponding PCB layout and wiring. One end of the parasitic inductor L D1 of the drain line is connected to the positive terminal of switch S1, and the negative terminal of switch S1 is connected to one end of the parasitic inductor L S1 of the source line. The other end of the parasitic inductor L S1 of the source line is connected to the positive terminal of diode D1, the negative terminal of diode D1 is connected to the negative terminal of diode D2, and the positive terminal of diode D2 is connected to one end of the parasitic inductor L D2 of the drain line. The other end of the parasitic inductor L D2 of the drain line is connected to the positive terminal of switch S2, and the negative terminal of switch S2 is connected to one end of the parasitic inductor L S2 of the source line, forming a first symmetrical bridge arm, and the midpoint of this bridge arm is connected to one end of inductor L1. One end of the parasitic inductor L D3 of the drain line is connected to the positive terminal of switch S3, and the negative terminal of switch S3 is connected to one end of the parasitic inductor L S3 of the source line. The other end of the parasitic inductor L S3 of the source line is connected to the negative terminal of diode D3, the positive terminal of diode D3 is connected to the positive terminal of diode D4, and the negative terminal of diode D4 is connected to one end of the parasitic inductor L D4 of the drain line. The other end of the parasitic inductor L D4 of the drain line is connected to the positive terminal of switch S4, and the negative terminal of switch S4 is connected to one end of the parasitic inductor L S4 of the source line, forming a second symmetrical bridge arm, and the midpoint of this bridge arm is connected to one end of inductor L2. The other ends of inductors L1 and L2 are connected to the midpoint of the connection of the load inductor L, load resistor R, and capacitors C f1 and C f2 . The other end of capacitor C f1 is connected to the other end of the parasitic inductor L D3 of the drain line, and the other end of capacitor C f2 is connected to the other end of the parasitic inductor L S4 of the source line. The parasitic inductors L D1 and L D3 of the drain line are connected through inductor L o . The parasitic inductors L S2 and L S4 of the source line are connected through inductor L n . The parasitic inductor L D1The other end is connected to the voltage source U i1 The positive terminal of the voltage source U i1 The negative terminal is connected to the positive terminal of the voltage source U i2 The positive terminal of the parasitic inductance L of the source line S2 The other end is connected to the voltage source U i2 The negative terminal

[0111] Extra auxiliary sources are added respectively between the gate parasitic inductances and the source line parasitic inductances of the four drive circuits to achieve decoupling of the gate circuit and the power circuit. The drive power supply V of the first drive circuit G1 The positive terminal is connected to one end of the drive resistor R G1 One end of the drive resistor R G1 The other end is connected to the gate of the switch S1. The negative terminal of the drive power supply V G1 Is connected to one end of the gate parasitic inductance L G1 One end of the gate parasitic inductance L G1 The other end is connected to the negative terminal of the switch S1 through the extra auxiliary source and the parasitic inductance L of the source line S1 Together; The positive terminal of the drive power supply V of the second drive circuit G2 Is connected to one end of the drive resistor R G2 One end of the drive resistor R G2 The other end is connected to the gate of the switch S2. The negative terminal of the drive power supply V G2 Is connected to one end of the gate parasitic inductance L G2 One end of the gate parasitic inductance L G2 The other end is connected to the negative terminal of the switch S2 through the extra auxiliary source and the parasitic inductance L of the source line S2 Together. The positive terminal of the drive power supply V of the third drive circuit G3 Is connected to one end of the drive resistor R G3 One end of the drive resistor R G3 The other end is connected to the gate of the switch S3. The negative terminal of the drive power supply V G3 Is connected to one end of the gate parasitic inductance L G3 One end of the gate parasitic inductance L G3 The other end is connected to the negative terminal of the switch S3 through the extra auxiliary source and the parasitic inductance L of the source line S3 Together. The positive terminal of the drive power supply V of the fourth drive circuit G4 Is connected to one end of the drive resistor R G4 One end of the drive resistor R G4 The other end is connected to the gate of the switch S4. The negative terminal of the drive power supply V G4 Is connected to one end of the gate parasitic inductance L G4 One end of the gate parasitic inductance L G4 The other end is connected through the extra auxiliary source and the parasitic inductance L of the source lineS4 Are all connected to the negative terminal of switch S4.

[0112] Solution 2

[0113] Combined with Figure 8 As shown, it consists of a double buck symmetric half - bridge power converter, four drive circuits, four additional auxiliary sources, and distributed filter capacitors, forming a vertical layout of a double buck symmetric half - bridge power converter with distributed filter capacitors.

[0114] Solution 2 adds distributed filter capacitors on the basis of Solution 1, consisting of n + 1 small - value capacitors C1 - C n+1 which are n connected in parallel at both ends of voltage sources U i1 and U i2 where capacitor C n is close to the first symmetric bridge arm, capacitor C n+1 is connected in parallel between the first symmetric bridge arm and the second symmetric bridge arm, and the inductors L o and L n in Solution 1 are each separated into two segments. Inductor L o is separated into L o1 and L o2 and inductor L n is separated into L n1 and L n2 One end of capacitor C n+1 is connected to the mid - point of inductors L o1 and L o2 and the other end of capacitor C n+1 is connected to the mid - point of inductors L n1 and L n2 This layout reduces the coupling between inductors and decreases the parasitic inductance of the power loop.

[0115] Solution 3

[0116] Combined with Figure 9 As shown, it consists of a double buck symmetric half - bridge power converter, four drive circuits, four additional auxiliary sources, and distributed filter capacitors, forming a horizontal staggered layout of a double buck symmetric half - bridge power converter with distributed filter capacitors.

[0117] Solution 3 has the same connection method as Solution 2, but the two bridge arms of the double buck symmetric half - bridge power converter change from vertical layout to horizontal staggered layout, making the power loops of each bridge arm keep the current in reverse.

[0118] The double buck symmetric half - bridge power converter consists of switches S1, S2, S3, S4, diodes D1, D2, D3, D4, inductors L1, L2, capacitors C f1 , C f2, load inductor L and load resistor R, the parasitic inductance L of the drain line D1 , L D2 , L D3 , L D4 , the parasitic inductance L of the source line S1 , L S2 , L S3 , L S4 and dual voltage sources U i1 , U i2 are composed, and inductors L o and L n are set in the corresponding PCB layout and wiring. The two arms of the dual buck symmetric half-bridge power converter are horizontally staggered. From left to right, they are: the positive terminal of diode D2 is connected to one end of the parasitic inductance L D2 of the drain line, the other end of the parasitic inductance L D2 of the drain line is connected to the positive terminal of switch S2, and the negative terminal of switch S2 is connected to one end of the parasitic inductance L S2 of the source line; the negative terminal of diode D4 is connected to one end of the parasitic inductance L D4 of the drain line, the other end of the parasitic inductance L D4 of the drain line is connected to the positive terminal of switch S4, and the negative terminal of switch S4 is connected to one end of the parasitic inductance L S4 of the source line; the positive terminal of diode D1 is connected to one end of the parasitic inductance L S1 of the source line, the other end of the parasitic inductance L S1 of the source line is connected to the negative terminal of switch S1, and the positive terminal of switch S1 is connected to one end of the parasitic inductance L D1 of the drain line; the negative terminal of diode D3 is connected to one end of the parasitic inductance L S3 of the source line, the other end of the parasitic inductance L S3 of the source line is connected to the negative terminal of switch S3, and the positive terminal of switch S3 is connected to one end of the parasitic inductance L D3 of the drain line. The negative terminal of diode D1 is connected to the negative terminal of diode D2. At the same time, the negative terminal of diode D1 is connected to one end of inductor L1 together. The positive terminal of diode D3 is connected to the positive terminal of diode D4. At the same time, the positive terminal of diode D3 is connected to one end of inductor L2 together. The other ends of inductors L1 and L2 are connected to the midpoint of the connection of load inductor L and load resistor R and capacitors C f1 and C f2 . The other end of capacitor C f1 is connected to the other end of the parasitic inductance L D3 of the drain line, and the other end of capacitor C f2 is connected to the other end of the parasitic inductance L S4 of the source line. The parasitic inductance L of the drain lineD1 and L D3 is connected through an inductor L o The parasitic inductor L of the source line S2 and L S4 is connected through an inductor L n The parasitic inductor L of the drain line D1 The other end of is connected to the positive terminal of the voltage source U i1 The positive terminal of the voltage source U i1 The negative terminal of is connected to the positive terminal of the voltage source U i2 The parasitic inductor L of the source line S2 The other end of is connected to the negative terminal of the voltage source U i2 .

[0119] An additional auxiliary source is respectively added between the gate parasitic inductors and the source line parasitic inductors of the four driving circuits to decouple the gate circuit and the power circuit, and the current flowing through the driving circuit is also reversed by horizontal interleaved layout. The positive terminal of the driving power supply V G1 of the first driving circuit is connected to one end of the driving resistor R G1 , the other end of the driving resistor R G1 is connected to the gate of the switch S1, the negative terminal of the driving power supply V G1 is connected to one end of the gate parasitic inductor L G1 , the other end of the gate parasitic inductor L G1 is connected to the negative terminal of the switch S1 together with the additional auxiliary source and the parasitic inductor L S1 of the source line; the positive terminal of the driving power supply V G2 of the second driving circuit is connected to one end of the driving resistor R G2 , the other end of the driving resistor R G2 is connected to the gate of the switch S2, the negative terminal of the driving power supply V G2 is connected to one end of the gate parasitic inductor L G2 , the other end of the gate parasitic inductor L G2 is connected to the negative terminal of the switch S2 together with the additional auxiliary source and the parasitic inductor L S2 of the source line. The positive terminal of the driving power supply V G3 of the third driving circuit is connected to one end of the driving resistor R G3 , the other end of the driving resistor R G3 is connected to the gate of the switch S3, the negative terminal of the driving power supply V G3 is connected to one end of the gate parasitic inductor L G3 , the other end of the gate parasitic inductor L G3 is connected to the negative terminal of the switch S3 together with the additional auxiliary source and the parasitic inductor L S3 of the source line. The positive terminal of the driving power supply V G4The positive terminal of is connected to the driving resistor R G4 One end of the driving resistor R G4 The other end is connected to the gate of the switch S4, and the driving power supply V G4 The negative terminal of is connected to the gate parasitic inductance L G4 One end of the gate parasitic inductance L G4 The other end is connected to the negative terminal of the switch S4 through the parasitic inductance L of the additional auxiliary source and the source line S4 Together. Among them, the first driving loop and the third driving loop are adjacent, and the driving currents of the two driving loops are in opposite directions; the second driving loop and the fourth driving loop are adjacent, and the driving currents of the two driving loops are in opposite directions.

[0120] The distributed filter capacitor consists of n + 1 small-value capacitors C1~C n+1 Composed, the capacitors C1~C n+1 Are connected in parallel at both ends of the voltage source U i1 And U i2 Among them, the capacitor C n Is close to the bridge arms where the switches S1, S2 and the diodes D1, D2 are located, and the capacitor C n+1 Is close to the bridge arms where the switches S3, S4 and the diodes D3, D4 are located.

[0121] Solution Four

[0122] Combined Figure 10 As shown, it consists of a double buck symmetric half-bridge power converter, four driving loops, four additional auxiliary sources, a distributed filter capacitor and two separation slots.

[0123] Based on Solution Three, Solution Four adds two identical separation slots under the switches S2 and S4 and under the switches S1 and S3 respectively, so that the inductors L o And L n Are respectively separated into two sections, and the inductor L o Is separated into L o1 And L o2 The inductor L n Is separated into L n1 And L n2 The symmetric parasitic inductance can reduce the mutual coupling between the inductors. The capacitors C1~C n+1 Are connected in parallel at both ends of the voltage source U i1 And U i2 Among them, the capacitor C n+1 Connected to the voltage source U i2 One end connecting the negative pole is connected to the midpoint of the inductors L n1 And L n2 The capacitor C n+1 Connected to the voltage source U i1One end of the positive electrode is connected to the inductor L o1 and L o2 at the midpoint.

[0124] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent conditions of the claims are intended to be encompassed within the present invention. Any reference signs in the claims should not be construed as limiting the claimed invention.

[0125] In addition, it should be understood that although this specification is described according to embodiments, not each embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for suppressing switching transient noise of a dual buck symmetric half-bridge power converter, characterized in that: The dual buck symmetric half-bridge power converter consists of GaN HEMT switches S 1、 S 2、 S 3、 S 4, diodes D 1、 D 2、 D 3、 D 4, inductors L 1、 L 2, capacitors C f1 、 C f2 ,load inductor L and load resistor R ,the parasitic inductance of the drain line L D1 、 L D2 、 L D3 、 L D4 ,the parasitic inductance of the source line L S1 、 L S2 、 L S3 、 L S4 and the dual voltage source U i1 、 U i2 and inductors are set on the corresponding PCB layout and wiring L o and L n ; One end of the L D1 is connected to S the positive terminal of 1. One end of the S negative terminal of 1 is connected to L S1 one end of the L S1 The other end of the D is connected to D the positive terminal of 1. One end of the D negative terminal of 1 is connected to D the negative terminal of 2. One end of the L D2 positive terminal of 2 is connected to L D2 one end of the S The other end of the S negative terminal of 2 is connected to L S2 one end, forming a first symmetric bridge arm, and the midpoint of this bridge arm is connected to L one end of 1; One end of the L D3 is connected to S the positive terminal of 3. One end of the S negative terminal of 3 is connected to L S3 one end of the L S3 The other end of the D negative terminal of 3 is connected to D the positive terminal of 3 is connected to D the positive terminal of 4. One end of the D negative terminal of 4 is connected to L D4 one end of the L D4 The other end of the S is connected to S the positive terminal of 4. One end of the L S4 negative terminal of 4 is connected to L one end, forming a second symmetric bridge arm, and the midpoint of this bridge arm is connected to L one end of 2; The other ends of 1 and the L 2 are connected to L one end of the C f1 and C f2 At the midpoint of the connection, L the other end of the R is grounded through C f1 The other end of the L D3 The other end of C f2 is connected to L S4 the other end; L D1 The other end of L D3 and the other end of L o are connected through L S2 The other end of L S4 and the other end of L n are connected through L D1 The other end of U i1 is connected to the positive terminal of U i1 The negative terminal of U i2 is connected to the positive terminal of L S2 The other end of U i2 is connected to the negative terminal of The dual buck symmetric half-bridge power converter is provided with four driving circuits and four additional auxiliary source electrodes to form a vertical layout of the dual buck symmetric half-bridge power converter; Driving circuits are respectively arranged on the four switches. The driving circuit includes a driving power supply, a driving resistor and a gate parasitic inductor. The positive terminal of the driving power supply is connected to one end of the driving resistor. The other end of the driving resistor is connected to the gate of the corresponding switch. The negative terminal of the driving power supply is connected to one end of the gate parasitic inductor. The other end of the gate parasitic inductor is connected to the negative terminal of the corresponding switch through the additional auxiliary source electrode. The parasitic inductor of the corresponding source line is connected to the negative terminal of the corresponding switch.

2. A method for suppressing switching transient noise of a dual buck - symmetric half - bridge power converter according to claim 1, characterized in that: The dual buck - symmetric half - bridge power converter is also provided with distributed filter capacitors, including capacitors C 1~ C n+1 , capacitor C 1~ C n in parallel at both ends of the U i1 and U i2 series branch. Among them, capacitor C n is close to the first symmetric bridge arm, and capacitor C n+1 is in parallel between the first symmetric bridge arm and the second symmetric bridge arm, and divides L o and L n into two segments respectively. The L o is divided into L o1 and L o2 . The L n is divided into L n1 and L n2 . One end of capacitor C n+1 is connected to the mid - point of the L o1 and the L o2 . The other end of capacitor C n+1 is connected to the mid - point of the L n1 and the L n2 .

3. A method for suppressing switching transient noise of a dual buck symmetric half-bridge power converter, characterized in that: The dual buck - symmetric half - bridge power converter consists of GaN HEMT switches S 1、 S 2、 S 3、 S 4, diodes D 1、 D 2、 D 3、 D 4, inductors L 1、 L 2, capacitors C f1 、 C f2 , load inductors L and load resistors R , the parasitic inductance of the drain line L D1 、 L D2 、 L D3 、 L D4 , the parasitic inductance of the source line L S1 、 L S2 、 L S3 、 L S4 and the dual - voltage source U i1 、 U i2 are composed, and inductors L o and L n ; The D positive terminal of 2 is connected to L D2 one end of L D2 and the other end of S is connected to the positive terminal of 2. The S negative terminal of 2 is connected to L S2 one end of D The negative terminal of 4 is connected to L D4 one end of L D4 and the other end of S is connected to the positive terminal of 4. The S negative terminal of 4 is connected to L S4 one end of D The positive terminal of 1 is connected to L S1 one end of L S1 and the other end of S is connected to the negative terminal of 1. The S positive terminal of 1 is connected to L D1 one end of D The negative terminal of 3 is connected to L S3 one end of L S3 and the other end of S is connected to the negative terminal of 3. The S positive terminal of 3 is connected to L D3 one end of D The negative terminal of 1 is connected to D the negative terminal of 2. At the same time, D the negative terminal of 1 is connected to L one end of 1. D The positive terminal of 3 is connected to D the positive terminal of 4. At the same time, D the positive terminal of 3 is connected to L one end of 2. The L other end of 1 and the L other end of 2 are connected to L one end of C f1 and C f2 at the midpoint of the connection. L The other end of R is grounded through C f1 The other end of L D3 The other end of the C f2 is connected to the other end of L S4 ; the other end of the L D1 and the other end of the L D3 are connected through the L o ; the other end of the L S2 and the other end of the L S4 are connected through the L n ; L D1 The other end is connected to the U i1 positive terminal of the U i1 ; the negative terminal of the U i2 is connected to the positive terminal of L S2 ; the other end of the U i2 is connected to the negative terminal of the The dual buck symmetric half-bridge power converter is provided with four driving circuits, four additional auxiliary source electrodes and distributed filter capacitors to form a horizontal interleaved layout of the dual buck symmetric half-bridge power converter; Driving circuits are respectively arranged on the four switches. The driving circuit includes a driving power supply, a driving resistor and a gate parasitic inductor. The positive terminal of the driving power supply is connected to one end of the driving resistor. The other end of the driving resistor is connected to the gate of the corresponding switch. The negative terminal of the driving power supply is connected to one end of the gate parasitic inductor. The other end of the gate parasitic inductor is connected to the negative terminal of the corresponding switch through the additional auxiliary source electrode. The parasitic inductor of the corresponding source line is connected to the negative terminal of the corresponding switch; The distributed filtering capacitor includes a capacitor C 1 to C n+1 , the capacitor C 1 to C n+1 is connected in parallel at both ends of the U i1 and U i2 series branch, where the capacitor C n is close to the S half-bridge arm where 2 and D 2 are located, and the capacitor C n+1 is close to the S half-bridge arm where 4 and D 4 are located.

4. A method for suppressing switch transient noise of a dual buck symmetric half-bridge power converter according to claim 3, characterized in that: The said L o and the said L n are respectively symmetrically divided into two segments by adding separation grooves below S 2 and S 4, and also below S 1 and S 3. They are separated into L o and L o1 and L o2 , L n and are separated into L n1 and L n2 , where the capacitor C n+1 is connected such that one end of the negative electrode is connected to the midpoint of the said U i2 and the said L n1 and the capacitor L n2 is connected such that one end of the positive electrode is connected to the midpoint of the said C n+1 and the said U i1 and the said L o1 and the said L o2 .

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