A high-switching converter with self-balancing current and voltage and its control method

Abstract

This invention discloses a high-switching-ratio power converter with self-balancing current and voltage and its control method, belonging to the field of power electronics technology. The high-switching-ratio power converter proposed in this invention can achieve current / voltage self-balancing without applying additional control circuitry. Based on the charge balance relationship of the flying capacitor during the proposed control process, the inductor current can automatically reach balance without applying additional control circuitry. Based on the voltage clamping relationship caused by the reverse conduction of the semiconductor switching diode, the flying capacitor voltage can automatically reach balance without applying additional control circuitry. This not only simplifies the control circuit design and improves operational reliability, but also ensures optimal current ripple cancellation when the inductor currents are superimposed, reducing output current ripple.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and more specifically, relates to a high-switching-ratio converter with current and voltage self-balancing and its control method. Background Technology

[0002] To meet the growing power demands of applications such as data centers and automotive electronics, power supply bus voltage is gradually evolving from 12V to 48V to reduce energy transfer losses on the lines. High-transfer-ratio power converters can directly convert high-voltage bus voltage to the supply voltage required by low-voltage loads, thus exhibiting good power density and conversion efficiency, and are suitable for point-of-load power supply under the 48V bus voltage standard.

[0003] Existing high-slew-ratio power converter topologies employ a cascaded structure of a discontinuous buck charge pump and a continuous buck converter. The discontinuous buck charge pump enables pre-stepping with high power density, while the continuous buck converter allows for precise output voltage regulation and avoids hard charging by the charge pump. By combining the advantages of both, this cascaded structure allows for high-slew-ratio continuous bucking while maintaining power density and efficiency.

[0004] Traditional switching buck converters require extremely narrow duty cycles (D) to achieve very high slew rates (CR) for voltage conversion. At higher operating frequencies, this narrow duty cycle results in extremely short switching on-times. However, due to limitations imposed by control and drive circuit delays, the switching on-time cannot be lower than the system's minimum requirement. Therefore, traditional switching buck converters struggle to achieve extremely high slew rates. Secondly, traditional switching buck converters suffer from current-voltage overlap losses during the switching process of their power devices. Since the switching voltage of a traditional switching buck converter equals the bus voltage, an increase in the bus voltage leads to higher overlap losses, resulting in decreased converter efficiency. Finally, when multiple phases of a traditional switching buck converter operate in parallel, the mismatch in circuit parasitic parameters causes an imbalance in the current carried by each phase in the open-loop state, leading to localized component heating and accelerated aging, severely impacting the converter's reliability. In addition, the voltage on the flying capacitor of existing converters that can achieve high slew rate cannot be guaranteed to be balanced in open-loop condition, which may lead to increased output current ripple and degraded converter performance. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a high-switching-ratio converter with self-balancing current and voltage and its control method, thereby solving the problems of limited switching ratio, large switching overlap loss, and current / voltage imbalance in existing buck converters.

[0006] To achieve the above objectives, the present invention provides a high transfer ratio converter with current-voltage self-balancing, comprising: first to sixth switches S1 to S6, first to third flying capacitors C1 to C3, first and second inductors L1 and L2, and an output capacitor C. o ;

[0007] S1's drain is connected to the input voltage V. BUS The source is connected to one end of C1 and the drain of S2;

[0008] The drain of S2 is connected to the source of S1 and one end of C1, and the source of S2 is connected to the drain of S3 and one end of C2.

[0009] The drain of S3 is connected to the source of S2 and one end of C2, and the source of S3 is connected to the drain of S4 and one end of C3.

[0010] The drain of S4 is connected to the source of S3 and one end of C3, and the source of S4 is connected to the drain of S6 and the other end of C2.

[0011] The drain of S5 is connected to the other end of C1 and one end of L1, and the source is connected to ground.

[0012] The drain of S6 is connected to the other end of C2 and one end of L2, and the source is connected to ground.

[0013] One end of L1 is connected to the drain of S5, the other end of C1, and the other end of C3; the other end is connected to C... o One end;

[0014] One end of L2 is connected to the source of S4, the drain of S6, and the other end of C2. The other end is connected to C. o One end;

[0015] C o The other end is connected to the ground.

[0016] Furthermore, the current-voltage self-balancing high-switching converter has 5 operating phases in the operating mode;

[0017] In phase Φ1, S1 and S6 are on, while S2 to S5 are off; V BUS When L1 is energized by C1, the voltage across L1 is V. L1 =V BUS -V C1 -V Co L2 demagnetizes, and the voltage V across L2 decreases. L2 =-V Co ;

[0018] In phase Φ2, S2 and S5 are on, while S1, S3, S4, and S6 are off; C1 and C2 are connected in series to excite L2, and the voltage across L2 is V. L2 =V C1 -VC2 -V Co L1 demagnetizes, and the voltage V across L1 increases. L1 =-V Co ;

[0019] In phase Φ3, S3 and S6 are on, while S1, S2, S4, and S5 are off; C2 and C3 are connected in series to excite L1, and the voltage across L1 is V. L1 =V C2 -V C3 -V Co L2 demagnetizes, and the voltage V across L2 decreases. L2 =-V Co ;

[0020] In phase Φ4, S4 and S5 are conducting, while S1-S3 and S6 are disconnected; C3 energizes L2, and the voltage across L2 is V. L2 =V C3 -V Co L1 demagnetizes, and the voltage V across L1 increases. L1 =-V Co ;

[0021] In phase Φ5, S5 and S6 are conducting, while S1 to S4 are disconnected; L1 and L2 are demagnetized, and the voltage across L1 and L2 is equal to -V. Co ;

[0022] The converter operates alternately with a 90° phase difference between any adjacent phases from Φ1 to Φ4. Phases other than Φ1 to Φ4 operate at phase Φ5, where V... C1 V is the voltage across C1. C2 V is the voltage across C2. C3 V is the voltage across C3. Co C o Voltage at both ends.

[0023] Furthermore, the volt-second balance relationship between the inductors L1 and L2 in steady state is expressed as follows:

[0024]

[0025] Among them, T sw For switching cycles;

[0026] In steady state under operating mode, the relationship between the slip ratio CR and duty cycle D of the current-voltage self-balancing high slip ratio converter is expressed as follows:

[0027] Furthermore, the voltage across C1 is 3V. BUS / 4, the voltage across C2 is V BUS / 2, the voltage across C3 is V BUS / 4, so that the flying capacitors C1 to C3 can achieve voltage balance.

[0028] This invention also provides a control method for a high-switching-ratio converter with self-balancing current and voltage, controlling the switches in the aforementioned high-switching-ratio converter, specifically including:

[0029] In phase Φ1, S1 and S6 are on, while S2 to S5 are off; V BUS When L1 is energized by C1, the voltage across L1 is equal to (V). BUS -V C1 -V Co L2 demagnetizes, and the voltage across L2 equals -V. Co ;

[0030] In phase Φ2, S2 and S5 are on, while S1, S3, S4, and S6 are off; C1 and C2 are connected in series to excite L2, and the voltage across L2 is equal to (V C1 -V C2 -V Co L1 demagnetizes, and the voltage across L1 equals -V. Co ;

[0031] In phase Φ3, S3 and S6 are on, while S1, S2, S4, and S5 are off; C2 and C3 are connected in series to excite L1, and the voltage across L1 is equal to (V C2 -V C3 -V Co L2 demagnetizes, and the voltage across L2 equals -V. Co ;

[0032] In phase Φ4, S4 and S5 are conducting, while S1-S3 and S6 are disconnected; C3 energizes L2, and the voltage across L2 is equal to (V). C3 -V Co L1 demagnetizes, and the voltage across L1 equals -V. Co ;

[0033] In phase Φ5, S5 and S6 are conducting, while S1 to S4 are disconnected; L1 and L2 are demagnetized, and the voltage across L1 and L2 is equal to -V. Co ;

[0034] Φ1~Φ4 alternate between any two adjacent phases with a 90° phase difference, where V C1 V is the voltage across C1. C2 V is the voltage across C2. C3 V is the voltage across C3. Co C o Voltage at both ends.

[0035] The present invention also provides a computer-readable storage medium comprising a stored computer program, wherein the computer program, when executed by a processor, controls the aforementioned control method of the device where the storage medium is located.

[0036] The present invention also provides an electronic device, comprising: a computer-readable storage medium and a processor;

[0037] The computer-readable storage medium is used to store executable instructions;

[0038] The processor is used to read executable instructions stored in the computer-readable storage medium and execute the control method described above.

[0039] Compared with the prior art, the above-described technical solutions conceived in this invention can achieve the following results.

[0040] Beneficial effects:

[0041] 1. The high-transfer-ratio power converter topology and its control method proposed in this invention can achieve current / voltage self-balancing without the application of additional control circuitry. Based on the charge balance relationship of the flying capacitor during the proposed control process, the inductor current can automatically reach balance without additional control circuitry. Based on the voltage clamping relationship caused by the reverse conduction of the semiconductor switching diode during the proposed control process, the flying capacitor voltage can automatically reach balance without the application of additional control circuitry. This not only simplifies the control circuit design and improves operational reliability, but also ensures optimal current ripple cancellation when the inductor currents are superimposed, reducing output current ripple.

[0042] 2. The high slew rate power converter topology proposed in this invention uses only 6 semiconductor switches, compared to existing high slew rate power converter topologies, and the switching voltage is V. BUS / 4. By reducing the number of semiconductor switches and the switching voltage, the power loss caused by current-voltage overlap during high-frequency switching is reduced, thereby improving the energy efficiency of the converter. Attached Figure Description

[0043] Figure 1 This is a circuit topology for an existing high-switching-ratio power converter;

[0044] Figure 2 This presents a control method and key waveforms for an existing high-switching-ratio power converter.

[0045] Figure 3 The present invention provides a circuit topology for a high-switching-ratio power converter;

[0046] Figure 4This invention provides a control method and key waveforms for a high-switching-ratio power converter.

[0047] Figure 5 This invention provides a potential voltage clamping relationship that a high-transfer-ratio power converter satisfies during the high-side conduction phase. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0049] A conventional high-transfer-ratio power converter topology and its control method are described. Figure 1 , Figure 2 express. Figure 1 The topology and structure of this converter are shown. It consists of a cascaded 2:1 charge pump and dual buck converters, including seven semiconductor switches S1 to S7, two flying capacitors C1 and C2, and two inductors L1 and L2. The 2:1 charge pump can pre-reduce the bus voltage by half, while the dual buck converters can further reduce the output voltage of the charge pump to the voltage required by the load with a transfer ratio of 2 / D.

[0050] Figure 2 The control method and key waveforms of the converter topology are illustrated. The converter has four operating phases (Φ1 to Φ4). During the high-side conduction of phase Φ1, S1 and S3 are turned on; C1 and C2 are connected in series and pass through I... L1 Charging; L1 excitation, its high-side voltage is equal to (V BUS -V C1 -V C2 L2 demagnetizes, and its low-side voltage is equal to 0. During the high-side conduction of Φ2 phase, S5 and S6 are turned on; C1 is turned off, and C2 passes through I. L2 Discharge; L2 is energized, and its high-side voltage is equal to V. C2 L1 demagnetizes, and its low-side voltage is equal to 0. During the high-side conduction of Φ3 phase, S2 and S4 are turned on; C1 and C2 are connected in series, and C1 passes through I... L1 Discharge, C1 passes through I L1 Charging; L1 excitation, its high-side voltage is equal to (V C1 -V C2 L2 demagnetizes, and its low-side voltage is equal to 0. During the high-side conduction of Φ4 phase, S5 and S6 are turned on; C1 is turned off, and C2 passes through I. L2 Discharge; L2 is energized, and its high-side voltage is equal to V. C2L1 is demagnetized, and its low-side voltage is equal to 0. During the low-side conduction period of phases Φ1 to Φ4, S5 and S7 are turned on; C1 and C2 are turned off; L1 and L2 are demagnetized, and their low-side voltages are both equal to 0. In order to achieve maximum inductor current ripple cancellation, any adjacent phases of Φ1 to Φ4 alternate with a 90° phase difference. According to the working principle, the volt-second balance relationship of inductors L1 and L2 in steady state can be described by formula (1):

[0051]

[0052] Assuming that in equilibrium, the voltage across C1 (V) C1 ) is V BUS / 2, Voltage across C2 (V) C2 ) is V BUS / 4, substituting into formula (1), the transfer ratio of the converter topology can be derived as:

[0053]

[0054] In existing high-slew-ratio power converter topologies, the voltage across the flying capacitor cannot automatically reach equilibrium. Without additional control circuitry, V can only be derived from the steady-state volt-second balance of L1 and L2. C2 equals V BUS / 4, while V C1 It can be any value. If V C1 Deviation from equilibrium value (V) during operation BUS If the current change rate is not equal on L1 and L2, then the optimal current ripple cancellation cannot be achieved when they are superimposed, which will eventually lead to the deterioration of the output current ripple.

[0055] The semiconductor switches S1 to S4 used in the 2:1 charge pump of the existing high-switching power converter topology operate at V BUS At a switching voltage of / 2, the overlapping of current and voltage during the switching process generates energy loss, which is proportional to the switching voltage. High switching voltage semiconductor switches S1 to S4 will cause high power loss during high-frequency switching, thereby reducing the energy efficiency of the converter.

[0056] The circuit schematic of this invention is shown below. Figure 3 As shown. The high-turnover power converter topology consists of semiconductor switches S1 to S6, flying capacitors C1 to C3, inductors L1 and L2, and output capacitor C. o composition.

[0057] The drain of S1 is connected to the input voltage V. BUSThe source of S2 is connected to one end of C1 and the drain of S2; the drain of S2 is connected to the source of S1 and one end of C1, and its source is connected to the drain of S3 and one end of C2; the drain of S3 is connected to the source of S2 and one end of C2, and its source is connected to the drain of S4 and one end of C3; the drain of S4 is connected to the source of S3 and one end of C3, and its source is connected to the drain of S6 and the other end of C2; the drain of S5 is connected to the other end of C1 and one end of L1, and its source is connected to ground; the drain of S6 is connected to the other end of C2 and one end of L2, and its source is connected to ground; one end of inductor L1 is connected to the drain of S5, the other end of C1, and the other end of C3, and the other end is connected to C... o One end of inductor L2 is connected to the source of S4, the drain of S6, and the other end of C2. o One end.

[0058] Figure 4 The control method and key waveforms of the converter topology are illustrated. The converter has four operating phases (Φ1 to Φ4), and within one cycle, the time outside of phases Φ1 to Φ4 can be considered as Φ5. During the high-side conduction of phase Φ1, S1 and S6 are turned on; C2 and C3 are turned off, and C1 conducts through I... L1 Charging; L1 excitation, its high-side voltage is equal to (V BUS -V C1 The voltage across the terminals is equal to (V) BUS -V C1 -V Co When L2 demagnetizes, its low-side voltage is equal to 0, and the voltage across its terminals is equal to -V. Co During the high-side conduction of phase Φ2, S2 and S5 are turned on; C3 is turned off, and C1 and C2 are connected in series and pass through I. L2 Discharge; L2 excitation, its high-side voltage equals (V C1 -V C2 The voltage across the terminals is equal to (V) C1 -V C2 -V Co When L1 is demagnetized, its low-side voltage is equal to 0, and the voltage across its terminals is equal to -V. Co During the high-side conduction of phase Φ3, S3 and S6 are turned on; C1 is turned off, and C2 and C3 are connected in series and pass through I. L1 Discharge; L1 is energized, and its high-side voltage is equal to (V C2 -V C3 The voltage across the terminals is equal to (V) C2 -V C3 -V Co When L2 demagnetizes, its low-side voltage is equal to 0, and the voltage across its terminals is equal to -V. Co During the high-side conduction of Φ4 phase, S4 and S5 are turned on; C1 and C2 are turned off, and C3 passes through I. L2 Discharge; L2 is energized, and its high-side voltage is equal to V. C3 The voltage across the terminals is equal to (V) C3 -VCo During the low-side conduction period of phases Φ1 to Φ4, S5 and S7 are on; C1 to C3 are off; L1 and L2 are demagnetized, and their low-side voltages are both equal to 0, with the voltage across them equal to -V. Co To achieve maximum inductor current ripple cancellation, Φ1 to Φ4 alternate between any adjacent phases with a 90° phase difference. Based on this working principle, the charge balance relationship of the flying capacitors C1 to C3 in steady state can be described by formula (3):

[0059] I L1 ·(DT SW ) = I L2 ·(DT SW (3)

[0060] Based on the charge balance relationship described in formula (3), the current balance flowing through the converter inductors L1 and L2 can be derived:

[0061] I L1 =I L2 (4)

[0062] Furthermore, due to the presence of a parasitic body diode within the semiconductor switch, under the aforementioned control method, the potential voltage clamping relationship satisfied by the voltage across the flying capacitors C1 to C3 during the high-side conduction phase of phases Φ1 to Φ4 is as follows: Figure 5 As shown, and can be described by formula (5):

[0063]

[0064] Where V TH The threshold voltage for the parasitic diode to conduct is approximately 0.7V. By solving and simplifying the system of inequalities in the simultaneous equations, the voltage balance of the converter capacitor can be derived, and the balance values ​​are as follows:

[0065]

[0066] The balance error is ±V TH Due to the self-balancing current / voltage of the converter, its operational reliability is superior to that of traditional switching buck converters and existing high-switching buck converters.

[0067] Furthermore, based on the aforementioned working principle, the volt-second balance relationship between inductors L1 and L2 in steady state can be described by formula (7):

[0068]

[0069] Substituting equation (6) into equation (7), the transfer ratio of the converter topology can be derived as follows:

[0070]

[0071] Compared to traditional switching buck converter topologies, the transfer ratio is increased by 4 times.

[0072] Finally, since the voltage across the flying capacitor automatically stabilizes near its equilibrium value during operation, under the aforementioned control method, all semiconductor switches used in the converter topology operate at V... BUS At a switching voltage of / 4, compared to existing high-switching-ratio buck converters, the energy loss caused by current-voltage overlap during switching is reduced, thus improving energy efficiency.

[0073] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A current-voltage self-balancing high conversion ratio converter, characterized in that, Comprise: First to sixth switches S1-S6, first to third flying capacitors C1-C3, first and second inductors L1 and L2, output capacitor C o ; The drain of S1 is connected to the input voltage V BUS The source of S1 is connected to the drain of S2. The drain of S2 connects the source of S1 and one end of C1, and the drain of S3 connects the source of S2 and one end of C2; The drain of S3 connects the source of S2 and one end of C2, and the drain of S4 connects the source of S3 and one end of C3; The drain of S4 connects the source of S3 and one end of C3, and the drain of S6 connects the other end of C2 and one end of L2; The drain of S5 connects the other end of C1 and one end of L1, and the source is connected to the ground; The drain of S6 connects the other end of C2 and one end of L2, and the source is connected to the ground; One end of L1 is connected to the drain of S5, the other end of C1 and the other end of C3, and the other end is connected to one end of C o . One end of L2 is connected to the source of S4, the drain of S6 and the other end of C2, and the other end is connected to one end of C o . C o the other end is connected.

2. The current voltage self-balancing high conversion ratio converter of claim 1, wherein, The current-voltage self-balanced high-voltage conversion ratio converter has five working phases Φ1-Φ5 in the working mode; In Φ1 phase, S1 and S6 are on, S2~S5 are off; V BUS By C1 exciting L1, the voltage V L1 =V BUS -V C1 -V Co ; L2 demagnetization, the voltage V L2 =-V Co ; In Φ2 phase, S2 and S5 are on, S1, S3, S4 and S6 are off; C1 and C2 are in series to excite L2, the voltage V L2 = V C1 -V C2 -V Co at both ends of L2; L1 is de-excited, the voltage V L1 =-V Co at both ends of L1; In Φ3 phase, S3 and S6 are on, S1, S2, S4 and S5 are off; C2 and C3 are in series to excite L1, the voltage V across L1 is L1 =V C2 -V C3 -V Co ; L2 is de-excited, the voltage V across L2 is L2 =-V Co ; In Φ4 phase, S4 and S5 are on, S1-S3 and S6 are off; C3 excites L2, voltage V L2 =V C3 -V Co appears at both ends of L2; L1 is demagnetized, voltage V L1 =-V Co appears at both ends of L1; In Φ5 phase, S5 and S6 are turned on, S1-S4 are turned off; L1 and L2 are demagnetized, and the voltage across L1 and L2 is equal to -V Co ; Φ1~Φ4 any adjacent phase between the phase difference of 90 ° alternating operation, Φ1~Φ4 phase outside the transformer works in the Φ5 phase, wherein V C1 is the C1 voltage across both ends, V C2 is the C2 voltage across both ends, V C3 is the C3 voltage across both ends, V Co is the C o voltage across both ends.

3. The current voltage self-balancing high-convertion-ratio converter of claim 1, wherein, The volt-second balance relationship of the inductors L1 and L2 in the steady state is represented as: wherein T sw is the switch period, V C1 is the voltage across C1, V C2 is the voltage across C2, V C3 is the voltage across C3, V Co is the voltage across C o is the voltage across C When in steady state in the working mode, the relationship between the conversion ratio CR and the duty cycle D of the current-voltage self-balanced high conversion ratio converter is expressed as: .

4. The current voltage self-balancing high-convertion-ratio converter of claim 1, wherein, In the flying capacitor C1~C3 voltage equalization, C1 voltage is 3V BUS / 4, C2 voltage is V BUS / 2, C3 voltage is V BUS / 4.

5. A control method of a current-voltage self-balancing high conversion ratio converter, characterized by, The control method of the current-voltage self-balanced high-voltage conversion ratio converter according to any one of claims 1 to 4, specifically comprises: In Φ1 phase, S1 and S6 are turned on, and S2-S5 are turned off; V BUS By exciting L1 through C1, the voltage across L1 is equal to (V BUS -V C1 -V Co ); L2 is demagnetized, and the voltage across L2 is equal to -V Co ; In Φ2 phase, S2 and S5 are on, S1, S3, S4 and S6 are off; C1 and C2 are in series to excite L2, the voltage across L2 is equal to (V C1 -V C2 -V Co ); L1 is de-excited, the voltage across L1 is equal to -V Co ; In Φ3 phase, S3 and S6 are on, S1, S2, S4 and S5 are off; C2 and C3 are in series to excite L1, the voltage across L1 is equal to (V C2 -V C3 -V Co ); L2 is de-excited, the voltage across L2 is equal to -V Co ; In Φ4 phase, S4 and S5 are on, S1-S3 and S6 are off; C3 excites L2, voltage across L2 equals (V C3 -V Co ); L1 is demagnetized, voltage across L1 equals -V Co ; In Φ5 phase, S5 and S6 are turned on, S1-S4 are turned off; L1 and L2 are demagnetized, and the voltage across L1 and L2 is equal to -V Co ; Φ1~Φ4 any adjacent phase between the phase difference of 90 ° alternating operation, wherein V C1 is the voltage across C1, V C2 is the voltage across C2, V C3 is the voltage across C3, V Co is the voltage across C o is the voltage across C.

6. A computer readable storage medium characterized by The computer readable storage medium comprises a stored computer program, wherein the computer program controls the device where the storage medium is located to execute the control method according to claim 5 when the computer program is run by the processor.

7. An electronic device, comprising: Comprise: A computer readable storage medium and a processor; The computer readable storage medium is used to store executable instructions; The processor is used to read the executable instructions stored in the computer readable storage medium, and execute the control method according to claim 5.

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