Calibration method and device, equipment, storage medium and program product

Abstract

The invention discloses a calibration method and device, equipment, a storage medium and a program product, and the method comprises the steps: determining a data set in a preset register list, wherein the data set comprises a plurality of groups of candidate bias voltages of a to-be-calibrated chip; according to a data set in a preset register list, values of bias voltage of the chip to be calibrated are sequentially adjusted, a radio frequency signal received by the chip to be calibrated is tested, test data of multiple groups of N-order intermodulation points are obtained, and N is a positive integer; determining at least two candidate intermodulation points based on the test data of the plurality of groups of N-order intermodulation points; and retesting the radio frequency signal received by the chip to be calibrated according to the at least two candidate intermodulation points, and determining a target intermodulation point. Therefore, aiming at the intermodulation distortion problem in the radio frequency system, the signal distortion and interference can be more effectively reduced, and the accuracy of test data is ensured; moreover, the calibration efficiency can be improved, the test cost is reduced, and the overall performance of the radio frequency system is improved.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a calibration method, apparatus, device, storage medium and program product. Background Art

[0002] In wireless communication systems, the quality of RF signals is critical to system performance. Many electronic devices and systems rely on RF signal processing and transmission. However, nonlinear distortion problems often occur in RF systems, especially intermodulation distortion (IMD). Intermodulation distortion can cause signal distortion and interference, thus affecting the performance of electronic devices and the accuracy of data.

[0003] In the related art, although there are some solutions to intermodulation distortion, the existing calibration methods usually take a lot of time and resources, are difficult to achieve high accuracy and high efficiency, and reduce the overall performance of the RF system. Summary of the invention

[0004] The present application proposes a calibration method, apparatus, device, storage medium and program product, which can improve calibration efficiency and reduce testing costs, thereby improving the overall performance of the radio frequency system.

[0005] The technical solution of this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a calibration method, the method comprising:

[0007] Determine a data set in a preset register list; wherein the data set includes multiple sets of candidate bias voltages for the chip to be calibrated;

[0008] The bias voltage value of the chip to be calibrated is adjusted in sequence according to the data set in the preset register list, and a plurality of groups of test data of N-order intermodulation points are obtained by testing the radio frequency signal received by the chip to be calibrated, where N is a positive integer;

[0009] Determine at least two candidate intermodulation points based on multiple groups of N-order intermodulation point test data;

[0010] The radio frequency signal received by the chip to be calibrated is retested according to at least two candidate intermodulation points to determine a target intermodulation point.

[0011] In a second aspect, an embodiment of the present application provides a calibration device, the calibration device comprising a determination unit, a test unit and a retest unit, wherein:

[0012] A determination unit configured to determine a data set in a preset register list; wherein the data set includes multiple groups of candidate bias voltages of the chip to be calibrated;

[0013] The test unit is configured to adjust the bias voltage value of the chip to be calibrated in sequence according to the data set in the preset register list, and obtain multiple groups of test data of N-order intermodulation points by testing the radio frequency signal received by the chip to be calibrated, where N is a positive integer;

[0014] The determination unit is further configured to determine at least two candidate intermodulation points based on the test data of the multiple groups of N-order intermodulation points;

[0015] The retest unit is configured to retest the radio frequency signal received by the chip to be calibrated according to at least two candidate intermodulation points to determine a target intermodulation point.

[0016] In a third aspect, an embodiment of the present application provides a calibration device, the calibration device comprising a memory and a processor, wherein:

[0017] A memory for storing computer programs that can be run on the processor;

[0018] A processor is used to execute the method described in the first aspect when running a computer program.

[0019] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method described in the first aspect is implemented.

[0020] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program or instructions, which implement the method described in the first aspect when the computer program or instructions are executed by a processor.

[0021] A calibration method, apparatus, device, storage medium and program product provided by the embodiments of the present application determine a data set in a preset register list, the data set including multiple groups of candidate bias voltages of a chip to be calibrated; adjust the bias voltage values ​​of the chip to be calibrated in sequence according to the data set in the preset register list, and obtain multiple groups of test data of N-order intermodulation points by testing the radio frequency signal received by the chip to be calibrated, where N is a positive integer; determine at least two candidate intermodulation points based on the test data of the multiple groups of N-order intermodulation points; and retest the radio frequency signal received by the chip to be calibrated according to the at least two candidate intermodulation points to determine the target intermodulation point. In this way, the intermodulation distortion problem in the radio frequency system can be more effectively reduced by reducing signal distortion and interference, ensuring the accuracy of the test data, and dynamically adjusting the bias voltage of the chip to be calibrated according to the data set in the preset register list can also improve the test accuracy, while improving the calibration efficiency and reducing the time cost required for the test process; in addition, adaptively adjusting the bias voltage of the chip to be calibrated according to the data set in the preset register list can also avoid errors and waste that may exist in the traditional manual adjustment method, and improve the resource utilization efficiency during the test process; and the calibration method can also ensure the stability and robustness of the system during the test process, reduce the system performance fluctuations caused by nonlinear distortion, and make the system stable and reliable, thereby improving the overall performance of the radio frequency system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a calibration method provided in an embodiment of the present application Figure 1 ;

[0023] Figure 2 A schematic diagram of a calibration method provided in an embodiment of the present application Figure 2 ;

[0024] Figure 3 A schematic diagram of a calibration method provided in an embodiment of the present application Figure 3 ;

[0025] Figure 4 A schematic diagram of a calibration method provided in an embodiment of the present application Figure 4 ;

[0026] Figure 5 A schematic diagram of a calibration method provided in an embodiment of the present application Figure 5 ;

[0027] Figure 6 A schematic diagram of the structure of a calibration device provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the hardware structure of a calibration device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0031] It should also be noted that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0032] It should also be noted that in the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0033] To facilitate understanding of the technical solutions of the embodiments of the present application, the relevant technologies of the embodiments of the present application are described below. The following related technologies can be arbitrarily combined with the technical solutions of the embodiments of the present application as optional solutions, and they all belong to the protection scope of the embodiments of the present application.

[0034] With the rapid development of wireless communication technology, wireless communication system products are becoming more and more popular. Radio Frequency (RF) chips are at the forefront of wireless communication systems, and their structure and performance directly affect the entire communication system. Typically, many electronic devices and systems rely on RF signal processing and transmission. The quality of RF signals is critical to the performance of wireless communication systems, radar systems, and other RF applications. However, nonlinear distortion problems often occur in RF systems, and one of the main problems is intermodulation distortion (IMD). Intermodulation distortion can cause signal distortion and interference, which can affect the performance of the device and the accuracy of the data.

[0035] In order to solve the intermodulation distortion problem, researchers are constantly working to find feasible calibration methods. Although there are some solutions to intermodulation distortion, the existing calibration methods usually take a lot of time and resources, and it is difficult to achieve high accuracy and high efficiency. Therefore, there is an urgent need for a more intelligent and effective calibration technology to improve the overall performance of the RF system.

[0036] In recent years, variable adjustment and fitting algorithms have attracted widespread attention in the field of RF system calibration. This calibration method is based on some adjustable parameters in the system and uses mathematical models and optimization algorithms to find the best parameter configuration to minimize intermodulation distortion and improve system performance. Among them, controlling the bias voltage of the RF chip by adjusting the value of the register is considered to be an effective calibration method.

[0037] Based on this, in order to improve test efficiency and reduce test costs, a new technical solution is proposed for the current chip test calibration, specifically, an optimal intermodulation point calibration method based on variable adjustment and fitting algorithm is proposed. The core idea of ​​this calibration method is: by accurately adjusting the bias voltage of the RF chip to minimize intermodulation distortion, it can improve the overall performance of the system and solve the problems of long calibration time and low accuracy in related technologies.

[0038] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0039] In one embodiment of the present application, Figure 1 A schematic diagram of a calibration method provided in an embodiment of the present application Figure 1 .like Figure 1 As shown, the method may include:

[0040] S101, determining a data set in a preset register list.

[0041] In the embodiment of the present application, nonlinear distortion problems often occur during the test process of the chip to be tested in the radio frequency system, especially intermodulation distortion, which will cause signal distortion and interference, thereby affecting the overall performance of the system. Among them, intermodulation distortion refers to the distortion of the sum and difference of an input signal introduced by an amplifier. For example, if two signals act on the input end of the amplifier at the same time, then due to the nonlinear characteristics of the components, it will cause the interaction between the two signals, and generate additional signals that are not in the original signal. This distortion caused by the mutual modulation of the signals is called intermodulation distortion.

[0042] It should be noted that in the embodiments of the present application, the calibration method can be applied to a calibration device, or a calibration device integrated with the device. The calibration device here refers to an electronic device with a calibration function. For example, taking a test system as an example, the test system may include a calibration device and a calibrated RF chip (referred to as a "chip to be calibrated"), and the calibration device can perform test and calibration on the intermodulation distortion of the RF chip.

[0043] It should also be noted that, in the embodiment of the present application, in order to solve the intermodulation distortion problem, a preset register list is provided here, and the preset register list can be set in the RF chip, that is, the chip to be calibrated described in this article. Then, the bias voltage of the chip to be calibrated is adjusted according to the data set in the preset register list to minimize the intermodulation distortion. Among them, in the preset register list, the data set can include multiple sets of candidate bias voltages of the chip to be calibrated.

[0044] It should also be noted that after the chip to be calibrated receives the RF signal, the RF signal can generate two paths through signal processing: an in-phase component (Inphase, I) and a quadrature component (Quadrate, Q), which are synchronized in time but have a phase difference of 90 degrees. In this way, for the preset register list, the data set therein can include an in-phase data set and a quadrature data set. Accordingly, each set of candidate bias voltages can include an in-phase data (i.e., I data) and a quadrature data (i.e., Q data).

[0045] Exemplarily, referring to Table 1, a list of 8 scan register values ​​is defined here, so as to ensure that the test data of the intermodulation point is fluctuating and continuous during calibration.

[0046] Table 1

[0047]

[0048] As shown in Table 1, taking the first row of register values ​​as an example, the in-phase data set (I data set) may include: 48, 56, 64, 72, 80; the quadrature data set (Q data set) may include: 47, 55, 63, 71, 79. By using double traversal of the IQ data set (including the I data set and the Q data set), for example, the I data set includes 5 data and the Q data set includes 5 data, 5*5=25 parameter combinations can be formed, thereby effectively covering the parameter space and increasing the accuracy and robustness of calibration.

[0049] S102, adjusting the bias voltage value of the chip to be calibrated in sequence according to the data set in the preset register list, and obtaining multiple groups of N-order intermodulation point test data by testing the radio frequency signal received by the chip to be calibrated, where N is a positive integer.

[0050] It should be noted that the value of N can be 2, 3, 4, etc. Among them, if the value of N is 2, it can be called the second-order intermodulation point (Inter Modulation Two, IM2); if the value of N is 3, it can be called the third-order intermodulation point (Inter Modulation Three, IM3). In the embodiment of the present application, the calibration method is described in detail below by taking the IM2 point as an example.

[0051] It should also be noted that in the embodiment of the present application, in combination with the data set in the preset register list shown in Table 1, the double traversal of the IQ data set is used to adjust the value of the bias voltage of the chip to be calibrated in turn, which can effectively cover the parameter space and ensure that the scanned IM2 test data is fluctuating and continuous. Among them, the bias voltage may include an I component bias voltage and a Q component bias voltage. Here, the I component bias voltage can be adjusted by traversing the in-phase data set (I data set), and the Q component bias voltage can be adjusted by traversing the orthogonal data set (Q data set) to achieve double traversal of the IQ data set. In the embodiment of the present application, taking N=2 as an example, the RF signal received by the chip to be calibrated contains a second-order intermodulation distortion amount. By adjusting the bias voltage of the chip to be calibrated in turn, multiple groups of IM2 point test data can be obtained for the received RF signal test. Among them, a group of IM2 point test data can be obtained for each group of candidate bias voltages, so that according to the multiple groups of candidate bias voltages in the preset register list, multiple groups of IM2 point test data can be obtained.

[0052] Exemplarily, taking the first row of register values ​​as an example, the in-phase data set (I data set) may include: 48, 56, 64, 72, 80; the quadrature data set (Q data set) may include: 47, 55, 63, 71, 79. The bias voltage values ​​may be set to (48, 47), (48, 55), (48, 63), (48, 71), (48, 79), (56, 47), (56, 55), (56, 63), (56, 71), (56, 79), (64, 47), (64, 55), (64, 63), (64, 71), (64, 79) ..., (80, 79) and other 25 cases, thereby obtaining 25 IM2 test data. For the 8 scan register values ​​in Table 1, a total of 25+25+25+36+36+36+49+49+100=531 IM2 test data can be obtained.

[0053] S103: Determine at least two candidate intermodulation points based on multiple groups of N-order intermodulation point test data.

[0054] It should be noted that, in the embodiment of the present application, after obtaining multiple groups of N-order intermodulation point test data, at least two candidate intermodulation points can be determined accordingly, wherein the at least two candidate intermodulation points here may include a first candidate intermodulation point and a second candidate intermodulation point.

[0055] In some embodiments, determining at least two candidate intermodulation points based on multiple groups of test data of N-order intermodulation points may include: performing a fitting operation on the multiple groups of test data of N-order intermodulation points to obtain a fitting function, and performing an optimal solution based on the fitting function to determine a first candidate intermodulation point; and determining the intermodulation point with the best test performance in the multiple groups of test data of N-order intermodulation points as the second candidate intermodulation point.

[0056] That is to say, in the embodiment of the present application, the first candidate intermodulation point may be the optimal intermodulation point (or referred to as the "best intermodulation point") determined by the fitting algorithm, and the second candidate intermodulation point may be the intermodulation point with the best test performance among these candidate intermodulation points.

[0057] In a specific implementation, for the first candidate intermodulation point, multiple groups of N-order intermodulation point test data may be fitted to obtain a fitting function; then an optimal solution is obtained based on the fitting function to determine the first candidate intermodulation point.

[0058] Exemplarily, for the fitting expression adopted by the fitting operation, the formula may be as follows:

[0059] f(x,y)=p1x n y m +p2x n-1 y m +…+p n+1 y m +

[0060] p n+2 x n y m-1 +p n+3 x n-1 y m-1 +…+p 2n+2 y m-1 +

[0061] …

[0062] p m(n+1)+1 x n +p m(n+1)+2 x n-1 +…+p m(n+1)+n+1 (1)

[0063] Here, f(x, y) represents a two-dimensional matrix, x represents the value vector of the independent variable X, y represents the value vector of the independent variable Y, n represents the highest degree of X in the polynomial, and m represents the highest degree of Y in the polynomial. The fitting calculation is performed according to the formula and the coefficient vector p of the polynomial is returned to obtain the final fitting function; the optimal solution is obtained through the fitting function, and the obtained optimal solution is determined as the first candidate intermodulation point.

[0064] S104, retesting the radio frequency signal received by the chip to be calibrated according to at least two candidate intermodulation points to determine a target intermodulation point.

[0065] In an embodiment of the present application, after obtaining at least two candidate intermodulation points, the received RF signal can be retested according to the at least two candidate intermodulation points (e.g., the first candidate intermodulation point and the second candidate intermodulation point), and the retest results corresponding to the two candidate intermodulation points can be obtained; the intermodulation point with the best retest performance (i.e., the second-order intermodulation distortion in the received RF signal is the smallest) is selected as the target intermodulation point, so that the intermodulation distortion can be minimized. Exemplarily, taking the second-order intermodulation as an example, the target intermodulation point finally determined can be the optimal IM2 point.

[0066] That is to say, in the embodiment of the present application, a method for calibrating the best IM2 point based on variable adjustment and fitting algorithm is specifically provided, and the variable adjustment refers to adjusting the value of the bias voltage. First, by defining the change step size of the scan register, the continuity and volatility of the IM2 scan value are ensured. This register change scan can make the calibration process more comprehensive and accurate, and improve the system performance; then, by using the IQ double traversal in the register list, the parameter space can be effectively covered to find the best IM2 point, and the design of this double loop traversal increases the accuracy and robustness of the calibration; in addition, the IM2 value obtained by the test and the corresponding register setting are used as a matrix, and the best IM2 point is calculated using a polynomial fitting algorithm. The introduction of this fitting algorithm also provides an accurate and efficient way to determine the best calibration point; then the best IM2 point obtained is retested and compared to find the final best IM2 point. This retest method is also highly reliable and accurate, which can ensure the selection of the best calibration point.

[0067] The embodiment of the present application provides a calibration method, which is based on the combination of variable adjustment and fitting algorithm. It can more effectively reduce signal distortion and interference and ensure the accuracy of test data for the intermodulation distortion problem in the radio frequency system. It can also improve the test accuracy by dynamically adjusting the bias voltage according to the data set in the preset register list, while improving the calibration efficiency and reducing the time cost required for the test process. In addition, the bias voltage is adaptively adjusted according to the preset register list, which can also avoid the errors and waste that may exist in the traditional manual adjustment method, and improve the resource utilization efficiency during the test process. Moreover, the calibration method can also ensure the stability and robustness of the system during the test process, reduce the system performance fluctuations caused by nonlinear distortion, and make the system stable and reliable, thereby improving the overall performance of the radio frequency system.

[0068] In another embodiment of the present application, based on the calibration method described in the above embodiment, the bias voltage of the chip to be calibrated may include a first group of bias voltages and a second group of bias voltages.

[0069] In the embodiment of the present application, the first group of bias voltages may include a first bias voltage and a second bias voltage, and the second group of bias voltages may include a third bias voltage and a fourth bias voltage. The first bias voltage may be represented by vbias_ip_sel, the second bias voltage may be represented by vbias_qp_sel, the third bias voltage may be represented by vbias_in_sel, and the fourth bias voltage may be represented by vbias_qn_sel.

[0070] In the embodiment of the present application, the first bias voltage may be referred to as the I component bias voltage in the first group, the second bias voltage may be referred to as the Q component bias voltage in the first group; the third bias voltage may be referred to as the I component bias voltage in the second group, and the fourth bias voltage may be referred to as the Q component bias voltage in the second group. Here, the I component bias voltage may be represented by vbias_i, and the Q component bias voltage may be represented by vbias_q. That is, vbias_i may be composed of vbias_ip_sel and vbias_in_sel, and vbias_q may be composed of vbias_qp_sel and vbias_qn_sel.

[0071] In addition, in the embodiment of the present application, for the scan register defined by the bias voltage, the first bias voltage is vbias_ip_sel<20:14>, the third bias voltage is vbias_in_sel<27:21>, the second bias voltage is vbias_qp_sel<6:0>, and the fourth bias voltage is vbias_qn_sel<6:0>. It should be noted that <20:14>, <27:21>, <6:0>, <6:0>, etc. refer to the floating range of the scan register.

[0072] In some embodiments, Figure 2 A schematic diagram of a calibration method provided in an embodiment of the present application Figure 2 .like Figure 2 As shown, the method may include:

[0073] S201, determining a data set in a preset register list.

[0074] It should be noted that in the embodiment of the present application, the preset register list is shown in Table 1. Among them, in order to ensure that the test data of the intermodulation point is fluctuating and continuous during calibration, Table 1 defines a list of 8 scan register values. In the test, the test frequency point and port are determined according to the test frequency band actually required, and then reasonable adaptation is performed according to the test frequency point and port.

[0075] It should also be noted that, in the embodiment of the present application, the data set in the preset register list may include an in-phase data set (I data set) and an orthogonal data set (Q data set), wherein the I data set includes multiple I data, and the Q data set includes multiple Q data. In other words, the data set here may include multiple groups of candidate bias voltages for the chip to be calibrated, and each group of candidate bias voltages includes one I data and one Q data.

[0076] It can be seen from Table 1 that there are repetitions in the IQ data in the preset register list. For example, there are a lot of repetitions in the register values ​​in the first, fourth, and seventh rows of Table 1. This is because the test data of the intermodulation point fluctuates. In some cases, multiple tests are performed on a certain combination of bias voltages, and then a set of test data with the best test performance is found.

[0077] It can be understood that in an embodiment of the present application, when testing the received RF signal, for the first group of bias voltages and the second group of bias voltages, the value of one group of bias voltages can be fixed first, and then the value of the other group of bias voltages can be adjusted in sequence according to the data set in the preset register list.

[0078] S202, fixing the values ​​of the first group of bias voltages, adjusting the values ​​of the second group of bias voltages in sequence according to the data sets in the preset register list, and obtaining multiple groups of first test data of N-order intermodulation points by testing the radio frequency signal received by the chip to be calibrated.

[0079] In an embodiment of the present application, the values ​​of the first group of bias voltages may be fixed first. The first group of bias voltages includes a first bias voltage and a second bias voltage. Accordingly, fixing the values ​​of the first group of bias voltages may include: setting the first bias voltage and the second bias voltage to preset constant values.

[0080] Exemplarily, the preset constant value may be 63. That is, the first bias voltage and the second bias voltage are set to 63. For example, vbias_ip_sel=vbias_qp_sel=63.

[0081] After fixing the values ​​of the first group of bias voltages, the values ​​of the second group of bias voltages can then be adjusted in sequence according to the data sets in the preset register list. In some embodiments, adjusting the values ​​of the second group of bias voltages in sequence according to the data sets in the preset register list can include: setting the third bias voltage and the fourth bias voltage to the current cycle value in the in-phase data set and the current cycle value in the orthogonal data set, respectively, by looping through the in-phase data set and the orthogonal data set in the preset register list.

[0082] That is to say, in an embodiment of the present application, the dynamic adjustment of the second group of bias voltages can be implemented based on a preset register list. Specifically, the I data set and the Q data set in the preset register list can be looped through, and the values ​​of the second group of bias voltages can be set while traversing. Exemplarily, after fixing vbias_ip_sel=vbias_qp_sel=63, the I data set and the Q data set in the preset register list are looped through, and the values ​​of the second group of bias voltages (vbias_in_sel and vbias_qn_sel) are set to be equal to the current loop value, and then the first test data of multiple groups of IM2 points are obtained through testing.

[0083] S203, fixing the values ​​of the second group of bias voltages, adjusting the values ​​of the first group of bias voltages in sequence according to the data sets in the preset register list, and obtaining multiple groups of second test data of N-order intermodulation points by testing the radio frequency signal received by the chip to be calibrated.

[0084] In the embodiment of the present application, the value of the second group of bias voltages can be fixed at this time. Wherein, the second group of bias voltages includes a third bias voltage and a fourth bias voltage. Accordingly, fixing the value of the second group of bias voltages can include: setting the third bias voltage and the fourth bias voltage to preset constant values.

[0085] Exemplarily, the preset constant value may also be 63. That is, the third bias voltage and the fourth bias voltage are set to 63. For example, vbias_in_sel=vbias_qn_sel=63.

[0086] After fixing the values ​​of the second group of bias voltages, the values ​​of the first group of bias voltages can then be adjusted in sequence according to the data sets in the preset register list. In some embodiments, adjusting the values ​​of the first group of bias voltages in sequence according to the data sets in the preset register list can include: looping through the in-phase data set and the orthogonal data set in the preset register list, and setting the first bias voltage and the second bias voltage to the current cycle value in the in-phase data set and the current cycle value in the orthogonal data set, respectively.

[0087] That is to say, in the embodiment of the present application, the dynamic adjustment of the first group of bias voltages can also be implemented based on the preset register list. Specifically, the I data set and the Q data set in the preset register list can be looped through, and the values ​​of the first group of bias voltages can be set while traversing. Exemplarily, after fixing vbias_in_sel=vbias_qn_sel=63, the I data set and the Q data set in the preset register list are looped through, and the values ​​of the first group of bias voltages (vbias_ip_sel and vbias_qp_sel) are set to be equal to the current loop value, and then the second test data of multiple groups of IM2 points are obtained through testing.

[0088] S204: Determine at least two candidate intermodulation points according to the plurality of groups of first test data of N-order intermodulation points and the plurality of groups of second test data of N-order intermodulation points.

[0089] In the embodiment of the present application, the at least two candidate intermodulation points may be optimal intermodulation points obtained according to a fitting algorithm, for example, the at least two candidate intermodulation points at this time may include a first optimal intermodulation point and a second optimal intermodulation point. The first optimal intermodulation point may be obtained by fitting calculation based on the first test data of the multiple groups of N-order intermodulation points obtained in step S202, and the second optimal intermodulation point may be obtained by fitting calculation based on the second test data of the multiple groups of N-order intermodulation points obtained in step S203.

[0090] In the embodiment of the present application, the at least two candidate intermodulation points may also include an optimal intermodulation point with the best test performance, for example, the at least two candidate intermodulation points at this time may also include a third optimal intermodulation point and a fourth optimal intermodulation point. The third optimal intermodulation point refers to an intermodulation point with the best test performance in the first test data of multiple groups of N-order intermodulation points, and the fourth optimal intermodulation point refers to an intermodulation point with the best test performance in the second test data of multiple groups of N-order intermodulation points.

[0091] S205 , retesting the radio frequency signal received by the chip to be calibrated according to at least two candidate intermodulation points to determine a target intermodulation point.

[0092] In an embodiment of the present application, after obtaining at least two candidate intermodulation points, the received RF signal can be retested according to the at least two candidate intermodulation points (e.g., the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point, and the fourth optimal intermodulation point), and the retest results corresponding to the four candidate intermodulation points can be obtained; the intermodulation point that can minimize the second-order intermodulation distortion in the received RF signal, that is, the intermodulation point with the best retest performance is selected as the target intermodulation point, so as to minimize the intermodulation distortion. For example, taking the second-order intermodulation as an example, the target intermodulation point finally determined can be the optimal IM2 point.

[0093] In another embodiment of the present application, based on the calibration method described in the above embodiment, see Figure 3 After step S203, the method may further include:

[0094] S301, performing fitting operation on a plurality of groups of first test data of N-order intermodulation points to obtain a first fitting function, and performing optimal solution according to the first fitting function to determine a first optimal intermodulation point.

[0095] Here, the first optimal intermodulation point may be obtained by fitting and calculating the first test data of the multiple groups of N-order intermodulation points obtained in step S202.

[0096] For example, taking the second-order intermodulation point (IM2) as an example, for the first test data of the multiple groups of N-order intermodulation points obtained in step S202, the IM2 test value and the corresponding bias voltage (vbias_i, vbias_q) can be mapped into a matrix, and then the fitting calculation is performed through the above formula (1) to obtain a first fitting function. By performing optimal solution on the first fitting function, the first optimal intermodulation point can be fitted, that is, the best IM2 point (vbias_i, vbias_q, IM2 test value) fitted in this case.

[0097] S302, performing fitting operation on the plurality of groups of second test data of N-order intermodulation points to obtain a second fitting function, and performing optimal solution according to the second fitting function to determine a second optimal intermodulation point.

[0098] Here, the second optimal intermodulation point may be obtained by fitting and calculating the second test data of the multiple groups of N-order intermodulation points obtained in step S203.

[0099] For example, taking the second-order intermodulation point (IM2) as an example, for the second test data of the multiple groups of N-order intermodulation points obtained in step S203, the IM2 test value and the corresponding bias voltage (vbias_i, vbias_q) can also be mapped into a matrix, and then the fitting calculation is performed through the above formula (1) to obtain a second fitting function. By performing optimal solution on the second fitting function, the second optimal intermodulation point can be fitted, that is, the best IM2 point (vbias_i, vbias_q, IM2 test value) fitted in this case.

[0100] S303, determining a third optimal intermodulation point having the best test performance among the first test data of the multiple groups of N-order intermodulation points, and determining a fourth optimal intermodulation point having the best test performance among the second test data of the multiple groups of N-order intermodulation points.

[0101] S304, re-testing the radio frequency signal received by the chip to be calibrated according to the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point, and the fourth optimal intermodulation point to determine a target intermodulation point.

[0102] It should be noted that in the embodiment of the present application, there is no particular order in which step S301, step S302, and step S303 are executed. Step S301 and step S302 may be executed first, and then step S303; or step S303 may be executed first, and then step S301 and step S302, etc., without any limitation here.

[0103] In addition, in an embodiment of the present application, after obtaining the above-mentioned four candidate intermodulation points, the received RF signal can be retested according to the four candidate intermodulation points (for example, the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point and the fourth optimal intermodulation point), and the retest results corresponding to each of the four candidate intermodulation points can be obtained; the target intermodulation point is determined therefrom to minimize the intermodulation distortion.

[0104] In some embodiments, for determining the target intermodulation point, see Figure 4 , step S304 may further include the following steps:

[0105] S304-1, re-testing the radio frequency signal received by the chip to be calibrated according to the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point and the fourth optimal intermodulation point, and determining the re-test data corresponding to the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point and the fourth optimal intermodulation point.

[0106] S304-2, according to the re-measurement data corresponding to the first optimal inter-modulation point, the second optimal inter-modulation point, the third optimal inter-modulation point and the fourth optimal inter-modulation point, determine the inter-modulation point with the best re-measurement performance as the target inter-modulation point.

[0107] That is to say, in the embodiment of the present application, in order to obtain a more accurate optimal intermodulation point, the four intermodulation points obtained are retested to obtain retest data of the four intermodulation points; then the intermodulation point that can minimize the second-order intermodulation distortion in the received RF signal, that is, the intermodulation point with the best retest performance is selected as the target intermodulation point, so as to minimize the intermodulation distortion. For example, taking the second-order intermodulation as an example, the target intermodulation point finally determined can be the optimal IM2 point.

[0108] Thus, in the embodiment of the present application, in order to solve the intermodulation distortion problem in the RF chip testing process, an intelligent and efficient calibration method is proposed here, which can more effectively reduce signal distortion and interference, ensure the accuracy of test data, and dynamically adjust the bias voltage according to the data set in the preset register list, so as to improve the test accuracy, while improving the calibration efficiency and reducing the time cost required for the testing process; in addition, the bias voltage is adaptively adjusted according to the data set in the preset register list, so as to avoid the errors and waste that may exist in the traditional manual adjustment method, and improve the resource utilization efficiency in the testing process; and the calibration method can also ensure the stability and robustness of the system during the testing process, reduce the system performance fluctuations caused by nonlinear distortion, make the system stable and reliable, and thus improve the overall performance of the RF system.

[0109] In another embodiment of the present application, based on the calibration method described in the above embodiment, taking the second-order intermodulation point as an example, Figure 5 A schematic diagram of a calibration method provided in an embodiment of the present application Figure 5 .like Figure 5 As shown, the method may include:

[0110] S501, register step definition.

[0111] In the embodiment of the present application, for the register step definition, the calibration method ensures that the value of the IM2 point scan has a large value and a small value by defining the scanned register change step. This definition of register change can make the calibration process more comprehensive and accurate, and improve system performance.

[0112] S502, looping the IQ data set and fixing a specific register value.

[0113] In the embodiment of the present application, for the IQ double loop traversal, the calibration method uses a double loop to traverse the register list of the I data set and the Q data set, and fixes a specific register value for testing, which can effectively cover the parameter space and find the best IM2 point. This double loop traversal design increases the accuracy and robustness of the calibration.

[0114] S503, determine the best IM2 point by polynomial fitting.

[0115] In the embodiment of the present application, for the polynomial fitting algorithm, the IM2 value obtained by the test and the corresponding register are mapped into a data matrix, and then the optimal IM2 point is calculated using the polynomial fitting algorithm. The introduction of this fitting algorithm provides an accurate and efficient way to determine the optimal calibration point.

[0116] S504, re-measure the IM2 value and compare it to determine the target intermodulation point.

[0117] In the embodiment of the present application, for the comparison of the retested IM2 values, the best IM2 point obtained in the previous operation is brought into the retest, and the retested IM2 values ​​are compared to find the final best IM2 point to minimize the intermodulation distortion. This comparison method of the retested IM2 values ​​is highly reliable and accurate, and can ensure the selection of the best calibration point.

[0118] That is, in the embodiment of the present application, a calibration method for the best IM2 point based on variable adjustment and fitting algorithm is proposed. First, the register change is defined. The calibration method ensures that the value of the IM2 scan has continuity and volatility by defining the register change step of the scan. This register change scan can make the calibration process more comprehensive and accurate, and improve the system performance. Then, a double loop is used to traverse the list of IQ data sets, so that the fixed register value is used to perform a double traversal of the IQ data set to effectively cover the parameter space and find the best IM2 point. This double loop traversal design increases the accuracy and robustness of the calibration. The IM2 value obtained by the test and the corresponding register setting are used as a matrix, and the best IM2 point is calculated using a polynomial fitting algorithm. The introduction of this fitting algorithm provides an accurate and efficient way to determine the best calibration point. In addition, for the comparison of the retest IM2 value, the best IM2 point obtained by the above steps is brought into the retest IM2 value, and compared to find the best IM2 point. This comparison method of the retest IM2 value is highly reliable and accurate, and can ensure the selection of the best calibration point.

[0119] In a possible implementation, the calibration method may specifically include:

[0120] Step 1, define the stepping of the floating range of the scanned registers (vbias_ip_sel<20:14>, vbias_in_sel<27:21>, vbias_qp_sel<6:0>, vbias_qn_sel<6:0>);

[0121] Step 2: To ensure that the scanned IM2 value is fluctuating and continuous, as shown in Table 1, eight scan register value lists are defined here, and reasonable adaptation is performed according to the tested frequency and port;

[0122] Step 3, fix vbias_ip_sel = vbias_qp_sel = 63, loop through the register list that previously selected I and Q, set vbias_in_sel and vbias_qn_sel values ​​to the current loop values ​​while looping, test IM2 values ​​and record the results;

[0123] Step 4, fix vbias_in_sel = vbias_qn_sel = 63, loop through the previously selected I and Q register lists, set vbias_ip_sel and vbias_qp_sel values ​​to the current loop values ​​while looping, test the IM2 value and record the result;

[0124] Step 5, mapping the test IM2 value in step 3 and the corresponding vbias_i and vbias_q data into a matrix, and calculating through a fitting formula to obtain a fitted optimal IM2 point (vbias_i, vbias_q, IM2);

[0125] Step 6, mapping the test IM2 value in step 4 and the corresponding vbias_i and vbias_q data into a matrix, and calculating through a fitting formula to obtain a fitted optimal IM2 point (vbias_i, vbias_q, IM2);

[0126] Step 7: Take the best IM2 point fitted in steps 5 and 6 and the point with the best IM2 test performance, a total of 4 points, into the retest IM2 value to find the best IM2 point as the final target intermodulation point.

[0127] The fitting formula used in step 5 and step 6 is shown in the above formula (1). Here, f(x, y) represents a two-dimensional matrix, x represents the value vector of the independent variable X, y represents the value vector of the independent variable Y, n represents the highest degree of X in the polynomial, and m represents the highest degree of Y in the polynomial. The fitting calculation is performed according to the formula and the coefficient vector p of the polynomial is returned, thereby obtaining the final fitting function; the optimal solution is obtained through the fitting function, and the optimal solution obtained is determined as the best IM2 point.

[0128] In the embodiment of the present application, the specific implementation of the aforementioned embodiment is elaborated in detail through the above embodiment. It can be seen that an optimal IM2 point calibration method based on variable adjustment and fitting algorithm is proposed here, aiming to solve the problem of long calibration time and low precision of the traditional calibration method. By introducing variable adjustment and fitting algorithm, on the one hand, the test accuracy can be improved: the intelligent calibration method can calibrate the chip more accurately by dynamic adjustment, thereby improving the accuracy and reliability of the test. In particular, for the intermodulation distortion problem in the radio frequency system, it can more effectively reduce signal distortion and interference, and ensure the accuracy of the test data. On the other hand, the calibration efficiency is improved: through intelligent optimization algorithm and adaptive parameter adjustment, this calibration method can quickly find the best parameter configuration, improve the efficiency of calibration and reduce the time cost required for the test process. This will help to improve the overall test efficiency, shorten the product launch cycle, and reduce R&D costs. On the other hand, reduce the test cost: the intelligent calibration method can be adaptively adjusted according to the real-time system status, avoiding the errors and waste that may exist in the traditional manual adjustment method, thereby reducing the cost of the test. In addition, through the global optimization algorithm and the data-driven calibration model, the waste of resources can be minimized and the resource utilization efficiency in the test process can be improved. On the other hand, the system stability is enhanced: through the real-time feedback mechanism, the calibration method can timely discover and correct the intermodulation distortion problem, ensure the stability and robustness of the system during the test, reduce the system performance fluctuations caused by nonlinear distortion, and improve the stability and reliability of the system. In summary, the calibration method proposed in the embodiment of the present application has the beneficial technical effects of high precision, high speed, enhanced system stability and improved test efficiency in the chip IM2 calibration test, thereby improving the overall performance of the RF system.

[0129] In yet another embodiment of the present application, Figure 6 A schematic diagram of the structure of a calibration device provided in an embodiment of the present application. Figure 6 As shown, the calibration device 60 may include a determination unit 601, a test unit 602 and a retest unit 603, wherein:

[0130] The determining unit 601 is configured to determine a data set in a preset register list; wherein the data set includes multiple groups of candidate bias voltages of the chip to be calibrated;

[0131] The test unit 602 is configured to adjust the bias voltage value of the chip to be calibrated in sequence according to the data set in the preset register list, and obtain multiple groups of N-order intermodulation point test data by testing the radio frequency signal received by the chip to be calibrated, where N is a positive integer;

[0132] The determination unit 601 is further configured to determine at least two candidate intermodulation points based on the test data of multiple groups of N-order intermodulation points;

[0133] The re-test unit 603 is configured to re-test the radio frequency signal received by the chip to be calibrated according to at least two candidate inter-modulation points to determine a target inter-modulation point.

[0134] In some embodiments, the at least two candidate intermodulation points include a first candidate intermodulation point and a second candidate intermodulation point; see Figure 6 The calibration device 60 may further include a fitting unit 604, configured to perform a fitting operation on the test data of multiple groups of N-order intermodulation points to obtain a fitting function, and perform an optimal solution based on the fitting function to determine a first candidate intermodulation point; and a determination unit 601, further configured to determine the intermodulation point with the best test performance in the test data of the multiple groups of N-order intermodulation points as the second candidate intermodulation point.

[0135] In some embodiments, the bias voltage of the chip to be calibrated includes a first group of bias voltages and a second group of bias voltages; accordingly, the test unit 602 is also configured to fix the value of the first group of bias voltages, adjust the value of the second group of bias voltages in sequence according to the data set in the preset register list, and obtain multiple groups of first test data of N-order intermodulation points by testing the radio frequency signal received by the chip to be calibrated; and fix the value of the second group of bias voltages, adjust the value of the first group of bias voltages in sequence according to the data set in the preset register list, and obtain multiple groups of second test data of N-order intermodulation points by testing the radio frequency signal received by the chip to be calibrated.

[0136] In some embodiments, at least two candidate intermodulation points include a first optimal intermodulation point and a second optimal intermodulation point; accordingly, the fitting unit 604 is also configured to perform a fitting operation on the first test data of multiple groups of N-order intermodulation points to obtain a first fitting function, and perform an optimal solution based on the first fitting function to determine the first optimal intermodulation point; and perform a fitting operation on the second test data of multiple groups of N-order intermodulation points to obtain a second fitting function, and perform an optimal solution based on the second fitting function to determine the second optimal intermodulation point.

[0137] In some embodiments, the determination unit 601 is further configured to determine a third optimal intermodulation point with the best test performance in the first test data of multiple groups of N-order intermodulation points, and to determine a fourth optimal intermodulation point with the best test performance in the second test data of multiple groups of N-order intermodulation points; the re-test unit 603 is further configured to re-test the RF signal received by the chip to be calibrated according to the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point and the fourth optimal intermodulation point to determine the target intermodulation point.

[0138] In some embodiments, the re-test unit 603 is further configured to re-test the RF signal received by the chip to be calibrated according to the first optimal inter-modulation point, the second optimal inter-modulation point, the third optimal inter-modulation point and the fourth optimal inter-modulation point, and determine the re-test data corresponding to the first optimal inter-modulation point, the second optimal inter-modulation point, the third optimal inter-modulation point and the fourth optimal inter-modulation point; according to the re-test data corresponding to the first optimal inter-modulation point, the second optimal inter-modulation point, the third optimal inter-modulation point and the fourth optimal inter-modulation point, the inter-modulation point with the best re-test performance is determined as the target inter-modulation point.

[0139] In some embodiments, the first group of bias voltages includes a first bias voltage and a second bias voltage; accordingly, the test unit 602 is further configured to set the first bias voltage and the second bias voltage to 63 .

[0140] In some embodiments, the second group of bias voltages includes a third bias voltage and a fourth bias voltage; accordingly, the test unit 602 is further configured to set the third bias voltage and the fourth bias voltage to 63.

[0141] In some embodiments, the data set in the preset register list includes an in-phase data set and an orthogonal data set; accordingly, the test unit 602 is also configured to set the third bias voltage and the fourth bias voltage to the current cycle value in the in-phase data set and the current cycle value in the orthogonal data set, respectively, by looping through the in-phase data set and the orthogonal data set in the preset register list.

[0142] In some embodiments, the test unit 602 is further configured to set the first bias voltage and the second bias voltage to the current cycle value in the in-phase data set and the current cycle value in the orthogonal data set respectively by looping through the in-phase data set and the orthogonal data set in the preset register list.

[0143] It is understandable that in the embodiments of the present application, a "unit" may be a part of a circuit, a part of a processor, a part of a program or software, etc., and of course, it may be a module, or it may be non-modular. Moreover, the components in the present embodiment may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional module.

[0144] If the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the method described in this embodiment. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0145] Therefore, this embodiment provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by at least one processor, the steps of the calibration method described in any one of the above embodiments are implemented.

[0146] In some embodiments, Figure 7 A schematic diagram of the hardware structure of a calibration device provided in an embodiment of the present application. Figure 7 As shown, the calibration device 70 may include: a communication interface 701, a memory 702 and a processor 703; each component is coupled together via a bus system 704. It is understood that the bus system 704 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 704 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 7 Various buses are labeled as bus system 704. Among them, the communication interface 701 is used for receiving and sending signals during the process of sending and receiving information with the chip under test;

[0147] A memory 702, used to store a computer program that can be run on the processor 703;

[0148] The processor 703 is configured to execute, when running the computer program:

[0149] Determine a data set in a preset register list; wherein the data set includes multiple groups of candidate bias voltages of the chip to be calibrated; sequentially adjust the values ​​of the bias voltages of the chip to be calibrated according to the data set in the preset register list, and obtain multiple groups of test data of N-order intermodulation points by testing the radio frequency signal received by the chip to be calibrated, where N is a positive integer; determine at least two candidate intermodulation points based on the test data of the multiple groups of N-order intermodulation points; retest the radio frequency signal received by the chip to be calibrated according to the at least two candidate intermodulation points to determine the target intermodulation point.

[0150] It can be understood that the memory 702 in the embodiment of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus random access memory (DRRAM). The memory 702 of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0151] The processor 703 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 703. The above processor 703 may be a general processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware decoding processor to be executed, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 702, and the processor 703 reads the information in the memory 702 and completes the steps of the above method in combination with its hardware.

[0152] It is understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit may be implemented in one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in the present application, or a combination thereof.

[0153] For software implementation, the techniques described herein can be implemented by modules (e.g., procedures, functions, etc.) that perform the functions described herein. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0154] Optionally, as another embodiment, the processor 703 is further configured to execute the steps of the method described in any one of the aforementioned embodiments when running the computer program.

[0155] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

[0156] An embodiment of the present application further provides a computer program product comprising instructions, including a computer program or instructions, which, when executed by a processor, implements the steps in the calibration method provided in the foregoing embodiment.

[0157] The embodiment of the present application also provides a computer program, which can be applied to the calibration device in the embodiment of the present application. When the computer program is run, the calibration device can execute the steps in the calibration method provided in the aforementioned embodiment.

[0158] It should be understood that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium, storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0159] It should be understood that "one embodiment" or "an embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in one embodiment" or "in some embodiments" appearing throughout the specification may not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments. The above description of each embodiment tends to emphasize the differences between the various embodiments, and the same or similar aspects can be referenced to each other. For the sake of brevity, this article will not repeat them.

[0160] It should also be noted that in this application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0161] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0162] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0163] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0164] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0165] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0166] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A calibration method, characterized in that: The method comprises: Determine a data set in a preset register list; wherein the data set includes multiple groups of candidate bias voltages for the chip to be calibrated; The bias voltage value of the chip to be calibrated is adjusted in sequence according to the data set in the preset register list, and multiple groups of test data of N-order intermodulation points are obtained by testing the radio frequency signal received by the chip to be calibrated, where N is a positive integer; Determine at least two candidate intermodulation points based on the test data of the multiple groups of N-order intermodulation points; The radio frequency signal received by the chip to be calibrated is retested according to the at least two candidate intermodulation points to determine a target intermodulation point.

2. The method according to claim 1, characterized in that The at least two candidate intermodulation points include a first candidate intermodulation point and a second candidate intermodulation point; and the determining at least two candidate intermodulation points based on the test data of the multiple groups of N-order intermodulation points includes: Performing a fitting operation on the test data of the multiple groups of N-order intermodulation points to obtain a fitting function, and performing an optimal solution according to the fitting function to determine the first candidate intermodulation point; and An intermodulation point with the best test performance among the test data of the multiple groups of N-order intermodulation points is determined as the second candidate intermodulation point.

3. The method according to claim 1, characterized in that The bias voltage of the chip to be calibrated includes a first group of bias voltages and a second group of bias voltages; The step of sequentially adjusting the bias voltage value of the chip to be calibrated according to the data set in the preset register list, and obtaining multiple groups of N-order intermodulation point test data by testing the radio frequency signal received by the chip to be calibrated, includes: Fixing the values ​​of the first group of bias voltages, adjusting the values ​​of the second group of bias voltages in sequence according to the data sets in the preset register list, and obtaining the first test data of the multiple groups of N-order intermodulation points by testing the radio frequency signal received by the chip to be calibrated; The values ​​of the second group of bias voltages are fixed, the values ​​of the first group of bias voltages are adjusted in sequence according to the data sets in the preset register list, and the second test data of the multiple groups of N-order intermodulation points are obtained by testing the radio frequency signal received by the chip to be calibrated.

4. The method according to claim 3, characterized in that The at least two candidate intermodulation points include a first optimal intermodulation point and a second optimal intermodulation point; and the determining at least two candidate intermodulation points based on the test data of the multiple groups of N-order intermodulation points includes: Performing a fitting operation on the first test data of the multiple groups of N-order intermodulation points to obtain a first fitting function, and performing an optimal solution according to the first fitting function to determine the first optimal intermodulation point; A fitting operation is performed on the plurality of groups of second test data of N-order intermodulation points to obtain a second fitting function, and an optimal solution is performed according to the second fitting function to determine the second optimal intermodulation point.

5. The method according to claim 4, characterized in that The method further comprises: Determine a third optimal intermodulation point having the best test performance in the first test data of the multiple groups of N-order intermodulation points, and determine a fourth optimal intermodulation point having the best test performance in the second test data of the multiple groups of N-order intermodulation points; The retesting the radio frequency signal received by the chip to be calibrated according to the at least two candidate intermodulation points to determine the target intermodulation point includes: The radio frequency signal received by the chip to be calibrated is retested according to the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point, and the fourth optimal intermodulation point to determine the target intermodulation point.

6. The method according to claim 5, characterized in that The retesting the radio frequency signal received by the chip to be calibrated according to the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point, and the fourth optimal intermodulation point to determine the target intermodulation point includes: Re-test the radio frequency signal received by the chip to be calibrated according to the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point, and the fourth optimal intermodulation point, and determine the re-test data corresponding to each of the first optimal intermodulation point, the second optimal intermodulation point, the third optimal intermodulation point, and the fourth optimal intermodulation point; According to the re-test data corresponding to the first optimal inter-modulation point, the second optimal inter-modulation point, the third optimal inter-modulation point and the fourth optimal inter-modulation point, the inter-modulation point with the best re-test performance is determined as the target inter-modulation point.

7. The method according to any one of claims 3 to 6, characterized in that The first group of bias voltages includes a first bias voltage and a second bias voltage, and the second group of bias voltages includes a third bias voltage and a fourth bias voltage; The fixing of the values ​​of the first group of bias voltages includes: setting the first bias voltage and the second bias voltage to 63; The fixing of the values ​​of the second group of bias voltages includes: setting the third bias voltage and the fourth bias voltage to 63.

8. The method according to claim 7, characterized in that The data sets in the preset register list include an in-phase data set and an orthogonal data set; The step of sequentially adjusting the values ​​of the second group of bias voltages according to the data sets in the preset register list comprises: setting the third bias voltage and the fourth bias voltage to the current cycle value in the in-phase data set and the current cycle value in the orthogonal data set respectively by looping through the in-phase data set and the orthogonal data set in the preset register list; The step of sequentially adjusting the values ​​of the first group of bias voltages according to the data sets in the preset register list includes: looping through the in-phase data set and the orthogonal data set in the preset register list, and setting the first bias voltage and the second bias voltage to the current cycle value in the in-phase data set and the current cycle value in the orthogonal data set, respectively.

9. A calibration device, characterized in that: The calibration device comprises a determination unit, a test unit and a retest unit, wherein: The determining unit is configured to determine a data set in a preset register list; wherein the data set includes multiple groups of candidate bias voltages of the chip to be calibrated; The test unit is configured to adjust the bias voltage value of the chip to be calibrated in sequence according to the data set in the preset register list, and obtain multiple groups of N-order intermodulation point test data by testing the radio frequency signal received by the chip to be calibrated, where N is a positive integer; The determining unit is further configured to determine at least two candidate intermodulation points based on the test data of the multiple groups of N-order intermodulation points; The retest unit is configured to retest the radio frequency signal received by the chip to be calibrated according to the at least two candidate intermodulation points to determine a target intermodulation point.

10. A calibration device, characterized in that: The calibration device comprises a memory and a processor, wherein: The memory is used to store a computer program that can be run on the processor; The processor is configured to execute the method according to any one of claims 1 to 8 when running the computer program.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

12. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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