Clock synchronization method and device of signal sequence, electronic equipment and storage medium

Abstract

The invention provides a clock synchronization method and device for a signal sequence, electronic equipment and a storage medium, and the method comprises the steps: receiving a first signal sequence transmitted through a channel between a signal transmitting end and a signal receiving end, and carrying out the demodulation of the first signal sequence, and obtaining a second signal sequence; performing dispersion compensation on the second signal sequence to obtain a third signal sequence; processing the third signal sequence for multiple times to obtain a target frequency control word; and adjusting a clock carried by the first signal sequence based on the target frequency control word to obtain a target clock, thereby solving the technical problem that the clock carried by the signal sequence determined by the signal receiving end is inaccurate because the influence of optical fiber dispersion on the signal sequence is not considered in the prior art. The purpose of synchronizing the clock of the signal receiving end with the clock carried by the signal sequence sent by the signal sending end is achieved.

Description

Technical Field

[0001] The present application relates to the technical field, and in particular to a clock synchronization method, device, electronic device and storage medium for a signal sequence. Background Art

[0002] Clock recovery is a key technology in digital communication systems. It aims to extract the clock information of the transmitted signal sequence from the received signal sequence in order to correctly perform data demodulation and symbol detection. Clock recovery technology is used to deal with clock offset, phase error and channel distortion introduced during digital signal transmission.

[0003] In the prior art, the clock synchronization between the signal receiving end and the signal transmitting end is performed by the Gardner algorithm. However, in the existing clock synchronization scheme based on the Gardner algorithm, whether it is the realization of low complexity or high precision, most of the functions are realized without considering dispersion. However, in order to transmit more data, the transmission speed of modern optical communication networks is very high, which leads to more serious dispersion broadening of pulse signals in the signal sequence during the transmission process. First, the dispersion broadening will aggravate the inter-symbol interference. The dispersion broadening causes the time delay expansion of the pulse signal during the transmission process, and the different parts of the pulse signal are distorted when they arrive at the receiving end, thereby causing inter-symbol interference. The Gardner algorithm usually assumes that there is no interference between symbols, but the dispersion effect may cause overlap between the received symbols, affecting the estimation of the timing error and the accuracy of the symbol decision. In addition, the dispersion broadening causes the shape of the pulse signal to become blurred, and the front and rear boundaries of different symbols are difficult to accurately identify. The Gardner algorithm relies on the relationship between sampling points to optimize the timing estimation, but due to the dispersion effect, the optimal sampling point may be offset, resulting in a decrease in the timing synchronization performance of the algorithm. Finally, dispersion broadening exacerbates the distortion of the pulse shape and affects the clarity of the received signal. The Gardner algorithm adjusts the sampling time by detecting the peak of the signal, but dispersion broadening will cause the signal to lose its ideal pulse shape, making it difficult for the algorithm to effectively recover symbols. Existing related technologies are difficult to resist dispersion broadening in high-speed communication systems, which will lead to reduced accuracy and performance of the Gardner algorithm, inaccurate clock synchronization, and ultimately greatly increase the bit error rate of the communication system. Summary of the invention

[0004] In view of this, the purpose of the present application is to propose a clock synchronization method, device, electronic device and storage medium for a signal sequence to overcome all or part of the deficiencies in the prior art.

[0005] Based on the above purpose, the present application provides a clock synchronization method for a signal sequence, which is applied to a signal receiving end, and the method includes: receiving a first signal sequence transmitted through a channel between a signal transmitting end and the signal receiving end, and demodulating the first signal sequence to obtain a second signal sequence; performing dispersion compensation on the second signal sequence to obtain a third signal sequence; performing multiple processing on the third signal sequence to obtain a target frequency control word; and adjusting the clock carried by the first signal sequence based on the target frequency control word to obtain a target clock.

[0006] Optionally, the second signal sequence includes a plurality of first pulse signals, and the third signal sequence includes a plurality of second pulse signals; and performing dispersion compensation on the second signal sequence to obtain the third signal sequence comprises: performing dispersion compensation on the second signal sequence by the following formula: s )=IFFT(FFT(x(m1T s ))G1(z,w)), Among them, x'(m2T s ) is the third signal sequence, m2 represents the plurality of second pulse signals, T s is the independent clock sampling period of the signal receiving end, IFFT represents inverse fast Fourier transform, FFT represents fast Fourier transform, x(m1T s ) is the second signal sequence, m1 represents the multiple first pulse signals, G1(z,w) is the transfer function of dispersion in the time domain, j is a complex unit, D is the dispersion coefficient, λ is the wavelength, c is the speed of light, w is the predetermined frequency component, and z represents the signal sequence transmission length.

[0007] Optionally, the third signal sequence includes multiple second pulse signals; the multiple processing of the third signal sequence to obtain a target frequency control word includes: for each processing, performing the following operations: randomly selecting multiple target pulse signals from the multiple second pulse signals, and determining the second frequency control word for the next processing based on the multiple target pulse signals and the first frequency control word of the current processing; in response to determining that the second frequency control word and the first frequency control word are different, using the second frequency control word as the first frequency control word for the next processing and entering the next processing; in response to determining that the second frequency control word and the first frequency control word are the same, exiting multiple processing and determining the second frequency control word as the target frequency control word.

[0008] Optionally, adjusting the clock carried by the first signal sequence based on the target frequency control word to obtain the target clock includes: determining a target sampling clock frequency based on the target frequency control word; and adjusting the clock according to the target sampling clock frequency to obtain the target clock.

[0009] Optionally, determining the second frequency control word for the next processing based on the multiple target pulse signals and the first frequency control word for the current processing includes: performing interpolation calculations on the multiple target pulse signals to obtain a fifth signal sequence corresponding to the current processing; determining a clock error corresponding to the current processing based on the fifth signal sequence; and determining the second frequency control word based on the clock error and the first frequency control word.

[0010] Optionally, performing interpolation calculation on the multiple target pulse signals to obtain a fifth signal sequence corresponding to the current processing includes: performing interpolation calculation on the multiple target pulse signals according to the following formula: μ(k)=kT i / T s -m2'(k), where x'(kT i ) is the fifth signal sequence, x'(m2'T s ) is the third signal sequence, m2' represents the multiple target pulse signals, T s is the independent clock sampling period of the signal receiving end, k is the kth pulse period of interpolation, T i is the sampling period corresponding to cubic interpolation, h I represents the interpolation algorithm, m2'(k)=int(kT i / T s ), m2'(k) represents the basic index of the target pulse signal.

[0011] Optionally, determining a clock error corresponding to a current processing of the signal receiving end based on the fifth signal sequence includes: determining the clock error by using the following formula:

[0012] ξ(n)=y I (n-1 / 2)[y I (n)-y I (n-1)]+y Q (n-1 / 2)[y Q (n)-y Q (n-1)],y I =real(x'(kT i )),y Q =imag(x'(kT i )), where ξ(n) is the clock error corresponding to the current processing, x'(kT i ) is the fifth signal sequence, real represents the real part, imag represents the imaginary part, k is the kth pulse period of the interpolation, T i is the sampling period corresponding to cubic interpolation, and n represents the sequence number of the nth processing.

[0013] Optionally, determining the second frequency control word based on the clock error and the first frequency control word includes: W(n+1)=W(n)+C1[ξ(n)-ξ(n-1)]+C2ξ(n), wherein W(n+1) is the second frequency control word, W(n) is the first frequency control word, C1 is the first proportional coefficient, C2 is the second proportional coefficient, ξ(n) is the clock error of the current processing, ξ(n-1) is the clock error of the previous processing, and n represents the sequence number of the nth processing.

[0014] Based on the same inventive concept, the present application also provides a clock synchronization device for a signal sequence, which is applied to a signal receiving end, and the device includes: a receiving module, configured to receive a first signal sequence transmitted through a channel between a signal transmitting end and the signal receiving end, and demodulate the first signal sequence to obtain a second signal sequence; a dispersion compensation module, configured to perform dispersion compensation on the second signal sequence to obtain a third signal sequence; a processing module, configured to process the third signal sequence multiple times to obtain a target frequency control word; and an adjustment module, configured to adjust the clock carried by the first signal sequence based on the target frequency control word to obtain a target clock.

[0015] Based on the same inventive concept, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method as described above when executing the computer program.

[0016] As can be seen from the above, the clock synchronization method, device, electronic device and storage medium of the signal sequence provided by the present application include receiving a first signal sequence transmitted through a channel between a signal transmitting end and a signal receiving end, and demodulating the first signal sequence to obtain a second signal sequence, so as to achieve the purpose of preliminarily restoring the first signal sequence to the signal sequence sent by the signal transmitting end. The second signal sequence is dispersion compensated to obtain a third signal sequence, which eliminates the influence of optical fiber dispersion on the second signal sequence, so that the second signal sequence is relatively close to the signal sequence sent by the signal transmitting end, and further makes the third signal sequence accurate. The third signal sequence is processed multiple times to obtain a target frequency control word, so that the frequency control word is accurate. Based on the target frequency control word, the clock carried by the first signal sequence is adjusted to obtain the target clock, thereby ensuring the accuracy of the clock carried by the signal sequence determined by the signal receiving end. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of a flow chart of a clock synchronization method for a signal sequence according to an embodiment of the present application;

[0019] Figure 2 A first structural diagram of a clock synchronization method for a signal sequence according to an embodiment of the present application;

[0020] Figure 3 A second structural diagram of a clock synchronization method for a signal sequence according to an embodiment of the present application;

[0021] Figure 4 This is a schematic diagram of the interpolation principle of the clock synchronization method for the signal sequence of an embodiment of the present application;

[0022] Figure 5 A schematic diagram of the timing relationship of sampling points in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of a clock error calculation framework for a signal sequence according to an embodiment of the present application;

[0024] Figure 7 A schematic diagram of a curve showing the variation of the bit error rate with the signal-to-noise ratio under different dispersion conditions in an embodiment of the present application;

[0025] Figure 8 A schematic diagram of a curve showing the variation of the bit error rate with the signal-to-noise ratio before and after dispersion compensation in an embodiment of the present application;

[0026] Fig. 9 A schematic diagram of the structure of a clock synchronization device for a signal sequence according to an embodiment of the present application;

[0027] Fig.10 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0029] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0030] As described in the background technology section, clock recovery is a key technology in digital communication systems, which aims to extract the clock information of the transmitted signal sequence from the received signal sequence in order to correctly perform data demodulation and symbol detection. Clock recovery technology is to deal with clock offset, phase error and channel-induced distortion in the process of digital signal transmission. With the continuous development of communication technology, especially in the fields of high-speed transmission, power transmission system and wireless communication, the accuracy and robustness of clock recovery are increasingly required, which promotes the continuous evolution of clock recovery technology. In early digital communication systems, the technology of clock recovery was relatively simple. The original digital communication system achieved clock synchronization through a special synchronization signal sequence (such as synchronization pulse or specific timing mode). The receiving end usually uses these signal sequences to recover the clock information of the transmitted signal sequence. In this process, the clock recovery method usually relies on sending a timing signal during the transmission process, and the receiving end recovers the clock by detecting the signal. This method is very effective in low-speed systems, but with the development of digital communication technology, especially the rise of high-speed data transmission, this simple clock recovery method has become inaccurate and impractical. Therefore, Phase-Locked Loop (PLL) technology has become an important means of clock recovery. PLL is a widely used technology for clock recovery. It locks the phase of the received signal sequence through a control loop. The basic principle of PLL is to compare the phase difference between the received signal sequence and the local clock signal sequence, and then adjust the local clock to keep it synchronized with the received signal. PLL can not only be used to recover the clock, but also to correct the frequency deviation. PLL has been widely used in communication systems.

[0031] However, as the communication rate continues to increase, the traditional analog PLL gradually exposes its limitations in high-speed digital communication, especially when the frequency changes greatly. With the development of digital communication systems, especially the progress of high-speed signal transmission and digital signal processing, digital phase-locked loop (DPLL) has gradually replaced analog PLL and become the mainstream technology for clock recovery. Digital phase-locked loop (DPLL) is a technology that realizes clock recovery through digital signal processing. DPLL uses digital computers to process the phase error of the input signal and automatically adjusts the local clock through digital algorithms to synchronize it with the clock of the input signal sequence. Compared with traditional analog PLL, DPLL has higher stability and accuracy, and can better adapt to the recovery of high-speed signal sequences. DPLL provides higher accuracy and stronger anti-interference ability through digital means, and is widely used in modern communication systems, especially in fiber-optic communication, high-speed local area network (such as Gigabit Ethernet) and digital television. Through digital signal processing, DPLL can maintain high-precision clock recovery in high noise and frequency drift environments.

[0032] In a general DPLL, it is mainly composed of four parts: interpolation filter, timing error detector, loop filter and control unit. Among the four parts, interpolation filter and timing error detector are the most important. The main function of the interpolation filter in the loop is to use the received asynchronous sampling sequence to fully digitally implement timing adjustment, output the synchronized sampling sequence, and complete the sampling rate conversion function. The process of completing the sampling rate conversion by the interpolation filter can actually be regarded as the second sampling process after the original signal is restored by the sampling value sequence. It is divided into two steps: (1) restore the analog signal through the interpolation filter according to the asynchronous sampling sequence. (2) resample the analog signal periodically to obtain the interpolated signal. In short, the design of the interpolation filter is actually the design of the interpolation filter coefficients. Generally, the commonly used design algorithms that can be used include piecewise parabolic algorithm and Cubic algorithm. The core goal of the timing error detector is to estimate the symbol timing error of the received signal, that is, to find the deviation between the sampling time of the receiving end and the ideal symbol boundary of the signal. This process usually involves sampling and comparing the input signal, and then detecting its offset relative to the ideal sampling time. Specifically, the timing error detector works through the following steps: (1) Signal sampling: The received signal is usually continuous time and needs to be sampled at a specific time. The timing error detector usually performs multiple samplings in each symbol period of the received signal. (2) Error calculation: The timing error is calculated by comparing the difference between the current sampling value of the signal and the ideal symbol boundary (or target sampling time). This error can be positive or negative, indicating that the current sampling point is advanced or delayed relative to the target sampling point. (3) Feedback mechanism: The timing error detector usually generates an error signal, which is used to adjust the sampling time of the system or the local clock to ensure that subsequent sampling can gradually approach the correct symbol timing. The design and working mode of the timing error detector can adopt a variety of methods, mainly based on its feedback mechanism and error estimation method. Common methods include zero-crossing detection, differential detection and maximum likelihood estimation. However, DPLL is sensitive to changes in the initial phase and requires precise initial settings to achieve an ideal locked state.

[0033] In the prior art, the clock synchronization between the signal receiving end and the signal transmitting end is performed by the Gardner algorithm. However, in the existing clock synchronization scheme based on the Gardner algorithm, whether it is the realization of low complexity or high precision, most of the functions are realized without considering dispersion. However, in order to transmit more data, the transmission speed of modern optical communication networks is very high, which leads to more serious dispersion broadening of pulse signals in the signal sequence during the transmission process. First, the dispersion broadening will aggravate the inter-symbol interference. The dispersion broadening causes the time delay expansion of the pulse signal during the transmission process, and the different parts of the pulse signal are distorted when they arrive at the receiving end, thereby causing inter-symbol interference. The Gardner algorithm usually assumes that there is no interference between symbols, but the dispersion effect may cause overlap between the received symbols, affecting the estimation of the timing error and the accuracy of the symbol decision. In addition, the dispersion broadening causes the pulse shape of the pulse signal to become blurred, and the front and rear boundaries of different symbols are difficult to accurately identify. The Gardner algorithm relies on the relationship between sampling points to optimize the timing estimation, but due to the dispersion effect, the optimal sampling point may be offset, resulting in a decrease in the timing synchronization performance of the algorithm. Finally, dispersion broadening exacerbates the distortion of the pulse shape and affects the clarity of the received signal. The Gardner algorithm adjusts the sampling time by detecting the peak of the signal, but dispersion broadening will cause the signal to lose its ideal pulse shape, making it difficult for the algorithm to effectively recover symbols. Existing related technologies are difficult to resist dispersion broadening in high-speed communication systems, which will lead to reduced accuracy and performance of the Gardner algorithm, inaccurate clock synchronization, and ultimately greatly increase the bit error rate of the communication system.

[0034] In view of this, the present application embodiment proposes a clock synchronization method for a signal sequence, referring to Figure 1 , applied to a signal receiving end, the method comprises the following steps:

[0035] Step 101: receiving a first signal sequence transmitted through a channel between a signal transmitting end and a signal receiving end, and demodulating the first signal sequence to obtain a second signal sequence.

[0036] In this step, the signal transmitting end generates a signal sequence, and the above signal sequence is sent to the signal receiving end through the channel between the signal transmitting end and the signal receiving end. However, due to the existence of external influences when the above signal sequence is transmitted in the channel, the above signal sequence changes. For example, the existence of the dispersion effect causes the pulse signal in the above sequence to have a pulse broadening phenomenon. It can be seen that the signal sequence sent by the signal transmitting end and the signal sequence received by the signal receiving end are not the same sequence. The signal receiving end receives the first signal sequence transmitted through the channel. In order for the signal receiving end to accurately process the first signal sequence, first, it is necessary to demodulate the first signal sequence to obtain a second signal sequence, wherein the demodulation can be coherent demodulation, so as to achieve the purpose of preliminarily restoring the first signal sequence to the signal sequence sent by the signal transmitting end.

[0037] It should be noted that at the signal transmitting end, the system laser transmits a signal sequence, which is modulated into a BPSK (Binary Phase Shift Keying) signal sequence by an IQ (I is in-phase, Q is quadrature) modulator. The modulated signal sequence is provided by an arbitrary waveform generator at the signal transmitting end, and its clock is t1, which improves the transmission quality of the signal sequence in the channel. s (t) can be expressed as:

[0038] x s (t1)=I(t1)cos(ωt1)+iQ(t1)cos(ωt1) Formula (1),

[0039] Among them, I(t1)cos(ωt1), Q(t1)sin(ωt1) represent the modulation signals of IQ channels, and i is an imaginary unit. In the channel, the signal sequence sent by the transmitter will be affected by the fiber dispersion, and the signal sequence becomes:

[0040] x s '(t1)=g(z,t1)x s (t1) Formula (2),

[0041] In the formula Among them, z represents the transmission distance of the signal sequence, D represents the dispersion coefficient, λ represents the wavelength, c represents the speed of light, and j is a complex unit.

[0042] At the signal receiving end, coherent detection is used to coherently demodulate the first signal sequence, and data of the first signal sequence is collected through an ADC (analog to digital converter), and the collection clock is t2. At this time, the clock t1 of the signal sending end and the clock t2 of the signal receiving end are inconsistent. In order to accurately apply the first signal sequence, clock synchronization is required.

[0043] Figure 2 The first structural diagram of the clock synchronization method of the signal sequence of the embodiment of the present application, at the signal transmitting end, the laser transmits a signal sequence, and the signal sequence is modulated by an IQ modulator to obtain a modulated signal sequence. The modulated signal sequence is provided by an arbitrary waveform generator at the signal transmitting end, and its clock is t1, that is, Time1. The signal sequence and the modulated signal sequence are sent to the signal receiving end through a channel, and the signal receiving end demodulates the received signal sequence through a 90° mixer, and collects data of the received signal sequence through an ADC, and obtains an acquisition clock of t2, that is, Time2.

[0044] Step 102: Perform dispersion compensation on the second signal sequence to obtain a third signal sequence.

[0045] In this step, since the first signal sequence is a signal sequence that is affected by fiber dispersion when transmitted through a channel and pulse broadening occurs, the influence of dispersion cannot be eliminated after demodulating the first signal sequence. In order to resist the clock synchronization error caused by dispersion, dispersion compensation is performed on the second signal sequence to obtain a third signal sequence, which eliminates the influence of fiber dispersion on the second signal sequence, making the second signal sequence relatively close to the signal sequence sent by the signal transmitting end, and further making the third signal sequence accurate.

[0046] Step 103: Process the third signal sequence multiple times to obtain a target frequency control word.

[0047] In this step, the third signal sequence is processed multiple times to obtain the target frequency control word. Exemplarily, the above-mentioned multiple processing method can be the Gardner algorithm. In a digital communication system, the signal received by the receiving end is usually a signal that has been modulated, transmitted, and may be interfered by noise. In order to correctly decode these signals, the receiving end needs to know the start time and phase of each symbol. The Gardner algorithm estimates these parameters by processing the received signal. The core idea is to interpolate between sampling points so that the instantaneous phase of the signal is in the form of a linear or quadratic function, and to maximize the correlation between adjacent sample points by selecting a suitable offset, which is mainly used for clock recovery. The algorithm estimates the symbol sequence of the signal by interpolating and comparing adjacent sample points, thereby achieving bit synchronization.

[0048] It should be noted that the broadening of dispersion will aggravate the inter-symbol interference of the signal sequence. The broadening of dispersion will also cause the time delay expansion of the pulse signal in the signal sequence during the channel transmission process. Different parts of the signal will be distorted when they arrive at the receiving end, which will cause inter-symbol interference. The Gardner algorithm usually assumes that there is no interference between symbols, but the dispersion effect may cause overlap between the received symbols, affecting the estimation of the timing error and the accuracy of symbol decision. If the influence of the broadening of the dispersion of the signal sequence is not considered, the Gardner algorithm will be directly applied, which will result in the frequency control word calculated by the Gardner algorithm being inaccurate. However, the present application takes into account the influence of the broadening of the dispersion of the signal sequence, and only uses the Gardner algorithm to calculate the frequency control word after eliminating the above-mentioned influence, so that the frequency control word is accurate.

[0049] Step 104: Based on the target frequency control word, adjust the clock carried by the first signal sequence to obtain a target clock.

[0050] In this step, the frequency control word can control the frequency, and the target frequency control word is provided to the sampling device of the signal receiving end (i.e., the device that fully analyzes the first signal sequence) in the form of an electrical signal. Based on the target frequency control word, the frequency reference of the external clock sampling of the sampling device can be determined. After obtaining the frequency reference, the clock carried by the first signal sequence is synchronized according to the frequency reference, which is equivalent to adjusting the clock carried by the first signal to obtain the target clock. The acquisition device can use the target clock for data acquisition, and the clock synchronization is achieved at this time to obtain accurate sampling data. Since the Gardner algorithm can be used to synchronize the clocks of the signal sequence sent by the signal transmitting end and the signal sequence received by the signal receiving end, in addition, the present application also takes into account the influence of the dispersion and broadband of the signal sequence, which is equivalent to improving the Gardner algorithm, eliminating the problem of inaccurate clock synchronization of the Gardner algorithm, and ensuring the accuracy of the clock carried by the signal sequence determined by the signal receiving end.

[0051] Figure 3The second structural diagram of the clock synchronization method of the signal sequence of the embodiment of the present application, after completing the local sampling of the signal sequence, the present application performs dispersion compensation, and processes the signal sequence after dispersion compensation through the interpolation filter for multiple times, and also includes timing error detection, the clock error obtained after the timing error detection, re-determines the interpolation position of the signal sequence through the loop filter, stores the interpolation information in the digital control oscillator, and continuously adjusts the output interpolation position with the output of the fractional interval counter, and finally passes the information to the interpolation filter timing adjustment, completes the feedback control, and completes the clock synchronization. The present application proposes a clock synchronization method based on the Gardner algorithm that can resist dispersion broadening. The invention adds a dispersion compensation module to the clock synchronization method, adopts a fully digital feedback scheme, can automatically feedback and adjust the data after dispersion compensation, completes the clock synchronization, so that the entire scheme can also achieve high-precision clock synchronization in the case of dispersion broadening, and finally effectively reduces the bit error rate of the system.

[0052] Through the above scheme, the first signal sequence transmitted through the channel between the signal transmitting end and the signal receiving end is received, and the first signal sequence is demodulated to obtain the second signal sequence, so as to achieve the purpose of preliminarily restoring the first signal sequence to the signal sequence sent by the signal transmitting end. The second signal sequence is dispersion compensated to obtain the third signal sequence, which eliminates the influence of fiber dispersion on the second signal sequence, so that the second signal sequence is relatively close to the signal sequence sent by the signal transmitting end, and further makes the third signal sequence accurate. The third signal sequence is processed multiple times to obtain the target frequency control word, so that the frequency control word is accurate. Based on the target frequency control word, the clock carried by the first signal sequence is adjusted to obtain the target clock, thereby ensuring the accuracy of the clock carried by the signal sequence determined by the signal receiving end.

[0053] In some embodiments, the second signal sequence includes a plurality of first pulse signals, and the third signal sequence includes a plurality of second pulse signals; and performing dispersion compensation on the second signal sequence to obtain the third signal sequence includes: performing dispersion compensation on the second signal sequence by the following formula: s )=IFFT(FFT(x(m1T s ))G1(z,w)), Among them, x'(m2T s ) is the third signal sequence, m2 represents the plurality of second pulse signals, T s is the independent clock sampling period of the signal receiving end, IFFT represents inverse fast Fourier transform, FFT represents fast Fourier transform, x(m1T s) is the second signal sequence, m1 represents the multiple first pulse signals, G1(z,w) is the transfer function of dispersion in the time domain, j is a complex unit, D is the dispersion coefficient, λ is the wavelength, c is the speed of light, w is the predetermined frequency component, and z represents the signal sequence transmission length.

[0054] In this embodiment, since the signal sequence is affected by the fiber dispersion in the channel, in order to resist the clock synchronization error caused by the dispersion, a dispersion compensation step is first performed in the clock synchronization method. First, it is known that the transmission equation of g(z,t1) in the first signal sequence in the frequency domain is:

[0055]

[0056] According to formula (3), a filter is designed, and its transfer function is:

[0057]

[0058] By processing the second signal sequence through this filter, dispersion compensation can be achieved. In addition, the Fourier principle shows that any continuously measured time series or signal can be expressed as an infinite superposition of sinusoidal signals of different frequencies. The Fourier transform algorithm created based on this principle uses the original signal directly measured to calculate the frequency, amplitude and phase of different sinusoidal signals in the signal in an accumulative manner. Fast Fourier transform (FFT) is a general term for efficient and fast calculation methods that use computers to calculate discrete Fourier transforms. Once the FFT processing of each forward signal sequence is completed, if you want to convert these forward slices back to the time domain, that is, the original spatial representation, you need to apply the inverse fast Fourier transform (IFFT) to achieve this. By designing a filter to achieve dispersion compensation, the purpose of dispersion compensation for the second signal sequence is achieved.

[0059] In some embodiments, the third signal sequence includes multiple second pulse signals; the multiple processing of the third signal sequence to obtain a target frequency control word includes: for each processing, performing the following operations: randomly selecting multiple target pulse signals from the multiple second pulse signals, and determining the second frequency control word for the next processing based on the multiple target pulse signals and the first frequency control word of the current processing; in response to determining that the second frequency control word and the first frequency control word are different, using the second frequency control word as the first frequency control word for the next processing and entering the next processing; in response to determining that the second frequency control word and the first frequency control word are the same, exiting multiple processing and determining the second frequency control word as the target frequency control word.

[0060] In this embodiment, the third signal sequence includes multiple second pulse signals. After dispersion compensation, the third signal sequence needs to be interpolated. The process of interpolation is essentially a resampling process of the collected signal, so it is necessary to select multiple target pulse signals from multiple second pulse signals multiple times. For each processing, the following operations are performed: multiple target pulse signals are randomly selected from multiple second pulse signals. It should be noted that multiple target pulse signals can also be selected from multiple second pulse signals according to a predetermined rule, wherein the predetermined rule is determined according to actual needs. For example, the predetermined rule is to select a predetermined number of target pulse signals from multiple second pulse signals in a predetermined order. Based on multiple target pulse signals and the first frequency control word of the current processing, the second frequency control word of the next processing can be determined. It should be noted that the first frequency control word of the current processing is regarded as zero when the first calculation is performed. When the second frequency control word and the first frequency control word are not the same, it means that the target pulse signal at this time is not balanced, and the second frequency control word is not the optimal solution. At this time, the frequency control word needs to be re-determined. Therefore, the second frequency control word is used as the first frequency control word for the next processing, and the next processing is entered. When it is determined that the second frequency word is the same as the first frequency word, it means that the pulse signal has reached a balance at this time, and the second frequency control word is the optimal solution. Multiple processing is exited, and the second frequency control word is determined as the target frequency control word. After determining the re-interpolation position, the interpolation information is stored in the numerically controlled oscillator (NCO), and the output interpolation position is continuously adjusted with the output of the loop filter. Finally, the information is passed to the interpolation filter timing adjustment, feedback control is completed, and clock synchronization is completed. By processing the third signal sequence multiple times, the purpose of accurately determining the target frequency control word is achieved.

[0061] It should be noted that after the re-interpolation position is determined, the interpolation information is stored in a numerically controlled oscillator (NCO). The NCO in the bit synchronization loop is a phase decrementer, and the differential equation is:

[0062] N(n+1)=[N(n)-W(n)]mod1 formula (5),

[0063] The mod function is a remainder function, mod(number,divisor), Number is the dividend and Divisor is the divisor, for example, mod(3,2) is equal to 1.

[0064] N(n) is the content of the NCO register at the nth working clock, N(n) = μ(k)W(m(k)), W(n) is the control word of the NCO, both are positive decimals. Note that the working cycle of the NCO is T s , and the period of the interpolator is T i, W(n) is the output of the loop filter, which in turn controls the NCO so that it can overflow at the optimal sampling time. When the loop reaches equilibrium, W(n) is approximately a constant, that is, W(n+1)=W(n), W(n)≈T s / T i , at this time the average 1 / W(n) cycle T s , the NCO will overflow once. The NCO continuously adjusts the output interpolation position according to the output of the loop filter, and finally passes the information to the interpolation filter for timing adjustment, completing feedback control and clock synchronization.

[0065] In some embodiments, adjusting the clock carried by the first signal sequence based on the target frequency control word to obtain the target clock includes: determining a target sampling clock frequency based on the target frequency control word; and adjusting the clock according to the target sampling clock frequency to obtain the target clock.

[0066] In this embodiment, the target clock sampling frequency is determined by the following formula:

[0067] f out =W optimal f in Formula (6),

[0068] Among them, f in Represents the clock sampling frequency without clock recovery synchronization, W optimal represents the target frequency control word, f out Represents the target sampling clock frequency. The numerically controlled oscillator (NCO) adjusts the output frequency and phase of the first signal sequence according to the target sampling clock frequency, and drives the sampling clock of the signal receiving end to synchronize with the clock of the signal sending end. Specifically, after the optimal sampling point is determined among multiple pulse signals, the target frequency control word overflowed by the NCO will control the sampling clock of the sampling device at the signal receiving end to achieve the purpose of adjusting the clock carried by the first signal sequence. The sampling clock is consistent with the clock of the sending signal, and the clock synchronization is completed at this time. When the NCO obtains the optimal frequency control word, that is, the target frequency control word, it uses the target frequency control word in the form of an electrical signal to provide it to the receiving end sampling device as the frequency reference for the external clock sampling of the device. The frequency is achieved by controlling the crystal oscillator of the clock chip, and its specific adjustment process is achieved by formula (6). Therefore, after having the adjusted frequency reference, the acquisition device can use this frequency for data acquisition, and at this time, clock synchronization is achieved, and accurate sampling data is obtained.

[0069] In some embodiments, determining the second frequency control word for the next processing based on the multiple target pulse signals and the first frequency control word for the current processing includes: performing interpolation calculations on the multiple target pulse signals to obtain a fifth signal sequence corresponding to the current processing; determining the clock error corresponding to the current processing based on the fifth signal sequence; and determining the second frequency control word based on the clock error and the first frequency control word.

[0070] In this embodiment, multiple pulse signals are interpolated to obtain the fifth signal sequence corresponding to the current processing. The process of interpolation operation is essentially a resampling process of the collected signal. The most important thing is the design of the interpolation filter. Exemplarily, the interpolation operation is completed by a cubic interpolation algorithm. Based on the fifth signal sequence, the clock error of the current processing is determined, wherein the clock error can reflect the clock error between the signal transmitting end and the signal receiving end. Based on the clock error and the first frequency control word, the second frequency control word is determined. Under the guidance of the clock error, the first frequency control word and the second frequency control word are close to each other, and then the second frequency control word approaches the target frequency control word. Under the guidance of the clock error, based on the first frequency control word, the purpose of accurately determining the second frequency control word is achieved.

[0071] In some embodiments, performing interpolation calculation on the multiple target pulse signals to obtain the fifth signal sequence corresponding to the current processing includes: performing interpolation calculation on the multiple target pulse signals by using the following formula: μ(k)=kT i / T s -m2'(k), where x'(kT i ) is the fifth signal sequence, x'(m2'T s ) is the third signal sequence, m2' represents the multiple target pulse signals, T s is the independent clock sampling period of the signal receiving end, k is the kth pulse period of interpolation, T i is the sampling period corresponding to cubic interpolation, h I represents the interpolation algorithm, m2'(k)=int(kT i / T s ), m2'(k) represents the basic index of the target pulse signal.

[0072] In this embodiment, the interpolation operation is performed on the third signal sequence by the designed interpolation filter. The function of the interpolation filter in the loop is to use the received asynchronous sampling sequence x'(m2'T s ), the timing adjustment is realized fully digitally, and the output sequence after synchronization is x'(kT i), complete the sampling rate conversion function, the specific input and output time correspondence relationship is as follows Figure 4 This embodiment adopts a cubic interpolation algorithm, and its formula is

[0073]

[0074] The cubic interpolation algorithm is used to approximate the curve between data points, thus providing more accurate interpolation results.

[0075] In some embodiments, determining the clock error corresponding to the current processing of the signal receiving end based on the fifth signal sequence includes: determining the clock error by the following formula: ξ(n)=y I (n-1 / 2)[y I (n)-y I (n-1)]+y Q (n-1 / 2)[y Q (n)-y Q (n-1)],y I =real(x'(kT i )),y Q =imag(x'(kT i )), where ξ(n) is the clock error corresponding to the current processing, x'(kT i ) is the fifth signal sequence, real represents the real part, imag represents the imaginary part, k is the kth pulse period of the interpolation, T i is the sampling period corresponding to cubic interpolation, and n represents the sequence number of the nth processing.

[0076] In this embodiment, after the interpolation operation, the interpolated fifth signal sequence needs to be subjected to timing error detection to obtain the error between the accurate clock and the current clock. In this embodiment, the step of determining the clock error in the Gardner algorithm is used to complete this step. The sampling point timing relationship of the algorithm is as follows: Figure 5 As shown, when y(n-1 / 2) = 0, there is no clock deviation, when y(n-1 / 2) < 0, the clock is delayed, and when y(n-1 / 2) > 0, the clock is advanced. In addition, the clock error calculation framework of the signal sequence after IQ demodulation is as follows Figure 6As shown, after receiving the signal sequence, the signal sequence is demodulated by the IQ demodulator, and the demodulated signal sequence is processed by the filter, and timing error detection is also performed, and the clock error obtained by the timing error detection is re-determined through the loop filter to interpolate the position of the signal sequence, and the timing error is corrected to obtain clock information. Since the fifth signal sequence in this embodiment takes into account the influence of dispersion, at this time, the clock error is determined by the step of determining the clock error in the Gardner algorithm, so that the determined clock error is accurate.

[0077] In some embodiments, the second frequency control word is determined based on the clock error and the first frequency control word, including: W(n+1)=W(n)+C1[ξ(n)-ξ(n-1)]+C2ξ(n), wherein W(n+1) is the second frequency control word, W(n) is the first frequency control word, C1 is the first proportional coefficient, C2 is the second proportional coefficient, ξ(n) is the clock error of the current processing, ξ(n-1) is the clock error of the previous processing, and n represents the sequence number of the nth processing.

[0078] In this embodiment, after the sampling clock error is obtained by the Gardner algorithm, the output error information is passed through a loop filter to determine the position of re-interpolation with a certain proportional coefficient. The proportional coefficient includes a first proportional coefficient and a second proportional coefficient, which can be determined based on historical experience. The clock error, the first frequency control word and a certain proportional coefficient are used for calculation to obtain the second frequency control word. The determination of the second frequency control word is converted into the calculation of the second frequency control word, so as to achieve the purpose of accurately determining the second frequency control word.

[0079] In another embodiment provided in the present application, the simulation results of the example of the invention are as follows: Figure 7 , as shown in 8. Figure 7 When the dispersion broadening of the system is low, D = 5 × 10 5 ps, the dispersion has little effect on the bit error rate of the system. However, as the dispersion increases, D = 10 7 When the dispersion reaches 0.5, the system cannot communicate. Therefore, in a communication system, even if the traditional clock synchronization method is used for synchronization, if the system dispersion reaches a certain level, the system may have a large bit error rate and the system cannot communicate. Therefore, in a dispersion system, a clock synchronization method that can resist dispersion is needed. The specific effect of the clock synchronization method based on the Gardner algorithm that can resist dispersion proposed by the present invention is as follows: Figure 8 As shown, in Figure 8 In the example, the dispersion broadening is set to D = 10 7ps, before clock synchronization, the system bit error rate was very high, reaching 0.5. After adopting the method of the present invention, the bit error rate dropped by up to 4 orders of magnitude, achieving a good effect of resisting dispersion and completing high-performance clock synchronization. The present invention proposes a clock synchronization method based on the Gardner algorithm that can resist dispersion, which can effectively reduce the system bit error rate in a high-speed communication system, that is, a system with dispersion broadening. The present invention adds a dispersion compensation module to the clock synchronization scheme, so that the entire scheme can also achieve high-precision clock synchronization in the case of dispersion broadening, and can reduce the system bit error rate by up to 4 orders of magnitude, so that the system bit error rate is greatly reduced, and communication can be completed even in the case of large dispersion.

[0080] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0081] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0082] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a clock synchronization device for a signal sequence.

[0083] refer to Fig. 9 , the clock synchronization device of the signal sequence is applied to the signal receiving end, and the device comprises:

[0084] The receiving module 10 is configured to receive a first signal sequence transmitted through a channel between a signal transmitting end and the signal receiving end, and demodulate the first signal sequence to obtain a second signal sequence.

[0085] The dispersion compensation module 20 is configured to perform dispersion compensation on the second signal sequence to obtain a third signal sequence.

[0086] The processing module 30 is configured to process the third signal sequence multiple times to obtain a target frequency control word.

[0087] The adjustment module 40 is configured to adjust the clock carried by the first signal sequence based on the target frequency control word to obtain a target clock.

[0088] Through the above-mentioned device, the first signal sequence transmitted through the channel between the signal transmitting end and the signal receiving end is received, and the first signal sequence is demodulated to obtain the second signal sequence, so as to achieve the purpose of preliminarily restoring the first signal sequence to the signal sequence sent by the signal transmitting end. The second signal sequence is dispersion compensated to obtain the third signal sequence, eliminating the influence of fiber dispersion on the second signal sequence, so that the second signal sequence is relatively close to the signal sequence sent by the signal transmitting end, and further makes the third signal sequence accurate. The third signal sequence is processed multiple times to obtain the target frequency control word, so that the frequency control word is accurate. Based on the target frequency control word, the clock carried by the first signal sequence is adjusted to obtain the target clock, thereby ensuring the accuracy of the clock carried by the signal sequence determined by the signal receiving end.

[0089] In some embodiments, the dispersion compensation module 20 is further configured such that the second signal sequence includes a plurality of first pulse signals, the third signal sequence includes a plurality of second pulse signals; and dispersion compensation is performed on the second signal sequence using the following formula: s )=IFFT(FFT(x(m1T s ))G1(z,w)), Among them, x'(m2T s ) is the third signal sequence, m2 represents the plurality of second pulse signals, T s is the independent clock sampling period of the signal receiving end, IFFT represents inverse fast Fourier transform, FFT represents fast Fourier transform, x(m1T s ) is the second signal sequence, m1 represents the multiple first pulse signals, G1(z,w) is the transfer function of dispersion in the time domain, j is a complex unit, D is the dispersion coefficient, λ is the wavelength, c is the speed of light, w is the predetermined frequency component, and z represents the signal sequence transmission length.

[0090] In some embodiments, the processing module 30 is also configured so that the third signal sequence includes multiple second pulse signals; for each processing, the following operations are performed: a plurality of target pulse signals are randomly selected from the multiple second pulse signals, and the second frequency control word for the next processing is determined based on the multiple target pulse signals and the first frequency control word for the current processing; in response to determining that the second frequency control word is different from the first frequency control word, the second frequency control word is used as the first frequency control word for the next processing, and the next processing is entered; in response to determining that the second frequency control word is the same as the first frequency control word, multiple processings are exited, and the second frequency control word is determined as the target frequency control word.

[0091] In some embodiments, the adjustment module 40 is further configured to determine a target sampling clock frequency based on a target frequency control word; and adjust the clock according to the target sampling clock frequency to obtain the target clock.

[0092] In some embodiments, the processing module 30 is further configured to perform interpolation calculations on the multiple target pulse signals to obtain a fifth signal sequence corresponding to the current processing; based on the fifth signal sequence, determine the clock error corresponding to the current processing; based on the clock error and the first frequency control word, determine the second frequency control word.

[0093] In some embodiments, the processing module 30 is further configured to perform interpolation calculation on the multiple target pulse signals by using the following formula: μ(k)=kT i / T s -m2'(k), where x'(kT i ) is the fifth signal sequence, x'(m2'T s ) is the third signal sequence, m2' represents the multiple target pulse signals, T s is the independent clock sampling period of the signal receiving end, k is the kth pulse period of interpolation, T i is the sampling period corresponding to cubic interpolation, h I represents the interpolation algorithm, m2'(k)=int(kT i / T s ), m2'(k) represents the basic index of the target pulse signal.

[0094] In some embodiments, the processing module 30 is further configured to determine the clock error by the following formula: ξ(n)=y I (n-1 / 2)[y I (n)-y I (n-1)]+y Q (n-1 / 2)[yQ (n)-y Q (n-1)],y I =real(x'(kT i )),y Q =imag(x'(kT i )), where ξ(n) is the clock error corresponding to the current processing, x'(kT i ) is the fifth signal sequence, real represents the real part, imag represents the imaginary part, k is the kth pulse period of the interpolation, T i is the sampling period corresponding to cubic interpolation, and n represents the sequence number of the nth processing.

[0095] In some embodiments, the processing module 30 is further configured as W(n+1)=W(n)+C1[ξ(n)-ξ(n-1)]+C2ξ(n), wherein W(n+1) is the second frequency control word, W(n) is the first frequency control word, C1 is the first proportional coefficient, C2 is the second proportional coefficient, ξ(n) is the clock error of the current processing, ξ(n-1) is the clock error of the previous processing, and n represents the sequence number of the nth processing.

[0096] For the convenience of description, the above device is described in terms of functions divided into various modules. Of course, when implementing the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0097] The device of the above embodiment is used to implement the clock synchronization method of the corresponding signal sequence in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0098] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the clock synchronization method of the signal sequence described in any of the above embodiments is implemented.

[0099] Fig.10 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0100] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0101] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0102] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0103] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0104] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).

[0105] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0106] The electronic device of the above embodiment is used to implement the clock synchronization method of the corresponding signal sequence in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0107] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the clock synchronization method of the signal sequence described in any of the above embodiments.

[0108] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0109] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the clock synchronization method of the signal sequence described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0110] Based on the same concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a computer program product, including computer program instructions. When the computer program instructions are run on a computer, the computer executes the clock synchronization method of the signal sequence described in any of the above embodiments, which has the beneficial effects of the corresponding method embodiments and will not be repeated here.

[0111] It should be noted that the embodiments of the present application can be further described in the following manner:

[0112] It is understandable that before using the technical solutions of each embodiment of the present disclosure, the type, scope of use, usage scenarios, etc. of the personal information involved will be informed to the user in an appropriate manner, and the user's authorization will be obtained.

[0113] For example, in response to receiving an active request from a user, a prompt message is sent to the user to clearly remind the user that the operation requested to be performed will require obtaining and using the user's personal information. Thus, the user can independently choose whether to provide personal information to software or hardware such as an electronic device, application, server, or storage medium that performs the operation of the technical solution of the present disclosure according to the prompt message.

[0114] As an optional but non-limiting implementation, in response to receiving the user's active request, the prompt information may be sent to the user in the form of a pop-up window, in which the prompt information may be presented in text form. In addition, the pop-up window may also carry a selection control for the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0115] It is understandable that the above notification and the process of obtaining user authorization are merely illustrative and do not constitute a limitation on the implementation of the present disclosure. Other methods that meet relevant laws and regulations may also be applied to the implementation of the present disclosure.

[0116] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0117] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0118] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0119] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A clock synchronization method for a signal sequence, characterized in that: Applied to a signal receiving end, the method comprises: receiving a first signal sequence transmitted through a channel between a signal transmitting end and the signal receiving end, and demodulating the first signal sequence to obtain a second signal sequence; performing dispersion compensation on the second signal sequence to obtain a third signal sequence; Processing the third signal sequence multiple times to obtain a target frequency control word; Based on the target frequency control word, the clock carried by the first signal sequence is adjusted to obtain a target clock.

2. The method according to claim 1, characterized in that: The second signal sequence includes a plurality of first pulse signals, and the third signal sequence includes a plurality of second pulse signals; The performing dispersion compensation on the second signal sequence to obtain a third signal sequence includes: The dispersion compensation of the second signal sequence is performed by the following formula: x'(m2T s )=IFFT(FFT(x(m1T s ))G1(z,w)), Among them, x'(m2T s ) is the third signal sequence, m2 represents the plurality of second pulse signals, Ts is the independent clock sampling period of the signal receiving end, IFFT represents inverse fast Fourier transform, FFT represents fast Fourier transform, x(m1T s ) is the second signal sequence, m1 represents the multiple first pulse signals, G1(z,w) is the transfer function of dispersion in the time domain, j is a complex unit, D is the dispersion coefficient, λ is the wavelength, c is the speed of light, w is the predetermined frequency component, and z represents the signal sequence transmission length.

3. The method according to claim 1, characterized in that: The third signal sequence includes a plurality of second pulse signals; The step of processing the third signal sequence multiple times to obtain a target frequency control word includes: For each processing, perform the following operations: Randomly selecting a plurality of target pulse signals from the plurality of second pulse signals, and determining a second frequency control word for next processing based on the plurality of target pulse signals and the first frequency control word for current processing; In response to determining that the second frequency control word is different from the first frequency control word, using the second frequency control word as the first frequency control word for next processing, and entering the next processing; In response to determining that the second frequency control word is the same as the first frequency control word, multiple processing is exited and the second frequency control word is determined as the target frequency control word.

4. The method according to claim 1, characterized in that: The adjusting the clock carried by the first signal sequence based on the target frequency control word to obtain a target clock includes: Determining a target sampling clock frequency based on a target frequency control word; The clock is adjusted according to the target sampling clock frequency to obtain the target clock.

5. The method according to claim 3, characterized in that: The determining, based on the multiple target pulse signals and the first frequency control word currently processed, a second frequency control word for next processing comprises: Performing interpolation calculation on the multiple target pulse signals to obtain a fifth signal sequence corresponding to the current processing; Determining a clock error corresponding to the current processing based on the fifth signal sequence; The second frequency control word is determined based on the clock error and the first frequency control word.

6. The method according to claim 5, characterized in that The interpolation calculation is performed on the multiple target pulse signals to obtain a fifth signal sequence corresponding to the current processing, including: The multiple target pulse signals are interpolated and calculated using the following formula: Among them, x'(kT i ) is the fifth signal sequence, x'(m2'T s ) is the third signal sequence, m2' represents the multiple target pulse signals, T s is the independent clock sampling period of the signal receiving end, k is the kth pulse period of interpolation, T i is the sampling period corresponding to cubic interpolation, h I represents the interpolation algorithm, m2'(k)=int(kT i / T s ), m2'(k) represents the basic index of the target pulse signal.

7. The method according to claim 5, characterized in that The determining, based on the fifth signal sequence, a clock error corresponding to the current processing of the signal receiving end includes: The clock error is determined by the following formula: ξ(n)=y I (n-1 / 2)[and I (n)-y I (n-1)]+y Q (n-1 / 2)[and Q (n)-y Q (n-1)], and I =real(x'(kT i )),and Q =imag(x'(kT i )), Where ξ(n) is the clock error corresponding to the current processing, x'(kT i ) is the fifth signal sequence, real represents the real part, imag represents the imaginary part, k is the kth pulse period of the interpolation, T i is the sampling period corresponding to cubic interpolation, and n represents the sequence number of the nth processing.

8. The method according to claim 5, characterized in that The determining the second frequency control word based on the clock error and the first frequency control word comprises: W(n+1)=W(n)+C1[ξ(n)-ξ(n-1)]+C2ξ(n), Among them, W(n+1) is the second frequency control word, W(n) is the first frequency control word, C1 is the first proportional coefficient, C2 is the second proportional coefficient, ξ(n) is the clock error of the current processing, ξ(n-1) is the clock error of the previous processing, and n represents the sequence number of the nth processing.

9. A clock synchronization device for a signal sequence, characterized in that: Applied to a signal receiving end, the device comprises: a receiving module, configured to receive a first signal sequence transmitted through a channel between a signal transmitting end and the signal receiving end, and demodulate the first signal sequence to obtain a second signal sequence; a dispersion compensation module, configured to perform dispersion compensation on the second signal sequence to obtain a third signal sequence; A processing module, configured to process the third signal sequence multiple times to obtain a target frequency control word; The adjustment module is configured to adjust the clock carried by the first signal sequence based on the target frequency control word to obtain a target clock.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 8 is implemented.

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