Testing Method, Device and Storage Medium

Abstract

This application discloses a testing method, device, and storage medium. The method includes: obtaining a video test signal generated by a host computer; inputting the video test signal into a target field programmable gate array (FPGA) module through a corresponding transceiver module; the target FPGA module being one of a plurality of target FPGA modules with different processing scales; the number of transceiver channels of the corresponding transceiver module corresponding to the processing scale of the target FPGA module; obtaining an output signal of the target FPGA module; and obtaining a test result according to the output signal. The embodiments of this application can be applicable to a variety of different test scenarios.

Description

Technical Field

[0001] This application belongs to the field of computer technology, and more specifically, relates to a testing method, device, and storage medium. Background Art

[0002] The ARINC818 bus is a digital video interface standard widely used in the aerospace field, which can achieve reliable transmission of high-definition video and control data. Due to its characteristics of high bandwidth, low latency, and reliability, it is suitable for flight display systems, aviation cameras, and other avionics equipment.

[0003] However, since both the ARINC818 bus emulation and testing are based on FPGA, the performance of emulation and testing will be restricted by the performance of the FPGA chip. Once the FPGA chip is determined, if the product needs to be upgraded, new hardware circuits need to be redesigned. Summary of the Invention

[0004] The purpose of the embodiments of this application is to provide a testing method, device, and storage medium, which can facilitate the testing of multi-channel video test signals with different numbers of channels.

[0005] In a first aspect, an embodiment of the present application provides a testing method, including: obtaining a first multi-channel video test signal of a flight electronic device generated by a host computer; determining the number of transceiver channels of the first multi-channel video test signal; according to the number of transceiver channels of the first multi-channel video test signal, inputting the first multi-channel video test signal into a first target field-programmable gate array (FPGA) module through a corresponding first multi-channel optical transceiver module; the first target FPGA module being one of multiple FPGA modules with different processing scales; the number of transceiver channels of the corresponding first multi-channel optical transceiver module corresponding to the processing scale of the first target FPGA module; obtaining a first output signal generated by the first target FPGA module processing the video test signal; obtaining a first test result according to the first output signal; after obtaining the first multi-channel video test signal of the flight electronic device generated by the host computer, further including: obtaining a second multi-channel video test signal of the flight electronic device generated by the host computer; the number of transceiver channels of the second multi-channel video test signal being different from that of the first multi-channel video test signal; determining the number of transceiver channels of the second multi-channel video test signal; according to the number of transceiver channels of the second multi-channel video test signal, inputting the second multi-channel video test signal into a second target FPGA module through a corresponding second multi-channel optical transceiver module; the second target FPGA module being one of the multiple FPGA modules with different processing scales; the processing scales of the first target FPGA module and the second target FPGA module being different; the number of transceiver channels of the second multi-channel optical transceiver module being different from that of the first multi-channel optical transceiver module; obtaining a second output signal generated by the second target FPGA module processing the video test signal; obtaining a second test result according to the second output signal.

[0006] In a possible implementation manner, before obtaining the output signal of the first target FPGA module, further including: converting the physical channel address of the first multi-channel video test signal into an equivalent physical channel address value; determining the range of the number of complete packets of each video test signal in the first multi-channel video test signal according to the number of channels of the first multi-channel video test signal and the equivalent value; using the first target FPGA module to segment each video test signal in the first multi-channel video test signal to obtain data segments of each video test signal; generating a sequence number, a complete packet number, and a unique serial number for each data segment; combining the first multi-channel video test signal into multiple complete packets according to the range of the number of complete packets, each complete packet including at least one data segment, to obtain bus data; converting the bus data into a first optical signal; using the first optical signal as the first output signal.

[0007] In a possible implementation manner, obtaining a first test result according to the first output signal includes: outputting the first optical signal to a test module outside the field programmable gate array module; receiving a second optical signal returned by the test module according to the first optical signal; converting the second optical signal into a differential signal, where the frequency of the differential signal is greater than a preset frequency threshold; performing an unpacking operation on the second optical signal to obtain unpacked data of the second optical signal; and comparing the unpacked data of the second optical signal with the first multi-channel video test signal to obtain the first test result.

[0008] In a possible implementation manner, before segmenting each video test signal in the multi-channel video test signal by using the first target field programmable gate array module to obtain data segments of each video test signal, it further includes: parsing the video test signal; sending a first storage instruction and first related parameters to a double data rate synchronous dynamic random access memory through a signal bus; and sending a second storage instruction and second related parameters to the double data rate synchronous dynamic random access memory through an address bus; the first storage instruction and / or the second storage instruction includes a row activation instruction; the double data rate synchronous dynamic random access memory determines a row address for storing the first multi-channel video test signal according to the first storage instruction and first related parameters, and performs a bank control decoding operation on the first storage instruction, first related parameters, second storage instruction, and second related parameters to obtain a bank address and a column address; the row address, the bank address, and the column address are used to read the first multi-channel video test signal; the double data rate synchronous dynamic random access memory reads the first multi-channel video test signal from a sense amplifier in the row address to a storage unit of the double data rate synchronous dynamic random access memory; comparing the unpacked data of the second optical signal with the first multi-channel video test signal to obtain the first test result includes: taking out the parsed first multi-channel video test signal from the double data rate synchronous dynamic random access memory and comparing it with the unpacked data of the second optical signal to obtain the first test result.

[0009] In a possible implementation, the first multi-channel optical transceiver module and the second multi-channel optical transceiver module are fixed to a carrier board through a transceiver module socket (which can be equivalent to a multi-channel optical transceiver module socket), and the multiple field programmable gate array modules with different processing scales are fixed to a core board; the carrier board and the core board are connected through a connector; the connector includes a carrier board connector and a core board connector; the core board connector includes multiple grooves, and the carrier board connector includes multiple protrusions; the core board further includes a double data rate synchronous dynamic random access memory and a quad serial peripheral interface flash memory; the carrier board further includes an optical module socket for arranging the multiple multi-channel optical transceiver modules; the multiple multi-channel optical transceiver modules include the first multi-channel optical transceiver module and the second multi-channel optical transceiver module; the multiple multi-channel optical transceiver modules are connected to the panel of the carrier board through an S-shaped trace; the panel of the carrier board is perpendicular to the optical module socket.

[0010] In a possible implementation, there are multiple multi-channel optical transceiver modules, and the signal parallel transceiver quantities of the multiple multi-channel optical transceiver modules are different; determining the transceiver channels of the first video test signal includes: obtaining the address bit symbol of the first multi-channel video test signal; determining the address of the physical channel for transmitting the first multi-channel video test signal according to the address bit symbol; and determining the transceiver channels of the first multi-channel video test signal according to the address of the physical channel.

[0011] In a possible implementation, when the physical channel address of the first multi-channel video test signal indicates that the transceiver channels of the first multi-channel video test signal are less than a first threshold, the first target field programmable gate array is a first-gear field programmable gate array; when the transceiver channels of the first multi-channel video test signal are greater than or equal to the first threshold and less than a second threshold, the first target field programmable gate array is a second-gear field programmable gate array; when the physical channel address of the first multi-channel video test signal indicates that the transceiver channels of the video test signal are greater than or equal to the second threshold, the first target field programmable gate array is a third-gear field programmable gate array; the processing scale corresponding to the first gear is less than the processing scale corresponding to the second gear, and the processing scale corresponding to the second gear is less than the processing scale corresponding to the third gear.

[0012] In a possible implementation manner, obtaining a first test result according to the first output signal includes: when the first output signal is an analog signal, inputting the first output signal into an analog signal recognition model; obtaining a clarity recognition result of the output signal and a corresponding object recognition result according to output data of the analog signal recognition model; when the object recognition result is a set type, determining whether the clarity recognition result is within a clarity range corresponding to the set type; when the clarity recognition result is not within the clarity range corresponding to the set type, the first test result indicates failure.

[0013] In a second aspect, an embodiment of the present application provides a test device, including: a test signal module, configured to obtain a first multi-channel video test signal of a flight electronic device generated by a host computer; a transceiver channel number module, configured to determine the transceiver channel number of the first multi-channel video test signal; an input module, configured to input the first multi-channel video test signal through a corresponding first multi-channel optical transceiver module into a first target field programmable gate array module according to the transceiver channel number of the first multi-channel video test signal; the first target field programmable gate array module is one of multiple field programmable gate array modules with different processing scales; the transceiver channel number of the corresponding first multi-channel optical transceiver module corresponds to the processing scale of the first target field programmable gate array module; an output module, configured to obtain a first output signal generated by the first target field programmable gate array module processing the video test signal; an output signal processing module, configured to obtain a first test result according to the first output signal.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, where the electronic device includes: a processor and a memory;

[0015] The memory is used to store a program for the electronic device to execute the information verification method based on the product life cycle management system provided in any embodiment of the present application, and to store data involved in implementing the information verification method based on the product life cycle management system;

[0016] The processor is configured to execute the program stored in the memory.

[0017] In a fourth aspect, an embodiment of the present application further provides a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the method provided in any embodiment of the present application.

[0018] The test method, device, and storage medium provided in the embodiments of the present application can input a corresponding target field programmable gate array module according to the number of channels of the video test signal, so as to implement the test of video test signals with different numbers of channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 It is a schematic flowchart of the method provided by the embodiment of the present application;

[0021] Figure 2 It is a schematic diagram of the carrier board structure of an embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of the structure of the core board connector of the embodiment of the present application;

[0023] Figure 4 It is a schematic diagram of the structure of the carrier board connector of the embodiment of the present application;

[0024] Figure 5 It is a schematic diagram of the structure of the multi-channel optical transceiver module of the embodiment of the present application;

[0025] Figure 6 It is a schematic diagram of the core board structure of the example of the present application;

[0026] Figure 7 It is a schematic diagram of the carrier board structure of the example of the present application;

[0027] Figure 8 It is a partial schematic diagram of the connection between the core board and the carrier board of the example of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] A testing method provided by an embodiment of the present application includes the following steps S11 to S15.

[0030] Step S11: Obtain multi-channel video test signals of the flying electronic device generated by the host computer.

[0031] In this embodiment, the multi-channel video test signals may include first multi-channel video test signals and / or second multi-channel video test signals.

[0032] Each video test signal can include at least one standard video packet, and each video packet can further include one or more video files. The host computer can obtain the video test signal from other devices or obtain the video file from the camera device configured by the host computer itself.

[0033] In a possible implementation manner, the standard video packet can be a data packet obtained by encapsulating the data of one or more video files according to a certain encapsulation format after encoding. The encapsulation format can include: transport stream (TS), Moving Picture Expert Group 4 (MP4), etc. Exemplarily, the standard video packet can include parts such as a packet header, a payload, and an adaptive adjustment field. The packet header can include the type, length, and synchronization information of the video packet, etc. The payload can include video content, audio content, or other service data. The adaptive adjustment field can include symbols for adjusting the length of the packet to meet the requirement of a fixed length. Among them, the synchronization information can include a decoding timestamp (DTS), a presentation timestamp (PTS), and a system reference clock (SCR), etc.

[0034] Exemplarily, the multiple-channel video test signal can be transmitted through physical channels corresponding to the number of transceiver channels. For example, when the multiple-channel video test signal is a 4-channel video test signal, it is transmitted through physical channel 1. When the multiple-channel video test signal is a 12-channel unidirectional signal, it is transmitted through physical channel 2. When the multiple-channel video test signal is a 12-channel bidirectional signal, it is transmitted through physical channel 3. When the multiple-channel video test signal is a 48-channel signal, it is transmitted through physical channel 4.

[0035] In a possible implementation manner, the host computer can generate a standard video packet and use the standard video packet as the multiple-channel video test signal. In a specific implementation manner, the host computer can generate and control various standard video packets through a preset software module or program module as the multiple-channel video test signal. These signals include but are not limited to monochromatic images, color bars, static pictures, dynamic scroll bars, etc. In addition, the host computer can also customize and generate specific test patterns according to test requirements, such as geometric correction test images, brightness contrast test images, etc., and then generate the multiple-channel video test signal according to the test patterns.

[0036] Step S12: Determine the number of transceiver channels of the multiple-channel video test signal.

[0037] Exemplarily, the number of transmission and reception channels of the multi-channel video test signal can be determined by the address of the physical channel used to transmit the multi-channel test signal. The address of the physical channel used to transmit the multi-channel video test signal can be set in the file name of the video packet. Thus, when receiving the video packet of the multi-channel video test signal, the physical channel address and the number of transmission and reception channels corresponding to the multi-channel video test signal can be determined through the file name of the video packet.

[0038] In a possible implementation, the physical channels of the multi-channel video test signals with different numbers of channels are connected to the corresponding multi-channel optical modules. Thus, when receiving the multi-channel video test signal, the number of channels of the multi-channel video test signal can be determined according to the optical module used to transmit the multi-channel video test signal. The multi-channel optical module can be one of the optical modules in other embodiments of the present application, and the multi-channel optical module can be a part of the physical channel.

[0039] Step S13: Input the multi-channel video test signal into the target field programmable gate array module through the corresponding multi-channel optical transceiver module according to the number of transmission and reception channels of the multi-channel video test signal; the target field programmable gate array module is one of multiple field programmable gate array (FPGA) modules with different processing scales; the number of transmission and reception channels of the corresponding multi-channel optical transceiver module corresponds to the processing scale of the target field programmable gate array module.

[0040] In this embodiment, the multi-channel optical transceiver module can include the first multi-channel optical transceiver module and / or the second multi-channel optical transceiver module in the foregoing embodiment. The target field programmable gate array module can include the first target field programmable gate array module and / or the second target field programmable gate array module in the foregoing embodiment.

[0041] The video test signal can include multiple different groups of signals. The foregoing multi-channel optical transceiver module can include multiple ones. Each different group of video test signals can be input into the target field programmable gate array through the corresponding multi-channel optical transceiver module. Exemplarily, the multi-channel optical transceiver module can include a 4-channel optical transceiver module, a 12-channel optical transceiver module, a 12-channel optical receiver module, a 12-channel optical transmitter module, and a 48-channel optical transceiver module.

[0042] The field programmable gate arrays with different processing scales described above can be configured with different resources. The resources configured for the field programmable gate arrays can be on-chip resources, including: configurable logic block resources, input / output resources, and routing resources. Different processing scales correspond to the resource scales of the field programmable gate arrays. The resource scales of the field programmable gate arrays can include a first scale (which can also be referred to as the third gear), a second scale (which can also be referred to as the second gear), and a third scale (which can also be referred to as the first gear). Among them, the resource level of the first scale is higher than that of the second scale, and the resource level of the second scale is higher than that of the third scale. In scenarios with 48 or fewer transceiver channels, the field programmable gate arrays of the third scale are used; for 48 to 96 transceiver channels, the field programmable gate arrays of the second scale are used; and for 96 to 152 transceiver channels, the field programmable gate arrays of the first scale can be used.

[0043] In a possible implementation, the FPGA can be divided into multiple gears (which can also be referred to as levels). For example, the FPGA can be divided into a high gear (i.e., the third gear in the foregoing embodiments), a medium gear (i.e., the second gear in the foregoing embodiments), and a low gear (i.e., the first gear in the foregoing embodiments) according to the number of transceiver channels.

[0044] The grading of the FPGA can be performed according to its number of high-speed interfaces, logic resources, memory capacity, etc. For example, for the Virtex UltraScale+ series FPGA, the low-end VU3P has 40 pairs of high-speed interfaces, 862050 logic resources, and 25.3 Mb of BRAM; the mid-range VU5P has 80 pairs of high-speed interfaces, 1313763 logic resources, and 36 Mb of BRAM; and the high-end VU13P has 128 pairs of high-speed interfaces, 3780000 logic resources, and 94.5 Mb of BRAM. One pair of high-speed interfaces is required for one transceiver channel. Therefore, if the number of transceiver channels is greater than 40, VU3P cannot be used, and VU5P or VU13P needs to be used, and so on.

[0045] Step S14: Obtain the output signal generated by the target field programmable gate array module when processing the video test signal.

[0046] In this embodiment, the output signal can include the foregoing first output signal and / or second output signal.

[0047] The above-mentioned target field-programmable gate array module can, according to the data frame structure defined by the ARINC818 protocol, re-frame and pack multiple-channel video test signals sent by the host computer to form a data frame, and send the packed data frame into the transmit buffer; then read the received data frame in the receive buffer, and parse the data according to the ARINC818 protocol, including parsing pixel data, control information, and synchronization signals, and perform error detection and correction. Finally, compare the transmitted data with the received data to obtain the test result.

[0048] The above-mentioned ARINC818 protocol, whose full name is the Avionics Digital Video Bus protocol, is an international standard specifically designed for avionics video systems formulated by the Aeronautical Radio, Inc. (ARINC).

[0049] Step S15: Obtain a test result according to the output signal.

[0050] In this embodiment, the test result may include the above-mentioned first test result and / or second test result.

[0051] In one implementation manner, obtaining a test result according to the output signal includes: when the output signal is an analog signal, input the output signal into an analog signal recognition model; obtain the clarity recognition result of the output signal and the corresponding object recognition result according to the output data of the analog signal recognition model; when the object recognition result is of a set type, determine whether the clarity recognition result is within the clarity range corresponding to the set type; when the clarity recognition result is not within the clarity range corresponding to the set type, the test result indicates failure.

[0052] In another implementation manner, obtaining a test result according to the output signal may include: when the output signal is a digital signal, compare the transmitted video test signal with the received video test signal one by one, and record the inconsistent unit signals as error codes; use the following formula to calculate the bit error rate according to the recorded error codes: bit error rate = number of error codes / total amount of data; when the bit error rate is less than the minimum requirement for normal passage, obtain a qualified test result, otherwise obtain an unqualified test result.

[0053] Through the test method provided by the embodiments of this application, the FPGA can be divided into multiple grades, and multiple different multi-channel transceiver modules are used to transmit and receive signals of different numbers of channels and transmit them to the target field-programmable gate array module of the corresponding grade. Therefore, when testing signals of different specifications, there is no need to re-assemble the FPGA and other modules, improving the test efficiency.

[0054] In the embodiments of the present application, different numbers of multi-channel video test signals can be tested by the same set of test equipment, improving the usability of the test equipment.

[0055] In one implementation, before obtaining the output signal of the target field programmable gate array module, it further includes: using the target field programmable gate array module to perform packet processing on the video test signal to obtain bus data; converting the bus data into a first optical signal; using the first optical signal as the output signal.

[0056] In one implementation, using the target field programmable gate array module to perform packet processing on the video test signal to obtain bus data includes: converting the physical channel addresses of the multi-channel video test signals into equivalent physical channel address values; determining the range of the number of whole packets of each video test signal in the multi-channel video test signals according to the number of channels of the multi-channel video test signals and the equivalent values; using the target field programmable gate array module to segment each video test signal in the multi-channel video test signals to obtain data segments of each video test signal; generating a sequential number, a whole packet number, and a unique serial number for each data segment; combining the multi-channel video test signals into multiple whole packets according to the range of the number of values, where each whole packet includes at least one data segment, to obtain bus data.

[0057] Exemplarily, when converting the physical channel address into an equivalent value, it can be converted according to a certain conversion method. For example, the last character of the physical channel address can be converted into an equivalent value according to the correspondence between the character and the value. At the same time, the range of the number of whole packets can be preset for each equivalent value. Thus, when identifying and parsing the multi-channel video test signals, the channel corresponding to the whole packet can be determined according to the range of the number of whole packets, avoiding the disorder of the order when the multi-channel video test signals are combined and split. Segmenting each video test signal in the multi-channel video test signals can include: segmenting each video test signal according to a preset segmentation interval. Through the sequential number, the order of each segment in the whole packet can be determined. Through the whole packet number, the whole packet to which each segment belongs can be determined. The unique serial number can be used to determine that the segments do not repeat.

[0058] In a possible implementation, there are multiple multi-channel optical transceiver modules, and the signal parallel transceiver numbers of the multiple multi-channel optical transceiver modules are different; determining the transceiver number of the multi-channel video test signals includes: obtaining the address bit symbol of the multi-channel video test signals; determining the address of the physical channel for transmitting the multi-channel video test signals according to the address bit symbol; determining the transceiver number of the multi-channel video test signals according to the address of the physical channel.

[0059] In the embodiments of the present application, multi-channel video test signals of different scales are sent through different physical channels.

[0060] In a possible implementation manner, when the physical channel address of the multi-channel video test signal indicates that the number of transceiver channels of the multi-channel video test signal is less than a first threshold, the target field-programmable gate array is a first-gear field-programmable gate array; when the number of transceiver channels of the multi-channel video test signal is greater than or equal to the first threshold and less than a second threshold, the target field-programmable gate array is a second-gear field-programmable gate array; when the physical channel address of the multi-channel video test signal indicates that the number of transceiver channels of the multi-channel video test signal is greater than or equal to the second threshold, the target field-programmable gate array is a third-gear field-programmable gate array.

[0061] In the embodiments of the present application, the target field-programmable gate array module can be used to convert electrical signals and optical signals of multi-channel video test signals.

[0062] In an implementation manner, obtaining the test result according to the output signal includes: outputting the first optical signal to a test module outside the field-programmable gate array module; receiving a second optical signal returned by the multi-channel test module according to the first optical signal; converting the second optical signal into a differential signal, the frequency of the differential signal being greater than a preset frequency threshold; performing an unpacking operation on the second optical signal to obtain unpacked data of the second optical signal; comparing the unpacked data of the second optical signal with the multi-channel video test signal to obtain the test result.

[0063] In the embodiments of the present application, the second optical signal can be a high-speed differential signal.

[0064] In an implementation manner, before using the target field-programmable gate array module to perform packet processing on the multi-channel video test signal to obtain bus data, it further includes: parsing the multi-channel video test signal; storing the parsed multi-channel video test signal in a double data rate synchronous dynamic random access memory; comparing the unpacked data of the second optical signal with the multi-channel video test signal to obtain the test result includes: taking out the parsed multi-channel video test signal from the double data rate synchronous dynamic random access memory and comparing it with the unpacked data of the second optical signal to obtain the test result.

[0065] In one embodiment, storing the parsed multi-channel video test signal in a double data rate synchronous dynamic random access memory includes: sending a first storage instruction (command) and first related parameters to the double data rate synchronous dynamic random access memory through a signal bus; and sending the storage instruction, as well as the second storage instruction and second related parameters, to the double data rate synchronous dynamic random access memory through an address bus; the first storage instruction and / or the second storage instruction includes a row activation instruction; the double data rate synchronous dynamic random access memory determines a row address for storing the multi-channel video test signal according to the first storage instruction and first related parameters, and performs a bank control decoding operation on the first storage instruction, first related parameters, second storage instruction and second related parameters to obtain a bank address and a column address; the row address, the bank address and the column address are used to read the multi-channel video test signal; the double data rate synchronous dynamic random access memory reads the multi-channel video test signal from sense amplifiers in the row address to a storage unit of the double data rate synchronous dynamic random access memory.

[0066] In one embodiment, the multi-channel optical transceiver module is fixed to a carrier board through a transceiver module socket, and a plurality of the field programmable gate array modules are fixed to a core board; the carrier board and the core board are connected through a connector; the connector includes a carrier board connector and a core board connector; the core board connector includes a plurality of grooves, and the carrier board connector includes a plurality of protrusions; the core board further includes a double data rate synchronous dynamic random access memory and a quad serial peripheral interface flash memory; the carrier board further includes an optical module socket for arranging the plurality of multi-channel optical transceiver modules; the plurality of multi-channel optical transceiver modules are connected to a panel of the carrier board through an S-shaped trace; the panel of the carrier board is perpendicular to the optical module socket.

[0067] In one implementation, a plurality of field programmable gate array modules include a plurality of field programmable gate array modules with different grades, each grade of field programmable gate array module corresponds to a multi-channel optical transceiver module, and the number of transceiver channels of the multi-channel optical transceiver modules corresponding to different grades of field programmable gate array modules is different. Thus, based on the carrier board and the core board provided in the present application, testing of video test signals with different numbers of channels can be achieved.

[0068] Correspondingly, in one embodiment of the present application, based on the above-mentioned core board and carrier board, the testing method may include the following steps:

[0069] Obtain a first multi-channel video test signal of a flight electronic device generated by a host computer;

[0070] Determine the number of transceiver channels of the first multi-channel video test signal;

[0071] According to the number of transceiver channels of the first multi-channel video test signal, input the first multi-channel video test signal into a first target field programmable gate array module through a corresponding first multi-channel optical transceiver module; the first target field programmable gate array module is one of multiple field programmable gate array modules with different processing scales; the number of transceiver channels of the corresponding first multi-channel optical transceiver module corresponds to the processing scale of the first target field programmable gate array module;

[0072] Obtain a first output signal generated by the first target field programmable gate array module processing the video test signal;

[0073] Obtain a first test result according to the first output signal;

[0074] After obtaining the first multi-channel video test signal of the flight electronic device generated by the host computer, it further includes:

[0075] Obtain a second multi-channel video test signal of the flight electronic device generated by the host computer; the number of transceiver channels of the second multi-channel video test signal is different from that of the first multi-channel video test signal;

[0076] Determine the number of transceiver channels of the second multi-channel video test signal;

[0077] According to the number of transceiver channels of the second multi-channel video test signal, input the second multi-channel video test signal into a second target field programmable gate array module through a corresponding second multi-channel optical transceiver module; the second target field programmable gate array module is one of the multiple field programmable gate array modules with different processing scales; the processing scales of the first target field programmable gate array module and the second target field programmable gate array module are different; the second multi-channel optical transceiver module is different from the first multi-channel optical transceiver module;

[0078] Obtain a second output signal generated by the second target field programmable gate array module processing the video test signal;

[0079] Obtain a second test result according to the second output signal.

[0080] Among them, the first multi-channel video test signal and the second multi-channel video test signal can be processed in parallel or serially, so that the embodiments of the present application can use the same set of carrier board and core board devices to implement the test of video test signals with different numbers of transceiver channels.

[0081] In one implementation, the structure of the carrier board can refer to Figure 2As shown. The carrier board may include: a multi-channel optical transceiver module socket, an FPGA core board, a DDR, an FPGA, a power supply, a clock, a PXIe (Peripheral Component Interconnect Express Extended) connector, and a QSPI (quad serial peripheral interface) flash memory. Among them, the FPGA is connected to the FPGA core board in a detachable manner. The multi-channel optical transceiver module socket is used to fix each multi-channel optical transceiver module, and the structure of the multi-channel optical transceiver module socket is as shown in Figure 5 As shown. The DDR, power supply, and clock are fixed on the FPGA core board. The PXIe connector is used for data transmission with the host computer. The DDR and QSPI flash memory are used to store the data required by the carrier board during the test.

[0082] The structure of the core board connector can be referred to Figure 3 As shown. In a possible implementation, the core board connector may include a plurality of grooves 31, and at both ends of the grooves 31, high-speed signal contact spring pieces 32 are provided. In the embodiment of the present application, the high-speed signal contact spring piece 32 may be a contact component used in a high-speed connector, which utilizes the elastic characteristics of the spring piece to ensure stable contact with the corresponding connector, thereby achieving high-speed and high-quality signal transmission.

[0083] The structure of the carrier board connector can be referred to Figure 4 As shown. In a possible implementation, the carrier board connector may include a plurality of protrusions 41, and at both ends of the protrusions 41, high-speed signal contact spring pieces 32 are provided. The protrusions 41 of the carrier board connector can be connected to the grooves of the core board connector, so that the carrier board is fixed to the core board.

[0084] In an example of the present application, the structure of the core board can be referred to Figure 6 As shown. In addition to including Figure 2In addition to the structure shown, it also includes multiple capacitors 61, DDR chips 63, resistors 64, passive crystal oscillators (crystals) 65, light emitting diodes (LEDs) 66, quad serial peripheral interface flash (QSPI flash) 67, crystal oscillators 68, low-dropout regulators (LDOs) 612, and level conversion chips 69. It also includes a power supply 610, field effect transistors 611, joint test action group (JTGA) test circuits 613, FPGA mezzanine connections (FMC) 614, and embedded multimedia cards (eMMC) 615.

[0085] Among them, the DDR chip 63 is the DDR in the foregoing embodiment. Figure 2 Based on the example shown, Figure 6 through the various components shown, the DDR, FPGA, QSPI flash, and clock are connected to enable the normal operation of the DDR, FPGA, QSPI flash, and clock.

[0086] Figure 7 is Figure 2 a possible structural schematic diagram of the carrier board shown, including an optical module 71, a multi-fiber push-on (MPO) 72, a mini display port (mini-DP) 73, an LED 74, an FMC 75, an MPO flange 76, a USB (universal serial bus) 77, and a panel 78. The multi-fiber push-on is equivalent to the multi-channel transceiver module socket in the foregoing embodiment. Through Figure 7 interfaces and other structures shown, the multi-channel transceiver module socket and the optical module are connected, and the carrier board and the core board are connected. Figure 7 The optical module 71 and the multi-fiber push-on 72 in are connected by an S-shaped wire. The FMC is equivalent to the connector between the carrier board and the core board in the foregoing embodiment.

[0087] Figure 8 is Figure 7 a partial enlarged schematic diagram. The FMC connectors of the carrier board and the core board are connected to realize the connection between the carrier board and the core board. At the same time, the core board can be at the bending point of the S-shaped wire.

[0088] The embodiment of the present application further provides a test device, including: a test signal module, configured to obtain a first multi-channel video test signal of a flight electronic device generated by a host computer; a transceiver channel number module, configured to determine the transceiver channel number of the first multi-channel video test signal; an input module, configured to input the first multi-channel video test signal through a corresponding multi-channel optical transceiver module into a first target field programmable gate array module according to the transceiver channel number of the first multi-channel video test signal; the first target field programmable gate array module being one of a plurality of field programmable gate array modules with different processing scales; the transceiver channel number of the corresponding multi-channel optical transceiver module corresponding to the processing scale of the first target field programmable gate array module; an output module, configured to obtain a first output signal generated by the first target field programmable gate array module processing the first multi-channel video test signal; an output signal processing module, configured to obtain a first test result according to the first output signal.

[0089] In a possible implementation manner, the test device further includes: a first test signal module, configured to obtain a second multi-channel video test signal of a flight electronic device generated by a host computer; the transceiver channel number of the second multi-channel video test signal being different from that of the first multi-channel video test signal; a first transceiver channel number module, configured to determine the transceiver channel number of the second multi-channel video test signal; a first input module, configured to input the second multi-channel video test signal through a corresponding second multi-channel optical transceiver module into a second target field programmable gate array module according to the transceiver channel number of the second multi-channel video test signal; the second target field programmable gate array module being one of the plurality of field programmable gate array modules with different processing scales; the processing scales of the first target field programmable gate array module and the second target field programmable gate array module being different; the second multi-channel optical transceiver module being different from the first multi-channel optical transceiver module; a first output module, configured to obtain a second output signal generated by the second target field programmable gate array module processing the first multi-channel video test signal; a first output signal processing module, configured to obtain a second test result according to the second output signal.

[0090] In a possible implementation, the test device further includes: a first conversion module, configured to convert the physical channel addresses of the multiplexed video test signals into physical channel address equivalent values; a quantity value range module, configured to determine the quantity value range of the entire packets of the multiplexed video test signals according to the number of channels of the multiplexed video test signals and the equivalent values; a segmentation module, configured to use the target field programmable gate array module to segment each video test signal in the multiplexed video test signals to obtain data segments of each video test signal; a numbering module, configured to generate sequence numbers, entire packet numbers, and unique serial numbers for each of the data segments; a bus data module, configured to combine the multiplexed video test signals into multiple entire packets according to the quantity value range, where each entire packet includes at least one data segment, to obtain bus data; a second conversion module, configured to convert the bus data into a first optical signal; and an output module, configured to use the first optical signal as the output signal.

[0091] In a possible implementation, the transceiver module is fixed to the carrier board through a transceiver module socket, and multiple field programmable gate array modules are fixed to the core board; the carrier board and the core board are connected through a connector; the connector includes a carrier board connector and a core board connector; the core board connector includes multiple grooves, and the carrier board connector includes multiple protrusions; the core board further includes a double data rate synchronous dynamic random access memory and a quad serial peripheral interface flash memory; the carrier board further includes an optical module socket for arranging the multiple multiplexed optical transceiver modules; the multiple transceiver modules are connected to the panel of the carrier board through S-shaped traces; and the panel of the carrier board is perpendicular to the optical module socket.

[0092] The above embodiments of the present invention are combinations of elements and features of the present invention. Unless otherwise mentioned, an element or feature can be regarded as selective. Each element or feature can be practiced without being combined with other elements or features. In addition, embodiments of the present invention can be constructed by combining some elements and / or features. The operation sequences described in the embodiments of the present invention can be rearranged. Some configurations of any embodiment can be included in another embodiment and can be replaced with corresponding configurations of another embodiment. It is obvious to those skilled in the art that claims that do not have an explicit citation relationship with each other in the appended claims can be combined into embodiments of the present invention, or can be included as new claims in the modification after the present invention is submitted.

[0093] In the form of firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. The software code can be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and can send data to the processor and receive data from the processor through various known means.

[0094] Aspects of the systems and methods described herein can be implemented as the functionality programmed into any of a variety of circuits, including programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electronically programmable logic and memory devices, standard cell-based devices, and application specific integrated circuits (ASICs). Some other possibilities for implementing these aspects of the system include: microcontrollers with memory, such as electrically erasable programmable read only memories (EEPROMs), embedded microprocessors, firmware, software, and the like. Additionally, these aspects of the system can be embodied in a microprocessor with software-based circuit simulation, discrete logic (sequential and combinational), custom devices, fuzzy (neural) logic, quantum devices, and combinations of any of the above various device types. Of course, the underlying device technology can be provided in a variety of component types, such as metal oxide semiconductor field effect transistor (MOSFET) technologies like complementary metal oxide semiconductor (CMOS), bipolar technologies like emitter coupled logic (ECL), polymer technologies (e.g., silicon conjugated polymers and metal conjugated polymer-metal structures), hybrid analog and digital, and the like.

[0095] The various functions or processes disclosed herein can be described as data and / or instructions embodied in various computer-readable media in terms of their behavior, register transfer, logic components, transistors, geometric layout, and / or other characteristics. Computer-readable media that can contain such formatted data and / or instructions include, but are not limited to, various forms of non-volatile storage media (e.g., optical, magnetic, or semiconductor storage media) and carrier waves that can be used to transmit such formatted data and / or instructions via wireless, optical, or wired signal media or any combination thereof. When received by any of a variety of circuits (e.g., a computer), such data and / or instructions can be processed by a processing entity (e.g., one or more processors).

[0096] The above description of the illustrated embodiments of the systems and methods is not intended to be exhaustive or to limit the systems and methods to the precise forms disclosed. While specific embodiments and examples of system components and methods have been described herein for purposes of illustration, those skilled in the art will appreciate that various equivalent modifications can be made within the scope of the systems, components, and methods. The teachings of the systems and methods provided herein can be applied to other processing systems and methods, and not just to the systems and methods described above.

[0097] Those skilled in the art will understand that various changes and / or modifications can be made to the present invention as shown in specific embodiments without departing from the spirit or scope of the broad description of the present invention. Therefore, the present embodiments are to be considered in all respects as illustrative and not restrictive. In addition, the present invention includes any combination of features (including features described in the abstract section) described for different embodiments, even if the feature or combination of features is not explicitly recited in the claims or the detailed description of the present embodiments.

[0098] Generally, in the following claims, the terms used should not be construed as limiting the systems and methods to the specific embodiments disclosed in the specification and claims, but should be construed to include all processing systems operating under the claims. Therefore, the systems and methods are not limited by the present disclosure, but rather the scope of the systems and methods is entirely determined by the claims.

[0099] Unless the context clearly requires otherwise, throughout the specification and claims, words such as "comprising", "including", etc. should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, interpreted in the sense of "including but not limited to". Words using the singular or plural also respectively include the singular or plural. In addition, "herein", "hereinafter", "above", "below" and words with similar meanings refer to the present application as a whole, rather than to any specific part of the present application. When the word "or" is used in reference to a list of two or more items, the word "or" includes all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0100] In addition, the terms "first", "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined with "first", "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means more than two, unless otherwise specifically defined.

[0101] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A testing method, characterized in that, Including: Obtaining a first multi-channel video test signal of a flight electronic device generated by a host computer; Determining the number of transceiver channels of the first multi-channel video test signal; According to the number of transceiver channels of the first multi-channel video test signal, inputting the first multi-channel video test signal into a first target field programmable gate array module through a corresponding first multi-channel optical transceiver module; The first target field programmable gate array module is one of multiple field programmable gate array modules with different processing scales; the number of transceiver channels of the corresponding first multi-channel optical transceiver module corresponds to the processing scale of the first target field programmable gate array module; the resource scale of the field programmable gate array includes a first scale, a second scale, and a third scale, where the resource level of the first scale is higher than that of the second scale, and the resource level of the second scale is higher than that of the third scale. For multi-channel video test signals with less than 48 transceiver channels, a field programmable gate array with the third scale is used. For multi-channel video test signals from 48 to 96 channels, a field programmable gate array with the second scale is used. For multi-channel video test signals from 96 to 152 channels, a field programmable gate array with the first scale is used; Obtaining a first output signal generated by the first target field programmable gate array module processing the first multi-channel video test signal; Obtaining a first test result according to the first output signal; After obtaining the first multi-channel video test signal of the flight electronic device generated by the host computer, it further includes: Obtaining a second multi-channel video test signal of the flight electronic device generated by the host computer; the number of transceiver channels of the second multi-channel video test signal is different from that of the first multi-channel video test signal; Determining the number of transceiver channels of the second multi-channel video test signal; According to the number of transceiver channels of the second multi-channel video test signal, inputting the second multi-channel video test signal into a second target field programmable gate array module through a corresponding second multi-channel optical transceiver module; the second target field programmable gate array module is one of the multiple field programmable gate array modules with different processing scales; the processing scales of the first target field programmable gate array module and the second target field programmable gate array module are different; the second multi-channel optical transceiver module is different from the first multi-channel optical transceiver module; Obtaining a second output signal generated by the second target field programmable gate array module processing the second multi-channel video test signal; Obtaining a second test result according to the second output signal; The first multi-channel optical transceiver module and the second multi-channel optical transceiver module are fixed to a carrier board through a transceiver module socket, and the multiple field programmable gate array modules with different processing scales are fixed to a core board; the carrier board and the core board are connected through a connector; the connector includes a carrier board connector and a core board connector; the core board connector includes multiple grooves, and the carrier board connector includes multiple protrusions; the core board further includes a double data rate synchronous dynamic random access memory and a quad serial peripheral interface flash memory; the carrier board further includes an optical module socket for arranging multiple multi-channel optical transceiver modules; the multiple multi-channel optical transceiver modules include the first multi-channel optical transceiver module and the second multi-channel optical transceiver module; the multiple multi-channel optical transceiver modules are connected to the panel of the carrier board through S-shaped traces; the panel of the carrier board is perpendicular to the optical module socket.

2. The method according to claim 1, characterized in that, Before obtaining the output signal of the first target field programmable gate array module, it further includes: Converting the physical channel address of the first multi-channel video test signal into an equivalent value of the physical channel address; Determining the range of the number of whole packets of each video test signal in the first multi-channel video test signal according to the number of channels of the first multi-channel video test signal and the equivalent value; Using the first target field programmable gate array module to segment each video test signal in the first multi-channel video test signal to obtain data segments of each video test signal; Generating a sequence number, a whole packet number, and a unique serial number for each data segment; Combining the first multi-channel video test signal into multiple whole packets according to the range of the number of values, with each whole packet including at least one data segment, to obtain bus data; Converting the bus data into a first optical signal; Taking the first optical signal as the first output signal.

3. The method according to claim 2, wherein The obtaining the first test result according to the first output signal includes: Outputting the first optical signal to a test module outside the field programmable gate array module; Receiving a second optical signal returned by the test module according to the first optical signal; Converting the second optical signal into a differential signal, and the frequency of the differential signal is greater than a preset frequency threshold; Performing an unpacking operation on the second optical signal to obtain unpacked data of the second optical signal; Comparing the unpacked data of the second optical signal with the first multi-channel video test signal to obtain the first test result.

4. The method according to claim 3, characterized in that, Before using the first target field programmable gate array module to segment each video test signal in the multi-channel video test signal to obtain data segments of each video test signal, it further includes: Parsing the video test signal; Sending a first storage instruction and first related parameters to the double data rate synchronous dynamic random access memory through a signal bus; and sending a second storage instruction and second related parameters to the double data rate synchronous dynamic random access memory through an address bus; the first storage instruction and / or the second storage instruction includes a row activation instruction; The double data rate synchronous dynamic random access memory determines a row address for storing the first multiplexed video test signal according to the first storage instruction and the first related parameter, and performs a bank control decoding operation on the first storage instruction, the first related parameter, the second storage instruction, and the second related parameter to obtain a bank address and a column address; the row address, the bank address, and the column address are used to read the first multiplexed video test signal; The double data rate synchronous dynamic random access memory reads the first multiplexed video test signal from an sense amplifier in the row address to a storage cell of the double data rate synchronous dynamic random access memory; The comparing the unpacked data of the second optical signal with the first multiplexed video test signal to obtain the first test result includes: Taking out the parsed first multiplexed video test signal from the double data rate synchronous dynamic random access memory and comparing it with the unpacked data of the second optical signal to obtain the first test result.

5. The method according to claim 1, characterized in that, There are multiple multiplexed optical transceiver modules, and the signal parallel transceiver quantities of the multiple multiplexed optical transceiver modules are different; the determining the transceiver number of the first multiplexed video test signal includes: Obtaining an address bit symbol of the first multiplexed video test signal; Determining an address of a physical channel for transmitting the first multiplexed video test signal according to the address bit symbol; Determining the transceiver number of the first multiplexed video test signal according to the address of the physical channel.

6. The method according to claim 5, wherein When the transceiver number of the first multiplexed video test signal represented by the physical channel address of the first multiplexed video test signal is less than a first threshold, the first target field programmable gate array is a field programmable gate array of a first gear; when the transceiver number of the first multiplexed video test signal is greater than or equal to the first threshold and less than a second threshold, the first target field programmable gate array is a field programmable gate array of a second gear; when the transceiver number of the video test signal represented by the physical channel address of the first multiplexed video test signal is greater than or equal to the second threshold, the first target field programmable gate array is a field programmable gate array of a third gear; the processing scale corresponding to the first gear is less than the processing scale corresponding to the second gear, and the processing scale corresponding to the second gear is less than the processing scale corresponding to the third gear.

7. The method according to claim 1, characterized in that, The obtaining the first test result according to the first output signal includes: When the first output signal is an analog signal, inputting the first output signal into an analog signal recognition model; Obtaining a clarity recognition result and a corresponding object recognition result of the output signal according to output data of the analog signal recognition model; When the object recognition result is a set type, determining whether the clarity recognition result is within a clarity range corresponding to the set type; When the clarity recognition result is not within the clarity range corresponding to the set type, the first test result indicates failure.

8. A testing device, characterized in that, Including: A test signal module for obtaining a first multi-channel video test signal of a flight electronic device generated by a host computer; A transceiver channel number module for determining the transceiver channel number of the first multi-channel video test signal; An input module for inputting the first multi-channel video test signal into a first target field programmable gate array module through a corresponding first multi-channel optical transceiver module according to the transceiver channel number of the first multi-channel video test signal; The first target field programmable gate array module is one of multiple field programmable gate array modules with different processing scales; the transceiver channel number of the corresponding first multi-channel optical transceiver module corresponds to the processing scale of the first target field programmable gate array module; the resource scale of the field programmable gate array includes a first scale, a second scale, and a third scale. Among them, the resource level of the first scale is higher than that of the second scale, and the resource level of the second scale is higher than that of the third scale. For multi-channel video test signals with 48 or fewer transceivers, a field programmable gate array with the third scale is used; for multi-channel video test signals from 48 to 96, a field programmable gate array with the second scale is used; for multi-channel video test signals from 96 to 152, a field programmable gate array with the first scale is used; An output module for obtaining a first output signal generated by the first target field programmable gate array module processing the first multi-channel video test signal; An output signal processing module for obtaining a first test result according to the first output signal; The first multi-channel optical transceiver module and the second multi-channel optical transceiver module are fixed to the carrier board through a transceiver module socket; the multiple field programmable gate array modules with different processing scales are fixed to the core board; the carrier board and the core board are connected through a connector; the connector includes a carrier board connector and a core board connector; the core board connector includes multiple grooves, and the carrier board connector includes multiple protrusions; the core board also includes a double data rate synchronous dynamic random access memory and a quad serial peripheral interface flash memory; the carrier board also includes an optical module socket for setting multiple multi-channel optical transceiver modules; the multiple multi-channel optical transceiver modules include the first multi-channel optical transceiver module and the second multi-channel optical transceiver module; the multiple multi-channel optical transceiver modules are connected to the panel of the carrier board through an S-shaped trace; the panel of the carrier board is perpendicular to the optical module socket.

9. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-7.

Images