Flat panel detector control method, flat panel detector and dynamic image acquisition system
Patent Information
- Application Number
- CN202411524665.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-11
AI Technical Summary
The existing flat panel detectors have low frame rates and split-screen images during image acquisition, which is difficult to meet the needs of high-performance image acquisition.
By using at least two spliced detection panels in the flat panel detector, each detection panel is equipped with an independent gate driving module and a reading module, the number of effective pulses in the row synchronization signal of the reading module is n+2. Realizes rapid reading and stitching of image data.
It effectively reduces the image acquisition time of the flat panel detector, improves the frame rate of image acquisition, and solves the split screen problem between different detection panel images.
Smart Images
Figure CN119421065A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of image acquisition technology, and more specifically, to a control method of a flat panel detector, a flat panel detector and a dynamic image acquisition system. Background Art
[0002] Flat Panel Detector (FPD) or Flat Panel X-ray Detector (FPXD) is an advanced X-ray imaging device, which has been widely used in medical imaging, industrial inspection and safety inspection. In some technical implementations, the flat panel detector is composed of a photoconductor array, a transistor array, a signal processing circuit and a reading circuit. When X-rays pass through the object to be inspected, the flat panel detector converts the rays into electrical signals, which are then processed by the signal processing circuit to finally generate a digital image.
[0003] Compared with traditional film imaging, flat-panel detectors have the advantages of high sensitivity, high resolution, and low radiation dose, which can provide clearer and more accurate imaging data for medical staff and testing personnel, and provide strong support for various disease diagnosis and product quality testing. In view of this, how to further improve the performance of flat-panel detectors so that flat-panel detectors can be more widely used is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present application provides a control method for a flat panel detector, a flat panel detector and a dynamic image acquisition system, which have better performance.
[0005] In a first aspect, a control method for a flat-panel detector is provided, wherein the flat-panel detector comprises: at least two mutually spliced detection panels, each detection panel comprises a pixel array composed of a plurality of detection pixels, and each detection panel is correspondingly provided with a gate driving module and a reading module; wherein the control method comprises: controlling the number of valid pulses in a row synchronization signal of the reading module to be n+2, wherein n is the number of pixel rows of the detection panel corresponding to the reading module, the row synchronization signal is a control signal for digital analysis by the reading module, the row synchronization signal is used to generate n+2 valid pulses in a row control signal of the gate driving module, and the valid pulses in the row control signal are used to drive each row of pixels in the detection panel to generate multiple rows of pixel data; through the reading module, at the time of n+2 valid pulses of the row synchronization signal, n+2 rows of data are read; the first row of data and the n+2th row of data in the n+2 rows of data are cropped, and the other n rows of data are used for image stitching of at least two detection panels.
[0006] Through the technical solution of the embodiment of the present application, at least two detection panels are spliced to form a flat panel detector, and each detection panel can read and collect data through an independent gate drive module and a reading module, so that the image acquisition time of the flat panel detector can be reduced by half, greatly improving the frame rate of image acquisition. Further, the digital control signal used for digital analysis of the reading module is used to drive the gate drive module, rather than the analog control signal of the reading module to drive the gate drive module, so that the analog control of each row of pixels by the reading module does not require a synchronization signal, which is conducive to reducing the image acquisition time of the reading module, and then reducing the image acquisition time of the flat panel detector. In addition, by setting the number of valid pulses of the row synchronization signal of the reading module to n+2, so that the row control signal of the gate drive module generates n+2 valid pulses, the reading module can read n+2 rows of data, and the control module deletes the invalid data of the 1st row and the n+2th row, and the remaining n rows of valid pixel data are used for subsequent image splicing, which can effectively solve the problem of split screens between images corresponding to different detection panels.
[0007] In some possible embodiments, the row synchronization signal is a control signal for the reading module to digitally analyze a frame of image, and the control method also includes: determining whether the window time between two adjacent frames of image is 0; if not, setting the window time identifier to a first state within the window time to indicate resetting the row control signal of the gate driving module, and / or clearing the row count corresponding to the row control signal; setting the window time identifier to a second state within the non-window time to indicate generating a row control signal based on the row synchronization signal, and / or performing row counting based on the row control signal.
[0008] In this way, within the window time between two adjacent frames, a window time identifier is set to reset the row control signal of the gate drive module and / or clear the row count, thereby ensuring an independent acquisition control effect for each frame of the image, and adjacent frames will not interfere with each other. Even when there is a window time between frames, the imaging effect of the flat-panel detector can be effectively guaranteed, further reducing the possibility of split-screen problems.
[0009] In some possible implementations, the detection panel is provided with a plurality of gate driving modules, each gate driving module is connected to a part of the rows of the pixel array of the detection panel, and the row synchronization signal is used to generate a row control signal of each gate driving module.
[0010] Through this implementation, the detection panel is configured with a plurality of gate driving modules, which is conducive to further expanding the size and resolution of the detection panel and ensuring the image acquisition effect and acquisition rate of the detection panel.
[0011] In some possible embodiments, the maximum number of driving rows of the gate driving module is k, where k is a positive integer less than n; the first gate driving module among multiple gate driving modules for driving the first k rows of pixels in the detection panel has a first row control signal including k valid pulses, and the first row control signal is generated based on the first k valid pulses in the row synchronization signal; the last gate driving module among multiple gate driving modules for driving the last i rows of pixels in the detection panel has a second row control signal including i+2 valid pulses, and the second row control signal is generated based on the last i+2 valid pulses in the row synchronization signal, wherein i is a positive integer less than or equal to k.
[0012] In some possible embodiments, an intermediate gate driving module other than the first gate driving module and the last gate driving module among the multiple gate driving modules is used to drive the middle j rows of pixels in the detection panel, and the intermediate gate driving module has a third row control signal including j valid pulses, and the third row control signal is generated based on the middle j valid pulses in the row synchronization signal, where j is a positive integer less than or equal to k.
[0013] In some possible implementations, the detection panel is correspondingly provided with a plurality of reading modules, and each reading module is connected to a part of the columns of the pixel array of the detection panel.
[0014] Through this implementation, the detection panel is configured with a plurality of reading modules, which is conducive to further expanding the size and resolution of the detection panel and ensuring the image acquisition effect and acquisition rate of the detection panel.
[0015] In some possible implementations, in two detection panels that are spliced and adjacent to each other, the two detection panels are adjacent to each other in the first row in the row scanning direction, and the row scanning directions of the two detection panels are opposite.
[0016] In this embodiment, after the two detection panels are spliced, the row scanning directions of the two panels are scanned from the middle of the entire panel to both sides, which can avoid the problem of middle misalignment of the image and maintain the continuity of the image.
[0017] In some possible embodiments, the flat panel detector further includes: a gate control module connected to the gate driving module, and the control method further includes: transmitting the row synchronization signal of the reading module to the gate control module, so that the gate control module generates each valid pulse in the row control signal of the gate driving module according to each valid pulse in the row synchronization signal.
[0018] In some possible embodiments, the control method further includes: inputting a window time identifier for indicating the window time into a gate control module, so that the gate control module controls a row control signal of the gate driving module according to a state of the window time identifier, and / or controls a row count based on the row control signal.
[0019] In some possible implementations, the gate driving modules of at least two detection panels are connected to the same gate control module.
[0020] In this way, all gate driving modules in the flat panel detector can be controlled by using only one gate control module, thereby achieving flexible control of each detection panel in the flat panel detector, and also helping to reduce circuit complexity.
[0021] In some possible implementations, the flat panel detector further includes: a reading control module connected to the reading module, controlling the number of valid pulses in the row synchronization signal of the reading module to be n+2, including: controlling the number of valid pulses in the row synchronization signal of the reading module to be n+2 through the reading control module.
[0022] In some possible implementations, at least two detection panels are configured with at least two reading control modules, and the reading module of each detection panel is connected to a corresponding reading control module.
[0023] In some possible implementations, the control method further includes: transmitting the cropped n lines of data to a host computer, so that the host computer performs image stitching based on the n lines of data.
[0024] In a second aspect, a flat-panel detector is provided, comprising: at least two detection panels spliced together, each detection panel comprising a pixel array composed of a plurality of detection pixels; at least two gate driving modules, for respectively driving the at least two detection panels; at least two reading modules, for respectively reading pixel data of the at least two detection panels; and a control module, for executing the control method of the first aspect or any possible implementation manner of the first aspect, so as to control the at least two detection panels to capture images through the at least two gate driving modules and the at least two reading modules.
[0025] In a third aspect, a dynamic image acquisition system is provided, comprising: a host computer, and the flat-panel detector provided in the second aspect; the host computer is used to send user instructions to the flat-panel detector to control the flat-panel detector to acquire images.
[0026] The technical solution of the embodiment of the present application realizes a high frame rate design for dynamic acquisition, adopts a spliced detection panel, and a reading module with a higher acquisition rate, combined with a gate drive module, and designs a control timing that conforms to dynamic acquisition, respectively configures and controls at least two detection panels, collects data from at least two detection panels at the same time, and combines with subsequent image cropping, and quickly transmits it to the host computer, effectively realizing high-speed image acquisition. Furthermore, this solution adopts a new control timing for a new dynamic acquisition platform, realizes the coordinated control of the reading module and the gate drive module, and effectively reduces the problem of screen splitting between images of different detection panels. In addition, in order to meet the test indicators and user needs of the flat-panel detector, a row synchronization signal and a window time identifier are adopted, and the row control signal of the gate drive module is cooperated to realize image acquisition for the window time, ensuring the verification of the flat-panel detector and the needs of dynamic acquisition for productization. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is a schematic structural diagram of a flat panel detector provided in an embodiment of the present application.
[0028] Figure 2 It is a schematic structural diagram of a detection layer in a flat-panel detector provided in an embodiment of the present application.
[0029] Figure 3 It is a schematic structural diagram of a flat-panel detector formed by splicing two detection panels provided in an embodiment of the present application.
[0030] Figure 4 It is a schematic flowchart of a control method of a flat panel detector provided in an embodiment of the present application.
[0031] Figure 5 It is a waveform diagram of a CDS signal, a SYNC signal in a reading module and a row control signal in a gate driving module provided in an embodiment of the present application.
[0032] Figure 6 It is a schematic flowchart of another control method of a flat panel detector provided in an embodiment of the present application.
[0033] Figure 7 The present application provides a schematic diagram of row scanning driving after two detection panels are spliced together.
[0034] Figure 8 is another schematic structural diagram of the flat panel detector provided in an embodiment of the present application.
[0035] Fig. 9 It is a schematic diagram of a row control signal corresponding to the first gate driving module provided in an embodiment of the present application, and a row synchronization signal waveform for generating the row control signal.
[0036] Fig.10 It is a schematic diagram of a row control signal corresponding to the intermediate gate driving module provided in an embodiment of the present application, and a row synchronization signal waveform for generating the row control signal.
[0037] Fig.11 It is a schematic diagram of a row control signal corresponding to the last gate driving module provided in an embodiment of the present application, and a row synchronization signal waveform for generating the row control signal.
[0038] Fig.12 It is a schematic structural block diagram of a dynamic image acquisition system provided in an embodiment of the present application.
[0039] Fig.13 It is a signal transmission schematic diagram of the dynamic image acquisition system provided in an embodiment of the present application. DETAILED DESCRIPTION
[0040] The technical solution in this application will be described below in conjunction with the accompanying drawings.
[0041] The present application relates to a flat panel detector (FPD) or a flat panel X-ray detector (FPXD). In some specific products, the flat panel detector can be applied to a dynamic image acquisition system, such as a medical imaging system or an industrial inspection system. As an example but not a limitation, a medical imaging system includes: a digital X-ray imaging system, an angiography system, an oral imaging system, a veterinary medical imaging system, etc. An industrial inspection system includes: an industrial non-destructive testing system for detecting defects or cracks inside a material, etc.
[0042] Figure 1 A schematic structural diagram of a flat panel detector 100 provided in an embodiment of the present application is shown.
[0043] like Figure 1 As shown, the flat panel detector 100 may include: an X-ray conversion layer 110 and a detection layer 120. The X-ray conversion layer 110 is used to convert X-rays passing through the object to be detected into other types of signals, such as visible light signals or charge signals. The detection layer 120 is used to detect the signals converted by the X-ray conversion layer 110 to generate an image of the object to be detected. As an example, the flat panel detector 100 may be an indirect conversion detector, wherein the X-ray conversion layer 110 may include a scintillator layer for converting X-rays into visible light, and the detection layer 120 may include a photoelectric conversion layer for converting visible light into charge; or, the flat panel detector 100 may also be a direct conversion detector, wherein the X-ray conversion layer 110 may include a conversion layer that directly converts X-rays into charge.
[0044] In order to detect the charge corresponding to the X-ray to generate an image, the detection layer 120 may include: a detection pixel array composed of a plurality of pixels 121 and related control circuits. As an example, Figure 2 A schematic structural diagram of the detection layer 120 is shown.
[0045] like Figure 2 As shown, a plurality of pixels 121 may be arranged in rows and columns to form a detection pixel array, and each pixel 121 may include: components such as a photodiode and a switch tube, wherein the photodiode may be used to convert the visible light converted by the X-ray conversion layer 110 into a charge signal again, and the switch tube may control the working state of the photodiode, thereby controlling the generation and reading of the charge signal. As an example, the switch tube may be a thin film transistor (TFT), or, in some alternative examples, the switch tube may also be a field effect transistor or other types of semiconductor switch tubes, and the specific type is not limited in the embodiments of the present application.
[0046] In addition to the plurality of pixels 121, the detection layer 120 may also include: a gate drive module 122 and a reading module 123, wherein the gate drive module 122 may be used to drive each row of pixels in the detection pixel array to turn on in sequence, and the reading module 123 may be used to control the pixel data (or image data) in the detection pixel array to be read out in sequence. Specifically, the gate drive module 122 may be connected to the gate of the switch tube in each row of pixels, so as to control the switching state of each pixel. The reading module 123 may be connected to the source and / or drain of the switch tube in each column of pixels, so as to control the reading of data in the switch tube.
[0047] In some specific implementations, the gate driving module 122 may be a gate driving integrated circuit (Gate Integrated Circuit, Gate IC), and the reading module 123 may be a read out integrated circuit (Read Out Integrated Circuit, ROIC).
[0048] Optionally, the gate driving module 122 and the reading module 123 may be integrated with the detection pixel array on the same substrate, or the gate driving module 122 and the reading module 123 may be separately disposed on different substrates from the detection pixel array.
[0049] With the development of modern technology, flat panel detectors are gradually developing towards large size and high resolution. In view of this, the embodiment of the present application provides a flat panel detector structure composed of at least two detection panels. As an example, Figure 3 A schematic structural diagram of a flat panel detector 200 formed by splicing two detection panels 210 is shown.
[0050] like Figure 3As shown, the flat panel detector 200 includes: two groups of detection components, each group of detection components includes: a detection panel 210, and a gate driving module 220 and a reading module 230 corresponding to the detection panel 210, wherein the detection panel 210 may include a pixel array composed of a plurality of detection pixels, the gate driving module 220 is connected to and drives each row of pixels in the pixel array, and the reading module 230 is connected to each column of pixels in the pixel array and reads the pixel data generated by the pixel array.
[0051] The two detection panels 210 in the two detection assemblies can be spliced together along the row arrangement direction. As an example, Figure 3 The last row of the detection panel 210 located above in the row scanning direction is arranged adjacent to the first row of the detection panel 210 located below in the row scanning direction. Or, in some other examples, Figure 3 The last rows of the two detection panels 210 are arranged adjacent to each other, or, Figure 3 The last row of one detection panel 210 is arranged adjacent to the first row of another detection panel 210 .
[0052] Optionally, in the embodiment of the present application, the relevant scheme of the detection pixels in the detection panel 210 can be referred to above. Figure 2 In addition, the related technical solutions of the gate driving module 220 and the reading module 230 in the embodiment of the present application can also be referred to above. Figure 2 Relevant descriptions of the gate driving module 122 and the reading module 123 in the illustrated embodiment.
[0053] Continue to see Figure 3 As shown, the flat panel detector 200 further includes: a control module 240, a gate driving module 220 and a reading module 230 connected to the two detection panels 210. The control module 240 may include a main controller of the flat panel detector 200, which may generate a variety of control signals for driving the flat panel detector 200, such as a control signal for controlling the gate driving module 220 and a control signal for controlling the reading module 230. In addition, the control module 240 may also receive an image signal of a pixel array read by the reading module 230, and process the image signal.
[0054] Understandably, Figure 3 The flat panel detector 200 shown may also include more than two detection components, each of which may include: a detection panel 210, and a gate driving module 220 and a reading module 230 corresponding to the detection panel 210. The control module 240 may be connected to the gate driving module 220 and the reading module 230 in each detection component group, and drive the two to control more than two detection panels to collect images.
[0055] In addition, in the embodiment of the present application, the number of rows of at least two detection panels 210 in the flat panel detector 200 may be the same or different, the number of columns of at least two detection panels 210 may be the same or different, and the pixel rows and columns of each detection panel 210 may be controlled by an independent gate driving module 220 and a reading module 230, so as to achieve a stable display effect after splicing.
[0056] In a specific product, at least two detection panels 210 are spliced together to present a display effect of a whole large detection panel in appearance. As mentioned above, in a whole large detection panel, each detection panel 210 of the at least two detection panels 210 can be controlled independently.
[0057] based on Figure 3 The structure of the flat panel detector 200 is shown. The present application also provides a control method of the flat panel detector 200. Figure 4 FIG. 1 is a schematic flow chart of a control method 300 provided in an embodiment of the present application. The control method 300 may be Figure 3 The control module 240 in is executed.
[0058] like Figure 4 As shown, the control method 300 of the flat panel detector includes the following steps.
[0059] S310: Control the number of valid pulses in the row synchronization signal of the reading module to be n+2, wherein n is the number of pixel rows of the detection panel corresponding to the reading module, and the row synchronization signal is a control signal for digital analysis by the reading module, and the row synchronization signal is used to generate n+2 valid pulses in the row control signal of the gate driving module, and each valid pulse in the row control signal is used to drive a row of pixels in the detection panel to generate a row of data.
[0060] S320: Reading n+2 rows of data at the time of n+2 valid pulses of the row synchronization signal through the reading module.
[0061] S330: cropping the first row of data and the n+2th row of data from the n+2 rows of data, and using the other n rows of data for image stitching of at least two detection panels.
[0062] In an embodiment of the present application, the reading module may include an analog circuit part and a digital circuit part, wherein the analog circuit part is used to collect analog signals output by pixels, and the digital circuit part is used to perform signal processing on the analog signals. As an example and not limitation, the analog circuit part may include a Correlated Double Sample (CDS) circuit, and the analog circuit part may receive an external CDS control signal to collect pixel data. In addition, the digital circuit part may also receive an external control signal, such as a line synchronization signal (Synchronization, SYNC) for digital analysis. The line synchronization signal may be a high-level effective pulse signal, and the reading module reads and digitally analyzes the pixel data of a row of pixels each time it receives a high-level pulse in the line synchronization signal.
[0063] In S310, the control module can control the row synchronization signal SYNC of the digital circuit part of the reading module, and by setting the number of valid pulses in the row synchronization signal SYNC, the number of rows of pixel data read by the reading module from the pixel array can be controlled. Optionally, the valid pulse of SYNC can be a high level pulse or a low level pulse.
[0064] When the number of valid SYNC pulses is n+2, the reading module can read n+2 rows of data. When the number of pixel rows of the detection panel is n, there are 2 rows of redundant data in the n+2 rows of data, and the redundant data can be removed in the subsequent data processing.
[0065] Further, in the embodiment of the present application, the SYNC of the reading module can not only be used to read and analyze each row of pixel data of the detection panel, but also can be used to generate a row control signal of the gate driving module. In some examples, the flat panel detector can also include a gate control module, and the SYNC can be input to the gate control module for controlling the gate driving module to generate one or more row control signals. In other examples, the control module can also generate the row control signal of the gate driving module according to the SYNC.
[0066] For ease of understanding, Figure 5 A schematic diagram of waveforms of a CDS signal, a SYNC signal in a reading module and a row control signal in a gate driving module is shown.
[0067] like Figure 5As shown, the reading module may have analog control signals of CDS1 and CDS2 for correlated double sampling of pixel data. SYNC is a digital control signal of the reading module. When the reading module receives the first valid pulse in SYNC, the first row of data can be analyzed, that is, the first row of data can be read. By analogy, when the reading module receives n+2 valid pulses in SYNC, n+2 rows of data can be read.
[0068] Optionally, the row control signal of the gate driving module includes an input signal of the gate driving module. Figure 5 In the embodiment, the row control signal of the gate driving module may include: a clock pulse signal and / or an output enable (OE) signal. The clock pulse signal is also written as a CPV signal, which can be a clock signal for all channels in the gate driving module. The two signals can be used as input control signals for related circuits in the gate driving module. For example, the related circuits may include shift registers and logic gates, etc. The two signals can be used as input signals of the shift registers and / or logic gates to control the gate driving module to generate output signals, thereby driving the gates of each row of pixels.
[0069] In the case where the gate control module generates the above-mentioned row control signal, the gate control module generates a valid pulse in CPV and OE every time it receives a valid pulse in SYNC. Corresponding to n+2 valid pulses in SYNC, the gate control module can generate a total of n+2 valid pulses in CPV and OE, wherein the first valid pulse in CPV and OE can be used to open the first row of pixels in the detection panel, and by analogy, the nth valid pulse in CPV and OE can be used to open the nth row of pixels in the detection panel. Optionally, the n+1th valid pulse and the n+2th valid pulse in CPV and OE can be buffered signals and are not used to open the pixels in the detection panel.
[0070] exist Figure 5 In the illustrated embodiment, in addition to being used to generate CPV and OE, SYNC can also generate a frame start signal, which is also written as an STV signal. The STV signal can be a start pulse of a shift register applied to a gate drive module. Specifically, the first valid pulse in SNYC can be used to generate a valid pulse of STV, and STV is subsequently in a reference level state. Optionally, the STV can also be generated by a gate control module.
[0071] It should be noted that see Figure 5As shown, at the moment when SYNC generates the first valid pulse and reads the first row of data, the gate drive circuit has not actually turned on the first row of pixels. Therefore, the first row of data read by the reading module is actually invalid data. At the moment when SYNC generates the second valid pulse, the second row of data read by the reading module is the real first row of pixel data of the detection panel. By analogy, the n+1th row of data read by the reading module at the moment of the n+1th valid pulse is the real nth row of pixel data of the detection panel. The n+2th row of data read by the reading module at the moment of the n+2th valid pulse is also invalid data.
[0072] In view of this, in S330, the control module can obtain the n+2 rows of data read by the reading module, and cut the invalid data of the first row and the invalid data of the n+2 rows of data. The remaining n rows of data are the real n rows of pixel data of the detection panel, which can be used to realize the subsequent image splicing of at least two detection panels. In this way, the spliced image is a coherent image, which will reduce the probability of split screen problems. In addition, the row control signal of the gate drive module has n+2 valid pulses, which can not only ensure that the reading module reads the complete n rows of pixel data of the detection panel, but also reserve sufficient buffer time for the n rows of pixels in the detection panel, so as to ensure the image acquisition effect of the n rows of pixels and further reduce the probability of split screen problems.
[0073] Optionally, in the embodiment of the present application, the sizes of at least two detection panels in the flat panel detector may be the same or different. For example, the number of pixel rows of each detection panel may be n. For each detection panel, the control module may control it using the above method to obtain pixel data of each detection panel.
[0074] Optionally, after the control module crops the data of each detection panel, the cropped image data can be sent to a host computer, which realizes image stitching and display of multiple detection panels. Alternatively, in some alternative embodiments, the control module realizes data cropping and stitching of each detection panel, and sends the stitched image to the host computer.
[0075] Through the technical solution of the embodiment of the present application, at least two detection panels are spliced to form a flat panel detector, and each detection panel can read and collect data through an independent gate drive module and a reading module, so that the image acquisition time of the flat panel detector can be reduced by half, greatly improving the frame rate of image acquisition. Furthermore, the gate drive module is driven by the digital control signal used for digital analysis of the reading module, rather than the analog control signal of the reading module to drive the gate drive module, so that the analog control of each row of pixels by the reading module does not require a synchronization signal, which is conducive to reducing the image acquisition time of the reading module, and then reducing the image acquisition time of the flat panel detector.
[0076] In addition, by setting the number of valid pulses of the row synchronization signal of the reading module to n+2, the row control signal of the gate driving module generates n+2 valid pulses, the reading module can read n+2 lines of data, and the control module deletes the invalid data in the 1st and n+2th lines, and the remaining n lines of valid pixel data are used for subsequent image stitching, which can effectively solve the problem of screen splitting between images corresponding to different detection panels.
[0077] Figure 6 A schematic flowchart of another control method 400 of a flat panel detector provided in an embodiment of the present application is shown.
[0078] like Figure 6 As shown, the control method 400 of the flat panel detector includes the following steps.
[0079] S410: Control the number of valid pulses in the row synchronization signal of each frame of the reading module to be n+2.
[0080] S420: Determine whether the window time between two adjacent image frames is 0.
[0081] S431: If yes, generate a row control signal of each frame for the gate driving module based on the row synchronization signal of each frame.
[0082] S432: Read n+2 lines of data through the reading module to collect each frame of image data.
[0083] S441: If not, within the window time, set the window time flag to the first state to indicate resetting the row control signal of the gate driving module, and / or clear the row count corresponding to the row control signal.
[0084] S442: During the non-window time, the window time flag is set to a second state to indicate the generation of a valid pulse in the row control signal, and / or, row counting is performed based on the row control signal.
[0085] S443: Based on the row synchronization signal of each frame, generate a row control signal of each frame of the gate driving module.
[0086] S444: Read n+2 lines of data through the reading module to collect each frame of image data.
[0087] S450: cropping the first row of data and the n+2th row of data from the n+2 rows of data, and using the other n rows of data for image stitching of at least two detection panels.
[0088] In the embodiment of the present application, in order to facilitate the testing of the flat panel detector or facilitate the user to collect a single image, etc., a window time can be introduced between two adjacent frames of images collected by the flat panel detector. The window time can be flexibly set according to actual needs, for example, it can be 1s, 10s, 20s, 30s, 60s, etc., and the embodiment of the present application does not limit its specific value. The window time can be set and input by the user, and the control module can receive the window time set by the user to determine whether it is 0.
[0089] The row synchronization signal SYNC of the reading module in the embodiment of the present application can be a synchronization control signal for one frame of image, that is, in the process of data analysis of one frame of image, the SYNC can have n+2 valid pulses. In the process of the flat panel detector continuously collecting multiple frames of images, the control module can set the SYNC of each frame of image to have n+2 valid pulses.
[0090] Before starting image acquisition, it can be determined whether the window time is 0. If it is 0, the SYNC of each frame can be used to generate the row control signal of each frame of the gate driving module, such as CPV, OE and STV mentioned above. The gate driving module can drive each row of pixels in the detection panel to turn on based on the row control signal of each frame, and the reading module can read n+2 rows of data based on the SYNC of each frame to collect one frame of image.
[0091] If the window time is not 0, there is a certain window time between the SYNCs of two adjacent frames, and the control module may be provided with a window time identifier to indicate that the window time is not 0. Further, within the window time, the controller may set the window time identifier to a first state, thereby indicating to reset the row control signal of the gate driving module, and / or clearing the row count corresponding to the row control signal.
[0092] As an example, after the control module sets the window time mark to the first state, the gate control module connected to the gate driving module can reset the row control signal of the gate driving module based on the window time mark of the first state, for example, keep the row control signal at a reference level, which can be understood as a non-valid level. When the valid pulse is at a high level, the reference level can be a low level, and vice versa. In addition, the gate control module can also clear the row count, which can be generated based on the row control signal, for example, based on the number of valid pulses in the row control signal.
[0093] In this way, within the window time between two adjacent frames, a window time identifier is set to reset the row control signal of the gate drive module and / or clear the row count, thereby ensuring an independent acquisition control effect for each frame of the image, and adjacent frames will not interfere with each other. Even when there is a window time between frames, the imaging effect of the flat-panel detector can be effectively guaranteed, further reducing the possibility of split-screen problems.
[0094] During the non-window time, the control module can set the window time identifier to a second state, which is different from the first state mentioned above. As an example, the second state and the first state can be a low level state and a high level state, respectively. The window time identifier of the second state can indicate the generation of a row control signal based on SYNC. For example, the gate control module can generate a valid pulse in the row control signal according to SYNC based on the window time identifier of the second state, so that the gate drive module drives each row of pixels in the detection panel to open, and the reading module can read n+2 rows of data based on the SYNC of each frame to collect a frame of image. In addition, in addition to indicating the generation of a row control signal, the window time identifier of the second state can also indicate row counting based on the row control signal, thereby more accurately ensuring that the gate drive module outputs n+2 drive signals to drive the detection panel.
[0095] It should be noted that the above Figures 4 to 6 In the illustrated embodiment, a detection panel with n rows of pixels is used to illustrate the relevant control method. For a flat-panel detector including multiple detection panels, each detection panel can be controlled in the manner of the above embodiment to obtain true pixel data of each detection panel for subsequent image stitching.
[0096] Figure 7 A schematic diagram of row scanning driving after two detection panels 210 are spliced together is shown in an embodiment of the present application.
[0097] As an example, Figure 7The two detection panels 210 shown in the figure each have n rows of pixels, and the gate driving module 220 corresponding to each detection panel 210 can receive n+2 valid pulses in the row control signal, such as Control_1 to Control_n+2 shown in the figure, and the n+2 valid pulses Control_1 to Control_n+2 are sequentially applied to the gate driving module 220, so that it drives the n rows of pixels of the scanning detection panel 210 in sequence. In the row scanning process of a frame of image, the first row of the upper detection panel 210 in the scanning direction is located at the bottom end of the detection panel 210, and the first row of the lower detection panel 210 in the scanning direction is located at the top end of the detection panel 210. In this case, the first rows of the two detection panels 210 in the scanning direction of each frame are adjacently arranged, and the row scanning directions of the two detection panels are opposite.
[0098] Continue to see Figure 7 As shown, when there is a window time between adjacent frames, after scanning n rows of pixels of the two detection panels 210, a new frame of image scanning starts after the window time, that is, scanning starts from the first row of pixels of the two detection panels 210.
[0099] It is understandable that when there is no window time between adjacent frames, or the window time is 0, a new frame of image scanning starts after the previous frame scans the last row of the detection panel 210, that is, scanning starts from the first row of pixels of the two detection panels 210.
[0100] pass Figure 7 The scanning method of the illustrated embodiment can reduce the possibility of problems in image splicing between two adjacent detection panels and effectively maintain the continuity of the image.
[0101] In the above embodiments, each detection panel of the flat-panel detector may be configured with only one gate driving module. In other embodiments, the detection panel may also be configured with multiple gate driving modules, which is beneficial to further expand the size and resolution of the detection panel and ensure the image acquisition effect and acquisition rate of the detection panel.
[0102] Figure 8 Another schematic structural diagram of the flat panel detector 200 provided in an embodiment of the present application is shown.
[0103] like Figure 8 As shown, for any detection panel 210 in the flat panel detector 200 , a plurality of gate driving modules 220 may be correspondingly provided, and each gate driving module 220 is connected to a part of the rows of the pixel array of the detection panel 210 .
[0104] For each gate driving module 220, the maximum number of driving rows is k, where k is a positive integer less than n. Among the multiple gate driving modules 220, the first gate driving module for driving the first k rows of pixels in the detection panel 210 can be used to receive the first row control signal including k valid pulses, for example, Figure 8 In the CPV[1,k] and OE[1,k] shown in FIG, the CPV[1,k] is used to represent a CPV signal having k valid pulses, and the OE[1,k] is used to represent an OE signal having k valid pulses.
[0105] Among the plurality of gate driving modules 220, the last gate driving module for driving the last i rows of pixels in the detection panel 210 may be used to receive a second row control signal including i+2 valid pulses, for example, Figure 8 CPV[1,i+2] and OE[1,i+2] shown in , where i≤k and i is a positive integer.
[0106] In addition, among the plurality of gate driving modules 220, other gate driving modules (also referred to as intermediate gate driving modules) except the first gate driving module and the last gate driving module may be used to receive a third row control signal including j valid pulses, where j≤k and j is a positive integer. In some embodiments, j=k, as an example, Figure 8 The intermediate gate drive module shown in FIG. 1 receives CPV[1, k] and OE[1, k].
[0107] For ease of understanding, Figures 9 to 11 The diagram shows the row control signals corresponding to the first gate driving module, the middle gate driving module and the last gate driving module, and the waveform diagram of the row synchronization signal for generating the row control signals.
[0108] like Fig. 9 As shown, for the first gate driving module, the first k valid pulses in the SYNC of the reading module generate the row control signals CPV and OE of the first gate driving module, and the row control signals CPV and OE include k valid pulses. In addition, SYNC is also used to generate the STV of the first gate driving module. See above Figure 5 The relevant analysis of the embodiment shown shows that at the first valid pulse of SYNC, the first row of data read is invalid data and needs to be clipped later. At the kth valid pulse of SYNC, the kth row of data read is the real k-1th row of pixel data. The first gate drive module drives the kth row of pixels to turn on at the kth valid pulse of CPV and OE.
[0109] like Fig.10As shown, for the intermediate gate driving module, the middle k valid pulses in the SYNC of the reading module can generate the row control signals CPV and OE of the intermediate gate driving module, and the row control signals CPV and OE include k valid pulses. In addition, SYNC is also used to generate the STV of each intermediate gate driving module. At the moment of the first valid pulse of SYNC, the first row of data read is the last row of pixel data driven by the previous gate driving module. At the moment of the kth valid pulse of SYNC, the kth row of data read is the second to last row of pixel data driven by the current gate driving module.
[0110] like Fig.11 As shown, for the last gate driver module, it is used to drive the last i rows of pixels of the detection panel. The row control signals CPV and OE of the last gate driver module include i+2 valid pulses, and the row control signals CPV and OE are generated based on the last i+2 valid pulses in the SYNC of the reading module. In addition, SYNC is also used to generate the STV of the last gate driver module. At the moment of the first valid pulse of SYNC, the first row of data read is the last row of pixel data driven by the previous gate driver module. At the moment of the i+1th valid pulse of SYNC, the i+1th row of data read is the last row of pixel data of the detection panel. At the moment of the i+2th valid pulse of SYNC, the i+2th row of data read is invalid data and needs to be subsequently trimmed.
[0111] It should be noted that in the embodiment of the present application, the row synchronization signal SYNC of the same reading module can be used to generate the row control signal of each gate driving module in multiple gate driving modules. Among them, multiple valid pulses in SYNC can sequentially generate valid pulses in multiple row control signals.
[0112] Return to see Figure 8 As shown, optionally, for any detection panel 210 in the flat panel detector 200, in addition to being provided with a plurality of gate driving modules 220, it may also be provided with a plurality of reading modules 230, each reading module being connected to a part of the columns of the pixel array of the detection panel 210. This embodiment can be helpful to further expand the size and resolution of the detection panel and ensure the image acquisition effect of the detection panel.
[0113] When the detection panel 210 is provided with a plurality of reading modules 230 , the row synchronization signal SYNC of the reading module in the above embodiment can be synchronously applied to the plurality of reading modules 230 . In other words, the row synchronization signal SYNC of each reading module 230 can adopt the technical solution in any of the above embodiments.
[0114] Continue to see Figure 8As shown, optionally, in the embodiment of the present application, the flat panel detector 200 may further include: a gate control module 250, which is connected between the control module 240 and the gate driving module 220, and is used to generate a control signal of the gate driving module 220, such as: the row control signal (CPV and / OE) mentioned above, and STV, etc.
[0115] As described in the relevant embodiments above, the gate control module 250 can receive relevant instructions from the control module 240 and receive the row synchronization signal SYNC of the reading module 230, and generate a valid pulse in the row control signal of the gate driving module 220 based on the valid pulse in the SYNC, and then transmit it to the gate driving module 220 so that it drives the corresponding pixel row in the detection panel 210.
[0116] Alternatively, if Figure 8 As shown, multiple gate driving modules 220 of two detection panels 210 in the flat panel detector 200 can be connected to the same gate control module 250. In other words, all gate driving modules 220 in the flat panel detector 200 can be controlled by only one gate control module 250, thereby achieving flexible control of each detection panel 210 in the flat panel detector 200, which is also conducive to reducing circuit complexity.
[0117] Continue to see Figure 8 As shown, optionally, in the embodiment of the present application, the flat panel detector 200 may further include: a reading control module 260, which may also be referred to as a source control module, etc., which is connected between the control module 240 and the reading module 230, and is used to generate a control signal for the reading module 230, such as: the line synchronization signal SYNC mentioned above, and CDS1 and CDS2, etc.
[0118] In some embodiments, the control module 240 can control the number of valid pulses in the row synchronization signal SYNC of the reading module 230 to be n+2 through the reading control module 260. Specifically, the control module 240 can send a control command to the reading control module 260, so that the reading control module 260 generates a row synchronization signal SYNC having n+2 valid pulses, thereby providing it to the reading module 230 to read each row of pixel data in the detection panel 210.
[0119] Alternatively, if Figure 8As shown, each detection panel 210 has a corresponding reading control module 260, and multiple reading modules 230 of each detection panel 210 can be connected to the same reading control module 260. Through this embodiment, each detection panel 210 is independently configured with a reading control module 260, which is conducive to improving the pixel data reading effect of each detection panel 210 and further ensuring the display performance of the flat panel detector 200.
[0120] Fig.12 A schematic structural block diagram of a dynamic image acquisition system 500 provided in an embodiment of the present application is shown.
[0121] like Fig.12 As shown, the dynamic image acquisition system 500 may include: a host computer, a main control board, a gate control module, source control modules A and B, and detection panels A and B. Among them, except the host computer, other components in the dynamic image acquisition system 500 can be understood as components in a flat-panel detector. In other words, the dynamic image acquisition system 500 may include: a host computer and a flat-panel detector, wherein the flat-panel detector may include a main control board, a gate control module, source control modules A and B, and detection panels A and B. Alternatively, the flat-panel detector in the dynamic image acquisition system 500 of the embodiment of the present application may also be the flat-panel detector provided in any of the above embodiments, such as the flat-panel detector 200 in the above embodiments.
[0122] In the dynamic image acquisition system 500, the host computer can be an electronic device that interacts with the user, which can receive relevant instructions input by the user, and then transmit the instructions to the flat-panel detector so that the flat-panel detector can perform image acquisition according to the user's instructions. In addition, the flat-panel detector can also transmit the acquired image to the host computer, and the host computer can display and present it to the user after processing it.
[0123] In the flat panel detector, the main control board is the core control unit, which is provided with functional modules such as the main control module, data processing module, clock & reset module, 10G network transmission module, storage module and power module. Specifically, the above-mentioned functional modules may include: chips, integrated circuits, discrete component circuits and other hardware forms. Optionally, the functional modules may be separate modules or modules in which any two or more are integrated with each other.
[0124] Optionally, the main control board in the embodiment of the present application may be the control module in any of the above embodiments.
[0125] Optionally, the main control module in the main control board may be, for example, a main control chip, which may control other functional modules on the main control board and other components in the flat panel detector to control the entire image acquisition process of the flat panel detector.
[0126] The 10 Gigabit network transmission module is a data transmission module, which can be used to realize command transmission, parameter transmission and image data transmission between the flat panel detector and the host computer.
[0127] The clock & reset generation module mainly provides the clock and reset signals required for the main control module to work, ensures the clock requirements of different modules, and ensures the control of related resets.
[0128] The storage module may include a volatile storage module and / or a non-volatile storage module, wherein the volatile storage module may be, for example, a double data rate (DDR) storage module, and the non-volatile storage module may be, for example, a secure digital card (SD) storage module. The storage module may be used to store image data collected by the flat panel detector, as well as required control parameters, user instructions, etc. Firstly, the storage module may cache the collected data to ensure the error packet retransmission mechanism of the 10 Gigabit network and improve the robustness of network transmission; secondly, the storage module may be used to cache and transmit back the correction parameters to ensure the accuracy of image acquisition.
[0129] The data processing module can be responsible for image data related processing, such as image data interception, etc., to ensure data integrity. Optionally, the data processing module can be integrated with the main control module into the same chip, or the data processing module and the main control module can also be set as two separate chips.
[0130] Understandably, Fig.12 For illustration only and not limitation, some functional modules in the main control board are shown, except Fig.12 In addition to the several modules illustrated in the figure, the main control board can also be provided with other modules according to actual needs, and the embodiments of the present application do not limit the specific structure thereof.
[0131] Continue to see Fig.12 As shown, the main control board can be connected to the gate control module and two source control modules (i.e., source control modules A and B), wherein the source control module can also be called a reading control module. The gate control module and the source control modules A&B mainly receive the relevant instructions of the main control board to control the gate and source chips (i.e., Fig.12 The timing of Gate IC and ROIC) shown in the figure is used to acquire image data.
[0132] Optionally, the source control module and the gate control module may be, for example, Figure 8 The read control module 260 and the gate control module 250 shown in the illustrated embodiment, and their related solutions can refer to the related descriptions of the above embodiments, and will not be elaborated here.
[0133] Fig.12 The Gate IC shown in the figure can be the gate driving module in any of the above embodiments, and the ROIC can be the reading module in any of the above embodiments. The Gate IC and the ROIC can be integrated on the detection panel to drive each pixel of the detection panel to collect images.
[0134] As an example, Fig.12 The two detection panels A and B are each configured with x Gate ICs and y ROICs, wherein x and y are positive integers, and their specific values can be flexibly set according to actual needs, and are not limited in the embodiments of the present application.
[0135] After the detection panels A and B are spliced, the row scanning direction of the two panels is scanned from the middle of the entire panel to both sides, which can avoid the problem of image misalignment in the middle and maintain the continuity of the image. In terms of hardware design, the GATEIC scanning methods of the two detection panels A and B are opposite, and the in and out directions of STV must also be swapped to ensure the synchronization of the starting acquisition rows of the two detection panels A and B.
[0136] In order to further explain the relationship between the multiple components in the entire dynamic image acquisition system 500, Fig.13 Shows Fig.12 A signal transmission schematic diagram of a dynamic image acquisition system 500 is shown.
[0137] like Fig.13 As shown in the figure, in the dynamic image acquisition system, each module interacts and controls to realize the overall functional system of data acquisition, transmission, storage and correction. The host computer, as a human-machine interface, issues instructions, parameters, collects images, and reads back parameters to the main control module through the 10G network transmission module. The main control module mainly receives instructions from the host computer, controls the gate control module and the source control module A&B, and collects, integrates and uploads data for the two detection panels A and B. The DDR storage module is a volatile storage module that needs to be re-read every time it is powered on. After the parameter reading is completed, the gate and source control are started to collect data, and the various correction algorithms are processed synchronously with the parameters. The processed image is first cached in the DDR storage module and then transmitted to the host computer through the 10G network. The clock and reset module mainly provides the clock and reset control signals required for the work of each module.
[0138] It should be noted that Fig.13 The Gate IC and ROIC are omitted in the figure. These two parts can be understood as being integrated into the detection panels A and B. The main control module can read the image data through the ROIC. In other words, the ROIC can be used to realize the image acquisition output of the detection panels A and B.
[0139] In addition, in each embodiment of the above text application, the flat-panel detector includes two detection panels as a schematic illustration. It can be understood that the flat-panel detector in each embodiment of the present application can also include more than two detection panels. The driving method and data acquisition method of each detection panel can refer to the relevant description of the above embodiment. After the data of more than two detection panels are acquired, the first row and the last row of data can be cropped to achieve image stitching.
[0140] The technical solution of the embodiment of the present application realizes a high frame rate design for dynamic acquisition, adopts a spliced detection panel, and a reading module with a higher acquisition rate, combined with a gate drive module, and designs a control timing that conforms to dynamic acquisition, respectively configures and controls at least two detection panels, collects data from at least two detection panels at the same time, and combines with subsequent image cropping, and quickly transmits it to the host computer, effectively realizing high-speed image acquisition. Furthermore, this solution adopts a new control timing for a new dynamic acquisition platform, realizes the coordinated control of the reading module and the gate drive module, and effectively reduces the problem of screen splitting between images of different detection panels. In addition, in order to meet the test indicators and user needs of the flat-panel detector, a row synchronization signal and a window time identifier are adopted, and the row control signal of the gate drive module is cooperated to realize image acquisition for the window time, ensuring the verification of the flat-panel detector and the needs of dynamic acquisition for productization.
[0141] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0142] It should be understood that in the method embodiments provided in the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0143] It should also be understood that the various implementation methods described in this specification can be implemented individually or in combination, and the embodiments of the present application are not limited to this.
[0144] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are the same as the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include majority forms, unless the context clearly indicates other meanings. In addition, the terms "first", "second", "third" etc. are only used for description purposes and cannot be understood as indicating or suggesting relative importance.
[0145] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.
[0146] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0147] In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
[0148] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.
[0149] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A control method for a flat panel detector, characterized in that: The flat panel detector comprises: at least two mutually spliced detection panels, each of the detection panels comprises a pixel array composed of a plurality of detection pixels, and each of the detection panels is correspondingly provided with a gate driving module and a reading module; the control method comprises: The number of valid pulses in the row synchronization signal of the reading module is controlled to be n+2, wherein n is the number of pixel rows of the detection panel corresponding to the reading module, the row synchronization signal is a control signal for digital analysis by the reading module, the row synchronization signal is used to generate n+2 valid pulses in the row control signal of the gate driving module, and the valid pulses in the row control signal are used to drive each row of pixels in the detection panel to generate multiple rows of pixel data; By means of the reading module, at the time of n+2 valid pulses of the row synchronization signal, n+2 rows of data are read; The first line of data and the n+2th line of data among the n+2 lines of data are cropped, and the other n lines of data are used for image stitching of at least two detection panels.
2. The control method according to claim 1, characterized in that: The line synchronization signal is a control signal for the reading module to perform digital analysis on a frame of image, and the control method further includes: Determine whether the window time between two adjacent frames of images is 0; If not, setting the window time identifier to a first state within the window time to indicate resetting the row control signal of the gate driving module, and / or clearing the row count corresponding to the row control signal; The window time identifier is set to a second state during non-window time to indicate that the row control signal is generated based on the row synchronization signal, and / or row counting is performed based on the row control signal.
3. The control method according to claim 1 or 2, characterized in that: The detection panel is correspondingly provided with a plurality of gate driving modules, each gate driving module is connected to a part of the rows of the pixel array of the detection panel, and the row synchronization signal is used to generate a row control signal of each gate driving module.
4. The control method according to claim 3, characterized in that: The maximum number of drive rows of the gate drive module is k, where k is a positive integer less than n; A first gate driving module among the plurality of gate driving modules for driving the first k rows of pixels in the detection panel has a first row control signal including k valid pulses, and the first row control signal is generated based on the first k valid pulses in the row synchronization signal; The last gate driving module among the multiple gate driving modules for driving the last i rows of pixels in the detection panel has a second row control signal including i+2 valid pulses, and the second row control signal is generated based on the last i+2 valid pulses in the row synchronization signal, where i is a positive integer less than or equal to k.
5. The control method according to claim 4, characterized in that: The intermediate gate driving modules among the multiple gate driving modules except the first gate driving module and the last gate driving module are used to drive the middle j rows of pixels in the detection panel, and the intermediate gate driving modules have a third row control signal including j valid pulses, and the third row control signal is generated based on the middle j valid pulses in the row synchronization signal, wherein j is a positive integer less than or equal to k.
6. The control method according to claim 1 or 2, characterized in that: The detection panel is correspondingly provided with a plurality of reading modules, and each reading module is connected to a part of the columns of the pixel array of the detection panel.
7. The control method according to claim 1 or 2, characterized in that: In two detection panels that are spliced and adjacent to each other, the two detection panels are adjacent to each other in the first row in the row scanning direction, and the row scanning directions of the two detection panels are opposite.
8. The control method according to claim 1 or 2, characterized in that: The flat panel detector further includes: a gate control module connected to the gate driving module, and the control method further includes: The row synchronization signal of the reading module is transmitted to the gate control module, so that the gate control module generates each valid pulse in the row control signal of the gate driving module according to each valid pulse in the row synchronization signal.
9. The control method according to claim 8, characterized in that: The control method further comprises: A window time identifier for indicating a window time is input into the gate control module, so that the gate control module controls the row control signal of the gate driving module according to the state of the window time identifier, and / or controls the row count based on the row control signal.
10. The control method according to claim 8, characterized in that: The gate driving modules of at least two detection panels are connected to the same gate control module.
11. The control method according to claim 1 or 2, characterized in that: The flat panel detector further includes: a reading control module connected to the reading module, the number of effective pulses in the line synchronization signal of the reading module being controlled to be n+2, including: The read control module is used to control the number of valid pulses in the row synchronization signal of the read module to be n+2.
12. The control method according to claim 11, characterized in that: At least two of the detection panels are configured with at least two of the reading control modules, and the reading module of each of the detection panels is connected to the corresponding reading control module.
13. The control method according to claim 1 or 2, characterized in that: The control method further comprises: The cropped n lines of data are transmitted to a host computer, so that the host computer performs image stitching based on the n lines of data.
14. A flat panel detector, characterized in that: include: At least two detection panels spliced together, each detection panel comprising a pixel array consisting of a plurality of detection pixels; At least two gate driving modules, used to drive the at least two detection panels respectively; At least two reading modules, used for respectively reading pixel data of the at least two detection panels; A control module, configured to execute the control method according to any one of claims 1 to 13, so as to control the at least two detection panels to capture images through the at least two gate driving modules and the at least two reading modules.
15. A dynamic image acquisition system, characterized in that: It comprises: a host computer, and the flat panel detector as claimed in claim 14; The host computer is used to send user instructions to the flat panel detector to control the flat panel detector to collect images.