Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprises a substrate and at least one functional layer, the functional layer comprises a first signal line and a second signal line, the first signal line and the second signal line are stacked on the substrate in the vertical direction, and the second signal line is located on the side, away from the substrate, of the first signal line; the first signal line and the second signal line are mutually insulated through an insulating film layer, the first signal line and the second signal line both extend in the first horizontal direction, and each of the first signal line and the second signal line is provided with a main body extension part and a leading-out end part; in the first signal line and the second signal line, the leading-out end part is positioned at at least one end of the main body extension part in the first horizontal direction; the orthographic projection of the main body extension part of the first signal line and the orthographic projection of the main body extension part of the second signal line on the substrate are overlapped; the orthographic projection of the leading-out end portion of the first signal line and the orthographic projection of the leading-out end portion of the second signal line on the substrate do not overlap. The scheme facilitates independent leading-out of each layer of signal lines.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductors, and in particular relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] With the development of the semiconductor industry, the market demand for DRAM (Dynamic Random Access Memory) storage density is getting higher and higher, but the existing 1T1C (T stands for transistor, C stands for capacitor) storage structure, that is, a storage structure including one transistor and one capacitor, is difficult to achieve three-dimensional stacking. The storage density is affected by the critical size when arranged in a plane, and the critical size is limited by the development of photolithography machines, so it is difficult to increase the storage density. The 2T0C storage structure (i.e., a storage structure including two transistors and no capacitor) can achieve an increase in storage density by continuously increasing the number of stacked layers without reducing the critical size, but for the 2T0C storage structure, there are multiple layers of signal lines, and how to lead out the signal lines of each layer has become an urgent problem to be solved. Summary of the invention

[0003] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the semiconductor device, which facilitates the extraction of signal lines at each layer and interconnection with other structures.

[0004] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising a substrate and at least one functional layer, wherein the functional layer comprises: a first signal line and a second signal line, which are stacked on the substrate in a vertical direction, wherein the second signal line is located on a side of the first signal line away from the substrate and is insulated from the second signal line by an insulating film layer, wherein the first signal line and the second signal line both extend in a first horizontal direction, wherein:

[0005] The first signal line and the second signal line both have a main extension portion and a lead-out end portion, and in the first signal line and the second signal line: the lead-out end portion is located at at least one end of the main extension portion in a first horizontal direction; the main extension portion of the first signal line and the main extension portion of the second signal line have overlapping orthographic projections on the substrate; the lead-out end portion of the first signal line and the lead-out end portion of the second signal line do not have overlapping orthographic projections on the substrate.

[0006] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:

[0007] providing a substrate; and

[0008] At least one functional layer is formed on the substrate, wherein the step of forming the functional layer comprises:

[0009] forming a first signal line and a first insulating film layer covering the first signal line on the substrate, wherein the first signal line extends in a first horizontal direction;

[0010] A second signal line extending in a first horizontal direction is formed on a side of the first insulating film layer away from the substrate; wherein

[0011] The first signal line and the second signal line each have a main body extension portion and a lead-out end portion, and in the first signal line and the second signal line: the lead-out end portion is located at least one end of the main body extension portion in the first horizontal direction;

[0012] The orthographic projections of the main extension portion of the first signal line and the main extension portion of the second signal line on the substrate overlap;

[0013] The orthographic projections of the lead-out end portion of the first signal line and the lead-out end portion of the second signal line on the substrate do not overlap.

[0014] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by staggering the lead-out ends of signal lines located in different layers and extending in the same direction without overlapping, it is convenient for signal lines of each layer to be independently led out without interfering with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0016] Figure 1 A schematic diagram of the three-dimensional structure of a semiconductor device provided by an embodiment of the present disclosure is shown.

[0017] Figure 2 Shows Figure 1 A cross-sectional view of the semiconductor device shown in FIG.

[0018] Figure 3 Shows Figure 1 A cross-sectional view of the semiconductor device shown in FIG.

[0019] Figure 4 Shows Figure 1 A cross-sectional view of a memory cell in the semiconductor device shown in FIG.

[0020] Figure 5 Shows Figure 1 A cross-sectional view of a memory cell in the semiconductor device shown in FIG.

[0021] Figure 6 to Figure 43 A schematic diagram of a cross-sectional structure corresponding to each step after executing each step in a method for manufacturing a semiconductor device shown in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0023] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0024] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0025] The present disclosure provides a semiconductor device, which may be a DRAM, but is not limited thereto. It may also be a ferroelectric random access memory (FeRAM) or other types of semiconductor devices, which are not limited here.

[0026] The structure of the semiconductor device according to the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0027] like Figure 1 As shown, the semiconductor device may include a substrate 10 and a functional layer 20, and the functional layer 20 may be formed on the substrate 10. In this embodiment, the functional layer 20 of the semiconductor device is configured to have two or more layers to increase the storage density of the semiconductor device, but is not limited thereto, and may also be configured to have a single layer.

[0028] When the functional layer 20 in the semiconductor device is provided with two or more layers, the semiconductor device can be understood as a three-dimensional stacked semiconductor device.

[0029] It should be understood that the semiconductor device is not limited to including the functional layer 20. In addition to the functional layer 20, it may also include a control circuit (not shown in the figure) and a reading circuit and other structures, which will not be described in detail here.

[0030] Combination Figure 2 and Figure 3 As shown, the substrate 10 may include a semiconductor base 101 and an insulating isolation layer 102 formed on the semiconductor base 101. In this embodiment, the insulating isolation layer 102 may be a stacked structure, which is a structure formed by stacking two or more film layers of different materials in sequence, but is not limited thereto, and the insulating isolation layer 102 may also be a single-layer structure.

[0031] For example, the material of the semiconductor substrate 101 may be an elemental semiconductor material such as silicon (Si) or germanium (Ge), but is not limited thereto, and may also be a crystalline inorganic compound semiconductor material such as silicon carbide (SiC) or silicon germanium (SiGe). The material of the insulating isolation layer 102 may include one or more insulating materials such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or may also include other low-K value materials.

[0032] like Figure 2 and Figure 3 As shown, the insulating isolation layer 102 may include a first film layer 1021 and a second film layer 1022 formed sequentially on the substrate 10, wherein the material of the first film layer 1021 may be a silicon oxide material, and the material of the second film layer 1022 may be a silicon nitride material, but is not limited thereto, and the materials of the first film layer 1021 and the second film layer 1022 may also be other insulating materials.

[0033] Combination Figure 2 and Figure 3 As shown, the functional layer 20 may include a first signal line 203 and a second signal line 205, which are stacked on the substrate 10 along a vertical direction Z. It should be noted that the vertical direction Z may be a direction intersecting with the substrate 10. Further, the vertical direction Z may be a direction perpendicular or approximately perpendicular to the substrate 10.

[0034] Among them, the second signal line 205 is located on the side of the first signal line 203 away from the substrate 10, and is insulated from the first signal line 203 by an insulating film layer. The first signal line 203 and the second signal line 205 both extend in the first horizontal direction X. It should be noted that the first horizontal direction X can be a direction parallel to the substrate 10.

[0035] The first signal line 203 and the second signal line 205 both have a main extension portion (not shown in the figure) and a lead-out end portion (not shown in the figure). In the first signal line 203 and the second signal line 205: the lead-out end portion is located at least one end of the main extension portion in the first horizontal direction X, and the lead-out end portion is used to receive a level signal output by the control circuit through a lead-out structure or output a level signal to the reading circuit.

[0036] Among them, the main extension portion of the first signal line 203 and the main extension portion of the second signal line 205 have overlapping orthographic projections on the substrate 10; the lead-out end portion of the first signal line 203 and the lead-out end portion of the second signal line 205 do not overlap in their orthographic projections on the substrate 10, that is, the lead-out end portions of the signal lines located in different layers and extending in the same direction are staggered and non-overlapping.

[0037] In this embodiment, the lead-out ends of the signal lines located in different layers and extending in the same direction are staggered and arranged without overlapping, so that the signal lines of each layer can be led out independently without interfering with each other.

[0038] In the first signal line 203 and the second signal line 205: the lead-out end portion has a first surface close to the substrate 10 and a second surface away from the substrate; wherein, in the first signal line 203 and the second signal line 205: the direction from the first surface to the second surface is the lead-out direction, but is not limited thereto, and the direction from the second surface to the first surface may also be the lead-out direction, so that the lead-out structure connected to the first signal line 203 and the lead-out structure connected to the second signal line 205 can be led out on the same side, which is convenient for manufacturing.

[0039] It should be noted that if the direction from the first surface to the second surface is the lead-out direction, then the end of the lead-out structure connected to the corresponding lead-out end that is away from the first surface is the end in the lead-out direction, which is used to connect to a control circuit or a reading circuit, etc.; if the direction from the second surface to the first surface is the lead-out direction, then the end of the lead-out structure connected to the corresponding lead-out end that is away from the second surface is the end in the lead-out direction, which is used to connect to a control circuit or a reading circuit, etc. In addition, it should be noted that the end of the lead-out structure opposite to its end can be defined as the head end.

[0040] For example, the head end of the lead-out structure may contact the first surface or the second surface of the corresponding lead-out end portion to achieve electrical connection. Specifically, when the direction from the second surface to the first surface is the lead-out direction, the lead-out structure contacts the first surface of the corresponding lead-out end portion, and when the direction from the first surface to the second surface is the lead-out direction, the lead-out structure contacts the second surface of the corresponding lead-out end portion. The surface in contact with the head end of the lead-out structure may be defined as the lead-out surface.

[0041] In this embodiment, the first surface of the lead-out end portion of the first signal line 203 and the second signal line 205 may be a lead-out surface, or the second surface of the lead-out end portion of the first signal line 203 and the second signal line 205 may be a lead-out surface, so as to contact with the head end of the lead-out structure to achieve electrical connection; but not limited to this, grooves or through holes may also be opened on the lead-out end portions of the first signal line 203 and the second signal line 205, so that the head end of the lead-out structure can be embedded in the groove or the through hole to contact with the lead-out end portions of the first signal line 203 and the second signal line 205, thereby achieving electrical connection between the two.

[0042] In this embodiment, the extension lengths of the second signal line 205 and the first signal line 203 may be designed to be different, that is, the extension lengths of the signal lines located at different layers and extending in the same direction may be designed to be different, so that portions of the longer signal lines among the multiple signal lines located at different layers and extending in the same direction are not blocked by the shorter signal lines. It should be noted that the unblocked portions are lead-out ends, so that the multiple signal lines located at different layers and extending in the same direction are arranged in a stepped shape, which facilitates the lead-out of the signal lines of each layer through different lead-out structures.

[0043] Among them, the stacking position of the longer signal line and the shorter signal line extending in the same direction can be determined according to the lead-out direction; for example, when the direction in which the second surface points to the first surface of the first signal line 203 and the second signal line 205 is the lead-out direction, the extension length of the first signal line 203 located in the same functional layer 20 is smaller than the extension length of the second signal line 205; or when the direction in which the first surface points to the second surface of the first signal line 203 and the second signal line 205 is the lead-out direction, the extension length of the second signal line 205 located in the same functional layer 20 is smaller than the extension length of the first signal line 203.

[0044] Optionally, in the first signal line 203 and the second signal line 205: both opposite ends of the main body extension portion in the first horizontal direction X are provided with lead-out ends for convenient connection with the control circuit.

[0045] In this embodiment, the functional layer 20 may be provided in multiple layers, and is sequentially stacked along the vertical direction Z on the substrate 10 .

[0046] Among them, when the functional layer 20 is provided with multiple layers, in two adjacent functional layers 20: when the direction in which the second surface points to the first surface in the first signal line 203 and the second signal line 205 is the lead-out direction, the extension length of the first signal line 203 of the functional layer 20 away from the substrate 10 is greater than the extension length of the second signal line 205 of the functional layer 20 close to the substrate 10; or when the direction in which the first surface points to the second surface in the first signal line 203 and the second signal line 205 is the lead-out direction, the extension length of the first signal line 203 of the functional layer 20 away from the substrate 10 is less than the extension length of the second signal line 205 of the functional layer 20 close to the substrate 10.

[0047] The functional layer 20 may further include a third signal line 204 extending in the second horizontal direction Y, the third signal line 204 having a main extension portion and a lead-out end portion, the lead-out end portion of the third signal line 204 being located at least one end of the main extension portion in the second horizontal direction Y. The third signal line 204 is stacked with the first signal line 203 and the second signal line 205 along the vertical direction Z, and is insulated from the adjacent signal lines by the insulating film layer. It should be noted that the second horizontal direction Y is a direction parallel to the substrate 10, and the second horizontal direction Y intersects with the first horizontal direction X, and further, the second horizontal direction Y and the first horizontal direction X may be perpendicular to each other.

[0048] The functional layer 20 also includes a fourth signal line 206 extending in the second horizontal direction Y, the fourth signal line 206 has a main extension portion and a lead-out end portion, the lead-out end portion of the fourth signal line 206 is located at least one end of its main extension portion in the second horizontal direction Y, the fourth signal line 206 is stacked along the vertical direction Z with the first signal line 203, the second signal line 205 and the third signal line 204, and is insulated from the adjacent signal lines by an insulating film layer.

[0049] Among them, the main extension portion of the fourth signal line 206 and the main extension portion of the third signal line 204 have overlapping orthographic projections on the substrate 10; the lead-out end portion of the fourth signal line 206 and the lead-out end portion of the third signal line 204 do not overlap in their orthographic projections on the substrate 10, that is, the lead-out end portion of the fourth signal line 206 and the lead-out end portion of the third signal line 204, which are located in different layers and extend in the same direction, are staggered and non-overlapping.

[0050] For example, in the functional layer 20 , the third signal line 204 is formed between the first signal line 203 and the second signal line 205 . In the functional layer 20 , the fourth signal line 206 is formed between the third signal line 204 and the second signal line 205 , or in the functional layer 20 , the fourth signal line 206 is formed on the side of the second signal line 205 away from the third signal line 204 .

[0051] It should be noted that, in the third signal line 204 and the fourth signal line 206: the lead-out end portion has a first surface close to the substrate 10 and a second surface away from the substrate 10; wherein, in the third signal line 204 and the fourth signal line 206: the direction from the first surface to the second surface is the lead-out direction or the direction from the second surface to the first surface is the lead-out direction, so that the lead-out structure connected to the third signal line 204 and the lead-out structure connected to the fourth signal line 206 can be led out on the same side, which is convenient for manufacturing.

[0052] For example, the first surface of the lead-out end portion of the third signal line 204 and the fourth signal line 206 may be a lead-out surface, or the second surface of the lead-out end portion of the third signal line 204 and the fourth signal line 206 may be a lead-out surface, so as to contact the head end (i.e., the starting end of the lead-out direction) of the lead-out structure to achieve electrical connection; but not limited to this, grooves or through holes may also be opened on the lead-out end portions of the third signal line 204 and the fourth signal line 206, so that the head end of the lead-out structure can be embedded in the groove or the through hole to contact the lead-out end portions of the third signal line 204 and the fourth signal line 206, thereby achieving electrical connection.

[0053] In this embodiment, the extension lengths of the third signal line 204 and the fourth signal line 206 may be designed to be different, that is, the extension lengths of the signal lines located at different layers and extending in the same direction may be designed to be different, so that portions of the longer signal lines among the multiple signal lines located at different layers and extending in the same direction are not blocked by the shorter signal lines. It should be noted that the unblocked portions are lead-out ends, so that the multiple signal lines located at different layers and extending in the same direction are arranged in a stepped shape, which facilitates the lead-out of the signal lines of each layer through different lead-out structures.

[0054] Among them, the stacking position of the longer signal line and the shorter signal line extending in the same direction can be determined according to the specific position of the lead-out surface (i.e., the lead-out direction); for example, when the direction from the second surface to the first surface of the third signal line 204 and the fourth signal line 206 is the lead-out direction, the extension length of the third signal line 204 located in the same functional layer 20 is less than the extension length of the fourth signal line 206; or when the direction from the first surface to the second surface of the third signal line 204 and the fourth signal line 206 is the lead-out direction, the extension length of the fourth signal line 206 located in the same functional layer 20 is less than the extension length of the third signal line 204.

[0055] Optionally, in the third signal line 204 and the fourth signal line 206 , lead-out ends are provided at opposite ends of the main body extension portion in the second horizontal direction Y, so as to facilitate connection with the control circuit.

[0056] Among them, when the functional layer 20 is provided with multiple layers, in two adjacent functional layers 20: when the direction in which the second surface points to the first surface in the third signal line 204 and the fourth signal line 206 is the lead-out direction, the length of the third signal line 204 of the functional layer 20 away from the substrate 10 is greater than the length of the fourth signal line 206 in the functional layer 20 close to the substrate 10; or when the direction in which the first surface points to the second surface in the third signal line 204 and the fourth signal line 206 is the lead-out direction, the length of the third signal line 204 of the functional layer 20 away from the substrate 10 is less than the length of the fourth signal line 206 in the functional layer 20 close to the substrate 10.

[0057] In addition, the semiconductor device may further include a first lead-out structure S1, a second lead-out structure S3, a third lead-out structure S2 and a fourth lead-out structure S4 which are spaced apart from each other. The first lead-out structure S1 to the fourth lead-out structure S4 all extend along the vertical direction Z and have different extension lengths.

[0058] Among them, one end of the first lead-out structure S1 (i.e., the starting end in the lead-out direction, which can also be defined as the head end) is in contact with the lead-out end of the first signal line 203, and the other end of the first lead-out structure S1 (i.e., the terminal in the lead-out direction, which can also be defined as the end) extends along the lead-out direction and penetrates each insulating film layer; one end of the second lead-out structure S3 (i.e., the starting end in the lead-out direction, which can also be defined as the head end) is in contact with the lead-out end of the second signal line 205, and the other end of the second lead-out structure S3 (i.e., the terminal in the lead-out direction, which can also be defined as the end) extends along the lead-out direction and penetrates each insulating film layer. layer; one end of the third lead-out structure S2 (i.e., the starting end in the lead-out direction, which can also be defined as the head end) is in contact with the lead-out end portion of the third signal line 204, and the other end of the third lead-out structure S2 (i.e., the terminal end in the lead-out direction, which can also be defined as the end portion) extends along the lead-out direction and passes through each insulating film layer; one end of the fourth lead-out structure S4 (i.e., the starting end in the lead-out direction, which can also be defined as the head end) is in contact with the lead-out end portion of the fourth signal line 206, and the other end of the fourth lead-out structure S4 (i.e., the terminal end in the lead-out direction, which can also be defined as the end portion) extends along the lead-out direction and passes through each insulating film layer.

[0059] The following is combined with Figure 1 To Attachment Figure 5 A specific embodiment of the present disclosure is described in detail.

[0060] The functional layer 20 may include a plurality of storage units 20a, combined with Figure 2 and Figure 3As shown, a plurality of storage units 20a may be arranged in an array along a first horizontal direction X and a second horizontal direction Y, so that the functional layer 20 is an array storage structure, which may increase the storage density of each functional layer 20, but is not limited thereto. The functional layer 20 may also include a single storage unit 20a, depending on the specific circumstances.

[0061] In this embodiment, the storage unit 20a may be a 2T0C structure. Specifically, refer to Figure 4 and Figure 5 As shown, the memory cell 20 a may at least include a first transistor 201 , a second transistor 202 , a first signal line 203 , a third signal line 204 , a second signal line 205 and a fourth signal line 206 .

[0062] The first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 all include a main extension portion (not shown in the figure) and a lead-out end portion (not shown in the figure). Figure 2 and Figure 3 As shown, the lead-out ends of the first signal line 203 , the third signal line 204 , the second signal line 205 and the fourth signal line 206 are located at opposite ends of the main extension part in its extension direction, and are used to be connected to the lead-out structure.

[0063] In addition, the first transistor 201 is connected to the main extension portion of the first signal line 203 and the main extension portion of the third signal line 204, and the second transistor 202 is connected to the main extension portion of the second signal line 205 and the main extension portion of the fourth signal line 206. One or more signal lines among the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 are used to receive the level signal output by the control circuit through the lead-out structure or output the level signal to the reading circuit, select the storage unit 20a to be read and written in the functional layer 20, thereby realizing the reading and writing operations of data.

[0064] Combination Figure 4 and Figure 5 As shown, the first transistor 201 and the second transistor 202 both include a channel portion SD and a gate portion G insulated from the channel portion SD. Specifically, a gate insulating portion GI is formed between the channel portion SD and the gate portion G. It should be understood that the channel portion SD includes a first connection region, a second connection region, and a channel region located between the first connection region and the second connection region, which are not numbered in the figure. One of the first connection region and the second connection region is a source region, and the other is a drain region. The gate portion G includes a gate region. Specifically, the gate portion G as a whole can be understood as a gate region.

[0065] The first connection area of ​​the first transistor 201 is connected to the main extension of the first signal line 203, for example: the first connection area of ​​the first transistor 201 can be directly in contact with the main extension of the first signal line 203, but not limited to this, other conductive structures can also be used for indirect electrical connection; the second connection area of ​​the first transistor 201 is connected to the main extension of the third signal line 204, for example: the second connection area of ​​the first transistor 201 can be directly in contact with the main extension of the first signal line 203, but not limited to this, other conductive structures can also be used for indirect electrical connection; the first connection area of ​​the second transistor 202 is connected to the gate area of ​​the first transistor 201, for example: the first connection area of ​​the second transistor 202 can be connected to the gate area of ​​the first transistor 201, or the first connection area of ​​the second transistor 202 can be connected to the gate area of ​​the first transistor 201 through the conductive contact pad 207; the second connection area of ​​the second transistor 202 is connected to the main extension of the second signal line 205, for example: the second connection area of ​​the second transistor 202 can be directly in contact with the main extension of the second signal line 205, but not limited to this, and other conductive structures can also be used for indirect electrical connection; the gate area of ​​the second transistor 202 is connected to the main extension of the fourth signal line 206, for example: the gate area of ​​the second transistor 202 is directly in contact with the main extension of the fourth signal line 206, but not limited to this, and other conductive structures can also be used for indirect electrical connection.

[0066] The storage unit 20a of this embodiment adopts a 2T0C structure. Compared with the 1T1C storage structure, while ensuring the storage performance of a single storage unit 20a, the occupied area of ​​the single storage unit 20a can be reduced, so that the number of storage units 20a in each functional layer 20 can be appropriately increased to improve the storage density of each functional layer 20, and then improve the storage density of the entire semiconductor device.

[0067] For example, in the same functional layer 20: the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 are stacked on top of each other and two adjacent signal lines are insulated from each other by an insulating film layer, so as to reduce the crosstalk between the signals of the first transistor 201 and the second transistor 202 while reducing the area occupied by the storage unit 20a.

[0068] It should be noted that the stacked arrangement mentioned in this embodiment means that each structure is located in a different film layer, and each film layer is stacked in one direction; the mutual insulation mentioned in this embodiment means that an insulating film layer is arranged between two adjacent layers of structures.

[0069] For example, the materials of the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 may include one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver); the insulating material may include one or more materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), TiO2 (titanium dioxide), SiN (silicon nitride), etc.

[0070] Among them, in the same functional layer 20: the first signal line 203 and the second signal line 205 can both extend in the first horizontal direction X, and the third signal line 204 and the fourth signal line 206 can both extend in the second horizontal direction Y. By designing the extension directions of the first signal line 203 and the third signal line 204 to be different, and the extension directions of the second signal line 205 and the fourth signal line 206 to be different, the design and control difficulty of the functional layer 20 is reduced while achieving control of the transistor. In addition, the parasitic capacitance generated between the two signal lines connected to the transistor can also be reduced. By designing the extension directions of the first signal line 203 and the second signal line 205 to be the same, and the extension directions of the third signal line 204 and the fourth signal line 206 to be the same, the design difficulty of the storage unit 20a and its occupied area can be further reduced.

[0071] Furthermore, the first horizontal direction X and the second horizontal direction Y are perpendicular to each other, so as to reduce the floor space occupied by the storage unit 20a.

[0072] In addition, when the functional layer 20 includes a plurality of memory cells 20a arranged in an array in the first horizontal direction X and the second horizontal direction Y, the plurality of memory cells 20a arranged in the first horizontal direction X share a first signal line 203 and a second signal line 205 extending in the first horizontal direction X. Figure 2 As shown; a plurality of storage units 20a arranged in the second horizontal direction Y share a third signal line 204 and a fourth signal line 206 extending in the second horizontal direction Y to reduce the difficulty of controlling the functional layer 20, thereby reducing costs.

[0073] Since the first signal line 203 and the second signal line 205 in the functional layer 20 are stacked and extend in the same direction, and the third signal line 204 and the fourth signal line 206 are stacked and extend in the same direction, therefore, in order to facilitate the independent lead-out of the signal lines located in different layers and extending in the same direction in the functional layer 20, the lengths of the signal lines located in different layers and extending in the same direction may be designed to be different in this embodiment, that is, the second signal line 205 and the first signal line 203 have different extension lengths, and the fourth signal line 206 and the third signal line 204 have different extension lengths. In this way, among the multiple signal lines located in different layers and extending in the same direction, portions of the longer signal lines are not blocked by the shorter signal lines, so that the multiple signal lines located in different layers and extending in the same direction are arranged in a stepped shape, which is convenient for the lead-out of the signal lines of each layer.

[0074] Combination Figures 1 to 3 As shown, each functional layer 20 corresponds to a first lead-out structure S1, a third lead-out structure S2, a second lead-out structure S3 and a fourth lead-out structure S4 which are arranged at intervals. The lead-out end of the first signal line 203 contacts the first lead-out structure S1, the lead-out end of the third signal line 204 contacts the third lead-out structure S2, the lead-out end of the second signal line 205 contacts the second lead-out structure S3, and the lead-out end of the fourth signal line 206 contacts the fourth lead-out structure S4. Each signal line can be connected to a control circuit or a reading circuit through the lead-out structure in contact with it, thereby realizing independent lead-out of the signal lines in the storage unit 20a.

[0075] It should be noted that the position where the lead-out end of the signal line mentioned above contacts the lead-out structure may be the lead-out surface (ie, the first surface or the second surface mentioned above). At this time, the insulating film layer formed on the side where the lead-out surface of the signal line is located may be penetrated by the lead-out structure corresponding thereto.

[0076] refer to Figure 2 and Figure 3 As shown, in the same functional layer 20 , the first signal line 203 , the third signal line 204 , the second signal line 205 and the fourth signal line 206 are stacked in the vertical direction Z.

[0077] In this embodiment, the first horizontal direction X and the second horizontal direction Y are directions parallel to the substrate 10, and the vertical direction Z is a direction perpendicular or approximately perpendicular to the substrate 10, that is, the extension directions of the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 are parallel to the substrate 10, and the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 are stacked in a direction perpendicular to the substrate 10, which can reduce the manufacturing difficulty and design cost.

[0078] In addition, combined Figures 2 to 5As shown, when the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 are stacked in the vertical direction Z, the first transistor 201 and the second transistor 202 can also be stacked in the vertical direction Z on the substrate 10, reducing the area occupied by the storage unit 20a, thereby improving the overall storage density of the functional layer 20.

[0079] When the direction from the first surface to the second surface in each signal line is the lead-out direction, that is, when the second signal line 205 is formed on the lead-out side of the first signal line 203, and the fourth signal line 206 is formed on the lead-out side of the third signal line 204, Figure 2 As shown, the extension length of the second signal line 205 is less than the extension length of the first signal line 203. Figure 3 As shown, the extension length of the fourth signal line 206 is shorter than the extension length of the third signal line 204, so as to facilitate the lead-out of each signal line through an independent lead-out structure.

[0080] It should be noted that the orthographic projection mentioned in the embodiment of the present disclosure refers to the projection generated by projecting in a direction perpendicular to the substrate 10 .

[0081] Optionally, in the same functional layer 20: the orthographic projections of the second signal line 205 at two opposite ends in the first horizontal direction X on the substrate 10 are both located within the orthographic projection of the first signal line 203 on the substrate 10; the orthographic projections of the fourth signal line 206 at two opposite ends in the second horizontal direction Y on the substrate 10 are both located within the orthographic projection of the third signal line 204 on the substrate 10.

[0082] Further, in the same functional layer 20: reference Figure 2 As shown, the two opposite edges of the first signal line 203 in the first horizontal direction X do not overlap with the orthographic projection of the second signal line 205 on the substrate 10, that is, the two opposite edges of the first signal line 203 in the first horizontal direction X are not blocked by the second signal line 205 on the side away from the substrate 10, and the two opposite edges of the first signal line 203 in the first horizontal direction X can be led out through the first lead-out structure S1; Figure 3 As shown, there is no overlap between the two relative edges of the third signal line 204 in the second horizontal direction Y and the positive projection of the fourth signal line 206 on the substrate 10, that is, the two relative edges of the third signal line 204 in the second horizontal direction Y are not blocked by the fourth signal line 206 on the side away from the substrate 10, and the two relative edges of the third signal line 204 in the second horizontal direction Y can be led out through the third lead-out structure S2, which is beneficial to the connection between the storage unit 20a and its surrounding circuits.

[0083] Continue to refer Figure 2As shown, the two opposite edges of the second signal line 205 in the first horizontal direction X can be led out through the second lead-out structure S3. Figure 3 As shown, two opposite edges of the fourth signal line 206 in the second horizontal direction Y can be led out through the fourth lead-out structure S4.

[0084] It is worth noting that the two opposite edges mentioned here refer to the lead-out end portions of each signal line located at opposite ends of the main body extension portion in its extension direction.

[0085] In addition, it should be noted that the reference Figure 3 As shown, the number of the first signal lines 203 may be equal to the number of the second signal lines 205 and correspond one to one in the vertical direction Z. Figure 2 As shown, the number of the third signal lines 204 may be equal to the number of the fourth signal lines 206 and correspond one to one in the vertical direction Z, but is not limited thereto, and the number may also be unequal, depending on the specific situation.

[0086] In addition, the widths and / or thicknesses of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 may be designed to be equal, but are not limited thereto. The widths and / or thicknesses of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 may also be designed to be slightly different according to actual conditions, depending on the actual performance required by the semiconductor device and processing conditions.

[0087] In this embodiment, the direction in which the lead-out end of the signal line is away from the substrate 10 can be defined as the lead-out direction. When the direction in which the lead-out end of the signal line is away from the substrate 10 is the lead-out direction: Figure 2 and Figure 3 As shown, the second signal line 205 can be formed on the side of the first signal line 203 away from the substrate 10, and the fourth signal line 206 can be formed on the side of the third signal line 204 away from the substrate 10. By designing the direction of the lead-out end of the signal line away from the substrate 10 as the lead-out direction, after the various film layers in the functional layer 20 are formed, the first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3 and the fourth lead-out structure S4 can be uniformly formed, which can reduce the manufacturing difficulty and improve the manufacturing efficiency while realizing the independent lead-out of each signal line.

[0088] It should be understood that when the direction in which the lead-out end of the signal line is away from the substrate 10 can be the lead-out direction, the end of the lead-out structure away from the substrate 10 can be connected to a control circuit or other circuits.

[0089] When the direction in which the lead-out end of the signal line is away from the substrate 10 is the lead-out direction, the first signal line 203 and the third signal line 204 can be designed to be closer to the substrate 10 than the second signal line 205 and the fourth signal line 206, and the first transistor 201 can be designed to be closer to the substrate 10 than the second transistor 202, so as to facilitate the first signal line 203 and the third signal line 204 to be connected to the first transistor 201, and the second signal line 205 and the fourth signal line 206 to be connected to the second transistor 202.

[0090] Combination Figures 2 to 5 As shown, when the direction in which the lead-out end of the signal line is away from the substrate 10 is the lead-out direction, the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 are stacked in sequence on the substrate 10, so that the extension directions of adjacent signal lines in the vertical direction Z in the functional layer 20 are different from each other, so as to reduce the parasitic capacitance generated between adjacent signal lines.

[0091] It should be noted that the present solution is not limited to designing the direction of the lead-out end of the signal line away from the substrate 10 as the lead-out direction. The direction of the lead-out end of the signal line close to the substrate 10 may also be designed as the lead-out direction. For example, when the direction of the lead-out end of the signal line close to the substrate 10 is the lead-out direction, the extension length of the second signal line 205 may be greater than the extension length of the first signal line 203, and the extension length of the fourth signal line 206 may be greater than the extension length of the third signal line 204. At this time, after the film layers of the functional layer 20 are formed in sequence, the lead-out structure may be uniformly formed on the substrate 10 side.

[0092] In addition, taking the direction in which the lead-out end of the signal line is away from the substrate 10 as an example, when multiple layers are provided in the functional layer 20 of the semiconductor device and are sequentially stacked on the substrate 10 in the vertical direction Z, in two adjacent functional layers 20: Figure 2 As shown, the extension length of the first signal line 203 in the functional layer 20 far from the substrate 10 is less than the extension length of the second signal line 205 in the functional layer 20 close to the substrate 10, as shown in FIG. Figure 3 As shown, the extension length of the third signal line 204 in the functional layer 20 away from the substrate 10 is shorter than the extension length of the fourth signal line 206 in the functional layer 20 close to the substrate 10, so as to facilitate the independent extraction of signal lines located in different layers and extending in the same direction in the entire semiconductor device.

[0093] In other words, when the direction in which the lead end of the signal line is away from the substrate 10 is the lead direction, the extension lengths of the signal lines located in different layers and having the same extension direction in the entire semiconductor device decrease sequentially in the direction away from the substrate 10 .

[0094] In order to protect the structure of each memory cell 20 a in the functional layer 20 , the functional layer 20 further includes an insulating film layer covering the memory cell 20 a .

[0095] Combination Figure 2 and Figure 3 As shown, in the functional layer 20: the first lead-out structure S1 penetrates each insulating film layer on its lead-out direction side, the third lead-out structure S2 penetrates each insulating film layer on its lead-out direction side; the second lead-out structure S3 penetrates each insulating film layer on its lead-out direction side; and the fourth lead-out structure S4 penetrates each insulating film layer on its lead-out direction side.

[0096] Among them, the first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3 and the fourth lead-out structure S4 all extend in the vertical direction Z and have different extension lengths. It should be understood that the lead-out structure connected to the signal line closer to the substrate 10 has a greater extension length.

[0097] After the multi-layer functional layers 20 are stacked in sequence on the substrate 10, the first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3 and the fourth lead-out structure S4 corresponding to each functional layer 20 are uniformly formed to simplify the processing steps and reduce costs.

[0098] In this embodiment, the second connection region of the channel portion SD in the transistor may be located on a side of the channel region away from the first connection region, that is, the channel region of the channel portion SD may extend in the vertical direction Z, so that the storage density may be increased and the leakage current may be reduced by increasing the length of the channel region without increasing the horizontal area of ​​the memory cell 20a. Figures 2 to 5 As shown, the gate portion G and the channel portion SD are arranged opposite to each other at least in a direction parallel to the substrate 10 .

[0099] Optionally, the materials of the channel portion SD and the gate portion G are both semiconductor materials. The gate portion G is made of semiconductor materials, which makes it easy to control the critical voltage of the transistor and has fewer contact surface defects.

[0100] Among them, the semiconductor material can be one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), and ITO (indium tin oxide), which is beneficial to reducing the leakage current of the transistor and reducing the power consumption of the transistor, but is not limited to this, and can also be other semiconductor materials such as silicon.

[0101] It should be understood that the semiconductor materials of the channel portion SD and the gate portion G may be the same or different. For example, the semiconductor material of the channel portion SD may include IGZO, and the semiconductor material of the gate portion G may include IZO.

[0102] For example, the first connection region of the channel portion SD of the first transistor 201 is formed between its gate portion G and the first signal line 203, and the channel region and the second connection region of the channel portion SD of the first transistor 201 are both arranged around its gate portion G. It should be understood that the channel region and the second connection region of the channel portion SD of the first transistor 201 are not limited to being arranged around its gate portion G, but may also be located on opposite sides of the gate portion G. The first connection region of the channel portion SD of the second transistor 202 is formed between its gate portion G and the gate portion G of the first transistor 201, and the channel region and the second connection region of the second transistor 202 are both arranged around its gate portion G. That is, the cross-section of the channel portion SD of the first transistor 201 and the second transistor 202 in the vertical direction Z can be understood as a U-shape. Compared with a flat vertical transistor, such a design can increase the length of the channel region of the first transistor 201 and the second transistor 202 while keeping the horizontal area unchanged, so as to improve the storage density.

[0103] Optionally, combined Figures 2 to 5 As shown, the third signal line 204 is disposed around the second connection region of the first transistor 201, and the second signal line 205 is disposed around the second connection region of the second transistor 202, so as to improve the integration density of the semiconductor structure.

[0104] In this embodiment, a conductive contact pad 207 is formed between the first connection area of ​​the channel portion SD of the second transistor 202 and the gate portion G of the first transistor 201; wherein the orthographic projections of the gate portions G of the first transistor 201 and the second transistor 202 on the substrate 10 overlap with the orthographic projections of the conductive contact pad 207 on the substrate 10. Further, the orthographic projections of the gate portions G of the first transistor 201 and the second transistor 202 on the substrate 10 may both be located within the orthographic projections of the conductive contact pad 207 on the substrate 10. By providing the conductive contact pad 207, it is beneficial to ensure the electrical conduction area between the gate portion G of the first transistor 201 and the first connection area of ​​the second transistor 202, thereby ensuring the working performance of the storage unit 20a.

[0105] The present disclosure also provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device described in any of the above embodiments, wherein the method for manufacturing a semiconductor device may include: providing a substrate 10; and forming at least one functional layer 20 on the substrate 10. The arrangement relationship, structural shape, length relationship, lead-out direction, etc. of each structure in the functional layer 20 can be referred to in the attached Figure 1 To Attachment Figure 5 The recorded contents and the contents described in any of the aforementioned schemes will not be elaborated here.

[0106] In this embodiment, the step of forming the functional layer 20 may include:

[0107] Step S1, forming a first signal line 203 and a first insulating film layer 209 covering the first signal line 203 on the substrate 10, wherein the first signal line 203 extends in a first horizontal direction X;

[0108] In step S2 , a second signal line 205 extending in the first horizontal direction X is formed on a side of the first insulating film layer 209 away from the substrate 10 .

[0109] In this embodiment, the step of forming the functional layer 20 may further include:

[0110] Before forming the second signal line 205: a third signal line 204, a second insulating film layer 210, a fourth signal line 206 and a third insulating film layer 212 are sequentially formed on a side of the first insulating film layer 209 away from the substrate 10, the third signal line 204 and the fourth signal line 206 both extend in the second horizontal direction Y, the third signal line 204 and the fourth signal line 206 are insulated from each other by the second insulating film layer 210, and the fourth signal line 206 and the second signal line 205 are insulated from each other by the third insulating film layer 212; or

[0111] Before forming the second signal line 205: a third signal line 204 and a second insulating film layer 210 are sequentially formed on a side of the first insulating film layer 209 away from the substrate 10; after forming the second signal line 205: a third insulating film layer 212 and a fourth signal line 206 are sequentially formed, the third signal line 204 and the fourth signal line 206 both extend in the second horizontal direction Y, the third signal line 204 and the second signal line 205 are insulated from each other by the second insulating film layer 210, and the second signal line 205 and the fourth signal line 206 are insulated from each other by the third insulating film layer 212.

[0112] The following is combined with Figures 1 to 43 The manufacturing method of the embodiment of the present disclosure is described in detail.

[0113] The step of forming the functional layer 20 on the substrate 10 may specifically include: step S100 , step S102 , step S104 , step S106 , step S108 , step S110 , step S112 , step S114 , step S116 , etc.

[0114] In step S100 , a first signal line 203 and a first insulating film layer 209 covering the first signal line 203 are sequentially formed on the substrate 10 .

[0115] For example, when the substrate 10 includes a semiconductor base 101 and an insulating isolation layer 102 formed on the semiconductor base 101 , forming the first signal line 203 on the substrate 10 can be understood as forming the first signal line 203 on a side of the insulating isolation layer 102 away from the semiconductor base 101 .

[0116] For example, the step of forming the first signal line 203 may specifically include: step S1001 , step S1002 , and step S1003 .

[0117] In step S1001, a plurality of first signal lines 203 spaced apart in a second horizontal direction Y are formed on the substrate 10. Figure 6 shown.

[0118] In step S1002, a first isolation material film 213a is formed. The first isolation material film 213a covers each first signal line 203 and fills between adjacent first signal lines 203. Figure 7 As shown;

[0119] In step S1003, the portion of the first isolation material film 213a that is higher than the first signal line 203 is removed to form a first isolation pattern layer 213. The surface of the first isolation pattern layer 213 away from the substrate 10 is flush with the surface of the first signal line 203 away from the substrate 10. That is, the surface of the first signal line 203 away from the substrate 10 is exposed, and the first isolation pattern layer 213 at least includes a first isolation portion 2131 filled between adjacent first signal lines 203. Figure 8 shown.

[0120] After step S1003 is performed, a first insulating film layer 209 covering the first signal line 203 is formed.

[0121] In step S102 , a third signal line 204 and a second insulating film layer 210 covering the third signal line 204 are sequentially formed on a side of the first insulating film layer 209 away from the substrate 10 , and a main extension portion of the third signal line 204 overlaps with a main extension portion of the first signal line 203 on the substrate 10 .

[0122] For example, the step of forming the third signal line 204 may specifically include: step S1021 , step S1022 , and step S1023 .

[0123] In step S1021, a plurality of third signal lines 204 are formed on a side of the first insulating film layer 209 away from the substrate 10 and spaced apart in the first horizontal direction X. Fig. 9 shown.

[0124] In step S1022, a second isolation material film 214a is formed. The second isolation material film 214a covers each third signal line 204 and fills between adjacent third signal lines 204. Fig.10 shown.

[0125] In step S1023, the portion of the second isolation material film 214a that is higher than the third signal line 204 is removed, and a second isolation pattern layer 214 is formed. The surface of the second isolation pattern layer 214 away from the substrate 10 is flush with the surface of the third signal line 204 away from the substrate 10. That is, the surface of the third signal line 204 away from the substrate 10 is exposed, and the second isolation pattern layer 214 at least includes a second isolation portion 2141 filled between adjacent third signal lines 204. Fig.11 shown.

[0126] After step S1023 is performed, a second insulating film layer 210 covering the third signal line 204 is formed.

[0127] In step S104, a first through hole H1 is formed that sequentially penetrates the second insulating film layer 210, the main extension portion of the third signal line 204, and the first insulating film layer 209. The first through hole H1 exposes the main extension portion of the first signal line 203 away from the surface of the substrate 10. Fig.12 and Fig.13 shown.

[0128] Combination Fig.12 and Fig.13 As shown, in the orthographic projection on the substrate 10 , the first through hole H1 is located in the intersection of the main extension portion of the first signal line 203 and the main extension portion of the third signal line 204 to reduce the difficulty of subsequent connection between the first transistor 201 and the first signal line 203 and the third signal line 204 .

[0129] In step S106, a first transistor 201 is formed in the first through hole H1, a first connection region of the first transistor 201 contacts the main extension portion of the first signal line 203, and a second connection region of the first transistor 201 contacts the main extension portion of the third signal line 204. Fig.14 and Fig.15 shown.

[0130] In step S108 , an interlayer insulating film layer 211 is formed, and the interlayer insulating film layer 211 covers the first transistor 201 and the second insulating film layer 210 .

[0131] In step S110 , a second signal line 205 and a third insulating film layer 212 covering the second signal line 205 are sequentially formed on a side of the interlayer insulating film layer 211 away from the substrate 10 .

[0132] For example, the step of forming the second signal line 205 may specifically include: step S1101 , step S1102 , and step S1103 .

[0133] In step S1101, a plurality of second signal lines 205 spaced apart in a second horizontal direction Y are formed on a side of the interlayer insulating film layer 211 away from the substrate 10, such as Fig.16 shown.

[0134] In step S1102, a third isolation material film 215a is formed. The third isolation material film 215a covers each second signal line 205 and fills between adjacent second signal lines 205. Fig.17 shown.

[0135] In step S1103, the portion of the third isolation material film 215a that is higher than the second signal line 205 is removed, and a third isolation pattern layer 215 is formed. The surface of the second isolation pattern layer 215 away from the substrate 10 is flush with the surface of the second signal line 205 away from the substrate 10, that is, the surface of the second signal line 205 away from the substrate 10 is exposed, and the third isolation pattern layer 215 at least includes a second isolation portion 2151 filled between adjacent second signal lines 205, such as Fig.18 shown.

[0136] After step S1103 is performed, a third insulating film layer 212 is formed to cover the second signal line 205 .

[0137] In step S112, a second through hole H2 is formed that sequentially penetrates the third insulating film layer 212, the second signal line 205, and the interlayer insulating film layer 211. The orthographic projections of the second through hole H2 and the first through hole H1 on the substrate 10 overlap. Fig.19 and Fig. 20 shown.

[0138] In step S114, a second transistor 202 is formed in the second through hole H2, a first connection region of the second transistor 202 is connected to the gate region (i.e., gate portion G) of the first transistor 201, and a second connection region of the second transistor 202 is in contact with the main extension portion of the second signal line 205, such as Fig.21 and Fig. 22 shown.

[0139] For example, in the orthographic projection on the substrate 10 , the second through hole H2 is located in the intersection of the main extension portion of the second signal line 205 and the main extension portion of the fourth signal line 206 to reduce the difficulty of subsequent connection between the second transistor 202 and the second signal line 205 and the fourth signal line 206 .

[0140] For example, in order to achieve connection between the first connection region of the second transistor 202 and the gate region of the first transistor 201 , a conductive contact pad 207 may be formed before forming the second transistor 202 .

[0141] Specifically, after forming the first transistor 201 and before forming the interlayer insulating film layer 211, the manufacturing method also includes: step S107, forming a conductive contact pad 207, the side of the conductive contact pad 207 close to the substrate 10 is in contact with the gate region of the first transistor 201, and the side of the conductive contact pad 207 away from the substrate 10 is in contact with the first connection region of the second transistor 202.

[0142] It should be noted that in order to avoid short-circuiting between the channel portion SD and the gate portion G of the first transistor 201, the conductive contact pad 207 and the channel portion SD of the first transistor 201 are insulated. For example, the side of the channel portion SD away from the substrate 10 is covered by the gate insulating portion GI, and the conductive contact pad 207 is insulated from the channel portion SD of the first transistor 201 through the gate insulating portion GI, or other insulating film layers may also be provided.

[0143] Among them, step S107 may specifically include step S1071, step S1072, step S1073, step S1074, step S1075, step S1076, and step S1077.

[0144] In step S1071 , a first conductive material film 301 and a first sacrificial material film 311 are sequentially formed, and the first conductive material film 301 and the sacrificial material film 311 cover the second insulating film layer 210 and the first transistor 201 .

[0145] For example, the first sacrificial material film 311 may include a stacked film of multiple film layers, such as: a SOC (Spin on carbon) film layer and a SiN (silicon nitride) film layer stacked in sequence, but not limited to this. The first sacrificial material film 311 may also be a single-layer structure, and its material may also include one or more insulating materials such as silicon oxynitride and silicon oxide.

[0146] In step S1072, a first photoresist mask pattern layer 321 is formed on a side of the first sacrificial material film 311 away from the first conductive material film 301. The first photoresist mask pattern layer 321 includes a plurality of first photolithography perforations 3210 arranged in an array in a first horizontal direction X and a second horizontal direction Y. The first photolithography perforations 3210 correspond to the first transistors 201 one by one. Fig.23 shown.

[0147] In step S1073, the first sacrificial material film 311 is patterned using the first photoresist mask pattern layer 321 to form a first sacrificial pattern layer 3110, wherein the first sacrificial pattern layer 3110 includes a plurality of first sacrificial through-holes 31101 disposed at intervals, the first sacrificial through-holes 31101 corresponding to the first photolithography through-holes 3210 one by one, and the first sacrificial through-holes 31101 expose the surface of the first conductive material film 301 away from the substrate 10, as shown in FIG. Fig.24 shown.

[0148] In step S1074 , the first photoresist mask pattern layer 321 is removed, and then a first intermediate mask material film is formed, the first intermediate mask material film covers the surface of the first sacrificial pattern layer 3110 away from the substrate 10 and fills the first sacrificial through hole 31101 .

[0149] In step S1075, a portion of the first intermediate mask material film that is higher than the first sacrificial pattern layer 3110 is removed to form a first intermediate mask pattern layer, wherein the first intermediate mask pattern layer includes a plurality of first intermediate mask blocks 331 that are spaced apart from each other. The first intermediate mask blocks 331 are located in the first sacrificial through-holes 31101, and a surface of the first intermediate mask block 331 that is away from the substrate 10 is flush with a surface of the first sacrificial pattern layer 3110 that is away from the substrate 10, as shown in FIG. Fig.25 shown.

[0150] In other embodiments, the first sacrificial material film 311 may be a plurality of sub-layers stacked in sequence. For example, when the first sacrificial material film 311 is a SOC film layer and a SiN film layer stacked in sequence, the material of the first intermediate mask material film may be SiN, and the SiN above the upper surface of the SOC film layer is removed to achieve reverse silicon nitride deposition. The removal process may be a planarization process, and the removal process may use the SOC film layer as a stop layer, and the planarization process may be chemical mechanical polishing (CMP). However, it is not limited thereto, and the material of the first intermediate mask material film may also be one or more insulating materials such as SiON, SiO2, etc., and the removal process may use other process methods such as etching, etc., and the end point of the removal process may be the entire first sacrificial material film 311 or the upper surface of any sub-layer thereof.

[0151] In step S1076, the first sacrificial pattern layer 3110 is removed, and the first intermediate mask block 331 is retained. Fig.26 shown.

[0152] In step S1077, the first conductive material film 301 is patterned using the first intermediate mask block 331 to form a plurality of conductive contact pads 207 arranged at intervals, and the conductive contact pads 207 correspond to the first transistors 201 one by one, such as Fig. 27 shown.

[0153] After forming the conductive contact pad 207 and before forming the interlayer insulating film layer 211, the manufacturing method may further include:

[0154] A fourth isolation material film 216a is formed on a side of the second insulating film layer 210 away from the substrate. The fourth isolation material film 216a covers each conductive contact pad 207 and fills between adjacent conductive contact pads 207. Fig.28As shown;

[0155] The portion of the fourth isolation material film 216a that is higher than the conductive contact pad 207 is removed to form a fourth isolation pattern layer 216, wherein the surface of the fourth isolation pattern layer 216 away from the substrate 10 is flush with the surface of the conductive contact pad 207 away from the substrate 10, that is, the surface of the conductive contact pad 207 away from the substrate 10 is exposed, and the fourth isolation pattern layer 216 at least includes a fourth isolation portion 2161 filled between adjacent conductive contact pads 207, such as Fig.29 shown.

[0156] In step S116 , a fourth signal line 206 and a fourth insulating film layer 208 covering the fourth signal line 206 are formed on a side of the second transistor 202 away from the substrate 10 . The main extension of the fourth signal line 206 contacts the gate region (ie, gate portion G) of the second transistor 202 .

[0157] It should be noted that, in order to avoid short-circuiting between the channel portion SD and the gate portion G of the second transistor 202, the main extension portion of the fourth signal line 206 is insulated from the channel portion SD of the first transistor 201. For example, the side of the channel portion SD away from the substrate 10 is covered by the gate insulating portion GI, and the main extension portion of the fourth signal line 206 is insulated from the channel portion SD of the second transistor 202 by the gate insulating portion GI, or other insulating film layers may also be provided.

[0158] Based on the foregoing, it can be known that in the present embodiment, the manufacturing methods of the first signal line 203 to the fourth signal line 206 can be the same. Specifically, the steps of forming the first signal line 203 to the fourth signal line 206 can include: first forming a plurality of spaced signal lines (i.e., first forming a conductive pattern layer); then forming an isolation material film, the isolation material film covering each signal line and filling between adjacent signal lines; thereafter, removing the portion of the isolation material film that is higher than the signal line to expose the upper surface of the signal line and form an isolation pattern layer, the surface of the isolation pattern layer away from the substrate is flush with the surface of the signal line away from the substrate, and the isolation pattern layer at least includes an isolation portion filled between adjacent signal lines.

[0159] It should be noted that after forming a plurality of spaced fourth signal lines 206, it is not necessary to remove the portion of the fourth insulating film layer 208 that is higher than the fourth signal line 206, but the present invention is not limited thereto. The portion of the fourth insulating film layer 208 that is higher than the fourth signal line 206 may be removed first in the same manner as the formation of the other first signal lines 203 to the third signal lines 206, and then subsequent production may be performed, such as covering with other insulating film layers or conductive layers, etc., depending on the specific circumstances.

[0160] In this embodiment, the formation of the conductive contact pad 207 and the fourth isolation pattern layer 216 may also be omitted.

[0161] In one embodiment, the method of forming a plurality of spaced-apart first signal lines 203, a third signal line 204, a second signal line 205, and a fourth signal line 206 may be the same. Specifically, the steps of forming a plurality of spaced-apart signal lines (i.e., a conductive pattern layer) may include: step S10, step S11, step S12, step S13, step S14, step S15, step S16, step S17, step S18, and step S19.

[0162] In step 10 , a second conductive material film 401 , a hard mask material film 501 , and a second sacrificial material film 411 are sequentially formed on the substrate 10 .

[0163] The hardness of the hard mask material film 501 may be greater than the hardness of the second sacrificial material film 411 to ensure better alignment for downward etching.

[0164] For example, the hard mask material film 501 may be an amorphous carbon (AC) film, but is not limited thereto, and other materials may also be used. The second sacrificial material film 411 may include multiple layers, such as a SiON film layer, a SOC film layer, and a SiON film layer stacked in sequence, but is not limited thereto, and other insulating materials may also be used, and may also be a single-layer film, which will not be described in detail herein.

[0165] It should be noted that the manufacturing of the hard mask material film 501 may be omitted in this embodiment, depending on the specific situation.

[0166] In step 11, a second photoresist mask pattern layer is formed on a side of the second sacrificial material film 411 away from the substrate 10. The second photoresist mask pattern layer includes a plurality of photoresist mask strips 421 spaced apart in the P direction. Fig.31 shown.

[0167] In step 12, the second sacrificial material film 411 is patterned using a second photoresist mask pattern layer to form a second sacrificial pattern layer, such as Fig.32 As shown, the second sacrificial pattern layer includes a plurality of sacrificial mask strips 4111 spaced apart in the P direction, and the sacrificial mask strips 4111 correspond to the photoresist mask strips 421 one by one.

[0168] In step 13, the second photoresist mask pattern layer is removed, and then an intermediate mask material film 502 covering each sacrificial mask strip 4111 is formed. Fig.32 shown.

[0169] For example, the material of the intermediate mask material film 502 may be SiO 2 , but is not limited thereto, and may also be insulating materials such as SiON and SiN.

[0170] In step 14, a trim mask layer 503 is formed on the side of the intermediate mask material film 502 away from the substrate 10, and the sacrificial mask strip 4111 is formed in its extension direction (for example: Fig.33 At least one edge region of the Q direction) is not covered by the trim mask layer 503, such as Fig.33 shown.

[0171] For example, the trim mask layer 503 may be a photoresist processed by a photolithography process, but is not limited thereto and may be other materials, which will not be described in detail herein.

[0172] In step 15, the trim mask layer 503 is used to remove the portion of the intermediate mask material film 502 that is not covered by the trim mask layer 503, such as Fig.34 As shown, at this time, the portion of the sacrificial mask strip 4111 not covered by the trimming mask layer 503 is exposed, but not limited to this. In this step, in addition to the portion of the intermediate mask material film 502 not covered by the trimming mask layer 503 being removed, the portion of the sacrificial mask strip 4111 not covered by the trimming mask layer 503 can also be removed.

[0173] In step 16, the trimming mask layer 503 is removed, and the intermediate mask material film 502 is patterned to form an intermediate mask pattern layer, which is composed of a plurality of intermediate mask strips 5021 that are disconnected from each other in the P direction. Intermediate mask strips 5021 are formed on opposite sides of each sacrificial mask strip 4111, and the intermediate mask strips 5021 formed on the side surfaces close to each other of two adjacent sacrificial mask strips 4111 are disconnected from each other, that is, two mutually disconnected intermediate mask strips are arranged between two adjacent sacrificial mask strips 4111, and are respectively formed on the side walls of a sacrificial mask strip 4111, such as Fig.35 shown.

[0174] It should be noted that when the intermediate mask material film 502 is patterned, only the intermediate mask material formed on the side wall of the sacrificial mask strip 4111 is retained to form the intermediate mask strip 5021, and the intermediate mask material on the remaining positions (for example: the side of the sacrificial mask strip 4111 away from the substrate 10 and the hard mask material film 501) is removed to disconnect the sacrificial mask strips 4111 from each other.

[0175] In step S17, the sacrificial pattern layer is removed, and the hard mask material film 501 is patterned using the intermediate mask pattern layer to form a hard mask pattern layer. Fig.36 As shown, the hard mask pattern layer includes a plurality of hard mask strips 5011 spaced apart in the P direction, and the hard mask strips 5011 correspond to the intermediate mask strips 5021 one by one.

[0176] In step S18, the intermediate mask strip 5021 is removed, and the second conductive material film 401 is patterned using the hard mask pattern layer to form a conductive pattern layer. Fig.37 As shown, the conductive pattern layer includes a plurality of signal lines 4011 arranged at intervals, and the signal lines 4011 correspond to the hard mask strips 5011 one by one;

[0177] In step S19, the hard mask pattern layer is removed, such as Fig.38 shown.

[0178] It should be noted that, when the signal line 4011 formed by sequentially adopting steps S10, step S11, step S12, step S13, step S14, step S15, step S16, step S17, step S18, and step S19 is the first signal line 203 or the second signal line 205 mentioned above, the P direction can be understood as the second horizontal direction Y mentioned above, and the Q direction can be understood as the first horizontal direction X mentioned above; and when the signal line 4011 formed by sequentially adopting steps S10, step S11, step S12, step S13, step S14, step S15, step S16, step S17, step S18, and step S19 is the third signal line 204 or the fourth signal line 206 mentioned above, the P direction can be understood as the first horizontal direction X mentioned above, and the Q direction can be understood as the second horizontal direction Y mentioned above.

[0179] The length of the trim mask layer 503 used in the step of forming the first signal line 203 in the first horizontal direction X is a first length, the length of the trim mask layer 503 used in the step of forming the second signal line 205 in the first horizontal direction X is a second length, the length of the trim mask layer 503 used in the step of forming the third signal line 203 in the second horizontal direction Y is a third length, and the length of the trim mask layer 503 used in the step of forming the fourth signal line 206 in the second horizontal direction Y is a fourth length.

[0180] Wherein, in the same functional layer 20: when the first surface is the lead-out surface, the second length is greater than the first length, so that the extension length of the second signal line 205 is greater than the extension length of the first signal line 203, and the fourth length is greater than the third length, so that the extension length of the fourth signal line 206 is greater than the extension length of the third signal line 204; or, when the second surface is the lead-out surface, the second length is less than the first length, so that the extension length of the second signal line 205 is less than the extension length of the first signal line 203, and the fourth length is less than the third length, so that the extension length of the fourth signal line 206 is less than the extension length of the third signal line 204.

[0181] Taking the second surface as the lead-out surface as an example, a specific description is given: in the step of forming the first signal line 203 and the second signal line 205, except that the extension length of the trim mask layer 503 in the Q direction in step S14 is different, the other process steps are the same, for example: the extension length of the trim mask layer 503 corresponding to the second signal line 205 in the Q direction is smaller than the extension length of the trim mask layer 503 corresponding to the first signal line 203 in the Q direction, so that the extension length of the second signal line 205 finally formed is smaller than the extension length of the first signal line 203. Similarly, in the step of forming the third signal line 204 and the fourth signal line 206, except that the extension length of the trim mask layer 503 in the P direction in step S14 is different, the other process steps are the same, for example: the extension length of the trim mask layer 503 corresponding to the fourth signal line 206 in the P direction is smaller than the extension length of the trim mask layer 503 corresponding to the third signal line 204 in the P direction, so that the extension length of the fourth signal line 206 finally formed is smaller than the extension length of the third signal line 204.

[0182] For example, the aforementioned conductive material film, hard mask material film 501 and second sacrificial material film 411 can be formed by a deposition process, such as: CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition) and other deposition processes, but not limited to this, and a coating process may also be used, depending on the specific situation.

[0183] For example, the material of the conductive material film mentioned above may be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) and other conductive materials; the insulating material may be one or more of SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), TiO2 (titanium dioxide), SiN (silicon nitride) and other materials.

[0184] It should be noted that when the preparation of the hard mask material film 501 in step S10 is omitted, after removing the sacrificial pattern layer, the second conductive material film 401 may be directly patterned using the intermediate mask pattern layer to form a conductive pattern layer.

[0185] In a specific embodiment, the steps of forming the first through hole H1 and the second through hole H2 may include step S20 , step S21 , step S22 , step S23 , step S24 , step S25 , and step S26 .

[0186] In step S20 , a third sacrificial material film 601 is formed on a side of the stack structure away from the substrate 10 . The stack structure includes a bottom insulating film layer 602 , an intermediate signal line 603 and a top insulating film layer 604 sequentially stacked on the substrate 10 .

[0187] For example, the third sacrificial material film 601 may include multiple film layers, such as: a SiON film layer, a SOC film layer, a SiON film layer, etc. stacked in sequence, but is not limited to this. Other insulating materials may also be used, and it may also be a single-layer film, which will not be described in detail here.

[0188] In step S21, a third photoresist mask pattern layer 605 is formed on a side of the third sacrificial material film 601 away from the substrate 10. The third photoresist mask pattern layer 605 includes a plurality of third photolithography perforations 6051 arranged in an array in the first horizontal direction X and the second horizontal direction Y. Fig.39 shown.

[0189] In step S22, the third sacrificial material film 601 is patterned using the third photoresist mask pattern layer 605 to form a third sacrificial pattern layer 6011, wherein the third sacrificial pattern layer 6011 includes a plurality of third sacrificial through-holes 60111 disposed at intervals, wherein the third sacrificial through-holes 60111 correspond to the third photolithography through-holes 6051 one by one, and the third sacrificial through-holes 60111 expose the surface of the top insulating film layer 604 away from the substrate 10, as shown in FIG. Fig.40 shown.

[0190] In step S23, the third photoresist mask pattern layer 605 is removed, and then an insulating material film 606 is formed. The insulating material film 606 covers the surface of the third sacrificial pattern layer 6011 away from the substrate 10 and fills the third sacrificial through-hole 60111. The portion of the insulating material film 606 located in the third sacrificial through-hole 60111 is a blind groove structure 6061, as shown in FIG. Fig.41 shown.

[0191] For example, the insulating material film 606 may be silicon oxide, but is not limited thereto, and may also be other insulating materials. The insulating material may be formed by an ALD deposition process, but is not limited thereto, and may also be formed by a CVD or other deposition process.

[0192] In step S24, the portion of the insulating material film 606 that is higher than the third sacrificial pattern layer 6011 and the bottom wall of the blind groove structure 6061 are removed, and the side wall of the blind groove structure 6061 is retained to form a target etching hole 60611. Fig.42 As shown, the aperture of the target etched hole 60611 is smaller than the aperture of the third sacrificial through-hole 60111 .

[0193] In step S25, the stacked structure is patterned using the target etched hole 60611 to form a through hole H that penetrates the stacked structure, such as Fig.43 shown.

[0194] In step S26, the third sacrificial pattern layer 6011 and the sidewall of the blind groove structure 6061 on the stacked structure are removed. Fig.43 shown.

[0195] Among them, in the step of forming the through hole H as the first through hole H1, the bottom insulating film layer 602 is the first insulating film layer 209, the intermediate signal line 603 is the third signal line 204, and the top insulating film layer 604 is the second insulating film layer 210; in the step of forming the through hole H as the second through hole H2, the bottom insulating film layer 602 is the interlayer insulating film layer 211, the intermediate signal line 603 is the second signal line 205 or the fourth signal line 206, and the top insulating film layer 604 is the third insulating film layer 212.

[0196] It should be noted that the material of the interlayer insulating film layer mentioned in this embodiment may be one or more of SiO2 (silicon dioxide), A12O3 (aluminum oxide), HfO2 (hafnium dioxide), TiO2 (titanium dioxide), SiN (silicon nitride) and the like.

[0197] In one embodiment, the steps of forming the first transistor 201 and the second transistor 202 both include:

[0198] forming a channel film, wherein the channel film covers a surface of the stack structure away from the substrate 10 and fills a through hole of the stack structure;

[0199] The channel film is patterned to form a channel portion SD located in the through hole, wherein the channel portion SD is in a groove shape, and a surface of a groove sidewall in the channel portion SD away from the substrate 10 is lower than a surface of the stack structure away from the substrate;

[0200] A gate insulating film and a gate electrode film are formed in sequence, the gate insulating film and the gate electrode film cover the surface of the stacked structure away from the substrate 10, the surface of the groove sidewall in the channel portion SD away from the substrate 10, and fill the groove in the channel portion SD, the portion of the gate insulating film located in the through hole is the gate insulating portion GI, a portion of the gate insulating portion GI is located in the groove of the channel portion SD, a portion of the gate insulating portion GI covers the surface of the groove sidewall in the channel portion SD away from the substrate 10, a portion of the gate insulating portion GI located in the groove of the channel portion SD is in a groove shape, a portion of the gate thin film located in the groove of the gate insulating portion GI is the gate portion G, and the groove of the gate insulating portion GI is filled with the gate portion G;

[0201] The gate insulating film and the gate film are removed from the stacked structure, so that the stacked structure, the gate insulating portion GI and the gate portion G are exposed away from the surface of the substrate 10 and are flush with each other to form a transistor located in the through hole.

[0202] Among them, in the step of forming the first transistor 201, the stacked structure includes a first insulating film layer 209, a third signal line 204 and a second insulating film layer 210 stacked in sequence, and the through hole is a first through hole H1; in the step of forming the second transistor 202, the stacked structure includes an interlayer insulating film layer 211, a second signal line 205 and a third insulating film layer 212 stacked in sequence, and the through hole is a second through hole H2.

[0203] For example, the channel film and the gate film may be one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), and ITO (indium tin oxide), which is beneficial to reducing the leakage current of the transistor and reducing the power consumption of the transistor, but is not limited thereto, and may also be other semiconductor materials such as silicon. The material of the gate insulating film may be one or more of SiO2 (silicon dioxide), A12O3 (aluminum oxide), HfO2 (hafnium dioxide), TiO2 (titanium dioxide), SiN (silicon nitride), and the like.

[0204] In this embodiment, the step of forming at least one functional layer 20 on the substrate 10 may specifically include: sequentially forming multiple functional layers 20 on the substrate 10, such as Figures 1 to 3 shown.

[0205] Combination Figure 2 and Figure 3 As shown, in two adjacent functional layers 20: the functional layer 20 away from the substrate 10 is defined as an upper functional layer, and the functional layer 20 close to the substrate 10 is defined as a lower functional layer, and when the second surface is a lead-out surface: the length of the trim mask layer 503 used in the step of forming the first signal line 203 of the upper functional layer in the first horizontal direction X is smaller than the length of the trim mask layer 503 used in the step of forming the second signal line 205 of the lower functional layer in the first horizontal direction X, so that the extension length of the first signal line 203 of the upper functional layer is smaller than the extension length of the second signal line 205 of the lower functional layer, and the length of the trim mask layer 503 used in the step of forming the third signal line 204 of the upper functional layer in the second horizontal direction Y is smaller than the length of the trim mask layer 503 used in the step of forming the fourth signal line 206 of the lower functional layer in the second horizontal direction Y, so that the extension length of the third signal line 204 of the upper functional layer is smaller than the extension length of the fourth signal line 206 of the lower functional layer.

[0206] But not limited to this, when the first surface is a lead-out surface: the length of the trim mask layer 503 used in the step of forming the first signal line 203 of the upper functional layer in the first horizontal direction X is greater than the length of the trim mask layer 503 used in the step of forming the second signal line 205 of the lower functional layer in the first horizontal direction X, so that the extension length of the first signal line 203 of the upper functional layer is greater than the extension length of the second signal line 205 of the lower functional layer, and the length of the trim mask layer 503 used in the step of forming the third signal line 204 of the upper functional layer in the second horizontal direction Y is greater than the length of the trim mask layer 503 used in the step of forming the fourth signal line 206 of the lower functional layer in the second horizontal direction Y, so that the extension length of the third signal line 204 of the upper functional layer is greater than the extension length of the fourth signal line 206 of the lower functional layer.

[0207] It should be noted that after a functional layer 20 is first formed on the substrate 10 and before another functional layer 20 is stacked, an insulating isolation layer 102 can be first formed on the surface of the lower functional layer (the functional layer 20 close to the substrate 10) away from the substrate 10, and then an upper functional layer (the functional layer 20 away from the substrate 10) is made to form electrical isolation between the upper functional layer 20.

[0208] In this embodiment, after the step of forming at least one functional layer 20 on the substrate 10, the manufacturing method further includes:

[0209] A first lead-out structure S1, a third lead-out structure S2, a second lead-out structure S3 and a fourth lead-out structure S4 are formed, extending along the vertical direction Z and spaced apart from each other. Each functional layer 20 corresponds to the first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3 and the fourth lead-out structure S4. Figure 2 and Figure 3 shown.

[0210] For example, with the second surface as the lead-out surface, the first lead-out structure S1 at least penetrates the fourth insulating film layer 208, the third insulating film layer 212, the interlayer insulating film layer 211, the second insulating film layer 210 and the first insulating film layer 209 of the corresponding functional layer 20 to contact the lead-out surface of the lead-out end of the first signal line 203 of the corresponding functional layer 20; the third lead-out structure S2 at least penetrates the fourth insulating film layer 208, the third insulating film layer 212, the interlayer insulating film layer 211 and the second insulating film layer 209 of the corresponding functional layer 20 10, so as to contact the lead-out surface of the lead-out end portion in the third signal line 204 of the corresponding functional layer 20; the second lead-out structure S3 at least penetrates the fourth insulating film layer 208 and the third insulating film layer 212 of the corresponding functional layer 20, so as to contact the lead-out surface of the lead-out end portion in the second signal line 205 of the corresponding functional layer 20; the fourth lead-out structure S4 at least penetrates the fourth insulating film layer 208 of the corresponding functional layer 20, so as to contact the lead-out surface of the lead-out end portion in the fourth signal line 206 of the corresponding functional layer 20.

[0211] For example, the materials of the first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3 and the fourth lead-out structure S4 may be one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0212] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations on the present disclosure. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure shall fall within the scope covered by the patent of the present disclosure.

Claims

1. A semiconductor device, characterized in that: The method comprises a substrate and at least one functional layer, wherein the functional layer comprises: A first signal line and a second signal line are stacked on the substrate in a vertical direction, the second signal line is located on a side of the first signal line away from the substrate, and is insulated from the second signal line by an insulating film layer, and the first signal line and the second signal line both extend in a first horizontal direction, wherein: The first signal line and the second signal line each have a main body extension portion and a lead-out end portion, and in the first signal line and the second signal line: the lead-out end portion is located at least one end of the main body extension portion in the first horizontal direction; The orthographic projections of the main extension portion of the first signal line and the main extension portion of the second signal line on the substrate overlap; The orthographic projections of the lead-out end portion of the first signal line and the lead-out end portion of the second signal line on the substrate do not overlap.

2. The semiconductor device according to claim 1, wherein: In the first signal line and the second signal line: the lead end portion has a first surface close to the substrate and a second surface away from the substrate; Among them, in the first signal line and the second signal line: the direction from the first surface to the second surface or the direction from the second surface to the first surface is the lead-out direction.

3. The semiconductor device according to claim 2, wherein: When the direction from the second surface to the first surface is the lead-out direction, the extension length of the first signal line located in the same functional layer is smaller than the extension length of the second signal line; or When the direction from the first surface to the second surface is the lead-out direction, an extension length of the second signal line located in the same functional layer is smaller than an extension length of the first signal line.

4. The semiconductor device according to claim 2 or 3, characterized in that The functional layer also includes: A third signal line extending in the second horizontal direction, the third signal line is stacked with the first signal line and the second signal line along the vertical direction, and is insulated from the adjacent signal lines by an insulating film layer, the second horizontal direction intersects the first horizontal direction, wherein, The third signal line has a main body extension portion and a lead-out end portion, and the lead-out end portion of the third signal line is located at at least one end of the main body extension portion in the second horizontal direction.

5. The semiconductor device according to claim 4, wherein: The functional layer also includes: A fourth signal line extending in the second horizontal direction, the fourth signal line and the first signal line, the second signal line and the third signal line are stacked in a vertical direction and insulated from adjacent signal lines by an insulating film layer, wherein: The fourth signal line has a main body extension portion and a lead-out end portion, and the lead-out end portion of the fourth signal line is located at at least one end of the main body extension portion in the second horizontal direction; The main body extension portion of the fourth signal line and the main body extension portion of the third signal line have overlapping orthographic projections on the substrate; The orthographic projections of the lead-out end portion of the fourth signal line and the lead-out end portion of the third signal line on the substrate do not overlap.

6. The semiconductor device according to claim 5, wherein: In the functional layer: the third signal line is formed between the first signal line and the second signal line, wherein, In the functional layer: the fourth signal line is formed between the third signal line and the second signal line, or In the functional layer: the fourth signal line is formed on a side of the second signal line away from the third signal line.

7. The semiconductor device according to claim 6, wherein: In the third signal line and the fourth signal line: the lead end portion has a first surface close to the substrate and a second surface away from the substrate; Among them, in the third signal line and the fourth signal line: the direction from the first surface to the second surface or the direction from the second surface to the first surface is the lead-out direction.

8. The semiconductor device according to claim 7, wherein: When the direction from the second surface to the first surface is the lead-out direction, the extension length of the third signal line located in the same functional layer is less than the extension length of the fourth signal line; or When the direction from the first surface to the second surface is the lead-out direction, the extension length of the fourth signal line located in the same functional layer is smaller than the extension length of the third signal line.

9. The semiconductor device according to claim 7, wherein: It also includes a first lead-out structure, a second lead-out structure, a third lead-out structure and a fourth lead-out structure which are spaced apart from each other, wherein the first lead-out structure to the fourth lead-out structure all extend in a vertical direction and have different extension lengths; One end of the first lead-out structure contacts the lead-out end of the first signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the second lead-out structure contacts the lead-out end of the second signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the third lead-out structure contacts the lead-out end of the third signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the fourth lead-out structure contacts the lead-out end of the fourth signal line, and the other end extends along the lead-out direction and penetrates through each insulating film layer; Each functional layer corresponds to the first lead-out structure, the second lead-out structure, the third lead-out structure and the fourth lead-out structure.

10. The semiconductor device according to claim 9, wherein: When the direction from the second surface to the first surface is the lead-out direction, the lead-out structure contacts the first surface of the lead-out end portion corresponding thereto; or When the direction from the first surface to the second surface is the lead-out direction, the lead-out structure contacts the second surface of the corresponding lead-out structure.

11. The semiconductor device according to claim 7, wherein: The functional layers are provided in multiple layers and are sequentially stacked on the substrate along a vertical direction, wherein in two adjacent functional layers: When the direction from the second surface to the first surface is the lead-out direction, the extension length of the first signal line of the functional layer far from the substrate is greater than the extension length of the second signal line of the functional layer close to the substrate, and the length of the third signal line of the functional layer far from the substrate is greater than the length of the fourth signal line in the functional layer close to the substrate; or When the direction from the first surface to the second surface is the lead-out direction, the extension length of the first signal line of the functional layer away from the substrate is smaller than the extension length of the second signal line of the functional layer close to the substrate, and the length of the third signal line of the functional layer away from the substrate is smaller than the length of the fourth signal line in the functional layer close to the substrate.

12. The semiconductor device according to claim 6, wherein: The functional layer further includes a first transistor and a second transistor sequentially stacked in a vertical direction, and the first transistor and the second transistor each include a gate region, a first connection region, and a second connection region; Among them, the first connection area of ​​the first transistor is connected to the main body extension part of the first signal line, the second connection area of ​​the first transistor is connected to the main body extension part of the third signal line, the first connection area of ​​the second transistor is connected to the gate area of ​​the first transistor, the second connection area of ​​the second transistor is connected to the main body extension part of the second signal line, and the gate area of ​​the second transistor is connected to the main body extension part of the fourth signal line.

13. The semiconductor device according to claim 12, wherein: In the functional layer: the fourth signal line is formed on a side of the second signal line away from the third signal line, and the first transistor and the second transistor both include: a channel portion, the channel portion comprising the first connection region, the second connection region, and a channel region located between the first connection region and the second connection region, wherein the second connection region is located on a side of the channel region away from the first connection region; The gate portion is insulated from the channel portion by a gate insulating portion, the gate portion and the channel portion are arranged opposite to each other at least in a horizontal direction, and the gate portion includes the gate region.

14. The semiconductor device according to claim 13, wherein: The first connection region of the first transistor is formed between the gate portion thereof and the main body extension portion of the first signal line, and the channel region and the second connection region of the first transistor are both arranged around the gate portion thereof; The first connection region of the second transistor is formed between the gate portion of the second transistor and the gate portion of the first transistor, and the channel region and the second connection region of the second transistor are both arranged around the gate portion of the second transistor.

15. The semiconductor device according to claim 14, wherein: The main body extension portion of the third signal line is arranged around the second connection area of ​​the first transistor; The main body extension portion of the second signal line is disposed around the second connection region of the second transistor.

16. The semiconductor device according to claim 14, wherein: A conductive contact pad is formed between the first connection region of the second transistor and the gate portion of the first transistor; The orthographic projections of the gate portions of the first transistor and the second transistor on the substrate overlap with the orthographic projections of the conductive contact pad on the substrate.

17. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: providing a substrate; and At least one functional layer is formed on the substrate, wherein the step of forming the functional layer comprises: forming a first signal line and a first insulating film layer covering the first signal line on the substrate, wherein the first signal line extends in a first horizontal direction; A second signal line extending in a first horizontal direction is formed on a side of the first insulating film layer away from the substrate; wherein The first signal line and the second signal line each have a main body extension portion and a lead-out end portion, and in the first signal line and the second signal line: the lead-out end portion is located at least one end of the main body extension portion in the first horizontal direction; The orthographic projections of the main extension portion of the first signal line and the main extension portion of the second signal line on the substrate overlap; The orthographic projections of the lead-out end portion of the first signal line and the lead-out end portion of the second signal line on the substrate do not overlap.

18. The manufacturing method according to claim 17, characterized in that: The step of forming the functional layer further comprises: Before forming the second signal line: forming a third signal line, a second insulating film layer, a fourth signal line and a third insulating film layer in sequence on a side of the first insulating film layer away from the substrate, the third signal line and the fourth signal line both extend in a second horizontal direction, the third signal line and the fourth signal line are insulated from each other by the second insulating film layer, and the fourth signal line and the second signal line are insulated from each other by the third insulating film layer; or Before forming the second signal line: a third signal line and a second insulating film layer are sequentially formed on a side of the first insulating film layer away from the substrate; after forming the second signal line: a third insulating film layer and a fourth signal line are sequentially formed, the third signal line and the fourth signal line both extend in a second horizontal direction, the third signal line and the second signal line are insulated from each other by the second insulating film layer, and the second signal line and the fourth signal line are insulated from each other by the third insulating film layer; Wherein, the third signal line and the fourth signal line both have a main body extension portion and a lead-out end portion, and in the third signal line and the fourth signal line: the lead-out end portion is located at least one end of the main body extension portion in the first horizontal direction; The main body extension portion of the third signal line and the main body extension portion of the fourth signal line have overlapping orthographic projections on the substrate; The orthographic projections of the lead-out end portion of the third signal line and the lead-out end portion of the fourth signal line on the substrate do not overlap.

19. The manufacturing method according to claim 18, characterized in that: In the first signal line, the second signal line, the third signal line and the fourth signal line: the lead-out end has a first surface close to the substrate and a second surface away from the substrate, and the direction from the first surface to the second surface or the direction from the second surface to the first surface is the lead-out direction.

20. The manufacturing method according to claim 19, characterized in that: The steps of forming the first signal line, the second signal line, the third signal line and the fourth signal line each include: Forming a stacked conductive material film, a sacrificial material film and a photoresist mask pattern layer in sequence on a substrate, wherein the photoresist mask pattern layer comprises a plurality of photoresist mask strips arranged at intervals; The sacrificial material film is patterned by using the photoresist mask pattern layer to form a sacrificial pattern layer, wherein the sacrificial pattern layer comprises a plurality of sacrificial mask strips arranged at intervals, and the sacrificial mask strips correspond one to one to the photoresist mask strips; Removing the photoresist mask pattern layer, and then forming an intermediate mask material film covering each of the sacrificial mask strips; forming a trimming mask layer on a side of the intermediate mask material film away from the substrate, wherein at least one edge region of the sacrificial mask strip in its extending direction is not covered by the trimming mask layer; Using the trim mask layer to remove the portion of the intermediate mask material film that is not covered by the trim mask layer; The trimming mask layer is removed, and then the intermediate mask material film is patterned to form an intermediate mask pattern layer, wherein the intermediate mask pattern layer is composed of a plurality of mutually disconnected intermediate mask strips, wherein the intermediate mask strips are formed on two opposite sides of each sacrificial mask strip, and the intermediate mask strips formed on the sides close to each other of two adjacent sacrificial mask strips are disconnected from each other; The sacrificial pattern layer is removed, and the conductive material film is patterned using the intermediate mask pattern layer to form a conductive pattern layer, wherein the conductive pattern layer includes a plurality of signal lines arranged at intervals, and the signal lines correspond to the intermediate mask strips one by one; The intermediate mask pattern layer is removed.

21. The manufacturing method according to claim 20, characterized in that: The step of forming the first signal line, the second signal line, the third signal line and the fourth signal line further includes: after forming the conductive material film on the substrate and before forming the sacrificial material film, forming a hard mask material film, the hardness of the hard mask material film being greater than the hardness of the sacrificial material film; Wherein, the step of patterning the conductive material film using the intermediate mask pattern layer to form a conductive pattern layer includes: Using the intermediate mask pattern layer to pattern the hard mask material film to form a hard mask pattern layer, wherein the hard mask pattern layer includes a plurality of hard mask strips arranged at intervals, and the hard mask strips correspond to the intermediate mask strips one by one; The intermediate mask strip is removed, and the conductive material film is patterned using the hard mask pattern layer to form a conductive pattern layer.

22. The manufacturing method according to claim 20, characterized in that: After forming the conductive pattern layer, the manufacturing method further comprises: forming an isolation material film, wherein the isolation material film covers each of the signal lines and fills between adjacent signal lines; The portion of the isolation material film that is higher than the signal line is removed to form an isolation pattern layer, wherein the surface of the isolation pattern layer away from the substrate is flush with the surface of the signal line away from the substrate, and the isolation pattern layer at least includes an isolation portion filled between adjacent signal lines.

23. The manufacturing method according to claim 20, characterized in that: The length of the trim mask layer used in the step of forming the first signal line in the first horizontal direction is a first length, the length of the trim mask layer used in the step of forming the second signal line in the first horizontal direction is a second length, the length of the trim mask layer used in the step of forming the third signal line in the second horizontal direction is a third length, and the length of the trim mask layer used in the step of forming the fourth signal line in the second horizontal direction is a fourth length; wherein, in the same functional layer: When the first surface is the lead-out surface, the second length is greater than the first length, so that the extension length of the second signal line is greater than the extension length of the first signal line, and the fourth length is greater than the third length, so that the extension length of the fourth signal line is greater than the extension length of the third signal line; or When the second surface is the lead-out surface, the second length is smaller than the first length so that the extension length of the second signal line is smaller than the extension length of the first signal line, and the fourth length is smaller than the third length so that the extension length of the fourth signal line is smaller than the extension length of the third signal line.

24. The manufacturing method according to claim 20, characterized in that: The step of forming at least one functional layer on the substrate comprises: A plurality of functional layers are stacked sequentially on the substrate, wherein in two adjacent functional layers: the functional layer far from the substrate is defined as an upper functional layer, and the functional layer close to the substrate is defined as a lower functional layer; wherein, When the first surface is the lead-out surface: the length of the trim mask layer used in the step of forming the first signal line of the upper functional layer in the first horizontal direction is greater than the length of the trim mask layer used in the step of forming the second signal line of the lower functional layer in the first horizontal direction, so that the extension length of the first signal line of the upper functional layer is greater than the extension length of the second signal line of the lower functional layer, and the length of the trim mask layer used in the step of forming the third signal line of the upper functional layer in the second horizontal direction is greater than the length of the trim mask layer used in the step of forming the fourth signal line of the lower functional layer in the second horizontal direction, so that the extension length of the third signal line of the upper functional layer is greater than the extension length of the fourth signal line of the lower functional layer; or When the second surface is the lead-out surface: the length of the trim mask layer used in the step of forming the first signal line of the upper functional layer in the first horizontal direction is smaller than the length of the trim mask layer used in the step of forming the second signal line of the lower functional layer in the first horizontal direction, so that the extension length of the first signal line of the upper functional layer is smaller than the extension length of the second signal line of the lower functional layer; the length of the trim mask layer used in the step of forming the third signal line of the upper functional layer in the second horizontal direction is smaller than the length of the trim mask layer used in the step of forming the fourth signal line of the lower functional layer in the second horizontal direction, so that the extension length of the third signal line of the upper functional layer is smaller than the extension length of the fourth signal line of the lower functional layer.

25. The manufacturing method according to claim 19, characterized in that: After the step of forming at least one functional layer on the substrate, the manufacturing method further comprises: A first lead-out structure, a second lead-out structure, a third lead-out structure and a fourth lead-out structure are formed which extend in the vertical direction and are spaced apart from each other, and each functional layer corresponds to the first lead-out structure, the second lead-out structure, the third lead-out structure and the fourth lead-out structure, wherein: One end of the first lead-out structure contacts the lead-out end of the first signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the second lead-out structure contacts the lead-out end of the second signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the third lead-out structure contacts the lead-out end of the third signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the fourth lead-out structure contacts the lead-out end portion of the fourth signal line, and the other end extends along the lead-out direction and penetrates through each insulating film layer.

26. The manufacturing method according to claim 18, characterized in that: The fourth signal line is formed on a side of the second signal line away from the substrate; Wherein, after forming the second insulating film layer and before forming the second signal line, the step of forming the functional layer further includes: forming a first through hole sequentially penetrating the second insulating film layer, the main body extension portion of the third signal line, and the first insulating film layer, wherein the first through hole exposes a surface of the main body extension portion of the first signal line away from the substrate; forming a first transistor in the first through hole, wherein a first connection region of the first transistor contacts the main body extension portion of the first signal line, and a second connection region of the first transistor contacts the main body extension portion of the third signal line; forming an interlayer insulating film layer, wherein the interlayer insulating film layer covers the first transistor and the second insulating film layer and is located on a side of the second signal line close to the substrate; Wherein, after forming the third insulating film layer and before forming the fourth signal line, the step of forming the functional layer further includes: forming a second through hole sequentially penetrating the third insulating film layer, the second signal line and the interlayer insulating film layer, wherein the second through hole overlaps with the orthographic projection of the first through hole on the substrate; forming a second transistor in the second through hole, wherein a first connection region of the second transistor is connected to a gate region of the first transistor, a second connection region of the second transistor is in contact with a main body extension portion of the second signal line, and a main body extension portion of the fourth signal line formed subsequently is in contact with the gate region of the second transistor; Wherein, after forming the fourth signal line, the step of forming the functional layer further includes: A fourth insulating film layer is formed to cover the fourth signal line.

27. The manufacturing method according to claim 26, characterized in that: The steps of forming the first through hole and the second through hole may both include: forming a sacrificial material film on a side of the stacked structure away from the substrate, wherein the stacked structure comprises a bottom insulating film layer, an intermediate signal line and a top insulating film layer sequentially stacked on the substrate; Forming a photoresist mask pattern layer on a side of the sacrificial material film away from the substrate, the photoresist mask pattern layer comprising a plurality of photolithography perforations arranged in an array in a first horizontal direction and a second horizontal direction; The sacrificial material film is patterned by using the photoresist mask pattern layer to form a sacrificial pattern layer, wherein the sacrificial pattern layer includes a plurality of sacrificial through-holes arranged at intervals, the sacrificial through-holes correspond to the photolithography through-holes one by one, and the sacrificial through-holes expose the surface of the top insulating film layer away from the substrate; The photoresist mask pattern is removed, and then an insulating material film is formed, the insulating material film covers the surface of the sacrificial pattern layer away from the substrate and fills the sacrificial through-hole, and the portion of the insulating material film located in the sacrificial through-hole is a blind groove structure; Removing a portion of the insulating material film that is higher than the sacrificial pattern layer and a bottom wall of the blind groove structure, and retaining a side wall of the blind groove structure to form a target etching hole, wherein the aperture of the target etching hole is smaller than the aperture of the sacrificial through hole; Performing patterning on the stacked structure using the target etched hole to form a through hole penetrating the stacked structure; removing the sacrificial pattern layer and the sidewall of the blind groove structure on the stacked structure; Among them, in the step of forming the first through hole, the bottom insulating film layer is the first insulating film layer, the intermediate signal line is the third signal line, and the top insulating film layer is the second insulating film layer; in the step of forming the second through hole, the bottom insulating film layer is the interlayer insulating film layer, the intermediate signal line is the second or fourth signal line, and the top insulating film layer is the third insulating film layer.

28. The manufacturing method according to claim 26, characterized in that: The steps of forming the first transistor and the second transistor both include: forming a channel film, wherein the channel film covers a surface of the stack structure away from the substrate and fills a through hole of the stack structure; The channel film is patterned to form a channel portion located in the through hole, wherein the channel portion is in a groove shape, and a surface of a groove sidewall in the channel portion away from the substrate is lower than a surface of the stacked structure away from the substrate, the channel portion includes the first connection area, the second connection area, and a channel area located between the first connection area and the second connection area, and the second connection area is located on a side of the channel area away from the first connection area; A gate insulating film and a gate electrode film are sequentially formed, wherein the gate insulating film and the gate electrode film cover the surface of the stack structure away from the substrate, the surface of the sidewall of the groove in the channel portion away from the substrate, and fill the groove in the channel portion, a portion of the gate insulating film located in the through hole is a gate insulating portion, a portion of the gate insulating portion is located in the groove of the channel portion, and a portion of the gate insulating portion covers the surface of the sidewall of the groove in the channel portion away from the substrate, a portion of the gate insulating portion located in the groove of the channel portion is in a groove shape, a portion of the gate thin film located in the groove of the gate insulating portion is a gate portion, the gate portion includes the gate region, and the groove of the gate insulating portion is filled with the gate portion; Removing the gate insulating film and the gate film portions that are higher than the stack structure, so that the stack structure, the gate insulating portion and the gate portion are exposed away from the surface of the substrate and are flush with each other, so as to form a transistor located in the through hole; Among them, in the step of forming the first transistor, the stacked structure includes the first insulating film layer, the third signal line and the second insulating film layer stacked in sequence, and the through hole is a first through hole; in the step of forming the second transistor, the stacked structure includes the interlayer insulating film layer, the second signal line and the third insulating film layer stacked in sequence, and the through hole is a second through hole.

29. The manufacturing method according to claim 26, characterized in that: After forming the first transistor and before forming the interlayer insulating film layer, the manufacturing method further includes: A conductive contact pad is formed, wherein a side of the conductive contact pad close to the substrate contacts the gate region of the first transistor, and a side of the conductive contact pad away from the substrate contacts the first connection region of the second transistor.

30. The manufacturing method according to claim 29, characterized in that: The step of forming the conductive contact pad comprises: forming a conductive material film and a sacrificial material film in sequence, wherein the conductive material film and the sacrificial material film cover the second insulating film layer and the first transistor; forming a photoresist mask pattern layer on a side of the sacrificial material film away from the conductive material film, wherein the photoresist mask pattern layer comprises a plurality of photolithographic perforations arranged in an array in a first horizontal direction and a second horizontal direction, and the photolithographic perforations correspond one to one to the first transistors; The sacrificial material film is patterned by using the photoresist mask pattern layer to form a sacrificial pattern layer, wherein the sacrificial pattern layer includes a plurality of sacrificial through-holes arranged at intervals, the sacrificial through-holes correspond to the photolithography through-holes one by one, and the sacrificial through-holes expose the surface of the conductive material film away from the substrate; The photoresist mask pattern layer is removed, and then an intermediate mask material film is formed, wherein the intermediate mask material film covers the surface of the sacrificial pattern layer away from the substrate and fills the sacrificial through-hole; Removing a portion of the intermediate mask material film that is higher than the sacrificial pattern layer to form an intermediate mask pattern layer, wherein the intermediate mask pattern layer comprises a plurality of intermediate mask blocks that are spaced apart from each other, the intermediate mask blocks are located in the sacrificial through-holes, and a surface of the intermediate mask block away from the substrate is flush with a surface of the sacrificial pattern layer away from the substrate; removing the sacrificial pattern layer and retaining the intermediate mask block; The conductive material film is patterned by using the intermediate mask block to form a plurality of conductive contact pads arranged at intervals, wherein the conductive contact pads correspond to the first transistors one by one.

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