Semiconductor device, memory device, and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device capable of achieving miniaturization or high integration. The semiconductor device includes a first layer and a second layer on the first layer, the first layer and the second layer each including a transistor, the transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor on the first oxide, a first insulator disposed so as to cover the first conductor, the second conductor, and the first oxide, and a second insulator on the first insulator. A second oxide disposed between the first conductor and the second conductor on the first oxide; a third insulator on the second oxide; a third conductor on the third insulator; and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor. The first insulator and the fourth insulator are less susceptible to oxygen permeation than the second insulator.

Description

This application is a divisional application of the invention patent application with the invention name “Semiconductor Device”, the international application date of April 16, 2019, and the application number 201980027125.4 (the international application number is PCT / IB2019 / 053094). Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, or storage devices are also a form of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, and electronic devices sometimes include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. One embodiment of the invention disclosed in this specification, etc., relates to an object, method, or manufacturing method. In addition, one embodiment of the present invention relates to a process, machine, product, or composition of matter. Background Art

[0004] As semiconductor thin films that can be applied to transistors, silicon-based semiconductor materials are widely known. In addition, as other materials, oxide semiconductors have attracted attention. As oxide semiconductors, for example, it is known that in addition to unit metal oxides such as indium oxide and zinc oxide, there are also multinary metal oxides. Among multinary metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly hot.

[0005] Through the study of IGZO, CAAC (c-axis aligned crystalline: c-axis oriented crystal) structure and nc (nanocrystalline: nanocrystalline) structure, which are neither single crystal nor amorphous, were discovered in oxide semiconductors (see non-patent documents 1 to 3). Non-patent documents 1 and 2 disclose a technology for manufacturing transistors using an oxide semiconductor having a CAAC structure. Furthermore, non-patent documents 4 and 5 disclose an oxide semiconductor having a lower crystallinity than a CAAC structure and a nc structure and also having tiny crystals.

[0006] A transistor using IGZO for an active layer has an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic are known (Non-Patent Documents 7 and 8). [Prior technical literature] [Non-patent literature]

[0007] [Non-patent document 1] S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 [Non-patent document 3] S. Ito et al., "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, p.151-154 [Non-patent document 4] S. Yamazaki et al., "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p. Q3012-Q3022 [Non-patent document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p. 155-164 [Non-patent document 6] K.Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-patent document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217 [Non-patent document 8] S.Amano et al., "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p.626-629 Summary of the invention Technical problem to be solved by the invention

[0008] One of the purposes of one embodiment of the present invention is to provide a semiconductor device that can achieve miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with high frequency characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with good reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with a small off-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with high productivity.

[0009] One of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a fast data writing speed. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a high degree of design freedom. One of the purposes of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device.

[0010] Note that the recording of the above-mentioned purpose does not prevent the existence of other purposes. In addition, one mode of the present invention does not need to achieve all of the above-mentioned purposes. In addition, the purposes other than these purposes are naturally clear from the records of the specification, drawings, claims, etc., and the purposes other than the above-mentioned purposes can be derived from the records of the specification, drawings, claims, etc. Solutions to technical problems

[0011] One embodiment of the present invention is a semiconductor device, which includes a first layer and a second layer on the first layer, the first layer and the second layer each including a transistor, the transistors in the first layer and the second layer including a first oxide, a first conductor and a second conductor on the first oxide, a first insulator configured in a manner covering the first conductor, the second conductor and the first oxide, a second insulator on the first insulator, a second oxide on the first oxide configured between the first conductor and the second conductor, a third insulator on the second oxide, a third conductor on the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor, wherein the first insulator and the fourth insulator are less likely to allow oxygen to permeate than the second insulator.

[0012] In the semiconductor device, the second oxide preferably has crystallinity. In addition, in the semiconductor device, the second oxide preferably contacts the side surface of the second insulator and includes a region in which the c-axis is oriented in a direction substantially perpendicular to the side surface. In addition, in the semiconductor device, the third oxide is preferably arranged in contact with the second oxide.

[0013] In addition, in the semiconductor device, preferably, a fifth insulator is disposed under the first oxide and the first insulator, a sixth insulator is disposed under the fifth insulator, and the sixth insulator is less likely to allow oxygen to permeate than the fifth insulator. In addition, in the semiconductor device, preferably, a fourth conductor is disposed under the sixth insulator so as to overlap with the first oxide.

[0014] Furthermore, in the above semiconductor device, the first insulator and the fourth insulator are preferably oxides containing one or both of aluminum and hafnium.

[0015] In the above semiconductor device, the first oxide and the second oxide preferably contain In, an element M (M is Al, Ga, Y, or Sn), and Zn.

[0016] Furthermore, in the above semiconductor device, preferably, a third layer is arranged below the first layer, and the third layer includes a seventh insulator on the silicon substrate and a fifth conductor on the seventh insulator. Effects of the Invention

[0017] According to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having good reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having a small off-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having high productivity can be provided.

[0018] In addition, a semiconductor device capable of retaining data for a long period of time can be provided. In addition, a semiconductor device with a fast data writing speed can be provided. In addition, a semiconductor device with a high degree of design freedom can be provided. In addition, a semiconductor device capable of suppressing power consumption can be provided. In addition, a novel semiconductor device can be provided.

[0019] Note that the description of these effects does not prevent the existence of other effects. In addition, one mode of the present invention does not need to have all of the above effects. In addition, effects other than these effects are naturally clear from the description of the specification, drawings, claims, etc., and effects other than the above effects can be derived from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] [ Figure 1 ] A cross-sectional view of a semiconductor device according to one embodiment of the present invention. [ Figure 2 ] A cross-sectional view of a semiconductor device according to one embodiment of the present invention. [FIG. 3] A to D are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [FIG. 4] A and B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [ Figure 5 ] A cross-sectional view of a semiconductor device according to one embodiment of the present invention. [ Figure 6 ] A cross-sectional view of a semiconductor device according to one embodiment of the present invention. [FIG. 7] A to D are a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [FIG. 8] A to D are a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [FIG. 9] A to D are a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [FIG. 10] A to D are a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [FIG. 11] A to D are a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] A to D are a top view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] A to D are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [ Fig.14 ] shows a cross-sectional view of the structure of a storage device according to one embodiment of the present invention. [Figure 15] A and B are cross-sectional views showing the structure of a storage device according to one embodiment of the present invention. [ Fig.16 ] is a block diagram showing the structure of a storage device according to one embodiment of the present invention. [Figure 17] A to H are circuit diagrams showing the structure of a storage device according to one embodiment of the present invention. [Figure 18] A and B are a schematic diagram and a stereoscopic diagram of a semiconductor device according to one embodiment of the present invention. [Figure 19] A to E are schematic diagrams of a storage device according to one embodiment of the present invention. [Figure 20] A to E are diagrams showing an electronic device according to one embodiment of the present invention. [Figure 21] A to C are diagrams showing an electronic device according to one embodiment of the present invention. [Figure 22] A to C are diagrams showing structural examples of a parallel computer, a computer, and a personal computer card according to one embodiment of the present invention. [ Fig.23 ]Cross-sectional TEM image of a transistor according to an embodiment of the present invention. [Figure 24] A and B are cross-sectional TEM images of a transistor according to an embodiment of the present invention. [Figure 25] A and B are diagrams showing the electrical characteristics of a transistor according to an embodiment of the present invention. Modes for Carrying Out the Invention

[0021] The following describes the embodiments with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments.

[0022] In the accompanying drawings, the size, thickness of the layer or the area are sometimes exaggerated for the sake of clarity. Therefore, the present invention is not necessarily limited to the above-mentioned dimensions. In addition, in the accompanying drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the accompanying drawings. For example, in the actual manufacturing process, layers or resist masks are sometimes unintentionally thinned due to treatments such as etching, but for ease of understanding, this is sometimes not reflected in the accompanying drawings. In addition, in the accompanying drawings, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding special reference numerals.

[0023] In addition, in order to facilitate understanding of the invention, in particular, in a top view (also called a plan view) or a perspective view, description of some components may be omitted. In addition, description of some hidden lines may be omitted.

[0024] In addition, in this specification, for the sake of convenience, ordinal numbers such as first and second are added, but they do not indicate the order of processes or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for description. In addition, the ordinal numbers recorded in this specification and the like are sometimes inconsistent with the ordinal numbers used to specify one embodiment of the present invention.

[0025] In this specification, for the sake of convenience, words and phrases such as "upper" and "lower" are used to indicate the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases described in this specification are not limited and can be appropriately replaced according to the situation.

[0026] For example, in this specification, when it is clearly stated that "X is connected to Y", it means the following: X is electrically connected to Y; X is functionally connected to Y; X is directly connected to Y. Therefore, it is not limited to the prescribed connection relationship (for example, the connection relationship shown in the drawings or text, etc.), and the connection relationship other than the connection relationship shown in the drawings or text is also included in the content described in the drawings or text.

[0027] Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films and layers, etc.).

[0028] In addition, the functions of the source and the drain may be interchanged when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification, the source and the drain may be interchanged.

[0029] In addition, in this specification, etc., depending on the structure of the transistor, the actual channel width in the region where the channel is formed (hereinafter, also referred to as the "effective channel width") and the channel width shown in the top view of the transistor (hereinafter, also referred to as the "apparent channel width") are sometimes different. For example, in the case where the gate electrode covers the side of the semiconductor, sometimes because the effective channel width is larger than the apparent channel width, its influence cannot be ignored. For example, in a miniature transistor with a gate electrode covering the side of the semiconductor, sometimes the proportion of the channel formation region formed on the side of the semiconductor increases. In this case, the effective channel width is larger than the apparent channel width.

[0030] In this case, it is sometimes difficult to estimate the effective channel width through actual measurement. For example, to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

[0031] In this specification, when simply describing "channel width", sometimes it refers to the apparent channel width. Alternatively, in this specification, when simply describing "channel width", sometimes it refers to the effective channel width. Note that the values ​​of channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing cross-sectional TEM images, etc.

[0032] Note that the impurities of a semiconductor refer to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. Sometimes, due to the inclusion of impurities, for example, the DOS (Density of States) of the semiconductor becomes higher, the crystallinity decreases, etc. When the semiconductor is an oxide semiconductor, as impurities that change the characteristics of the semiconductor, there are, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case where the semiconductor is an oxide semiconductor, water sometimes also acts as an impurity. In addition, when the semiconductor is an oxide semiconductor, sometimes, for example, oxygen vacancies are generated due to the entry of impurities. In addition, when the semiconductor is silicon, as impurities that change the characteristics of the semiconductor, there are, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0033] Note that in this specification and the like, silicon oxynitride refers to a substance containing more oxygen than nitrogen. Also, silicon nitride oxide refers to a substance containing more nitrogen than oxygen.

[0034] In this specification, etc., “insulator” may be referred to as “insulating film” or “insulating layer”. In addition, “conductor” may be referred to as “conductive film” or “conductive layer”. In addition, “semiconductor” may be referred to as “semiconductor film” or “semiconductor layer”.

[0035] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0036] Note that in this specification, a barrier film refers to a film having a function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, and when the barrier film has conductivity, it may be referred to as a conductive barrier film.

[0037] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS FET or an OS transistor can be referred to as a transistor containing an oxide or an oxide semiconductor.

[0038] Note that in this specification and the like, normally off means that when no potential is applied to the gate or a ground potential is applied to the gate, the current flowing through the transistor per channel width of 1 μm is 1×10 -20 Below A, 1×10 -18 A or less, or 1×10 -16 A or below.

[0039] (Implementation Method 1) Next, a structure and characteristics of a semiconductor device according to one embodiment of the present invention will be described.

[0040] Figure 1 It is a cross-sectional view of a semiconductor device in which layers 10_1 to 10_n (n is a natural number greater than or equal to 2) are stacked in order from the bottom surface. Note that hereinafter, any layer among layers 10_1 to 10_n may be referred to as layer 10 without an ordinal number.

[0041] Each of the layers 10_1 to 10_n includes at least one transistor 20. Figure 1 2 shows that each of the layers 10_1 to 10_n includes one transistor 20, but the present invention is not limited thereto, and the number of transistors included in each layer 10 may be different from each other. In addition, in the layer 10, circuit elements, wirings, electrodes, terminals, etc., such as switches, transistors, capacitors, inductors, resistors, and diodes may be appropriately provided according to the required functions of the semiconductor device.

[0042] like Figure 1As shown, transistor 20 includes insulator 30, insulator 32 on insulator 30, oxide 22a on insulator 32, conductor 28a and conductor 28b on oxide 22a, insulator 34 arranged to cover conductor 28a, conductor 28b and oxide 22a, insulator 36 on insulator 34, oxide 22b arranged between conductor 28a and conductor 28b on oxide 22a, insulator 24 on oxide 22b, conductor 26 on insulator 24, and insulator 38 in contact with the top surface of insulator 36, the top surface of oxide 22b, the top surface of insulator 24, and the top surface of conductor 26. Note that below, oxide 22a and oxide 22b are sometimes referred to as oxide 22 together.

[0043] Here, the conductor 28a and the conductor 28b are used as the source electrode and the drain electrode of the transistor 20, respectively. In addition, the conductor 26 is used as the gate electrode of the transistor 20, and the insulator 24 is used as the gate insulator of the transistor 20. In the transistor 20, the conductor 26, the insulator 24, and the oxide 22b are formed in a self-aligned manner to fill the opening formed by the insulator 36, the insulator 34, the conductor 28a, and the conductor 28b. Thus, the conductor 26 can be arranged reliably in the region between the conductor 28a and the conductor 28b without alignment.

[0044] Here, the insulator 38, the insulator 34, and the insulator 30 preferably have a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (not allowing the oxygen to pass through easily). For example, the insulator 38 and the insulator 34 preferably allow oxygen to pass through less easily than the insulator 30. Also, for example, the insulator 30 preferably allows oxygen to pass through less easily than the insulator 32. As such an insulator having a barrier property to oxygen, for example, an oxide containing one or both of aluminum and hafnium may be used.

[0045] In addition, the insulator 36 preferably contains oxygen that is released by heating. In addition, the insulator 36 is preferably an oxide, and may contain oxygen exceeding the stoichiometric composition. Note that the oxygen released by heating may be referred to as excess oxygen hereinafter.

[0046] Here, the height of the top surface of the insulator 36 is preferably substantially the same as the height of the top surface of the conductor 26, the top surface of the insulator 24, and the top surface of the oxide 22b. In addition, the insulator 36, the conductor 26, the insulator 24, and the oxide 22b are preferably covered by the insulator 38. In addition, the side surface of the insulator 36 is preferably in contact with the side surface of the oxide 22b. By adopting the above structure, the insulator 36 and the conductor 26 can be separated using the insulator 38 and the oxide 22b. As a result, the oxygen contained in the insulator 36 can be prevented from directly diffusing into the conductor 26.

[0047] In addition, the bottom surface of the insulator 36 is preferably in contact with the insulator 34. In addition, the insulator 34 is preferably in contact with the side surface of the oxide 22b, the top surface and side surface of the conductor 28a, the top surface and side surface of the conductor 28b, the side surface of the oxide 22a, and the top surface of the insulator 32. By adopting the above structure, the insulator 36 can be separated from the conductors 28a and 28b using the oxide 22b and the insulator 34. As a result, oxygen contained in the insulator 36 can be prevented from directly diffusing into the conductors 28a and 28b.

[0048] In addition, an insulator 40 may be provided on the insulator 38. Figure 1 In the embodiment, the insulator 30 of the upper layer 10 is provided in contact with the top surface of the insulator 40 in the lower layer 10, but the invention is not limited thereto. Circuit elements, such as switches, transistors, capacitors, inductors, resistors, and diodes, wiring, electrodes, or terminals, etc. may be appropriately provided between the lower layer 10 and the upper layer 10. In addition, a structure may be adopted in which the insulator 38 in the lower layer 10 serves as the insulator 30 in the upper layer 10 without providing the insulator 40.

[0049] The oxide 22a has a channel formation region in the region between the conductor 28a and the conductor 28b, and has a source region and a drain region in the vicinity of the region overlapping with the conductor 28a (conductor 28b) in a manner sandwiching the channel formation region. Sometimes the source region and / or the drain region has a shape protruding toward the inside of the conductor 28a (conductor 28b). In addition, the channel formation region of the transistor 20 is sometimes formed near the interface between the oxide 22a and the oxide 22b and / or in the oxide 22b in addition to the oxide 22a.

[0050] Here, in the transistor 20, a metal oxide used as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used as the oxide 22a and the oxide 22b. For example, as the metal oxide used as the oxide 22a and the oxide 22b, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this way, the off-state current (leakage current) of the transistor using the metal oxide with a wider energy gap is low. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0051] For example, metal oxides such as In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) are preferably used as the oxide 22a and the oxide 22b. In particular, aluminum, gallium, yttrium, or tin is preferably used as the element M. In addition, In-Ga oxide and In-Zn oxide can also be used as the oxide 22a and the oxide 22b.

[0052] Here, the atomic number ratio of the metal oxide used for oxide 22a relative to the element M of In can also be greater than the atomic number ratio of the metal oxide used for oxide 22b relative to the element M of In. In this way, by providing oxide 22b on oxide 22a, it is possible to suppress the diffusion of impurities from the structure formed above oxide 22b into oxide 22a. In addition, by making oxide 22a and oxide 22b contain a common element (as a main component) in addition to oxygen, the defect state density at the interface between oxide 22a and oxide 22b can be reduced. Because the defect state density at the interface between oxide 22a and oxide 22b can be reduced, the effect of interface scattering on carrier conduction is small, so that a high on-state current can be obtained.

[0053] It is preferable that both the oxide 22 a and the oxide 22 b have crystallinity. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 22 a and the oxide 22 b.

[0054] CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction, and the crystal structure has distortion. Distortion refers to the part where the lattice arrangement direction changes between the region where multiple nanocrystals are connected and the region where the lattice arrangement is consistent.

[0055] Nanocrystals are basically hexagonal, but are not limited to regular hexagons, and are sometimes non-regular hexagons. In addition, nanocrystals sometimes have lattice arrangements such as pentagons or heptagons in distortion. In addition, in CAAC-OS, it is difficult to observe clear grain boundaries (also called grain boundaries) even near the distortion. That is, it can be seen that the formation of grain boundaries can be suppressed due to the distortion of the lattice arrangement. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atoms arranged in the ab plane direction or the change in the bonding distance between atoms caused by the substitution of metal elements.

[0056] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M, Zn) layer, the layer can also be expressed as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be expressed as an (In, M) layer.

[0057] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. In addition, the crystallinity of metal oxides is sometimes reduced due to the entry of impurities or the generation of defects, so it can be said that CAAC-OS is a metal oxide with high crystallinity (oxygen vacancies (also called V O Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has heat resistance and high reliability.

[0058] Here, an example of CAAC-OS analyzed using X-ray diffraction (XRD) is described. For example, when the structure of CAAC-OS containing InGaZnO4 crystals is analyzed using the out-of-plane method, a peak sometimes appears near a diffraction angle (2θ) of 31°. Since this peak originates from the (009) plane of the InGaZnO4 crystal, it can be said that the crystals in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction roughly perpendicular to the formed surface or top surface of the CAAC-OS.

[0059] Next, an example of CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a beam diameter of 300nm is incident on a CAAC-OS containing InGaZnO4 crystals in a direction parallel to the sample surface, a diffraction pattern (also called a selected area transmission electron diffraction pattern) may be obtained. The diffraction pattern contains spots arising from the (009) plane of the InGaZnO4 crystals. Therefore, electron diffraction also shows that the crystals contained in the CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction roughly perpendicular to the formed surface or top surface of the CAAC-OS. On the other hand, when an electron beam with a beam diameter of 300nm is incident on the same sample in a direction perpendicular to the sample surface, a ring-shaped diffraction pattern is confirmed. Therefore, it can be said that electron diffraction using an electron beam also shows that the a-axis and b-axis of the crystals contained in the CAAC-OS do not have orientation.

[0060] In a transistor using an oxide semiconductor, if there are impurities and oxygen vacancies in the region where the channel is formed in the oxide semiconductor, the electrical characteristics are prone to change, sometimes reducing reliability. In addition, when there are oxygen vacancies in the region where the channel is formed in the oxide semiconductor or impurities (typically hydrogen) are absorbed by the oxygen vacancies, the transistor tends to become normally-on. When heat treatment is performed without supplying oxygen, there is a concern that oxygen in the oxide semiconductor will be detached to form oxygen vacancies. For example, through heat treatment in the manufacturing process of the transistor, oxygen is sometimes absorbed from the oxide semiconductor into the source electrode and the drain electrode to form oxygen vacancies in the oxide semiconductor.

[0061] In contrast, an insulator containing excess oxygen is provided near the oxide semiconductor, and a structure is adopted in which oxygen can be supplied from the insulator to the oxide semiconductor during heat treatment. However, when a conductor used as a gate, source or drain is arranged in contact with the insulator containing excess oxygen, there is a concern that oxygen contained in the insulator is absorbed by these conductors and is difficult to be supplied to the oxide semiconductor.

[0062] When multiple transistors are stacked as in this embodiment, the transistors in the lower layer are heated in each process of manufacturing the transistors in the upper layer. In other words, the lower the transistor is, the greater the thermal budget. Therefore, in the process of manufacturing the transistors in the upper layer, the oxygen in the insulator that may contain excess oxygen in the lower transistor is absorbed by the conductor and cannot supply oxygen to the oxide semiconductor. At this time, the amount of oxygen supplied to the oxide semiconductor is higher than the amount of oxygen absorbed from the oxide semiconductor. Therefore, even if the oxygen vacancies in the oxide semiconductor are greatly reduced when the transistors in the lower layer are completed, oxygen vacancies are formed in the oxide semiconductor in the manufacturing process of the transistors in the upper layer.

[0063] Here, refer to Figure 2 The behavior of oxygen 50 contained in insulator 36 when heat treatment is performed on transistor 20 according to this embodiment will be described. Figure 2 2 is an enlarged cross-sectional view of transistor 20. As described above, in the semiconductor device shown in this embodiment, insulator 36 containing excess oxygen is surrounded by insulator 38, oxide 22b, and insulator 34 and is separated from conductor 26, conductor 28a, and conductor 28b. Figure 2 As shown, even if the heat treatment is performed, oxygen 50 in insulator 36 is blocked by insulator 38, oxide 22b, and insulator 34 and does not diffuse directly into conductor 26, conductor 28a, and conductor 28b.

[0064] In addition, when oxygen in oxide 22a is released by heat treatment to form oxygen vacancies, oxygen diffuses from oxide 22b into oxide 22a near the interface between oxide 22a and oxide 22b, thereby filling the oxygen vacancies. The oxygen supplied to oxide 22a diffuses in oxide 22a while repeatedly filling the oxygen vacancies in oxide 22a.

[0065] In addition, by supplying oxygen to oxide 22a, oxygen vacancies are also formed in oxide 22b. At this time, oxygen 50 diffuses from insulator 36 to oxide 22b near the interface between insulator 36 and oxide 22b, thereby filling the oxygen vacancies. Oxygen 50 supplied to oxide 22b diffuses in oxide 22b while repeatedly filling oxygen vacancies in oxide 22b.

[0066] Here, the oxide 22b is preferably CAAC-OS. Figure 2 As shown, the oxide 22b includes a crystal layer 22bP extending in the ab plane direction and a crystal region having a c-axis 22bX perpendicular to the ab plane direction. In the oxide 22b, the c-axis 22bX is preferably oriented in a direction substantially perpendicular to the formed surface of the oxide 22b. Thus, the oxide 22b includes a region where the c-axis 22bX is oriented in a direction substantially perpendicular to the top surface of the oxide 22a, a region where the c-axis 22bX is oriented in a direction substantially perpendicular to the side surfaces of the conductor 28a, the insulator 34, and the insulator 36, and a region where the c-axis 22bX is oriented in a direction substantially perpendicular to the side surfaces of the conductor 28b, the insulator 34, and the insulator 36.

[0067] CAAC-OS has the property that oxygen diffuses more easily in the ab-plane direction than in the c-axis direction. Figure 2 As shown, oxygen 50 supplied from insulator 36 to oxide 22 b is preferentially diffused to the vicinity of the interface between oxide 22 b and oxide 22 a , thereby filling oxygen vacancies in oxide 22 b .

[0068] As described above, even if the transistor 20 shown in this embodiment is subjected to heat treatment after completion, the increase of oxygen vacancies in the oxide 22 can be suppressed by supplying oxygen from the insulator 36 to the oxide 22. Therefore, even in the lower layer 10, the variation of the electrical characteristics of the transistor 20 can be suppressed and the electrical characteristics can be stabilized, while the reliability of the transistor 20 can be improved.

[0069] By stacking the layers 10_1 to 10_n including the transistor 20, the occupied area of ​​the semiconductor device described in this embodiment in a plan view can be reduced, and the semiconductor device can be miniaturized or highly integrated.

[0070] According to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having good reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having a small off-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having high productivity can be provided.

[0071] As described above, the structure, method, and the like described in this embodiment can be implemented in combination with the structure, method, and the like described in other embodiments as appropriate.

[0072] (Implementation Method 2) Next, an example of a specific structure of the semiconductor device described in the above embodiment mode will be described with reference to FIGS. 3 to 13 .

[0073] <Structural Example of Semiconductor Device> Figure 3A , Figure 3B , Figure 3C and Figure 3D 1 is a top view and a cross-sectional view of a transistor 200 according to one embodiment of the present invention and the vicinity of the transistor 200. The transistor 200 corresponds to the transistor 20 described in the above embodiment. That is, as described in the above embodiment, the transistor 200 can be stacked.

[0074] Figure 3A 2 is a top view of a semiconductor device including transistor 200. Figure 3B and Figure 3C is a cross-sectional view of the semiconductor device. Figure 3B It is along Figure 3A The cross-sectional view along the dot-dash line A1-A2 in FIG. 1 is equivalent to the cross-sectional view along the channel length direction of the transistor 200. In addition, Figure 3C It is along Figure 3A The cross-sectional view along the dot-dash line A3-A4 in FIG. 1 is equivalent to the cross-sectional view along the channel width direction of the transistor 200. In addition, Figure 3D is Figure 3A A cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. Figure 3A In the top view, some of the components are omitted for clarity.

[0075] A semiconductor device according to one embodiment of the present invention includes a transistor 200, an insulator 214 used as an interlayer film, an insulator 274, an insulator 280, and an insulator 281. In addition, a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 200 and used as a plug is included. In addition, an insulator 241 (insulator 241a and insulator 241b) in contact with the side surface of the conductor 240 used as the plug is included.

[0076] In addition, an insulator 241 is provided in contact with the inner wall of the opening of the insulator 254, the insulator 274, and the insulator 281, and a first conductor of the conductor 240 is provided in contact with the side thereof, and a second conductor of the conductor 240 is provided inside thereof. Here, the height of the top surface of the conductor 240 and the height of the top surface of the insulator 281 may be substantially the same. In addition, in the transistor 200, the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, but the present invention is not limited to this. For example, the conductor 240 may also have a single-layer structure or a stacked structure of three or more layers. In addition, when the structure has a stacked structure, an ordinal number is sometimes assigned in the order of formation to distinguish them.

[0077] [Transistor 200] like Figure 1 As shown, the transistor 200 includes an insulator 214 and an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed in a manner buried in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, oxide 230c1, and oxide 230c2) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, and a conductor disposed on the insulator 250. The conductor 260 (conductor 260a and conductor 260b), conductor 242a and conductor 242b in contact with a portion of the top surface of oxide 230b, insulator 254 arranged to be in contact with a portion of the top surface of insulator 224, the side surface of oxide 230a, the side surface of oxide 230b, the side surface of conductor 242a, the top surface of conductor 242a, the side surface of conductor 242b, and the top surface of conductor 242b, insulator 280 arranged on insulator 254, and insulator 274 arranged on insulator 280. Conductor 260 includes conductor 260a and conductor 260b, and conductor 260a is arranged to surround the bottom surface and side surfaces of conductor 260b. Here, as Figure 3B As shown, the top surface of the conductor 260 is arranged to be substantially consistent with the top surface of the insulator 250, the top surface of the oxide 230c1, the top surface of the oxide 230c2, and the top surface of the insulator 280. In addition, the insulator 274 is in contact with the top surface of each of the conductor 260, the oxide 230c, and the insulator 250. Note that the oxide 230c1 and the oxide 230c2 are sometimes collectively referred to as the oxide 230c below.

[0078] Here, the insulator 214 corresponds to the insulator 30 in the transistor 20 of the above embodiment. In addition, the insulator 224 corresponds to the insulator 32 in the transistor 20 of the embodiment. In addition, the oxide 230b corresponds to the oxide 22a in the transistor 20 of the above embodiment. In addition, the conductor 242a and the conductor 242b correspond to the conductor 28a and the conductor 28b in the transistor 20 of the above embodiment. In addition, the insulator 254 corresponds to the insulator 34 in the transistor 20 of the above embodiment. In addition, the insulator 280 corresponds to the insulator 36 in the transistor 20 of the above embodiment. In addition, the oxide 230c corresponds to the oxide 22b in the transistor 20 of the above embodiment. In addition, the insulator 250 corresponds to the insulator 24 in the transistor 20 of the above embodiment. In addition, the conductor 260 corresponds to the conductor 26 in the transistor 20 of the above embodiment. In addition, the insulator 274 corresponds to the insulator 38 in the transistor 20 of the above embodiment. In addition, the insulator 281 corresponds to the insulator 40 in the transistor 20 of the above embodiment. In addition, the insulator 222 may correspond to the insulator 32 in the transistor 20 of the above embodiment.

[0079] Insulator 280 preferably has a region containing oxygen released by heating. By providing insulator 280 that releases oxygen by heating in contact with oxide 230c1, oxygen in insulator 280 can be efficiently supplied to oxide 230b through oxide 230c1.

[0080] Insulator 222, insulator 254, and insulator 274 preferably have a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). In addition, insulator 222, insulator 254, and insulator 274 preferably have a function of suppressing the diffusion of at least one of hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, the permeability of one or both of oxygen and hydrogen in insulator 222, insulator 254, and insulator 274 is preferably lower than that of insulator 224. The permeability of one or both of oxygen and hydrogen in insulator 222, insulator 254, and insulator 274 is preferably lower than that of insulator 250. The permeability of one or both of oxygen and hydrogen in insulator 222, insulator 254, and insulator 274 is preferably lower than that of insulator 280.

[0081] In addition, if Figure 3B , Figure 3C As shown, the insulator 254 is preferably in contact with the top surface and side surfaces of the conductor 242 a , the top surface and side surfaces of the conductor 242 b , the oxide 230 a and side surfaces of the oxide 230 b , and the top surface of the insulator 224 .

[0082] By adopting the above structure, insulator 274 and oxide 230c can be used to separate insulator 280 from conductor 260. Thus, oxygen contained in insulator 280 can be prevented from directly diffusing into conductor 260. In addition, insulator 280 can be separated from conductors 242a and 242b by oxide 230c and insulator 254. Thus, oxygen contained in insulator 280 can be prevented from directly diffusing into conductors 242a and 242b.

[0083] In addition, the oxide 230 preferably includes an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, and an oxide 230c disposed on the oxide 230b and at least a portion of which is in contact with the top surface of the oxide 230b. In addition, the oxide 230c may have a stacked structure of an oxide 230c1 and an oxide 230c2 in contact with the top surface of the oxide 230c1.

[0084] Note that the transistor 200 is shown here to have a four-layer structure of oxide 230a, oxide 230b, oxide 230c1 and oxide 230c2 stacked in a channel forming region (hereinafter, also referred to as a channel forming region) and its vicinity, but the present invention is not limited to this. For example, it may also have a single-layer structure of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c2, a three-layer structure of oxide 230a, oxide 230b and oxide 230c1, or a stacked structure of five or more layers. In addition, in the transistor 200, the conductor 260 has a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may also have a single-layer structure or a stacked structure of three or more layers.

[0085] Here, the conductor 260 is used as a gate electrode of the transistor, and the conductors 242a and 242b are used as source electrodes or drain electrodes. In the transistor 200, the conductor 260 used as the gate electrode is formed in a self-aligned manner to fill the opening formed by the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be arranged reliably in the region between the conductor 242a and the conductor 242b without alignment. In addition, as Figure 1 As shown, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a.

[0086] Furthermore, the transistor 200 preferably includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, a conductor 205 disposed so as to be buried in the insulator 214 and the insulator 216, and an insulator 222 disposed on the insulator 216 and the conductor 205. Furthermore, the insulator 224 is preferably disposed on the insulator 222.

[0087] In the transistor 200 , a metal oxide used as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230 a , the oxide 230 b , the oxide 230 c 1 , and the oxide 230 c 2 ) including the channel formation region.

[0088] Since the transistor 200 using an oxide semiconductor for the channel formation region has extremely small leakage current (off-state current) in the non-conducting state, a low-power semiconductor device can be provided. In addition, since the oxide semiconductor can be formed by sputtering or the like, it can be used to form the transistor 200 of a highly integrated semiconductor device.

[0089] As the oxide 230, a metal oxide such as In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used. In particular, aluminum, gallium, yttrium, or tin can be used as the element M. In addition, In-Ga oxide and In-Zn oxide can also be used as the oxide 230.

[0090] In addition, in a transistor using an oxide semiconductor, if there are impurities and oxygen vacancies in the region where the channel is formed in the oxide semiconductor, the electrical characteristics are prone to change, sometimes reducing reliability. In addition, when the region where the channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Therefore, it is preferred to reduce the oxygen vacancies in the region where the channel is formed as much as possible. For example, oxygen is supplied to oxide 230b through oxide 230c, etc. to fill the oxygen vacancies. Thus, the change of electrical characteristics is suppressed, so that a transistor with stable electrical characteristics and improved reliability can be provided.

[0091] In addition, when the element (for example, the second element) contained in the conductor 242 (conductor 242a and conductor 242b) provided in contact with the oxide 230 and used as the source electrode or the drain electrode has the function of absorbing oxygen of the oxide 230, a low resistance region may be partially formed between the oxide 230 and the conductor 242 or near the surface of the oxide 230. In this case, in the low resistance region, the impurity (hydrogen, nitrogen, or metal element, etc.) entering the oxygen vacancy is used as a donor, and the carrier density increases. In addition, the hydrogen entering the oxygen vacancy is sometimes referred to as V O H.

[0092] also, Figure 4A Show Figure 3B FIG. 2 is an enlarged view of a portion of the transistor 200 shown in FIG. Figure 4A As shown, a conductor 242 is sometimes provided in contact with the oxide 230, and a region 243 (region 243a and region 243b) is formed as a low resistance region at the interface between the oxide 230 and the conductor 242 and in the vicinity thereof. The oxide 230 includes a region 234 used as a channel formation region of the transistor 200, and a region 231 (region 231a and region 231b) including a part of the region 243 and used as a source region or a drain region. In the following drawings, the same region 243 is sometimes formed even if the region 243 is not shown in an enlarged view or the like.

[0093] In addition, although an example is shown in which regions 243a and 243b are provided in a diffused manner in the depth direction near the conductor 242 of the oxide 230b, the present invention is not limited thereto. Regions 243a and 243b may be formed appropriately according to the required electrical characteristics of the transistor. In the oxide 230, it is sometimes difficult to clearly observe the boundaries of each region. The concentration of the element detected in each region is not limited to changing in stages per region, but may also change gradually in each region.

[0094] like Figure 4A As shown in FIG. 1 , in the transistor 200 of one embodiment of the present invention, the bottom surface of the insulator 274 contacts the top surface of the oxide 230c, and the conductor 260 is separated from the insulator 280. Thus, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductor 260. Figure 4A As shown, in the transistor 200 of one embodiment of the present invention, the side surface of the oxide 230c is in contact with the side surface of the insulator 254, and the conductors 242a and 242b are separated from the insulator 280. Thus, oxygen included in the insulator 280 can be prevented from being absorbed by the conductors 242a and 242b.

[0095] Here, Figure 4B Show Figure 3C An enlarged view of a region of a portion of transistor 200 is shown. Figure 4B It is an enlarged view of a channel formation region in the W width direction of the transistor 200 .

[0096] like Figure 4B As shown, the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is preferably lower than the height of the bottom surface of the oxide 230b, based on the bottom surface of the insulator 224. In addition, when the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230b and the conductor 260 do not overlap is T2, T2 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0097] In this way, the conductor 260 used as the gate electrode covers the side and top surfaces of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250. This structure makes it easy for the electric field of the conductor 260 to act on the entire oxide 230b in the channel formation region. Therefore, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0098] As described above, a semiconductor device including a transistor with a large on-state current can be provided. In addition, a semiconductor device including a transistor with high frequency characteristics can be provided. In addition, a semiconductor device that suppresses the variation of electrical characteristics and realizes stable electrical characteristics and improves reliability can be provided. In addition, a semiconductor device including a transistor with a small off-state current can be provided.

[0099] Next, a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

[0100] The conductor 205 is arranged in a manner overlapping the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably provided in a manner buried in the insulator 214 and the insulator 216. Here, the flatness of the top surface of the conductor 205 is preferably high. For example, the average surface roughness (Ra) of the top surface of the conductor 205 is 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. Thus, the flatness of the insulator 224 formed on the conductor 205 can be improved and the crystallinity of the oxide 230b and the oxide 230c can be improved.

[0101] Here, the conductor 260 is sometimes used as a first gate (also called a top gate) electrode. In addition, the conductor 205 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the Vth of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without linking it with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be made greater than 0V and the off-state current can be reduced. Therefore, compared with when the negative potential is not applied to the conductor 205, when the negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced.

[0102] In addition, if Figure 3A As shown, conductor 205 is preferably larger than region 234 in oxide 230. In particular, Figure 3C As shown, conductor 205 preferably extends to a region outside the end of region 234 in oxide 230 intersecting the channel width direction. That is, conductor 205 and conductor 260 preferably overlap with an insulator outside the side surface of oxide 230 in the channel width direction.

[0103] With the above structure, the channel formation region in the region 234 can be electrically surrounded by the electric field of the conductor 260 serving as the first gate electrode and the electric field of the conductor 205 serving as the second gate electrode.

[0104] In addition, if Figure 3C As shown, the conductor 205 is extended to be used as wiring. However, the present invention is not limited to this, and a conductor used as wiring may be provided under the conductor 205. In addition, it is not necessary to provide a conductor 205 in each transistor. For example, the conductor 205 may be used in common in a plurality of transistors.

[0105] In addition, in the conductor 205, a first conductor is formed in contact with the inner wall of the opening of the insulator 216, and a second conductor is formed inside the conductor 205. Here, the height of the first conductor and the second conductor of the conductor 205 can be substantially the same as the height of the top surface of the insulator 216. Although the first conductor and the second conductor of the conductor 205 are stacked in the transistor 200, the present invention is not limited to this. For example, the conductor 205 may also have a single-layer structure or a stacked structure of three or more layers. In the case where the structure has a stacked structure, an ordinal number is sometimes given in the order of formation to distinguish them.

[0106] In addition, a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (not allowing the above impurities to pass through easily) may be used as the first conductor of the conductor 205. In addition, a conductor having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.) (not allowing the above oxygen to pass through easily) is preferably used. In this specification, "the function of suppressing the diffusion of impurities or oxygen" refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0107] When a conductor having a function of suppressing the diffusion of oxygen is used as the first conductor of the conductor 205, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 205. As the conductor having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Therefore, as the first conductor of the conductor 205, a single layer or a stack of the above conductive materials can be used.

[0108] In addition, as the second conductor of the conductor 205, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.

[0109] The insulator 214 preferably uses an insulating material having a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through easily). In addition, the insulator 214 is preferably used as a blocking insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Therefore, as the insulator 214, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. (not allowing the above impurities to pass through easily).

[0110] For example, silicon nitride or the like is preferably used as the insulator 214. Thus, it is possible to suppress diffusion of impurities such as water or hydrogen from the substrate side closer to the insulator 214 to the transistor 200 side. In addition, it is possible to suppress diffusion of oxygen contained in the insulator 224 or the like to the substrate side closer to the insulator 214. In addition, as the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material may be used.

[0111] In addition, the dielectric constants of the insulators 216, 280, and 281 are preferably lower than that of the insulator 214. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulators 216, 280, and 281, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores may be used as appropriate.

[0112] Insulator 222 and insulator 224 are used as gate insulators.

[0113] Here, in the insulator 224 in contact with the oxide 230, oxygen is preferably removed by heating. In this specification, oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulator 224. By providing the insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0114] Specifically, an oxide material from which a part of oxygen is released by heating is preferably used as the insulator 224. The oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 In addition, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0115] In addition, if Figure 3C As shown, the thickness of the region of the insulator 224 that does not overlap with the insulator 254 and the oxide 230b may be thinner than the thickness of other regions. The region of the insulator 224 that does not overlap with the insulator 254 and the oxide 230b preferably has a thickness sufficient to diffuse the oxygen.

[0116] The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (not allowing the oxygen to pass through easily). For example, the oxygen permeability of the insulator 222 is preferably lower than that of the insulator 224. By making the insulator 222 have a function of suppressing the diffusion of oxygen or impurities, it is preferable to reduce the oxygen contained in the oxide 230 that can diffuse to the insulator 220 side. In addition, the conductor 205 can be suppressed from reacting with the oxygen contained in the insulator 224 and the oxide 230.

[0117] Furthermore, the insulator 222 is preferably used as a blocking insulating film for suppressing impurities such as water and hydrogen from being mixed into the transistor 200 from the substrate side. For example, the hydrogen permeability of the insulator 222 is preferably lower than that of the insulator 224. By surrounding the insulator 224 and the oxide 230 with the insulator 222 and the insulator 254, impurities such as water and hydrogen can be suppressed from entering the transistor 200 from the outside.

[0118] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 222 is formed using such a material, the insulator 222 is used as a layer to suppress the release of oxygen from the oxide 230 or the entry of impurities such as hydrogen into the oxide 230 from the surrounding portion of the transistor 200.

[0119] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. In addition, the insulator may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0120] In addition, as the insulator 222, for example, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) can also be used in a single layer or a stacked layer. When miniaturization and high integration of transistors are carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulator. By using a high-k material as an insulator used as a gate insulator, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0121] In addition, the insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure composed of the same material, and may be a stacked structure composed of different materials.

[0122] The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. When the oxide 230a is provided under the oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed under the oxide 230a into the oxide 230b. When the oxide 230c is provided on the oxide 230b, it is possible to suppress the diffusion of impurities from the structure formed above the oxide 230c into the oxide 230b.

[0123] In addition, as shown in FIG. 3 and the like, the oxide 230c preferably includes an oxide 230c1 and an oxide 230c2 disposed on the oxide 230c1. The oxide 230c1 preferably includes at least one of the metal elements constituting the metal oxide used for the oxide 230b, and more preferably includes all of the above metal elements. Thus, the defect state density at the interface between the oxide 230b and the oxide 230c1 can be reduced.

[0124] In addition, the oxide 230 preferably has a stacked structure of oxides having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M in the constituent elements is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M relative to In is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic number ratio of In relative to the element M is preferably greater than the atomic number ratio of In relative to the element M in the metal oxide used for the oxide 230a. In addition, the oxide 230c can use a metal oxide that can be used for the oxide 230a or the oxide 230b. In addition, when a stacked structure of oxide 230c1 and oxide 230c2 is adopted, the diffusion of In to the side of insulator 250 can be suppressed by making the atomic number ratio of In in the constituent elements of the metal oxide used for oxide 230c2 smaller than the atomic number ratio of In in the constituent elements of the metal oxide used for oxide 230c1.

[0125] In addition, the oxide 230b is preferably crystalline. For example, CAAC-OS is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, it is possible to suppress the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode. Therefore, even if heat treatment is performed, it is possible to suppress the extraction of oxygen from the oxide 230b, so the transistor 200 is also stable to high temperatures or heat accumulation in the manufacturing process.

[0126] In addition, the oxide 230c1 and the oxide 230c2 preferably have crystallinity, and for example, CAAC-OS is preferably used.

[0127] In addition, it is preferable that the conduction band bottom energies of oxide 230a and oxide 230c2 are higher than the conduction band bottom energy of oxide 230b. In other words, the electron affinity of oxide 230a and oxide 230c2 is preferably lower than the electron affinity of oxide 230b.

[0128] Here, in the junction of oxide 230a, oxide 230b, and oxide 230c, the energy level of the conduction band bottom changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom of the junction of oxide 230a, oxide 230b, and oxide 230c continuously changes or continuously joins. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 230a and oxide 230b and the interface between oxide 230b and oxide 230c.

[0129] Specifically, as the oxide 230a, a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] may be used. Furthermore, as the oxide 230b, a metal oxide with In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] may be used. Furthermore, as the oxide 230c, a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:1 [atomic ratio] or Ga:Zn=2:5 [atomic ratio] may be used. In addition, as specific examples of the combination of oxide 230c1 and oxide 230c2, there can be cited a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide, and the like.

[0130] At this time, the main path of the carrier is oxide 230b. By making oxide 230a and oxide 230c have the above structure, the defect state density at the interface between oxide 230a and oxide 230b and the interface between oxide 230b and oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, so that transistor 200 can obtain high on-state current and high frequency characteristics.

[0131] As the oxide 230, a metal oxide used as an oxide semiconductor is preferably used. For example, as the metal oxide that becomes the region 234, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more is preferably used. In this way, by using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0132] Here, refer to Figure 5 and Figure 6The behavior of oxygen 290 included in insulator 280 when heat treatment is performed on transistor 200 according to this embodiment will be described. Figure 5 is an enlarged cross-sectional view of the transistor 200 in the channel length direction. Figure 6 2 is an enlarged cross-sectional view of the transistor 200 in the channel width direction. As described above, in the semiconductor device shown in this embodiment, the insulator 280 containing excess oxygen is surrounded by the insulator 274, the oxide 230c1, the oxide 230c2, and the insulator 254 and is separated from the conductor 260, the conductor 242a, and the conductor 242b. Figure 5 and Figure 6 As shown, even if the heat treatment is performed, oxygen 290 in insulator 280 is blocked by insulator 274, oxide 230c1, oxide 230c2, and insulator 254 and does not diffuse directly into conductor 260, conductor 242a, and conductor 242b.

[0133] In addition, when oxygen in the oxide 230b is released by heat treatment to form oxygen vacancies, oxygen diffuses from the oxide 230c1 to the oxide 230b near the interface between the oxide 230b and the oxide 230c1, thereby filling the oxygen vacancies. The oxygen supplied to the oxide 230b diffuses in the oxide 230b while repeatedly filling the oxygen vacancies in the oxide 230b.

[0134] In addition, by supplying oxygen to oxide 230b, oxygen vacancies are also formed in oxide 230c1. At this time, oxygen 290 diffuses from insulator 280 to oxide 230c1 near the interface between insulator 280 and oxide 230c1, thereby filling the oxygen vacancies. Oxygen 290 supplied to oxide 230c1 diffuses in oxide 230c1 while repeatedly filling oxygen vacancies in oxide 230c. Note that, as Figure 5 and Figure 6 As shown, sometimes the oxygen 290 in the oxide 230c1 diffuses into the oxide 230c2 and is supplied to the oxide 230b through the oxide 230c2.

[0135] Here, the oxide 230c1 is preferably CAAC-OS. Figure 5 and Figure 6As shown, the oxide 230c1 includes a crystal layer 230c1P extending in the ab plane direction and a crystal region having a c-axis 230c1X perpendicular to the ab plane direction. Here, in the oxide 230c1, the c-axis 230c1X is preferably oriented in a direction substantially perpendicular to the formed surface of the oxide 230c1. Thus, the oxide 230c1 includes a region where the c-axis 230c1X is oriented in a direction substantially perpendicular to the top surface of the oxide 230b, a region where the c-axis 230c1X is oriented in a direction substantially perpendicular to the side surfaces of the conductor 242a, the insulator 254, and the insulator 280, and a region where the c-axis 230c1X is oriented in a direction substantially perpendicular to the side surfaces of the conductor 242b, the insulator 254, and the insulator 280. In addition, like the oxide 230c1, the oxide 230c2 is also a CAAC-OS, such as Figure 5 and Figure 6 As shown, the oxide 230c2 may also include a crystal layer 230c2P extending in the ab plane direction and a crystal region having a c-axis 230c2X perpendicular to the ab plane direction.

[0136] CAAC-OS has the property that oxygen diffuses more easily in the ab-plane direction than in the c-axis direction. Figure 5 As shown, oxygen 290 supplied from the insulator 280 to the oxide 230c1 and the oxide 230c2 is preferentially diffused to the vicinity of the interface between the oxide 230c1 and the oxide 230b, and can fill oxygen vacancies in the oxide 230c.

[0137] As described above, even when the transistor 200 described in this embodiment is subjected to heat treatment after completion, oxygen is supplied from the insulator 280 to the oxide 230, thereby suppressing the increase of oxygen vacancies in the oxide 230. Therefore, even in the lower layer of the stacked structure, the transistor 200 can have stable electrical characteristics while suppressing fluctuations in electrical characteristics and improving the reliability of the transistor 200.

[0138] Note that although Figure 5 and Figure 6 Although an example in which oxygen 290 diffuses in oxide 230c1 and oxide 230c2 is shown, the present embodiment is not limited thereto. For example, a structure in which oxygen 290 diffuses only in oxide 230c1 and oxide 230c2 prevents diffusion of oxygen 290 may be adopted. By adopting this structure, absorption of oxygen 290 by conductor 260 can be further reduced.

[0139] Conductors 242 (conductors 242a and 242b) serving as a source electrode and a drain electrode are provided on the oxide 230b. The thickness of the conductor 242 is, for example, greater than or equal to 1 nm and less than or equal to 50 nm, and preferably greater than or equal to 2 nm and less than or equal to 25 nm.

[0140] As the conductor 242, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy containing the above metal elements as a component, or an alloy of the above metal elements in combination. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferable.

[0141] Similar to the insulator 222, the insulator 254 preferably has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) (not allowing the oxygen to pass through easily). For example, the oxygen permeability of the insulator 254 is preferably lower than that of the insulator 224. Figure 3B , Figure 3C As shown, the insulator 254 is preferably in contact with the top surface and side surfaces of the conductor 242a, the top surface and side surfaces of the conductor 242b, the side surfaces of the oxide 230a and the oxide 230b, and the top surface of the insulator 224. With the above structure, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 242a and 242b.

[0142] In addition, if Figure 3D As shown, the side surfaces of the oxides 230a and 230b in the channel width direction of the region overlapping the conductor 242b (conductor 242a) are also covered by the insulator 254. With the above structure, oxygen contained in the insulator 280 can be further prevented from being absorbed by the conductors 242a and 242b.

[0143] Furthermore, it is preferably used as a block insulating film for suppressing impurities such as water and hydrogen from entering the transistor 200 from the insulator 280 side. For example, the insulator 254 preferably has lower hydrogen permeability than the insulator 224.

[0144] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 by a sputtering method in an atmosphere containing oxygen, oxygen can be added to the vicinity of the region where the insulator 224 contacts the insulator 254. Thus, oxygen can be supplied from the region to the oxide 230 through the insulator 224. Here, by making the insulator 254 have a function of suppressing oxygen diffusion to the upper side, oxygen can be prevented from diffusing from the oxide 230 to the insulator 280. In addition, by making the insulator 222 have a function of suppressing oxygen diffusion to the lower side, oxygen can be prevented from diffusing from the oxide 230 to the insulator 216. In this way, oxygen is supplied to the region 234 used as the channel formation region in the oxide 230. Thus, oxygen vacancies in the oxide 230 can be reduced and the normally-on state of the transistor can be suppressed.

[0145] In addition, the insulator 254 may have a multilayer structure with two or more layers. For example, as the insulator 254, a two-layer structure may be formed by forming a first layer by sputtering in an atmosphere containing oxygen, and then forming a second layer by ALD. Since the ALD method is a film forming method with good coverage, disconnection or the like due to unevenness of the first layer can be prevented.

[0146] As the insulator 254, for example, an insulator containing an oxide of one or both of aluminum and hafnium can be formed. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. Alternatively, a nitride with high barrier properties such as silicon nitride can be used as the insulator 254.

[0147] The insulator 250 is used as a gate insulator. The insulator 250 is preferably arranged in contact with the top surface of the oxide 230c. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide with pores. In particular, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred.

[0148] As with the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen when heated. By providing the insulator 250 as a contact with the top surface of the oxide 230c, the region 234 of the oxide 230b can be efficiently supplied with oxygen. As with the insulator 224, it is preferable to reduce the concentration of impurities such as water or hydrogen in the insulator 250. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

[0149] In addition, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 into the conductor 260. By providing a metal oxide that suppresses diffusion of oxygen, oxygen diffusion from the insulator 250 into the conductor 260 is suppressed. In other words, a reduction in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0150] In addition, the metal oxide is sometimes used as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant as the metal oxide. By making the gate insulator have a stacked structure of the insulator 250 and the metal oxide, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0151] Specifically, metal oxides containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate), which are insulators containing oxides of one or both of aluminum and hafnium, are preferably used.

[0152] Although in Figure 1 In the figure, the conductor 260 has a two-layer structure, but may also have a single-layer structure or a stacked-layer structure of three or more layers.

[0153] As the conductor 260a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0154] In addition, when the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 250. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0155] In addition, as the conductor 260b, it is preferable to use a conductive material with tungsten, copper or aluminum as a main component. In addition, since the conductor 260 is also used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material with tungsten, copper or aluminum as a main component can be used. In addition, the conductor 260b can have a laminated structure, for example, it can have a laminated structure of titanium, titanium nitride and the above conductive materials.

[0156] The insulator 280 is preferably provided on the insulator 224, the oxide 230, and the conductor 242 via the insulator 254. The insulator 280 preferably contains oxygen that is released by heating. For example, as the insulator 280, it is preferred to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores. In particular, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferred because they easily form regions containing oxygen that is released by heating.

[0157] In addition, it is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulator 280. In addition, the top surface of the insulator 280 may be planarized.

[0158] The insulator 274 is preferably used as a barrier insulating film for suppressing the infiltration of impurities such as water and hydrogen into the insulator 280 from above, similarly to the insulator 210. For example, the insulator 274 can be an insulator that can be used for the insulator 210, the insulator 254, or the like.

[0159] Insulator 274 preferably has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.) like insulator 222, etc. (making it difficult for the oxygen to permeate). For example, insulator 274 preferably has lower oxygen permeability than insulator 280. Figure 3B and Figure 3C As shown, the insulator 274 is preferably in contact with the top surface of the conductor 260, the top surface of the insulator 250, the top surface of the oxide 230c, and the top surface of the insulator 280. By adopting the above structure, oxygen contained in the insulator 280 can be further prevented from being absorbed by the conductor 260.

[0160] The insulator 274 is preferably used as a block insulating film for suppressing impurities such as water and hydrogen from entering the transistor 200 from the insulator 281 side. For example, the insulator 274 preferably has lower hydrogen permeability than the insulator 280.

[0161] Insulator 274 is preferably formed by sputtering. Insulator 274 is preferably formed by sputtering in an atmosphere containing oxygen. By forming insulator 274 by sputtering, excess oxygen can be added to the vicinity of the region of insulator 280 that contacts insulator 274. Thus, oxygen can be supplied from this region to oxide 230b through oxide 230c. Here, by making insulator 274 have the function of inhibiting oxygen from diffusing upward, oxygen can be prevented from diffusing upward to insulator 280. In addition, by making insulator 254 have the function of inhibiting oxygen from diffusing downward, oxygen can be prevented from diffusing downward from insulator 280. In this way, oxygen is supplied to region 234 of oxide 230b used as a channel formation region. Thus, oxygen vacancies in oxide 230b can be reduced and the normally-on state of the transistor can be suppressed.

[0162] In addition, an insulator 281 used as an interlayer film is preferably provided on the insulator 274. As with the insulator 224 and the like, the concentration of impurities such as water and hydrogen in the insulator 281 is preferably reduced.

[0163] In addition, the conductors 240a and 240b are arranged in the openings formed in the insulators 281, 274, 280, and 254. The conductors 240a and 240b are provided so as to sandwich the conductor 260. In addition, the height of the top surface of the conductors 240a and 240b may be located on the same plane as the top surface of the insulator 281.

[0164] In addition, insulator 241a is provided in contact with the inner wall of the opening of insulator 281, insulator 274, insulator 280, and insulator 254, and the first conductor of conductor 240a is formed in contact with the side thereof. Conductor 242a is located at least a portion of the bottom of the opening, and conductor 240a is in contact with conductor 242a. Similarly, insulator 241b is provided in contact with the inner wall of the opening of insulator 281, insulator 274, insulator 280, and insulator 254, and the first conductor of conductor 240b is formed in contact with the side thereof. Conductor 242b is located at least a portion of the bottom of the opening, and conductor 240b is in contact with conductor 242b.

[0165] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a stacked structure.

[0166] When a laminated structure is used as the conductor 240, a conductive material having a function of inhibiting the penetration of impurities such as water or hydrogen is preferably used as the conductor in contact with the oxide 230a, the oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. In addition, a conductive material having a function of inhibiting the penetration of impurities such as water or hydrogen can also be used in a single layer or a laminated layer. By using this conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed into the conductor 240a and the conductor 240b. In addition, it is possible to prevent impurities such as water or hydrogen from entering the oxide 230 through the conductor 240a and the conductor 240b from the layer above the insulator 281.

[0167] As the insulator 241a and the insulator 241b, an insulator (for example, aluminum oxide or silicon nitride) that can be used for the insulator 254 or the like may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 254, it is possible to suppress impurities such as water or hydrogen from the insulator 280 from being mixed into the oxide 230 through the conductors 240a and 240b. In addition, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0168] Although not shown, the conductor used as wiring may be arranged in contact with the top surface of the conductor 240a and the top surface of the conductor 240b. The conductor used as wiring preferably uses a conductive material with tungsten, copper or aluminum as a main component. In addition, the conductor may have a laminated structure, for example, a laminated structure of titanium, titanium nitride and the above conductive materials. In addition, the conductor may be buried in the opening of the insulator.

[0169] 〈Materials Constituting Semiconductor Devices〉 Hereinafter, constituent materials that can be used for semiconductor devices will be described.

[0170] Substrate As a substrate for forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, etc. can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, etc., or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. can be cited. Furthermore, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate can also be cited, such as an SOI (Silicon On Insulator) substrate, etc. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can be cited. Furthermore, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, etc. can also be cited. Alternatively, a substrate having an element provided on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0171] Insulator Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0172] For example, when miniaturization and high integration of transistors are being carried out, problems such as leakage current may occur due to the thin filming of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. Therefore, it is preferable to select a material according to the function of the insulator.

[0173] In addition, as insulators with a relatively high dielectric constant, gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium can be cited.

[0174] Insulators having a relatively low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide or resin having pores.

[0175] In addition, by surrounding a transistor using an oxide semiconductor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen (insulator 214, insulator 222, insulator 254, insulator 274, etc.), the electrical characteristics of the transistor can be stabilized. As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, and metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride or silicon nitride can be used.

[0176] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by adopting a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, the oxygen vacancies contained in the oxide 230 can be filled.

[0177] Conductors As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy containing the above metal elements as a component, or an alloy combining the above metal elements, etc. For example, it is preferred to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Alternatively, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

[0178] In addition, a plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be used. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.

[0179] In addition, when an oxide is used in the channel formation region of the transistor, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen is preferably used as a conductor used as a gate electrode. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0180] In particular, as a conductor used as a gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in a metal oxide forming a channel. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can also be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen entering from an external insulator can sometimes be captured.

[0181] 《Metal Oxides》 A metal oxide used as an oxide semiconductor is preferably used as the oxide 230. The metal oxide that can be used for the oxide 230 according to the present invention is described below.

[0182] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it preferably contains aluminum, gallium, yttrium or tin. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.

[0183] Here, the case where the metal oxide is an In-M-Zn oxide containing indium, element M and zinc is considered. Note that element M is aluminum, gallium, yttrium or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. Note that as element M, a plurality of the above elements may be combined.

[0184] Note that in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide. Alternatively, a metal oxide containing nitrogen may also be referred to as a metal oxynitride.

[0185] [Structure of Metal Oxide] Oxide semiconductors (metal oxides) are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0186] [Impurities] Here, the influence of each impurity in the metal oxide is described.

[0187] When the metal oxide contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form a carrier. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal as a channel formation region tends to have a normally-on characteristic. Therefore, it is preferred to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide measured by SIMS (the concentration measured by secondary ion mass spectrometry (SIMS)) is 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0188] Hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to generate water, thus sometimes forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to the metal atom. Therefore, a transistor using a metal oxide containing hydrogen tends to have a normally-on characteristic.

[0189] Therefore, it is preferable to reduce the amount of hydrogen in the metal oxide as much as possible. Specifically, the hydrogen concentration in the metal oxide measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3By using a metal oxide in which impurities are sufficiently reduced in a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0190] As a metal oxide for a semiconductor of a transistor, a thin film with high crystallinity is preferably used. By using this thin film, the stability or reliability of the transistor can be improved. As the thin film, for example, a single crystal metal oxide thin film or a polycrystalline metal oxide thin film can be cited. However, forming a single crystal metal oxide thin film or a polycrystalline metal oxide thin film on a substrate requires a process of high temperature or laser heating. Therefore, the cost of the manufacturing process becomes high and the throughput decreases.

[0191] Non-patent Documents 1 and 2 report that In-Ga-Zn oxide (also called CAAC-IGZO) with a CAAC structure was discovered in 2009. Non-patent Documents 1 and 2 report that CAAC-IGZO has c-axis orientation, unclear grain boundaries, and can be formed on a substrate at low temperatures. In addition, it is also reported that transistors using CAAC-IGZO have excellent electrical characteristics and reliability.

[0192] In addition, In-Ga-Zn oxide (called nc-IGZO) with an nc structure was discovered in 2013 (see Non-Patent Document 3). It was reported that the atomic arrangement of nc-IGZO in a tiny region (e.g., a region greater than 1 nm and less than 3 nm) is periodic, and no regularity in crystal orientation is observed between different regions.

[0193] Non-patent literature 4 and non-patent literature 5 show the change of the average crystal size when the thin films of the above-mentioned CAAC-IGZO, nc-IGZO and IGZO with low crystallinity are irradiated with electron beams, respectively. In the IGZO thin film with low crystallinity, crystalline IGZO of about 1 nm can be observed before it is irradiated with an electron beam. Therefore, it is reported here that the existence of a completely amorphous structure (completely amorphous structure) has not been confirmed in IGZO. Furthermore, it is disclosed that the stability of CAAC-IGZO thin films and nc-IGZO thin films relative to electron beam irradiation is higher than that of IGZO thin films with low crystallinity. Therefore, it is preferable to use a CAAC-IGZO thin film or a nc-IGZO thin film as a semiconductor of a transistor.

[0194] Non-patent document 6 discloses that the leakage current of a transistor using metal oxide in the non-conducting state is extremely low. Specifically, the off-state current of the transistor per channel width of 1 μm is yA / μm (10 -24For example, a low-power CPU or the like that utilizes the low leakage current characteristic of a transistor using a metal oxide has been disclosed (see Non-Patent Document 7).

[0195] In addition, there are reports that use transistors using metal oxides to apply the transistors to display devices by taking advantage of their low leakage current characteristics (see non-patent document 8). In a display device, the displayed image is switched dozens of times in 1 second. The number of image switches per 1 second is called the refresh rate. In addition, the refresh rate is sometimes called the drive frequency. Such high-speed screen switching that is difficult for the human eye to recognize is believed to cause eye fatigue. Therefore, a technology has been proposed to reduce the refresh rate of the display device to reduce the number of image rewrites. In addition, the drive with a reduced refresh rate can reduce the power consumption of the display device. This driving method is called idle stop (IDS) drive.

[0196] The discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of transistors using the CAAC structure or metal oxides having the nc structure, the reduction of the cost of the manufacturing process, and the increase of the throughput. In addition, research has been conducted on the application of the transistors to display devices and LSIs by utilizing the low leakage current characteristic of the transistors.

[0197] <Method for Manufacturing Semiconductor Device> Next, refer to Figure 5 to Figure 1 2 Description Figure 1 The method for manufacturing a semiconductor device including a transistor 200 according to the present invention is shown. Figure 5 to Figure 1 2, A in each figure shows a top view. In addition, B in each figure shows a cross-sectional view of a portion along the dashed line A1-A2 in A, which is equivalent to a cross-sectional view in the channel length direction of transistor 200. In addition, C in each figure shows a cross-sectional view of a portion along the dashed line A3-A4 in A, which is equivalent to a cross-sectional view in the channel width direction of transistor 200. In addition, D in each figure shows a cross-sectional view of a portion along the dashed line A5-A6 in A. For the sake of clarity, some components are omitted in the top view of A in each figure and illustrated.

[0198] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition (ALD).

[0199] Note that the CVD method can be divided into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, the CVD method can be divided into a metal CVD (MCVD) method and an organic metal CVD (MOCVD) method according to the source gas used.

[0200] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used, the thermal CVD method is a film forming method that can reduce plasma damage to the object being processed. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation (charge up) due to receiving charges from plasma. At this time, the wiring, electrodes, components, etc. included in the semiconductor device are sometimes damaged due to the accumulated charge. On the other hand, since the above-mentioned plasma damage does not occur in the case of the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during film formation is not generated, so a film with fewer defects can be obtained.

[0201] In addition, the ALD method can utilize the self-regulation as a property of atoms to deposit the atoms of each layer, thereby exerting the effects of being able to form extremely thin films, being able to form films on structures with high aspect ratios, being able to form films with fewer defects such as pinholes, being able to form films with excellent coverage, and being able to form films at low temperatures. In addition, the ALD method also includes the PEALD (Plasma Enhanced ALD) method, which is a film formation method utilizing plasma. By utilizing plasma, film formation can be performed at lower temperatures, so it is sometimes preferred. Note that the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon than films formed using other film formation methods. In addition, quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

[0202] Unlike film-forming methods that deposit particles released from a target material, etc., CVD and ALD are film-forming methods that form films due to reactions on the surface of the object being processed. Therefore, the films formed by CVD and ALD are not easily affected by the shape of the object being processed and have good step coverage. In particular, the film formed by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for situations where the surface of an opening with a high aspect ratio is to be covered. Note that the ALD method has a relatively slow film-forming speed, so it is sometimes preferred to use it in combination with other film-forming methods with a fast film-forming speed, such as the CVD method.

[0203] The CVD method and the ALD method can control the composition of the obtained film by adjusting the flow ratio of the source gas. For example, when the CVD method or the ALD method is used, a film of any composition can be formed by adjusting the flow ratio of the source gas. In addition, for example, when the CVD method and the ALD method are used, a film whose composition continuously changes can be formed by changing the flow ratio of the source gas while forming the film. When the film is formed while changing the flow ratio of the source gas, since the time required for conveying and adjusting the pressure is not required, the film forming time can be shortened compared to the case where the film is formed using multiple film forming chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0204] In this embodiment, silicon nitride is formed by CVD as the insulator 214. Thus, by using an insulator such as silicon nitride, which does not easily allow copper to penetrate, as the insulator 214, even if a metal such as copper that easily diffuses is used as a conductor of a layer (not shown) below the insulator 214, diffusion of the metal to the layer above the insulator 214 can be suppressed.

[0205] Next, an insulator 216 is formed on the insulator 214. The insulator 216 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is formed as the insulator 216 by CVD.

[0206] Next, an opening reaching the insulator 214 is formed in the insulator 216 using a photolithography method. The opening includes, for example, a groove or a slit. In addition, the area where the opening is formed is sometimes referred to as an opening portion. When forming the opening, a wet etching method can be used, but a dry etching method is preferred for micro-machining. As the insulator 214, it is preferable to select an insulator that serves as an etching stop when etching the insulator 216 to form the opening. For example, when silicon oxide is used as the insulator 216 for forming the opening, silicon nitride, aluminum oxide, or hafnium oxide is preferably used as the insulator 214 as the insulator used as the etching stop film.

[0207] In addition, in the photolithography method, the resist is first exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, insulator, etc. into a desired shape. For example, a resist can be exposed using KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. to form a resist mask. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above light. Note that the above mask is not required when an electron beam or an ion beam is used. In addition, when removing the resist mask, a dry etching process such as an ashing process or a wet etching process can be performed, or a wet etching process can be performed after a dry etching process, or a dry etching process can be performed after a wet etching process.

[0208] Alternatively, a hard mask made of an insulator or a conductor can be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film that becomes a hard mask material can be formed on the insulating film that becomes the insulator 216 and a resist mask can be formed thereon, and then the hard mask material is etched to form a hard mask of a desired shape. The etching of the insulating film that becomes the insulator 216 can be performed after removing the resist mask or without removing the resist mask. In the case of the latter, the resist mask sometimes disappears during etching. In addition, the hard mask can also be removed by etching after the etching of the insulating film that becomes the insulator 216. On the other hand, when the hard mask material does not affect the subsequent process or can be used in the subsequent process, the hard mask does not necessarily have to be removed.

[0209] As a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which high-frequency power is applied to one of the parallel plate electrodes. Alternatively, a structure in which multiple different high-frequency powers are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which high-frequency power with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which high-frequency power with different frequencies is applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device or the like can be used.

[0210] After the opening is formed, a conductive film that becomes the first conductor of the conductor 205 is formed. The conductive film preferably includes a conductive barrier film that has the function of suppressing the penetration of impurities and oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, a laminated film of the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film that becomes the first conductor of the conductor 205 can be formed by sputtering, CVD, MBE, PLD, ALD, etc.

[0211] In this embodiment, tantalum nitride or a film of titanium nitride stacked on the tantalum nitride is formed as a conductive film to be the first conductive body of the conductive body 205. By using such a metal nitride as the first conductive body of the conductive body 205, even if a metal that easily diffuses, such as copper, is used as the second conductive body of the conductive body 205, diffusion of the metal from the first conductive body of the conductive body 205 to the outside can be suppressed.

[0212] Next, a conductive film that becomes the second conductive body 205 is formed on the conductive film that becomes the first conductive body 205. This conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as tungsten, copper, or aluminum is formed as the conductive film that becomes the second conductive body 205.

[0213] Next, a portion of the conductive film of the first conductive body 205 and the conductive film of the second conductive body 205 are polished and removed by performing CMP (Chemical Mechanical Polishing) processing, thereby exposing the insulator 216. As a result, the conductive film of the first conductive body 205 and the conductive film of the second conductive body 205 remain only in the opening. Thus, the conductive body 205 including the first conductive body 205 and the second conductive body 205 whose top surface is flat can be formed (see Figure 5 ) In addition, a part of the insulator 216 may be removed by the CMP process.

[0214] The method for forming the insulator 216 and the conductor 205 is not limited to the above method. For example, a conductive film to be the conductor 205 is formed on the insulator 214 and the conductive film is processed by photolithography to form the conductor 205. Then, an insulating film to be the insulator 216 is provided to cover the conductor 205 and a part of the insulating film is removed by CMP until a part of the conductor 205 is exposed to form the conductor 205 and the insulator 216.

[0215] By forming the conductor 205 and the insulator 216 using a CMP process in this manner, the planarity of the top surfaces of the conductor 205 and the insulator 216 can be improved, thereby improving the crystallinity of the CAAC-OS forming the oxide 230 a , the oxide 230 b , and the oxide 230 c in a subsequent step.

[0216] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, it is preferable to form an insulator containing an oxide of one or both of aluminum and hafnium. In addition, as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. When the insulator 222 has a barrier property to hydrogen and water, the hydrogen and water contained in the structure around the transistor 200 can be suppressed from diffusing into the inside of the transistor 200 through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0217] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0218] Next, an insulating film serving as the insulator 224 is formed over the insulator 222. The insulating film serving as the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0219] Next, heat treatment is preferably performed. The heat treatment is performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere or in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere, and then in order to compensate for the oxygen that has been released, the heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher.

[0220] In this embodiment, the treatment is performed at 400° C. for 1 hour in a nitrogen atmosphere, and then continuously at 400° C. for 1 hour in an oxygen atmosphere. By performing this heat treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed.

[0221] Alternatively, heat treatment may be performed after forming the insulator 222. The heat treatment may be performed under the conditions described above.

[0222] Here, in order to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. The plasma treatment containing oxygen preferably uses, for example, a device including a power supply for generating a high-density plasma using microwaves. Alternatively, a power supply for applying RF (Radio Frequency) to one side of the substrate may be included. High-density oxygen radicals can be generated by using high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulator 224 by applying RF to one side of the substrate. Alternatively, after performing a plasma treatment containing an inert gas using such a device, a plasma treatment containing oxygen may be performed to compensate for the detached oxygen. In addition, by appropriately selecting the conditions for the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 may be removed. At this time, heating treatment may not be performed.

[0223] Here, aluminum oxide may be formed on the insulator 224, for example, by sputtering, and the aluminum oxide may be subjected to CMP treatment until it reaches the insulator 224. By performing the CMP treatment, the surface of the insulator 224 may be flattened and the surface of the insulator 224 may be smoothed. By placing the aluminum oxide on the insulator 224 and performing CMP, it is easy to detect the end point of CMP. In addition, sometimes the thickness of the insulator 224 becomes thinner because a part of the insulator 224 is polished by CMP, but the thickness may be adjusted when the insulator 224 is formed. By flattening and smoothing the surface of the insulator 224, it is sometimes possible to prevent the coverage of the oxide formed below from being reduced and to prevent the yield of the semiconductor device from being reduced. In addition, by forming aluminum oxide on the insulator 224 by sputtering, oxygen can be added to the insulator 224, so it is preferred.

[0224] Next, an oxide film that becomes oxide 230a and an oxide film that becomes oxide 230b are sequentially formed on insulator 224. It is preferable to continuously form the oxide films without exposing them to the atmosphere. By forming the oxide films without exposing them to the atmosphere, impurities or moisture from the atmosphere can be prevented from adhering to the oxide film that becomes oxide 230a and the oxide film that becomes oxide 230b, so that the vicinity of the interface between the oxide film that becomes oxide 230a and the oxide film that becomes oxide 230b can be kept clean.

[0225] The oxide film to be the oxide 230 a and the oxide film to be the oxide 230 b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0226] For example, when the oxide film to be the oxide 230a and the oxide film to be the oxide 230b are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. In addition, when the above-mentioned oxide film is formed by sputtering, for example, the above-mentioned In-M-Zn oxide target can be used.

[0227] In particular, when forming the oxide film to be the oxide 230a, part of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas to form the oxide film to be the oxide 230a may be 70% or more, preferably 80% or more, and more preferably 100%.

[0228] In addition, in the case of forming an oxide film that becomes oxide 230b by sputtering, when the film is formed under the condition that the ratio of oxygen contained in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. A transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have a higher field effect mobility. In addition, by forming a film while heating the substrate, the crystallinity of the oxide film can be improved. Note that one embodiment of the present invention is not limited to this. In the case of forming an oxide film that becomes oxide 230b by sputtering, an oxygen-excess oxide semiconductor is formed by forming a film under the condition that the ratio of oxygen contained in the sputtering gas is greater than 30% and less than 100%, preferably 70% or more and less than 100%. A transistor using an oxygen-excess oxide semiconductor in a channel formation region can obtain relatively high reliability.

[0229] In this embodiment, an oxide film that becomes oxide 230a is formed by sputtering using a target material of In:Ga:Zn=1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]) or 1:3:4 [atomic ratio]. In addition, an oxide film that becomes oxide 230b is formed by sputtering using a target material of In:Ga:Zn=4:2:4.1 [atomic ratio]. The above oxide films can be formed by appropriately selecting film formation conditions and atomic ratios according to the characteristics required for oxide 230.

[0230] Here, the insulator 222, the insulator 224, the oxide film to be the oxide 230a, and the oxide film to be the oxide 230b are preferably formed without being exposed to the air. For example, a multi-chamber film formation apparatus can be used.

[0231] Next, heat treatment may be performed. As the conditions for the heat treatment, the above-mentioned heat treatment conditions may be used. By performing the heat treatment, impurities such as water and hydrogen in the oxide film that becomes the oxide 230a and the oxide film that becomes the oxide 230b may be removed. In this embodiment, the treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere, and then the treatment is continuously performed at a temperature of 400°C for 1 hour in an oxygen atmosphere.

[0232] Next, a conductive film to be the conductive layer 242A is formed over the oxide film 232B. The conductive film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0233] Next, the oxide film to be the oxide 230a, the oxide film to be the oxide 230b, and the conductive film to be the conductive layer 242A are processed into island shapes to form the oxide 230a, the oxide 230b, and the conductive layer 242A. In this step, the thickness of the region of the insulator 224 that does not overlap with the oxide 230a may become thinner (see FIG. 7).

[0234] Here, at least a portion of the oxide 230a, the oxide 230b, and the conductor layer 242A overlap with the conductor 205. In addition, the side surfaces of the oxide 230a, the oxide 230b, and the conductor layer 242A are preferably substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the oxide 230a, the oxide 230b, and the conductor layer 242A are substantially perpendicular to the top surface of the insulator 222, it is possible to achieve a small area and a high density when a plurality of transistors 200 are provided. Alternatively, a structure in which the angle formed by the oxide 230a, the oxide 230b, the conductor layer 242A and the top surface of the insulator 222 is relatively small may be adopted. In this case, the angle formed by the side surfaces of the oxide 230a and the oxide 230b and the top surface of the insulator 222 is preferably greater than 60° and less than 70°. By adopting the above-mentioned shape, the coverage of the insulator 273 and the like is improved in the subsequent process, and defects such as voids can be reduced.

[0235] In addition, there is a curved surface between the side surface of the conductor layer 242A and the top surface of the conductor layer 242A. That is, the end of the side surface and the end of the top surface are preferably curved (hereinafter also referred to as rounded). For example, at the end of the conductor layer 242A, the curved surface has a curvature radius of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less. When the end does not have a corner, the coverage of the film in the subsequent film forming process can be improved.

[0236] The oxide film and the conductive film can be processed by photolithography. Dry etching or wet etching can be used for the processing. Dry etching is suitable for micro-processing.

[0237] Next, an insulating film 254A is formed over the insulator 224 , the oxide 230 a , the oxide 230 b , and the conductive layer 242A (see FIG. 8 ).

[0238] As the insulating film 254A, an insulating film having a function of suppressing the permeation of oxygen is preferably used. For example, it is preferable to form an aluminum oxide film by sputtering. By forming the aluminum oxide film by sputtering and using a gas containing oxygen, oxygen can be introduced into the insulator 224. In other words, the insulator 224 can have excess oxygen.

[0239] Next, an insulating film serving as the insulator 280 is formed on the insulating film 254A. The insulating film serving as the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxynitride film can be formed by a PECVD method as the insulating film serving as the insulator 280. Alternatively, for example, a silicon oxide film can be formed by a sputtering method as the insulating film serving as the insulator 280.

[0240] Next, the insulating film to be the insulator 280 is subjected to a CMP process to form an insulator 280A having a flat top surface (see FIG. 8 ).

[0241] Next, a portion of the insulator 280A, a portion of the insulating film 254A, and a portion of the conductive layer 242A are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap with the conductive body 205. The conductive body 242a, the conductive body 242b, the insulator 254, and the insulator 280 are formed from the opening (see FIG. 9).

[0242] In addition, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductor may be processed under different conditions. For example, a part of the insulator 280A may be processed by dry etching, a part of the insulating film 254A may be processed by wet etching, and a part of the conductor layer 242A may be processed by dry etching.

[0243] By performing the above-described dry etching process, impurities caused by etching gas or the like may adhere to or diffuse on the surface or inside of the oxide 230a and the oxide 230b, etc. Examples of the impurities include fluorine and chlorine.

[0244] Cleaning is performed to remove the impurities, etc. The cleaning method includes wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning using a heat treatment, etc., and these cleaning methods may be appropriately combined.

[0245] As wet cleaning, an aqueous solution of oxalic acid, phosphoric acid, hydrofluoric acid or the like diluted with carbonated water or pure water may be used for cleaning. Alternatively, ultrasonic cleaning may be performed using pure water or carbonated water.

[0246] Next, heat treatment may be performed. Heat treatment may be performed under reduced pressure, and the oxide film 230C1 may be continuously formed without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen attached to the surface of the oxide 230b may be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b may be reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is 200° C. (see FIG. 10 ).

[0247] The oxide film 230C1 may be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230C1 may be formed by the same film forming method as the oxide film that becomes the oxide 230a or the oxide film that becomes the oxide 230b, depending on the characteristics required for the oxide film 230C1. In the present embodiment, the oxide film 230C1 is formed by sputtering using a target material having an In:Ga:Zn=4:2:4.1 [atomic ratio].

[0248] In particular, when forming oxide film 230C1, part of the oxygen contained in the sputtering gas may be supplied to oxide 230a and oxide 230b. Therefore, the ratio of oxygen contained in the sputtering gas of oxide film 230C1 may be 70% or more, preferably 80% or more, and more preferably 100%.

[0249] Next, the oxide film 230C2 may be formed continuously by sputtering, CVD, MBE, PLD, ALD, etc. The oxide film 230C2 may be formed by the same film forming method as the oxide film to be the oxide 230a or the oxide film to be the oxide 230b, depending on the characteristics required for the oxide film 230C2. In the present embodiment, the oxide film 230C2 is formed by sputtering using a target material having an In:Ga:Zn=1:3:4 [atomic ratio].

[0250] Next, heat treatment may be performed. Heat treatment may be performed under reduced pressure, and the insulating film 250A may be continuously formed without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen attached to the surface of the oxide film 230C2 and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide film 230C1, and the oxide film 230C2 can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0251] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, silicon oxynitride is preferably formed by a CVD method. The film forming temperature when forming the insulating film 250A is preferably 350° C. or higher and lower than 450° C., and particularly preferably about 400° C. By forming the insulating film 250A at a temperature of 400° C., an insulator with less impurities can be formed.

[0252] Next, the conductive film 260Aa and the conductive film 260Ab are formed. The conductive film 260Aa and the conductive film 260Ab can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, the CVD method is preferably used. In this embodiment, the conductive film 260Aa is formed by an ALD method, and the conductive film 260Ab is formed by a CVD method (see FIG. 11 ).

[0253] Next, the oxide film 230C1, the oxide film 230C2, the insulating film 250A, the conductive film 260Aa and the conductive film 260Ab are polished by CMP treatment until the insulator 280 is exposed, thereby forming oxide 230c1, oxide 230c2, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) (refer to Figure 12).

[0254] Next, a heat treatment may be performed. In this embodiment, the treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere. The heat treatment can reduce the water concentration and hydrogen concentration in the insulator 250 and the insulator 280 .

[0255] Next, an insulating film serving as the insulator 274 is formed on the insulator 280. The insulating film serving as the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film serving as the insulator 274, for example, an aluminum oxide film is preferably formed by a sputtering method. By forming the aluminum oxide film by a sputtering method, oxygen released by heat treatment can be added to the insulator 280 (see FIG. 12 ).

[0256] Next, heat treatment may be performed. In this embodiment, treatment is performed at 400° C. for 1 hour in a nitrogen atmosphere. By this heat treatment, oxygen added to the insulator 280 by forming the insulator 274 can be supplied to the oxide 230 b via the oxide 230 c.

[0257] Next, an insulator to be the insulator 281 may be formed on the insulator 274. The insulating film to be the insulator 281 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 12 ).

[0258] Next, openings that reach the conductors 242a and 242b are formed in the insulators 254, 280, 274, and 281. The openings may be formed using a photolithography method.

[0259] Next, an insulating film that becomes the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that becomes the insulator 241, an insulating film having a function of suppressing the penetration of oxygen is preferably used. For example, it is preferable to form an aluminum oxide film by an ALD method. In addition, as anisotropic etching, for example, a dry etching method can be performed. By making the side wall portion of the opening have such a structure, the penetration of oxygen from the outside can be suppressed, and oxidation of the conductor 240a and the conductor 240b to be formed next can be prevented. In addition, impurities such as water and hydrogen can be prevented from diffusing from the conductor 240a and the conductor 240b to the outside.

[0260] Next, a conductive film to be the conductor 240a and the conductor 240b is formed. The conductive film to be the conductor 240a and the conductor 240b preferably has a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it may be a laminated structure of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. The conductive film to be the conductor 240 can be formed by sputtering, CVD, MBE, PLD, ALD, etc.

[0261] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductors 240a and 240b, thereby exposing the insulator 281. As a result, the conductive film remains only in the opening, thereby forming the conductors 240a and 240b whose top surfaces are flat (see FIG. Figure 1 ). Note that a portion of the insulator 281 may be removed due to the CMP process.

[0262] Through the above process, it is possible to manufacture Figure 1 The semiconductor device of transistor 200 is shown. Figure 5 to Figure 1 2, the transistor 200 can be manufactured by the method for manufacturing a semiconductor device described in this embodiment.

[0263] In order to manufacture the semiconductor device having stacked transistors as described in the above embodiment, the above steps may be repeated to stack the transistors 200. Although the transistors located in the lower layer are subjected to excessive heat treatment after completion, as described above, oxygen can be supplied from the insulator 280 to the oxide 230 to suppress the increase of oxygen vacancies in the oxide 230. Therefore, even for the transistors 200 in the lower layer, the variation of electrical characteristics can be suppressed and stable electrical characteristics and good reliability can be provided to the semiconductor device.

[0264] According to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with small off-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0265] <Variation Example of Semiconductor Device> Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from the semiconductor device described in the above-mentioned <Structural example of semiconductor device>, will be described with reference to FIG. 13 .

[0266] in addition, Fig.13A is a top view. In addition, Fig. 13B It is along Fig.13A The cross-sectional view along the dot-dash line A1-A2 in FIG. 1 is equivalent to the cross-sectional view along the channel length direction of the transistor 200. In addition, Fig. 13C It is along Fig.13A The cross-sectional view along the dot-dash line A3-A4 in FIG. 1 is equivalent to the cross-sectional view along the channel width direction of the transistor 200. In addition, Fig.13D It is along Fig.13A The cross-sectional view of the dotted line A3-A4 in FIG. Fig.13A In the top view, some components are omitted for clarity.

[0267] In addition, in the semiconductor device shown in FIG. 13, the semiconductor device having the same structure as that shown in the semiconductor device (see Figure 1 ) are given the same reference numerals as the constituent elements having the same functions as the constituent elements of the semiconductor device. In this section, the constituent materials of the transistor 200 can be the materials described in detail in "Structural Example of Semiconductor Device".

[0268] The transistor 200 shown in Fig. 13 is different from the transistor 200 shown in Fig. 3 in that the conductor 242 is not provided. In the transistor 200 shown in Fig. 13, for example, an element that can increase the carrier density of the oxide 230 and reduce the resistance can be added as a dopant to form the region 243.

[0269] As dopants, elements that form oxygen vacancies or elements that bond to oxygen vacancies can be used. As such elements, boron or phosphorus can be typically cited. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, etc. can also be used. In addition, as typical examples of rare gases, there are helium, neon, argon, krypton and xenon, etc. In addition, one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum can also be added. Among the above-mentioned metal elements, boron and phosphorus are preferably used as dopants. When boron and phosphorus are used as dopants, the equipment of the production line of amorphous silicon or low-temperature polysilicon can be used, thereby reducing equipment investment. The concentration of the above-mentioned elements can be measured using SIMS, etc.

[0270] In particular, as an element added to region 243, an element that easily forms an oxide is preferably used. Typical examples of such an element include boron, phosphorus, aluminum, and magnesium. The element added to region 243 is likely to take away oxygen in oxide 230 to form an oxide. As a result, many oxygen vacancies are generated in region 243. Since the oxygen vacancies are bonded to hydrogen in oxide 230 to generate carriers, a region with extremely low resistance is formed. Furthermore, since the element added to region 243 exists in region 243 in a stable oxide state, it is not easy for the element to be separated from region 243 even if high-temperature treatment is performed in a subsequent process. That is, by using an element that easily forms an oxide as an element added to region 243, a region that is not easily increased in resistance even after a high-temperature process can be formed in oxide 230.

[0271] By forming the region 243 used as a source region or a drain region in the oxide 230 , the conductor 240 used as a plug can be connected to the region 243 without providing a source electrode and a drain electrode formed of metal.

[0272] When forming the region 243 by adding a dopant, for example, a mask such as a resist mask or a hard mask is provided at a position to form a channel formation region of the transistor 200, and the dopant is added. Thus, the region 243 containing the above element can be formed in a region of the oxide 230 that does not overlap with the mask.

[0273] As methods for adding dopants, the following can be used: ion implantation in which the ionized source gas is mass separated and then added; ion doping in which the ionized source gas is not mass separated and then added; and plasma immersion ion implantation. When mass separation is performed, the added ion species and their concentration can be strictly controlled. On the other hand, when mass separation is not performed, a high concentration of ions can be added in a short time. In addition, an ion doping method in which ionization is performed by generating clusters of atoms or molecules can also be used. Note that dopants can also be referred to as ions, donors, acceptors, impurities, elements, etc.

[0274] Furthermore, by adding an element that forms oxygen vacancies to the region 243 and performing heat treatment, the oxygen vacancies contained in the region 243 may capture hydrogen contained in the region 234 used as a channel formation region. Thus, the transistor 200 can be provided with stable electrical characteristics and reliability can be improved.

[0275] As described above, the structure, method, and the like described in this embodiment mode can be used in combination with the structure, method, and the like described in other embodiments and examples as appropriate.

[0276] (Implementation method 3) In this embodiment, refer to Fig.14 15 and FIG. 15 illustrate one embodiment of a semiconductor device.

[0277] [Storage device 1] Fig.14 An example of a semiconductor device (storage device) using a capacitor as one embodiment of the present invention is shown. A semiconductor device of one embodiment of the present invention includes a layer 291 including a transistor 300, a layer 290_1 on the layer 291, and a layer 290_2 on the layer 290_1. Here, the layer 291_1 includes a transistor 200_1, a capacitor 100_1, and wirings 1001_1 to 1006_1. In addition, the layer 291_2 includes a transistor 200_2, a capacitor 100_2, and wirings 1001_2 to 1006_2. Here, the layer 291_1 and the layer 291_2 have substantially the same structure, so the same conductor, insulator, and oxide are given the same symbol. In addition, the transistor 200_1 and the transistor 200_2 are sometimes collectively referred to as a transistor 200. In addition, the capacitor 100_1 and the capacitor 100_2 are sometimes collectively referred to as a capacitor 100. In addition, as the transistor 200, the transistor 200 described in the above embodiment can be used.

[0278] The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, by using it in a memory device, the stored content can be retained for a long time. In other words, since a refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be substantially reduced.

[0279] exist Fig.14 In the semiconductor device shown in FIG. 1 , the wiring 1001_1 and the wiring 1001_2 are electrically connected to the source of the transistor 300 , and the wiring 1002_1 and the wiring 1002_2 are electrically connected to the drain of the transistor 300 .

[0280] The wiring 1003_1 is electrically connected to one of the source and the drain of the transistor 200_1, the wiring 1004_1 is electrically connected to the first gate of the transistor 200_1, and the wiring 1006_1 is electrically connected to the second gate of the transistor 200_1. In addition, the other of the source and the drain of the transistor 200_1 is electrically connected to one of the electrodes of the capacitor 100_1, and the wiring 1005_1 is electrically connected to the other of the electrodes of the capacitor 100_1. In addition, the wiring 1001_1 may be electrically connected to the wiring 1003_1, the wiring 1004_1, the wiring 1005_1, or the wiring 1006_1. In addition, the wiring 1002_1 may be electrically connected to the wiring 1003_1, the wiring 1004_1, the wiring 1005_1, or the wiring 1006_1.

[0281] The wiring 1003_2 is electrically connected to one of the source and the drain of the transistor 200_2, the wiring 1004_2 is electrically connected to the first gate of the transistor 200_2, and the wiring 1006_2 is electrically connected to the second gate of the transistor 200_2. In addition, the other of the source and the drain of the transistor 200_2 is electrically connected to one of the electrodes of the capacitor 100_2, and the wiring 1005_2 is electrically connected to the other of the electrodes of the capacitor 100_2. In addition, the wiring 1001_2 may also be electrically connected to the wiring 1003_2, the wiring 1004_2, the wiring 1005_2, or the wiring 1006_2. In addition, the wiring 1002_2 may also be electrically connected to the wiring 1003_2, the wiring 1004_2, the wiring 1005_2, or the wiring 1006_2.

[0282] Fig.14 The memory device shown has a characteristic of being able to hold the potential at one electrode of the capacitor 100 by switching the transistor 200, and thus data can be written, held, and read.

[0283] In addition, by Fig.14 The memory devices shown are arranged in a matrix and can constitute a memory cell array.

[0284] Next, transistor 300 including layer 291 is described.

[0285] <Transistor 300> The transistor 300 is disposed on a substrate 311 and includes: a conductor 316 used as a gate electrode, an insulator 315 used as a gate insulator, a semiconductor region 313 formed by a portion of the substrate 311; and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region.

[0286] Here, an insulator 315 is arranged on the semiconductor region 313, and a conductor 316 is arranged on the insulator 315. In addition, the transistor 300 formed in the same layer is electrically isolated by an insulator 312 used as an element isolation insulating layer. As the insulator 312, the same insulator as the insulator 326 described later can be used. The transistor 300 can be a p-channel type or an n-channel type.

[0287] In the substrate 311, the channel forming region of the semiconductor region 313 or the region near it, the low resistance region 314a and the low resistance region 314b used as the source region or the drain region preferably contain semiconductors such as silicon-based semiconductors, and more preferably contain single crystal silicon. In addition, it can also be formed using materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenic), etc. Silicon that applies stress to the lattice and changes the interplanar spacing to control the effective mass can be used. In addition, the transistor 300 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs.

[0288] The low resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0289] As the conductor 316 used as the gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron can be used.

[0290] In addition, since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. In order to have both conductivity and embedding properties, a laminate of metal materials such as tungsten or aluminum is preferably used as the conductor, and tungsten is particularly preferably used in terms of heat resistance.

[0291] Here, in Fig.14In the transistor 300 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, the conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. Because the convex portion of the semiconductor substrate is utilized, this transistor 300 is also referred to as a FIN-type transistor. In addition, an insulator used as a mask for forming the convex portion may also be provided in a manner that contacts the upper surface of the convex portion. In addition, although a portion of the semiconductor substrate is processed to form the convex portion, the SOI substrate may also be processed to form a semiconductor film having a convex shape.

[0292] On the transistor 300, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films. In addition, a conductor 328 and a conductor 330, etc. electrically connected to the capacitor 100 or the transistor 200 are buried in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as a plug or wiring.

[0293] In addition, the insulator used as the interlayer film can be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 322, planarization can also be achieved by planarization treatment using a chemical mechanical polishing (CMP) method or the like.

[0294] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig.14 In the embodiment, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 is used as a plug or wiring.

[0295] Notice, Fig.14 The structure of the transistor 300 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method.

[0296] Next, the capacitor 100 and the wiring layer in the layer 290_1 and the layer 290_2 are described. Note that the following description is common to the layer 290_1 and the layer 290_2. In addition, since the above embodiment can be referred to, the detailed description of the transistor 200 is omitted.

[0297] <Capacitor 100> The capacitor 100 is disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric.

[0298] Alternatively, for example, the conductor 112 and the conductor 110 provided on the conductor 246 may be formed simultaneously. The conductor 112 is used as a plug or wiring for electrically connecting the capacitor 100, the transistor 200, or the transistor 300.

[0299] exist Fig.14 In the embodiment, the conductor 112 and the conductor 110 have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having high compactness with the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0300] As the insulator 130, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or the like may be used, and a stacked structure or a single-layer structure may be adopted. For example, as the insulator 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order may be used.

[0301] For example, the insulator 130 preferably uses a laminated structure of a material with high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material. By adopting this structure, the capacitor 100 can include an insulator with a high dielectric constant (high-k) to ensure sufficient capacitance, and can include an insulator with high dielectric strength to improve dielectric strength, thereby suppressing electrostatic damage to the capacitor 100.

[0302] Note that insulators that are high dielectric constant (high-k) materials (materials with a relatively high dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0303] On the other hand, materials with high dielectric strength (materials with low relative dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide or resin with pores, etc.

[0304] <Wiring Layer> A wiring layer including an interlayer film, wiring, and plugs may also be provided between the layers. In addition, the wiring layer may be provided in multiple layers according to the design. Here, in a conductor having the function of a plug or wiring, the same reference numeral is sometimes used to represent multiple structures. In addition, in this specification, etc., a wiring and a plug electrically connected to the wiring may also be a component. That is, a part of the conductor is sometimes used as a wiring, and a part of the conductor is sometimes used as a plug.

[0305] Similar to the conductor 356, the conductor 218 and the conductor (conductor 205) constituting the transistor 200 are filled in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. The conductor 218 is used as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, the insulator 150 is provided on the conductor 120 and the insulator 130.

[0306] Examples of insulators that can be used as the interlayer film include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides that have insulating properties.

[0307] For example, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0308] For example, as insulator 150, insulator 212, insulator 352 and insulator 354, it is preferred to have an insulator with a low relative dielectric constant. For example, the insulator preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide with pores and resin. Since silicon oxide and silicon oxynitride have thermal stability, by combining them with resin, a laminated structure with thermal stability and low relative dielectric constant can be achieved. As resins, for example, polyesters, polyolefins, polyamides (nylon, aramid, etc.), polyimides, polycarbonates or acrylic acid can be cited.

[0309] In addition, by surrounding a transistor using an oxide semiconductor with an insulator having a function of inhibiting the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, as the insulator 210 and the insulator 350, an insulator having a function of inhibiting the permeation of impurities such as hydrogen and oxygen can be used.

[0310] As an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, silicon oxynitride or silicon nitride can be used.

[0311] As the conductor that can be used for wiring and plugs, it is preferable to use a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0312] For example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, and the conductor 112, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials can be used in a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferred. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0313] 《Wiring or plug provided with an oxide semiconductor layer》 Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In this case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0314] For example, in Fig.14 In the embodiment, it is preferable to provide an insulator 276 between the insulator 224 having excess oxygen and the conductor 246. By providing the insulator 276 in contact with the insulator 222 and the insulator 274, the insulator 224 and the transistor 200 can have a structure sealed by the insulator having a barrier property. Furthermore, the insulator 276 is preferably also in contact with a portion of the insulator 280. When the insulator 276 extends to the insulator 280, the diffusion of oxygen and impurities can be further suppressed.

[0315] That is, by providing the insulator 276, absorption of excess oxygen in the insulator 224 by the conductor 246 can be suppressed. In addition, by providing the insulator 276, diffusion of hydrogen as an impurity into the transistor 200 through the conductor 246 can be suppressed.

[0316] Insulator 276 preferably uses an insulating material that has a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferably used. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride may also be used.

[0317] Note that Fig.142 shows a stacked structure of two layers, the layer 290_1 and the layer 290_2 , but the present invention is not limited thereto, and a structure in which three or more layers including the transistor 200 are stacked may be employed.

[0318] The above is an explanation of a structural example. By adopting this structure, a layer including transistor 200 can be stacked, so the occupied area when viewed from above can be reduced to make the semiconductor device miniaturized or highly integrated. By adopting this structure, it is possible to suppress changes in electrical characteristics while improving reliability in a semiconductor device using a transistor including an oxide semiconductor. In addition, a transistor including an oxide semiconductor with a large on-state current can be provided. In addition, a transistor including an oxide semiconductor with a small off-state current can be provided. In addition, a semiconductor device with reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0319] In addition, although the capacitor 100 is a planar type in the above structure, the shape of the capacitor is not limited thereto. Fig.15A As shown, capacitor 100 may also be cylindrical. Fig.15A The capacitor 100 shown includes a conductor 110 disposed in an opening formed in an insulator 283 provided on an insulator 281, an insulator 130 on the conductor 110 and the insulator 283, and a conductor 120 on the insulator 130. Fig.14 The transistor 200 and capacitor 100 shown are identical.

[0320] Note that Fig.15A In the embodiment, the capacitor 100 is disposed above the transistor 200, but the present embodiment is not limited thereto, and the capacitor 100 may be disposed below the transistor 200. In this way, by arranging the transistor 200 and the capacitor 100 in an overlapping manner, the occupied area of ​​the transistor and the capacitor when viewed from above can be reduced, thereby making the semiconductor device more highly integrated.

[0321] In addition, if Fig. 15B As shown in FIG. 1 , the transistor 200a and the transistor 200b may also use a structure in which the conductor 205, the oxide 230a, the oxide 230b, the conductor 242, the conductor 246, the insulator 241, and the conductor 112 are used in common. Here, the transistor 200a and the capacitor 100a have the same structure as the transistor 200b and the capacitor 100b. Fig.15A The transistor 200 and the capacitor 100 shown in the figure have the same structure. Therefore, the above description can be referred to for the details.

[0322] like Fig. 15BAs shown, by adopting a structure in which the transistor 200a and the transistor 200b share the conductor 246, the occupied area of ​​each transistor in a plan view can be reduced, and the semiconductor device can be more highly integrated.

[0323] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and examples as appropriate.

[0324] (Implementation 4) In this embodiment, refer to Fig.16 FIG. 17 and FIG. 18 illustrate a memory device (hereinafter sometimes referred to as an OS memory device) using a transistor using an oxide for a semiconductor (hereinafter sometimes referred to as an OS transistor) and a capacitor according to one embodiment of the present invention. The OS memory device is a memory device including at least a capacitor and an OS transistor for controlling the charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can be used as a non-volatile memory.

[0325] <Configuration Example of Storage Device> Fig.16 An example of the structure of an OS storage device is shown. The storage device 1400 includes a peripheral circuit 1411, a memory cell array 1470_1, and a memory cell array 1470_2. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460. In addition, the memory cell array 1470_1 and the memory cell array 1470_2 are sometimes collectively referred to as a memory cell array 1470.

[0326] The storage device 1400 corresponds to Fig.14 The row circuit 1420 and the column circuit 1430 correspond to the layer 291, the memory cell array 1470_1 corresponds to the layer 290_1, and the memory cell array 1470_2 corresponds to the layer 290_2.

[0327] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. Note that the above-mentioned wiring is a wiring connected to the memory cell included in the memory cell array 1470, and its details are described below. The amplified data signal is output as a data signal RDATA to the outside of the memory device 1400 through the output circuit 1440. In addition, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0328] The memory device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 from the outside. In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and WDATA is input to a write circuit.

[0329] The control logic circuit 1460 processes input signals (CE, WE, RE) from the outside to generate control signals for the row decoder and the column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals can be input as needed.

[0330] The memory cell array 1470_1 is formed on a portion of the peripheral circuit 1411, and the memory cell array 1470_2 is formed on the memory cell array 1470_1. The memory cell array 1470 includes a plurality of memory cells MC configured in rows and columns and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MC, the number of memory cells MC included in one column, and the like. In addition, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MC, the number of memory cells MC included in one row, and the like.

[0331] Notice, Fig.16 Although an example is shown in which two layers of memory cell arrays 1470 are stacked on the peripheral circuit 1411 , this embodiment is not limited thereto. For example, a structure in which three or more layers of memory cell arrays are stacked on the peripheral circuit 1411 may be employed.

[0332] FIG. 17 illustrates a configuration example of a memory cell that can be applied to the above-described memory cell MC.

[0333] [DOSRAM] FIG. 17A to FIG. 17C An example of a circuit configuration of a memory cell of a DRAM is shown. In this specification, etc., a DRAM using a 1-OS transistor 1-capacitor type memory cell may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Fig.17A The illustrated memory cell 1471 includes a transistor M1 and a capacitor CA. In addition, transistor M1 includes a gate (sometimes referred to as a front gate) and a back gate.

[0334] The first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring CAL.

[0335] The wiring BIL is used as a bit line, and the wiring WOL is used as a word line. The wiring CAL is used as a wiring for applying a specified potential to the second terminal of the capacitor CA. When writing and reading data, it is preferred to apply a low-level potential to the wiring CAL. The wiring BGL is used as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0336] Here, Fig.17A The storage unit 1471 shown corresponds to Fig.14 The layer 291_1 or the layer 291_2 of the memory device shown. That is, in the layer 291_1, the transistor M1 corresponds to the transistor 200_1, the capacitor CA corresponds to the capacitor 100_1, the wiring BIL corresponds to the wiring 1003_1, the wiring WOL corresponds to the wiring 1004_1, the wiring BGL corresponds to the wiring 1006_1, and the wiring CAL corresponds to the wiring 1005_1. In addition, in the layer 291_2, the transistor M1 corresponds to the transistor 200_2, the capacitor CA corresponds to the capacitor 100_2, the wiring BIL corresponds to the wiring 1003_2, the wiring WOL corresponds to the wiring 1004_2, the wiring BGL corresponds to the wiring 1006_2, and the wiring CAL corresponds to the wiring 1005_2. In addition, Fig.14 The transistor 300 shown corresponds to the transistor arranged in Fig.16 Transistors in row circuits 1420 and column circuits 1430 of memory device 1400 are shown.

[0337] In addition, the memory cell MC is not limited to the memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also be used as follows Fig. 17B The back gate of the transistor M1 is not connected to the wiring BGL but to the wiring WOL, as in the memory cell 1472 shown in FIG. Fig. 17C The memory cell 1473 shown in the figure is a memory cell composed of a transistor with a single gate structure, that is, a transistor M1 that does not include a back gate.

[0338] When the semiconductor device shown in the above embodiment is used for the memory cell 1471, etc., the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using the OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely low. In other words, since the written data can be maintained for a long time by the transistor M1, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be omitted. In addition, since the leakage current is extremely low, multi-value data or analog data can be maintained in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0339] In addition, in DOSRAM, when a sense amplifier is provided so as to overlap below the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and reduces the storage capacitance of the memory cell.

[0340] [NOSRAM] FIG. 17D to FIG. 17H An example of a circuit configuration of a gain unit type memory cell having two transistors and one capacitor is shown. Fig.17D The memory cell 1474 shown includes a transistor M2, a transistor M3, and a capacitor CB. In addition, the transistor M2 includes a top gate (sometimes simply referred to as a gate) and a back gate. In this specification, etc., a memory device including a gain unit type memory cell using an OS transistor for the transistor M2 is sometimes referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0341] The first terminal of the transistor M2 is connected to the first terminal of the capacitor CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitor CB.

[0342] Wiring WBL is used as a write bit line, wiring RBL is used as a read bit line, and wiring WOL is used as a word line. Wiring CAL is used as a wiring for applying a specified potential to the second terminal of capacitor CB. When writing, holding, and reading data, it is preferred to apply a low-level potential to wiring CAL. Wiring BGL is used as a wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0343] In addition, the memory cell MC is not limited to the memory cell 1474, and its circuit structure can be changed appropriately. For example, the memory cell MC can also be used as follows. Fig.17E The back gate of the transistor M2 is not connected to the wiring BGL but to the wiring WOL, as in the memory cell 1475 shown in FIG. Fig.17F The memory cell MC may be a memory cell composed of a single-gate structure transistor, i.e., a transistor M2 without a back gate, such as the memory cell 1476 shown in FIG. Figure 17G The memory cell 1477 shown in the figure has a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL.

[0344] When the semiconductor device shown in the above embodiment is used for the memory cell 1474, etc., the transistor 200 can be used as the transistor M2 and the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using the OS transistor as the transistor M2, the leakage current of the transistor M2 can be made extremely low. Thus, since the written data can be maintained for a long time by the transistor M2, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be omitted. In addition, since the leakage current is extremely low, multi-value data or analog data can be maintained in the memory cell 1474. The same is true for the memory cells 1475 to 1477.

[0345] By using OS transistors for the transistors M2 and M3 , a circuit can be formed using only n-type transistors in the memory cell array 1470 .

[0346] In addition, the transistor M3 may also be a transistor including silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The field effect mobility of the Si transistor is sometimes higher than that of the OS transistor. Therefore, as the transistor M3 used as a readout transistor, a Si transistor may also be used. In addition, by using a Si transistor for the transistor M3, the transistor M2 may be stacked on the transistor M3, thereby reducing the occupied area of ​​the memory cell and realizing high integration of the memory device.

[0347] in addition, Fig.17H An example of a gain unit type memory cell having three transistors and one capacitor is shown. Fig.17HThe memory cell 1478 shown includes transistors M4 to M6 and a capacitor CC. The capacitor CC can be set appropriately. The memory cell 1478 is electrically connected to the wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring for supplying a low-level potential. In addition, the memory cell 1478 can also be electrically connected to the wirings RBL and WBL without being electrically connected to the wiring BIL.

[0348] The transistor M4 is an OS transistor including a back gate, and the back gate is electrically connected to the wiring BGL. In addition, the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not include a back gate.

[0349] In addition, transistors M5 and M6 may each be an n-channel Si transistor or a p-channel Si transistor. Alternatively, transistors M4 to M6 may all be OS transistors. In this case, only n-type transistors may be used to form a circuit in memory cell array 1470.

[0350] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be extremely low.

[0351] Note that the structures of the peripheral circuit 1411 and the memory cell array 1470 described in this embodiment are not limited to the above structures. In addition, the configuration or function of these circuits and wirings connected to the circuits, circuit elements, etc. may be changed, removed, or added as needed.

[0352] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and examples as appropriate.

[0353] (Implementation 5) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is described with reference to Fig. 18. A plurality of circuits (systems) are mounted on the chip 1200. Such a technology of integrating a plurality of circuits (systems) on one chip is sometimes called a system on chip (SoC).

[0354] like Fig.18AAs shown, the chip 1200 includes a central processing unit (CPU) 1211, a graphics processing unit (GPU) 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0355] Bumps (not shown) are provided on the chip 1200. Fig.18B As shown in the figure, it is connected to the first surface of the printed circuit board (PCB) 1201. In addition, a plurality of bumps 1202 are arranged on the back of the first surface of the PCB 1201, and the bumps 1202 are connected to the motherboard 1203.

[0356] In addition, a storage device such as a DRAM 1221 and a flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM described in the above embodiment mode may be applied to the DRAM 1221. In addition, the NOSRAM described in the above embodiment mode may be applied to the flash memory 1222, for example.

[0357] CPU1211 preferably has multiple CPU cores. In addition, GPU1212 preferably has multiple GPU cores. In addition, CPU1211 and GPU1212 may each have a memory for temporarily storing data. Alternatively, a memory commonly used by CPU1211 and GPU1212 may be provided on chip 1200. The above-mentioned NOSRAM or DOSRAM may be applied to the memory. In addition, GPU1212 is suitable for parallel calculation of multiple data, which can be used for image processing or product-sum operations. By providing an image processing circuit or product-sum operation circuit using the oxide semiconductor of the present invention as GPU1212, image processing and product-sum operations can be performed with low power consumption.

[0358] In addition, since CPU1211 and GPU1212 are provided on the same chip, the wiring between CPU1211 and GPU1212 can be shortened, and data can be transferred from CPU1211 to GPU1212, data can be transferred between memories possessed by CPU1211 and GPU1212, and calculation results can be transferred from GPU1212 to CPU1211 after calculations in GPU1212 are completed at high speed.

[0359] The analog operation unit 1213 includes one or both of an analog / digital (A / D) conversion circuit and a digital / analog (D / A) conversion circuit. In addition, the above-mentioned product-sum operation circuit may be provided in the analog operation unit 1213.

[0360] The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0361] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, an image capture device, a controller, etc. The controller includes a mouse, a keyboard, a game console controller, etc. As the above-mentioned interface, a universal serial bus (USB), a high-definition multimedia interface (HDMI: High-Definition Multimedia Interface) (registered trademark), etc. can be used.

[0362] The network circuit 1216 includes a network circuit such as a local area network (LAN) and may also include a network security circuit.

[0363] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at a low cost.

[0364] The motherboard 1203 including the PCB 1201 provided with the chip 1200 having the GPU 1212 , the DRAM 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0365] The GPU module 1204 can reduce its size due to having the chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles due to its high image processing capabilities. In addition, by utilizing the product-sum operation circuit using the GPU 1212, operations such as deep neural networks (DNN), convolutional neural networks (CNN), recursive neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN) can be performed, thereby using the chip 1200 as an AI chip, or the GPU module can be used as an AI system module.

[0366] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0367] (Implementation method 6) In this embodiment, an application example of a storage device using the semiconductor device shown in the above embodiment is described. The semiconductor device shown in the above embodiment can be applied to, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smart phone, an e-book reader terminal, a digital camera (including a video camera), a video playback device, a navigation system, etc.). Note that here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). Figure 19 schematically shows several structural examples of a removable storage device. For example, the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used in various storage devices or removable memories.

[0368] Fig.19A 11 is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device described in the above embodiment can be assembled with the memory chip 1105 on the substrate 1104.

[0369] Fig.19B This is a schematic diagram of the appearance of an SD card. Fig.19C 11 is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip with a wireless communication function can also be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be assembled with the memory chip 1114 on the substrate 1113, etc.

[0370] Fig.19D This is a schematic diagram of the appearance of SSD. Fig.19E1150 is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and a DOSRAM chip can be used, for example. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled with the memory chip 1154 on the substrate 1153, etc.

[0371] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and examples as appropriate.

[0372] (Implementation 7) The semiconductor device according to one embodiment of the present invention can be applied to a processor or chip such as a CPU or GPU. Specific examples of electronic devices including a processor or chip such as a CPU or GPU according to one embodiment of the present invention are shown in FIG.

[0373] <Electronic equipment and systems> A GPU or chip according to one embodiment of the present invention can be installed in a variety of electronic devices. As examples of electronic devices, for example, in addition to electronic devices with larger screens such as television devices, desktop or notebook personal computers, displays for computers, etc., digital signage, and large-scale game machines such as pinball machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices can also be cited. In addition, by setting an integrated circuit or chip according to one embodiment of the present invention in an electronic device, the electronic device can be provided with artificial intelligence.

[0374] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, an image or information can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0375] An electronic device of one embodiment of the present invention may also include a sensor (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared).

[0376] An electronic device of one embodiment of the present invention may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc. FIG. 20 shows an example of an electronic device.

[0377] [Mobile phone] Fig. 20A The figure shows a mobile phone (smartphone) which is one of the information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511 . The display portion 5511 is provided with a touch panel as an input interface, and the housing 5510 is provided with buttons.

[0378] By applying a chip of one embodiment of the present invention to the information terminal 5500, an application program utilizing artificial intelligence can be executed. Examples of the application program utilizing artificial intelligence include an application program that recognizes a conversation and displays the content of the conversation on the display unit 5511, an application program that recognizes text or graphics input by a user to a touch panel provided on the display unit 5511 and displays the text or graphics on the display unit 5511, and an application program that performs biometric recognition such as fingerprints or voiceprints.

[0379] [Information terminal 1] Fig. 20B The tabletop information terminal 5300 is shown. The tabletop information terminal 5300 includes an information terminal body 5301 , a display 5302 , and a keyboard 5303 .

[0380] As with the above-mentioned information terminal 5500, by applying a chip of one embodiment of the present invention to the desktop information terminal 5300, an application program utilizing artificial intelligence can be executed. Examples of applications utilizing artificial intelligence include design support software, article proofreading software, and menu automatic generation software. In addition, by using the desktop information terminal 5300, novel artificial intelligence can be developed.

[0381] Note that in the above example, Fig. 20A and Fig. 20B Smartphones and desktop information terminals are shown as examples of electronic devices, but information terminals other than smart phones and desktop information terminals may also be applied. Examples of information terminals other than smart phones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0382] [Information Terminal 2] Fig.21A The tablet information terminal 5000 is shown. The tablet information terminal 5000 includes a housing 5002 and a display portion 5001 . The display portion 5001 is provided with a touch panel as an input interface, and buttons are provided on the housing 5002 .

[0383] By applying a GPU or chip of one embodiment of the present invention to a tablet information terminal 5000, a low-power tablet information terminal 5000 can be realized. In addition, low power consumption can reduce heat generated by the circuit, thereby reducing the negative impact of heat on the circuit itself, peripheral circuits, and modules.

[0384] The tablet information terminal 5000 can be held in the center of the controller 5010. By using the controller 5010, the tablet information terminal 5000 can receive an operation that is more accurate and faster than a touch panel. Thus, the tablet information terminal 5000 can be used as a portable game machine.

[0385] In addition, the controller 5010 may include one or more of the above sensors. In addition, the controller 5010 may be connected by wire or wirelessly without holding the tablet information terminal 5000.

[0386] In addition, the tablet information terminal 5000 can be kept on a cradle 5020. The cradle 5020 has at least one of the following functions: a function of charging the tablet information terminal 5000 and its accessories; a function of outputting output data (e.g., image data, sound data, or text data, etc.) of the tablet information terminal 5000; a function of connecting to an input device (e.g., a mouse, keyboard, recording medium drive, or controller 5010, etc.) to transmit input data to the tablet information terminal 5000; a function of connecting the tablet information terminal 5000 to a communication line by wire or wireless.

[0387] By using such a cradle 5020 , the tablet information terminal 5000 can be used as a personal computer, a workstation, or a stationary game console.

[0388] In addition, the cradle 5020 may also include a GPU chip, a main memory or a storage, etc. When these are included, for example, image data output from the information terminal 5000 can be up-converted.

[0389] [Fixed game consoles] Fig.20D The following is a diagram showing a stationary gaming machine 5100 as one example of a gaming machine. The stationary gaming machine 5100 includes a gaming machine body 5101, a controller 5102 that can be connected wirelessly or by wire, and the like.

[0390] By applying a GPU or chip of one embodiment of the present invention to a stationary gaming machine 5100, a low-power stationary gaming machine 5100 can be realized. In addition, low power consumption can reduce heat generated by the circuit, thereby reducing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0391] [Portable game console] Fig.20E A portable game machine 5200 as an example of a game machine is shown. The portable game machine includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0392] By applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, a low-power portable game console 5200 can be realized. In addition, low power consumption can reduce heat generated by the circuit, thereby reducing the negative effects of heat on the circuit itself, peripheral circuits, and modules.

[0393] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, a portable game console 5200 having artificial intelligence can be realized.

[0394] The performance of the progress of the game, the words and deeds of creatures appearing in the game, and the phenomena occurring in the game are originally specified by the program of the game, but by applying artificial intelligence to the portable game machine 5200, it is possible to achieve performance not limited to the game program. For example, it is possible to express the content of the questions asked by the game player, the progress of the game, the sequence of events occurring in the game, the words and deeds of characters appearing in the game, etc., without being limited to the changes in the program in the game.

[0395] Furthermore, when using the portable game console 5200 to play a game that requires multiple players, artificial intelligence can be used to construct an anthropomorphic game player, whereby the artificial intelligence game player can be used as an opponent, and one person can play the game that requires multiple players.

[0396] In the above, a fixed game console and a portable game console are shown as examples of a game console, but the game console to which the GPU or chip of one embodiment of the present invention is applied is not limited thereto. As a game console to which the GPU or chip of one embodiment of the present invention is applied, for example, an arcade game console installed in an entertainment facility (game center, amusement park, etc.), a pitching machine for batting practice installed in a sports facility, etc. can be cited.

[0397] [Electrical products] Fig.21AAn electric refrigerator-freezer 5800 is shown as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0398] By applying a chip of one embodiment of the present invention to an electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on the food stored in the electric refrigerator-freezer 5800 or the expiration date of the food, a function of automatically adjusting the temperature of the electric refrigerator-freezer 5800 according to the stored food, and the like.

[0399] In the above example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners including heating and cooling units, washing machines, dryers, audio-visual equipment, etc.

[0400] [Mobile body] The GPU or chip according to one embodiment of the present invention can be applied to a vehicle as a mobile object and the vicinity of a driver's seat of the vehicle.

[0401] Fig.21B1 is a diagram showing a car 5700 which is an example of a moving object. Fig.21B2 It is a diagram showing the periphery of the front windshield in the interior of a vehicle. Fig.21B2 Display panel 5701, display panel 5702, display panel 5703 installed on the instrument panel, and display panel 5704 installed on the pillar are shown.

[0402] The display panels 5701 to 5703 can provide various information by displaying the speedometer, tachometer, driving distance, fuel gauge, gear status, and air conditioning settings. In addition, the user can appropriately change the display content and layout displayed on the display panel according to preference, which can improve the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0403] By displaying the image captured by the camera device (not shown) installed in the car 5700 on the display panel 5704, the field of view (blind spot) blocked by the pillar can be supplemented. That is, by displaying the image captured by the camera device installed outside the car 5700, the blind spot can be supplemented, thereby improving safety. In addition, by displaying the image that supplements the invisible part, safety can be confirmed more naturally and comfortably. The display panel 5704 can also be used as a lighting device.

[0404] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an automatic driving system of the automobile 5700. The chip can also be used in a system for navigation, danger prediction, etc. In addition, information such as navigation and danger prediction can be displayed on the display panels 5701 to 5704.

[0405] Although a car is described as an example of a mobile body in the above example, the mobile body is not limited to a car. For example, a tram, a monorail, a ship, a flying object (a helicopter, an unmanned aircraft (drone), an airplane, a rocket), etc. can also be cited as a mobile body, and a chip of one embodiment of the present invention can be applied to these mobile bodies to provide a system using artificial intelligence.

[0406] [Broadcasting and Television System] A GPU or a chip according to one embodiment of the present invention can be applied to a broadcasting television system.

[0407] Fig. 21C The data transmission in the broadcast television system is schematically shown. Specifically, Fig. 21C The diagram shows the path of radio waves (broadcast television signals) transmitted from a broadcasting station 5680 to a television receiver (TV) 5600 in each home. The TV 5600 is provided with a receiver (not shown), and the broadcast television signals received by the antenna 5650 are transmitted to the TV 5600 via the receiver.

[0408] Although in Fig. 21C Although a UHF (Ultra High Frequency) antenna is shown as the antenna 5650 , a BS or 110-degree CS antenna, a CS antenna, or the like may be used as the antenna 5650 .

[0409] Radio waves 5675A and 5675B are terrestrial broadcast television signals. Radio tower 5670 amplifies received radio waves 5675A and transmits radio waves 5675B. Each household can watch terrestrial TV broadcasts with TV 5600 by receiving radio waves 5675B with antenna 5650. In addition, the broadcast television system may be satellite broadcast television using artificial satellites, data broadcast television using optical lines, etc., and is not limited to Fig. 21C Terrestrial broadcast television shown.

[0410] In addition, a chip of one embodiment of the present invention can also be applied to the above-mentioned broadcasting and television system to form a broadcasting and television system using artificial intelligence. When broadcasting and television data is sent from a broadcasting and television station 5680 to TV5600 in each household, an encoder is used to compress the broadcasting and television data; when the antenna 5650 receives the broadcasting and television data, a decoder of a receiver included in TV5600 is used to restore the broadcasting and television data. By utilizing artificial intelligence, for example, a display model contained in a displayed image can be identified in a variation compensation prediction that is one of the compression methods of the encoder. In addition, intra-frame prediction using artificial intelligence can also be performed. For example, when TV5600 receives low-resolution broadcasting and television data and displays it at a high resolution, supplementary image processing such as up-conversion can be performed in the recovery of the broadcasting and television data performed by the decoder.

[0411] The above-mentioned broadcasting and television system using artificial intelligence is suitable for ultra-high-definition television (UHDTV: 4K, 8K) playback with increased broadcasting and television data volume.

[0412] In addition, as an application of artificial intelligence on the TV 5600 side, for example, a recording device with artificial intelligence can be provided in the TV 5600. By adopting this structure, the recording device with artificial intelligence can learn the user's preferences and automatically record television programs that match the user's preferences.

[0413] The electronic device, the functions of the electronic device, the application examples of artificial intelligence and the effects thereof, and the like described in this embodiment mode can be implemented in combination with the description of other electronic devices as appropriate.

[0414] <Parallel Computers> By creating a cluster using a plurality of computers according to one embodiment of the present invention, a parallel computer can be constructed.

[0415] Fig.22A A large-scale parallel computer 5400 is shown. In the parallel computer 5400, a plurality of rack-mounted computers 5420 are housed in a rack 5410.

[0416] The computer 5420 may have, for example, Fig. 22B The structure of the stereogram is shown. Fig. 22B In the embodiment, the computer 5420 includes a motherboard 5430, which includes a plurality of slots 5431, a plurality of connection terminals 5432, and a plurality of connection terminals 5433. A personal computer card 5421 is inserted into the slot 5431. The personal computer card 5421 includes connection terminals 5423, 5424, and 5425, which are connected to the motherboard 5430.

[0417] The personal computer card 5421 is a processing board including a CPU, a GPU, a storage device, etc. according to one embodiment of the present invention. For example, Fig. 22C The personal computer card 5421 is shown to include a board 5422, and the board 5422 includes a connection terminal 5423, a connection terminal 5424, a connection terminal 5425, a chip 5426, a chip 5427, and a connection terminal 5428. Note that Fig. 22C Chips other than chip 5426 and chip 5427 are shown. For descriptions of these chips, refer to the description of chip 5426 and chip 5427 described below.

[0418] The connection terminal 5428 has a shape that can be inserted into the slot 5431 of the motherboard 5430, and is used as an interface for connecting the personal computer card 5421 and the motherboard 5430. Examples of the standard of the connection terminal 5428 include PCIe and the like.

[0419] The connection terminals 5423, 5424, and 5425 can be used as interfaces for supplying power to the personal computer card 5421 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5421, for example. Examples of the specifications of the connection terminals 5423, 5424, and 5425 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5423, 5424, and 5425, HDMI (registered trademark) and the like can be cited as the specifications.

[0420] The chip 5426 includes a terminal (not shown) for inputting and outputting signals, and the chip 5426 and the PC card 5421 can be electrically connected by inserting the terminal into a socket (not shown) included in the PC card 5421. As the chip 5426, for example, a GPU of one embodiment of the present invention can be used.

[0421] The chip 5427 includes a plurality of terminals, and the chip 5427 and the personal computer card 5421 can be electrically connected by soldering the terminals to wirings provided in the personal computer card 5421 by reflow soldering. Examples of the chip 5427 include a storage device, an FPGA (Field Programmable Gate Array), and a CPU.

[0422] By using a computer according to one embodiment of the present invention Fig.22A The computer 5420 of the parallel computer 5400 shown can, for example, perform large-scale calculations required for learning and inference of artificial intelligence.

[0423] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and examples as appropriate. [Example]

[0424] In this example, a semiconductor device in which the transistors described in the above embodiment mode are stacked is manufactured, and the electrical characteristics of the transistors are measured by observation using a scanning transmission electron microscope (STEM).

[0425] In this embodiment, a semiconductor device (hereinafter referred to as sample 1) is manufactured in which transistors having the same structure as the transistor 200 described in the above embodiment are stacked in two layers. Hereinafter, the transistor in the lower layer of sample 1 is referred to as transistor 200_1, and the transistor in the upper layer is referred to as transistor 200_2. In sample 1, transistors 200_1 and 200_2 are stacked at a density of 0.05 / μm. 2 The density is configured in each layer.

[0426] First, the structures of transistors 200_1 and 200_2 are described. As shown in FIG3 , transistors 200_1 and 200_2 include an insulator 214, an insulator 216 disposed on the insulator 214, a conductor 205 disposed in a manner buried in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, conductors 242a and 242b disposed in a manner separated from each other on the oxide 230b, and an insulator 224 disposed on the insulator 224. An insulator 254 is disposed on the conductor 242a, the conductor 242b and the insulator 224, an insulator 280 is arranged on the insulator 254, an oxide 230c1 is arranged on the oxide 230b, an oxide 230c2 is arranged on the oxide 230c1, an insulator 250 is arranged on the oxide 230c2, a conductor 260a and a conductor 260b are arranged on the insulator 250, and an insulator 274 is arranged on the insulator 280, the oxide 230c1, the oxide 230c2, the insulator 250 and the conductor 260.

[0427] Aluminum oxide having a thickness of 40 nm was used as the insulator 214. Silicon oxynitride was used as the insulator 216. A conductive film in which tantalum nitride, titanium nitride, and tungsten were stacked in this order was used as the conductor 205.

[0428] Aluminum oxide with a thickness of 5 nm formed by ALD method was used as insulator 222. Silicon oxynitride with a thickness of 35 nm was used as insulator 224. After insulator 224 was formed, it was heat treated at 400° C. for 1 hour in a nitrogen atmosphere, and then heat treated at 400° C. for 1 hour in an oxygen atmosphere. Furthermore, the surface of insulator 224 was subjected to CMP treatment.

[0429] As the oxide 230a, an In-Ga-Zn oxide having a thickness of 5 nm formed by a DC sputtering method was used. In addition, when forming the oxide 230a, a target material with an In:Ga:Zn ratio of 1:3:4 [atomic number ratio] was used, an oxygen gas of 45 sccm was used as a film-forming gas, a film-forming pressure of 0.7 Pa, a film-forming power of 500 W, a substrate temperature of 200°C, and a distance between the target material and the substrate of 60 mm was used.

[0430] As the oxide 230b, an In-Ga-Zn oxide having a thickness of 20 nm formed by a DC sputtering method was used. In addition, when forming the oxide 230b, a target material with an In:Ga:Zn ratio of 4:2:4.1 [atomic number ratio] was used, argon gas 30 sccm and oxygen gas 15 sccm were used as film forming gases, the film forming pressure was set to 0.7 Pa, the film forming power was set to 500 W, the substrate temperature was set to 200°C, and the distance between the target and the substrate was set to 60 mm. In addition, after the oxide 230b was formed, it was heat treated at 400°C for 1 hour in a nitrogen atmosphere, and then heat treated at 400°C for 1 hour in an oxygen atmosphere.

[0431] Tantalum nitride with a thickness of 25 nm was used for the conductor 242 a and the conductor 242 b . In addition, a stacked film of aluminum oxide with a thickness of 5 nm formed by sputtering and aluminum oxide with a thickness of 3 nm formed thereon by ALD was used for the insulator 254 .

[0432] The insulator 280 is made of silicon oxynitride formed by a PECVD method.

[0433] As the oxide 230c1, an In-Ga-Zn oxide having a thickness of 5 nm formed by a DC sputtering method was used. In addition, when forming the oxide 230c1, a target material having an In:Ga:Zn ratio of 4:2:4.1 [atomic number ratio] was used, an oxygen gas of 45 sccm was used as a film-forming gas, a film-forming pressure of 0.7 Pa, a film-forming power of 500 W, a substrate temperature of 200° C., and a distance between the target material and the substrate of 60 mm were used.

[0434] As the oxide 230c2, an In-Ga-Zn oxide having a thickness of 5 nm formed by a DC sputtering method was used. In addition, when forming the oxide 230c2, a target material having an In:Ga:Zn ratio of 1:3:4 [atomic number ratio] was used, an oxygen gas of 45 sccm was used as a film-forming gas, a film-forming pressure of 0.7 Pa, a film-forming power of 500 W, a substrate temperature of 200°C, and a distance between the target material and the substrate of 60 mm was used.

[0435] Silicon oxynitride with a thickness of 10 nm was used as the insulator 250. Titanium nitride with a thickness of 10 nm was used as the conductor 260a. Tungsten was used as the conductor 260b.

[0436] Aluminum oxide having a thickness of 40 nm formed by RF sputtering was used as the insulator 274. When forming the insulator 274, an Al2O3 target was used, argon gas 25 sccm and oxygen gas 25 sccm were used as film-forming gases, the film-forming pressure was set to 0.4 Pa, the film-forming power was set to 2500 W, the substrate temperature was set to 250° C., and the distance between the target and the substrate was set to 60 mm.

[0437] The transistors 200_1 and 200_2 in the sample 1 having the above structure are designed to have a channel length of 360 nm and a channel width of 360 nm. Also, like the transistor 200 , the transistors 200_1 and 200_2 in the sample 1 include a conductor 240 , an insulator 241 , and an insulator 281 in addition to the above structure.

[0438] Note that since transistor 200_2 is manufactured on transistor 200_1, transistor 200_1 is subjected to heat accumulation during the manufacture of transistor 200_2. However, in the manufacturing process of transistor 200_2, heat treatment is not performed after forming insulator 224, but heat treatment is performed at 400° C. for 1 hour in a nitrogen atmosphere after forming insulator 274. After manufacturing sample 1, heat treatment is also performed at 400° C. for 4 hours in a nitrogen atmosphere.

[0439] Next, a cross-sectional STEM image of a part of the manufactured sample was taken using "HD-2300" manufactured by Hitachi High-Technologies Corporation at an accelerating voltage of 200 kV. Fig.23 This is a cross-sectional STEM image taken at a magnification of 15,000 times. Fig.24A This photo was taken at a magnification of 100,000 times. Fig.23 A cross-sectional STEM image of the transistor 200_1 in FIG. Fig. 24B This photo was taken at a magnification of 100,000 times. Fig.23 Cross-sectional STEM image of transistor 200_2 in FIG.

[0440] like Fig.23 As shown, in Sample 1, the transistor 200_2 is stacked on the transistor 200_1.

[0441] In addition, if Fig.24A As shown, in transistor 200_1, insulator 280 is separated from conductor 260, conductor 242a, and conductor 242b by insulator 274, oxide 230c2, and insulator 254. Fig. 24B As shown, in transistor 200_2 , insulator 280 is separated from conductor 260 , conductor 242 a , and conductor 242 b by insulator 274 , oxide 230 c 2 , and insulator 254 .

[0442] Next, 13 transistors 200_1 and 13 transistors 200_2 in sample 1 are subjected to I d -V g Measurement. d -V g During the measurement, the drain potential V d Set to +0.1V, +3.3V, and set the source potential V s Set to 0V and set the top gate potential V G Sweep from -3.3V to +3.3V. Set the bottom gate potential V bg Set to 0V. In addition, d -V g The measurements were performed using a semiconductor parameter analyzer manufactured by Deutsche Telekom.

[0443] Fig.25A The I of the 13 elements of the transistor 200_1 is shown. d -V g curve, Fig.25B The I of the 13 elements of the transistor 200_2 is shown. d -V g curve.

[0444] like Fig.25A and Fig.25B As shown, both transistor 200_1 and transistor 200_2 exhibit good switching characteristics.

[0445] This shows that the semiconductor device in which the transistor 200 according to one embodiment of the present invention is stacked exhibits good electrical characteristics even when heat treatment is repeatedly performed.

[0446] At least a part of the structure, method, etc. shown in this embodiment can be implemented in combination with other embodiment modes and examples described in this specification as appropriate. [Explanation of symbols]

[0447] 10: layer, 10_n: layer, 10_1: layer, 10_2: layer, 20: transistor, 22: oxide, 22a: oxide, 22b: oxide, 22bP: layer, 22bX: c-axis, 24: insulator, 26: conductor, 28a: conductor, 28b: conductor, 30: insulator, 32: insulator, 34: insulator, 36: insulator, 38: insulator, 40: insulator, 50: oxygen, 100: capacitor, 100_1: capacitor, 100_2: capacitor, 100a: capacitor, 100b: capacitor, 110: conductor body, 112: conductor, 120: conductor, 130: insulator, 150: insulator, 200: transistor, 200_1: transistor, 200_2: transistor, 200a: transistor, 200b: transistor, 205: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 218: conductor, 220: insulator, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230b: oxide, 230c: oxide, 230c1: oxide, 230c 1P: layer, 230c1X: c-axis, 230c2: oxide, 230c2P: layer, 230c2X: c-axis, 230C1: oxide film, 230C2: oxide film, 231: region, 231a: region, 231b: region, 232B: oxide film, 234: region, 240: conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242A: conductor layer, 242b: conductor, 243: region, 243 a: region, 243b: region, 246: conductor, 250: insulator, 250A: insulating film, 254: insulator, 254A: insulating film, 260: conductor, 260a: conductor, 260Aa: conductive film, 260Ab: conductive film, 260b: conductor, 273: insulator, 274: insulator, 276: insulator, 280: insulator, 280A: insulator, 281: insulator, 283: insulator, 290: oxygen, 290_1: layer, 290_2: layer, 291: layer, 291_1: layer, 291_2: layer

Claims

1. A semiconductor device comprising: a first transistor; a capacitor element electrically connected to the first transistor; as well as The second transistor, Wherein, the semiconductor device comprises: an oxide semiconductor layer having a channel formation region of the first transistor and a channel formation region of the second transistor; a first conductive layer, the first conductive layer being located above the oxide semiconductor layer and having a function of being a gate electrode of the first transistor; a second conductive layer, the second conductive layer being located above the oxide semiconductor layer and having a function of a gate electrode of the second transistor; a first insulating layer having a region located above the first conductive layer and a region located above the second conductive layer; a third conductive layer having a region in contact with a top surface of the first insulating layer and electrically connected to one of a source region and a drain region of the first transistor and one of a source region and a drain region of the second transistor; and a fourth conductive layer having a region located below the oxide semiconductor layer, The oxide semiconductor layer has: a first region overlapping with the first conductive layer; a second region overlapping with the second conductive layer; and a third region not overlapping with the first conductive layer, not overlapping with the second conductive layer, and overlapping with the fourth conductive layer, The third conductive layer is electrically connected to the oxide semiconductor layer via the opening of the first insulating layer. The opening has a portion overlapping with the third region, The opening has a portion overlapping with the fourth conductive layer.

2. A semiconductor device comprising: a first transistor; a capacitor element electrically connected to the first transistor; a second transistor; as well as a third transistor electrically connected to the first transistor and the second transistor, Wherein, the semiconductor device comprises: an oxide semiconductor layer having a channel formation region of the first transistor and a channel formation region of the second transistor; a first conductive layer, the first conductive layer being located above the oxide semiconductor layer and having a function of being a gate electrode of the first transistor; a second conductive layer, the second conductive layer being located above the oxide semiconductor layer and having a function of a gate electrode of the second transistor; a first insulating layer having a region located above the first conductive layer and a region located above the second conductive layer; a third conductive layer having a region in contact with a top surface of the first insulating layer and electrically connected to one of a source region and a drain region of the first transistor and one of a source region and a drain region of the second transistor; a fourth conductive layer having a region located below the oxide semiconductor layer; a fifth conductive layer, the fifth conductive layer having a region in contact with a top surface of the first insulating layer and electrically connected to one of a source region and a drain region of the third transistor; a second insulating layer having a region located below the fourth conductive layer; and a semiconductor region having a region located below the second insulating layer and having a channel formation region of the third transistor, The oxide semiconductor layer has: a first region overlapping with the first conductive layer; a second region overlapping with the second conductive layer; and a third region not overlapping with the first conductive layer, not overlapping with the second conductive layer, and overlapping with the fourth conductive layer, The third conductive layer is electrically connected to the oxide semiconductor layer via the opening of the first insulating layer. The opening has a portion overlapping with the third region, The opening has a portion overlapping with the fourth conductive layer, The semiconductor region contains silicon.

3. The semiconductor device according to claim 1 or 2, The third conductive layer has a region in contact with a top surface of the oxide semiconductor layer.

4. The semiconductor device according to claim 2, The third conductive layer and the fifth conductive layer contain the same material.

5. A semiconductor device comprising: a first conductive layer; a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of the first transistor and a channel formation region of the second transistor; a second conductive layer having a region located above the oxide semiconductor layer and having a function as a gate electrode of the first transistor; a third conductive layer having a region located above the oxide semiconductor layer and having a function as a gate electrode of the second transistor; a second insulating layer having a region in contact with a top surface of the second conductive layer and a region in contact with a top surface of the third conductive layer, and having first to third openings; a fourth conductive layer electrically connected to one of the source region and the drain region of the first transistor and one of the source region and the drain region of the second transistor through the first opening of the second insulating layer; a fifth conductive layer electrically connected to the other of the source region and the drain region of the first transistor via the second opening of the second insulating layer; as well as a sixth conductive layer electrically connected to the other of the source region and the drain region of the second transistor via the third opening of the second insulating layer, The first opening of the second insulating layer has a portion overlapping the first conductive layer.

6. A semiconductor device comprising: a first conductive layer; a first insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the first insulating layer and having a channel formation region of the first transistor and a channel formation region of the second transistor; a second conductive layer having a region located above the oxide semiconductor layer and having a function as a gate electrode of the first transistor; a third conductive layer having a region located above the oxide semiconductor layer and having a function as a gate electrode of the second transistor; a second insulating layer having a region in contact with a top surface of the second conductive layer and a region in contact with a top surface of the third conductive layer, and having first to third openings; a fourth conductive layer electrically connected to one of the source region and the drain region of the first transistor and one of the source region and the drain region of the second transistor through the first opening of the second insulating layer; a fifth conductive layer electrically connected to the other of the source region and the drain region of the first transistor via the second opening of the second insulating layer; as well as a sixth conductive layer electrically connected to the other of the source region and the drain region of the second transistor via the third opening of the second insulating layer, The first opening of the second insulating layer has a portion overlapping with the first conductive layer, The oxide semiconductor layer contains indium and oxygen.

7. The semiconductor device according to claim 5 or 6, When the first transistor and the second transistor are cross-sectioned along a channel length direction, the first conductive layer has no portion overlapping with the second opening of the second insulating layer and the third opening of the second insulating layer.

8. A semiconductor device comprising: a first transistor including an oxide semiconductor in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; as well as a third transistor, the third transistor being electrically connected to the first transistor and the second transistor, respectively, and containing silicon in a channel formation region, Wherein, the semiconductor device comprises: a semiconductor region including a channel formation region of the third transistor; a first insulating layer having a region located above the semiconductor region; a first conductive layer having a region located above the first insulating layer; a second insulating layer having a region located above the first conductive layer; an oxide semiconductor layer having a region located above the second insulating layer and having a channel formation region of the first transistor and a channel formation region of the second transistor; a second conductive layer having a region located above the oxide semiconductor layer and having a function as a gate electrode of the first transistor; a third conductive layer having a region located above the oxide semiconductor layer and having a function as a gate electrode of the second transistor; a third insulating layer having a region in contact with a top surface of the second conductive layer and a region in contact with a top surface of the third conductive layer, and having first to third openings; a fourth conductive layer, the fourth conductive layer being electrically connected to one of the source region and the drain region of the first transistor and one of the source region and the drain region of the second transistor respectively through the first opening of the third insulating layer; a fifth conductive layer electrically connected to the other of the source region and the drain region of the first transistor via the second opening of the third insulating layer; and a sixth conductive layer, the sixth conductive layer being electrically connected to the other of the source region and the drain region of the second transistor via the third opening of the third insulating layer, The first opening of the third insulating layer has a portion overlapping with the first conductive layer.

9. The semiconductor device according to claim 8, When the first transistor and the second transistor are cross-sectioned along a channel length direction, the first conductive layer has no portion overlapping with the second opening of the third insulating layer and the third opening of the third insulating layer, respectively.

10. A storage device, comprising: Peripheral circuits; a first memory cell formed on the peripheral circuit; as well as a second memory cell formed on the first memory cell, The peripheral circuit includes a row circuit, a column circuit, an output circuit and a control logic circuit. The first memory cell and the second memory cell each include a transistor using an oxide semiconductor in a channel formation region. The channel formation region has a c-axis-oriented region.

11. A method for manufacturing a semiconductor device, wherein: A transistor is formed, the transistor comprising: a first insulator; a second insulator on the first insulator; a first oxide on the second insulator; a first conductor and a second conductor on the first oxide; a third insulator configured to cover the first conductor, the second conductor, and the first oxide; a fourth insulator on the third insulator; a second oxide on the first oxide and configured between the first conductor and the second conductor; a fifth insulator on the second oxide; a third conductor on the fifth insulator; and a sixth insulator in contact with a top surface of the fourth insulator, a top surface of the second oxide, a top surface of the fifth insulator, and a top surface of the third conductor, The transistor is thermally treated to diffuse oxygen from the second oxide into the first oxide.

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