Memory preparation method and memory

Abstract

The invention provides a preparation method of a memory and the memory. The method comprises the steps of forming a first metal layer and a first protection layer located on one side of the first metal layer; forming a storage unit array structure on one side, deviating from the first metal layer, of the first protection layer, wherein the array structure is electrically connected with the first metal layer through a first metal connecting layer; forming a second protection layer on one side, deviating from the first metal layer, of the array structure, and reducing the thickness of the second protection layer through a side wall etching technology to obtain a storage unit protection side wall; filling through a chemical vapor deposition process to form a third protective layer, wherein a step structure is formed on the third protective layer corresponding to a position between two adjacent storage units; and depositing an oxide layer on one side, deviating from the array structure, of the third protection layer, wherein an air gap is formed between the oxide layer and the third protection layer. The performance and the preparation efficiency of the memory are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a memory and a memory. Background Art

[0002] Traditional NOR Flash embedded flash memory technology has reached its physical limit at the semiconductor 40nm process node, and HKMG (high-k metal gate) material technology cannot be used in the poly (polysilicon) process of traditional NOR Flash storage cells at process nodes below 40nm. The storage cells need to be made and then the HKMG layer needs to be remade, which is quite complicated and the cost is greatly increased. Currently, no embedded non-volatile memory supplier has completed the mass production of NOR Flash at 28nm and below process nodes, and embedded memory technology is facing major challenges.

[0003] The new embedded non-volatile memory back-end capacitor process technology breaks the limitation that embedded non-volatile memory is not suitable for process nodes below 40 nanometers due to the size of traditional front-end process devices. As a relatively leading technology in the new embedded non-volatile memory, resistive random access memory (RRAM) stores and erases data by changing the resistivity of solid dielectrics in the material. When storing data, RRAM solid dielectric materials form conductive "filaments" under the action of an external electric field and enter a low-resistance state; when erasing data, reverse pressure is applied to break the "filaments" and enter a high-resistance state. Its storage principle requires continuous changes in the internal resistance state of the material, making it slightly weaker in storage and erase operation time than other new embedded non-volatile memories, such as MRAM (Magnetoresistive Random Access Memory) magnetoresistive memory and FRAM (Ferroelectric Random Access Memory) ferroelectric memory.

[0004] RRAM uses back-end capacitor process technology as a replacement for future Flash memory with process nodes below 40 nanometers. RRAM uses back-end capacitor process, and its back-end array structure and metal wiring will cause RC delay and leakage. Because of its storage principle of changing the internal resistance state of the material, the operation time is longer than other new embedded non-volatile memories.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In response to the problems in the prior art, the purpose of the present application is to provide a method for preparing a memory and a memory, which, without the need for an additional mask, reduces RC delay, reduces leakage, improves the overall operating speed and effectively compensates for the shortfall in storage erase operation time by preparing a memory containing a novel air gap structure.

[0007] The present application provides a method for preparing a memory, comprising:

[0008] forming a first metal layer and a first protective layer located on one side of the first metal layer;

[0009] forming a memory cell array structure on a side of the first protection layer away from the first metal layer, wherein the array structure is electrically connected to the first metal layer via a first metal connection layer;

[0010] forming a second protective layer on a side of the array structure away from the first metal layer, and reducing the thickness of the second protective layer by sidewall etching technology to obtain a protective sidewall of the storage unit;

[0011] Filling and forming a third protective layer by a chemical vapor deposition process, wherein the third protective layer has a step structure corresponding to a position between two adjacent storage units;

[0012] An oxide layer is deposited on a side of the third protective layer away from the array structure, and an air gap is formed between the oxide layer and the third protective layer at a position corresponding to the step structure.

[0013] In some embodiments, forming a first metal layer and a first protective layer located on one side of the first metal layer comprises the following steps:

[0014] forming a first metal layer;

[0015] Depositing an etch stop layer on one side of the first metal layer;

[0016] A first protection layer is deposited on a side of the etch stop layer away from the first metal layer.

[0017] In some embodiments, forming a memory cell array structure on a side of the first protection layer away from the first metal layer comprises the following steps:

[0018] Depositing a first electrode layer, a fixed dielectric and a second electrode layer in sequence on a side of the first protective layer away from the first metal layer;

[0019] The memory cell array structure is formed by photolithography and etching processes.

[0020] In some embodiments, forming a second protective layer on a side of the array structure away from the first metal layer includes:

[0021] A second protection layer is formed on a side of the array structure away from the first metal layer by a chemical vapor deposition process.

[0022] In some embodiments, depositing an oxide layer on a side of the third protection layer away from the array structure comprises the following steps:

[0023] A plasma enhanced chemical vapor deposition process is used to deposit an oxide layer on a side of the third protective layer away from the array structure.

[0024] In some embodiments, the oxide layer is a BD2 ultra-low dielectric constant oxide layer.

[0025] In some embodiments, reducing the thickness of the second protective layer includes reducing the thickness of the second protective layer to less than 100 Å.

[0026] In some embodiments, after forming the air gap at the step structure, the method further includes the following steps:

[0027] A second metal layer is formed on a side of the oxide layer away from the array structure, and the second metal layer is electrically connected to the array structure through a second metal connection layer.

[0028] In some embodiments, the first protective layer and the third protective layer are tetraethoxysilane protective layers, and the second protective layer is a silicon nitride protective layer or a silicon carbonitride protective layer.

[0029] The present application also provides a memory, which is obtained by using the memory preparation method, and the memory includes:

[0030] A first metal layer;

[0031] A first protective layer, located on one side of the first metal layer;

[0032] A memory cell array structure, located on a side of the first protection layer away from the first metal layer, the array structure being electrically connected to the first metal layer via a first metal connection layer;

[0033] A storage unit protection sidewall, located on a side of the array structure away from the first protection layer;

[0034] A third protection layer is located on a side of the storage unit protection side wall away from the array structure, and the third protection layer has a step structure formed at a position corresponding to a position between two adjacent storage units;

[0035] an oxide layer, located on a side of the third protective layer away from the array structure, and an air gap is provided between the oxide layer and the third protective layer at a position corresponding to the step structure;

[0036] The second metal layer is located on a side of the oxide layer away from the array structure, and the second metal layer is electrically connected to the array structure through a second metal connection layer.

[0037] The memory manufacturing method and memory provided in this application have the following advantages:

[0038] By adopting the present application, a memory device containing a novel air gap structure is prepared, RC delay is reduced, leakage is reduced, the overall operating rate is improved, and the shortage of storage erase operation time is effectively compensated, thereby effectively improving the product performance of the memory device. Furthermore, when forming the air gap, no additional mask is required, thereby improving the memory preparation efficiency and reducing the memory cost.

[0039] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0041] Figure 1 is a flow chart of a method for preparing a memory according to an embodiment of the present application;

[0042] Figure 2 It is a schematic diagram of the structure after a first metal layer, an etch stop layer and a first protective layer are formed in the preparation process of a memory device according to an embodiment of the present application;

[0043] Figure 3 It is a schematic structural diagram after forming through holes in the etch stop layer and the first protective layer during the preparation process of the memory of one embodiment of the present application;

[0044] Figure 4 is a schematic structural diagram after a first metal connection layer is formed in a preparation process of a memory device according to an embodiment of the present application;

[0045] Figure 5 It is a schematic structural diagram after a first electrode layer, a fixed dielectric and a second electrode layer are sequentially deposited in a preparation process of a memory device according to an embodiment of the present application;

[0046] Figure 6 is a schematic structural diagram after a memory cell array structure is formed in a preparation process of a memory according to an embodiment of the present application;

[0047] Figure 7 is a schematic structural diagram of forming a second protective layer during the preparation process of a memory device according to an embodiment of the present application;

[0048] Figure 8 is a schematic structural diagram of a memory device after the second protective layer is thinned during the preparation process of the memory device according to an embodiment of the present application;

[0049] Fig. 9 is a schematic structural diagram after a third protective layer is formed in a preparation process of a memory device according to an embodiment of the present application;

[0050] Fig.10 is a schematic diagram of the structure after an oxide layer is formed in the preparation process of a memory device according to an embodiment of the present application;

[0051] Fig.11 is a schematic structural diagram after a second through hole is formed in an oxide layer during the preparation process of a memory device according to an embodiment of the present application;

[0052] Fig.12 It is a schematic diagram of the structure of a memory according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both represent "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.

[0054] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.

[0055] In view of the problems of RC delay and leakage that may exist in existing memories, as well as the problem that the storage erase operation time of the memory is long, the present application provides a method for preparing a memory, which reduces RC delay and leakage by adding an air gap between the metal layers of the memory, thereby improving the overall operating rate and effectively making up for the lack of storage erase operation time. The memory can be an RRAM memory, which breaks the limitation that embedded non-volatile memory is not suitable for process nodes below 40 nanometers due to problems such as the size of traditional front-end process devices, and makes up for the defect that its storage erase operation time is long, making RRAM memory more suitable for large-scale promotion and application. However, the present application is not limited to this, and the preparation method of the memory and the structure of the memory can also be applied to other types of memories, all of which are within the scope of protection of the present application. The following will take the memory as an RRAM memory as an example to specifically introduce the preparation method of the memory and the structure of the memory, but it is not intended to limit the scope of protection of the present application.

[0056] like Figure 1 As shown, the present application provides a method for preparing a memory, comprising the following steps:

[0057] S100: forming a first metal layer and a first protective layer located on one side of the first metal layer;

[0058] The first metal layer is, for example, a copper layer; the first protective layer is, for example, a TEOS (tetraethoxysilane) protective layer;

[0059] S200: forming a memory cell array structure on a side of the first protection layer away from the first metal layer, wherein the array structure is electrically connected to the first metal layer via a first metal connection layer;

[0060] The first metal connection layer is, for example, a titanium nitride TiN layer;

[0061] S300: forming a second protective layer on a side of the array structure away from the first metal layer, and reducing the thickness of the second protective layer by sidewall etching technology to obtain a protective sidewall of a storage unit;

[0062] The second protective layer is, for example, a SiN (silicon nitride) protective layer or a SiCN (silicon carbon nitride) protective layer;

[0063] S400: filling and forming a third protection layer by a chemical vapor deposition process, wherein the third protection layer has a step structure corresponding to a position between two adjacent storage units;

[0064] The third protective layer is, for example, a TEOS protective layer;

[0065] S500: depositing an oxide layer on a side of the third protective layer away from the array structure, and forming an air gap between the oxide layer and the third protective layer at a position corresponding to the step structure.

[0066] By adopting the preparation method of the memory of the present application, in order to reduce RC delay and leakage, an air gap with a dielectric constant of 1 can be introduced between the metal layers of the memory as an isolation medium between the back-end metal layers and the upper and lower layers, which can effectively reduce the K value of the dielectric layer in the back-end process, thereby reducing RC delay and leakage, improving the overall operating rate and effectively compensating for the lack of storage erase operation time, effectively improving the product performance of the memory, and when forming the air gap, there is no need to use an additional mask, thereby improving the memory preparation efficiency and reducing the memory cost.

[0067] In this embodiment, the step S100: forming a first metal layer and a first protective layer located on one side of the first metal layer, comprises the following steps:

[0068] forming a first metal layer;

[0069] Depositing an etch stop layer on one side of the first metal layer; the etch stop layer is, for example, a SiCN layer;

[0070] A first protection layer is deposited on a side of the etch stop layer away from the first metal layer.

[0071] In this embodiment, the step S200 of forming a memory cell array structure on a side of the first protection layer away from the first metal layer comprises the following steps:

[0072] A first electrode layer, a fixed dielectric and a second electrode layer are sequentially deposited on a side of the first protective layer away from the first metal layer; wherein the first electrode layer (lower electrode) is electrically connected to the first metal layer through a first metal connection layer;

[0073] The first electrode layer and the second electrode layer can be made of metal materials such as aluminum Al, titanium Ti, tungsten W, etc., and the fixed dielectric can be made of metal oxides with resistive switching properties such as hydrofluoric acid Hf / iron Fe / magnesium Mg as oxide medium;

[0074] The memory cell array structure is formed by photolithography and etching processes.

[0075] In this embodiment, the step S300 of forming a second protective layer on a side of the array structure away from the first metal layer includes:

[0076] A second protection layer is formed on a side of the array structure away from the first metal layer by a chemical vapor deposition process.

[0077] The second protective layer is, for example, a SiN film or a SiCN film. Compared with the fixed dielectric, the SiN film or the SiCN film deposited by chemical vapor deposition has a higher K value, which is not conducive to reducing the K value of the overall metal interlayer dielectric, and needs to be thinned as much as possible by sidewall etching technology. In this embodiment, in the step S300, the thickness of the second protective layer is reduced by the sidewall etching technology, including reducing the thickness of the second protective layer to less than 100A.

[0078] In this embodiment, the step S500 of depositing an oxide layer on a side of the third protection layer away from the array structure comprises the following steps:

[0079] A plasma enhanced chemical vapor deposition process is used to deposit an oxide layer on the side of the third protective layer away from the array structure. In this embodiment, the oxide layer is a BD2 ultra-low dielectric constant oxide layer. Plasma Enhanced Chemical Vapor Deposition (PECVD) is a method for preparing semiconductor thin film materials and other material films by chemically reacting and depositing them on a substrate after ionizing them in a deposition chamber using glow discharge. It enhances the activity of chemical vapor reaction substances through plasma activation, increases the surface reaction rate, and significantly reduces the film deposition temperature through high-energy ions. BD2 ultra-low dielectric constant oxide film is a thin film material with special properties. The BD2 ultra-low dielectric constant oxide film prepared by plasma enhanced chemical vapor deposition process has a K value of only 2.55 and has poor filling ability, which is suitable for forming dielectric air gaps in RRAM memory cell array structures.

[0080] In this embodiment, after step S500, the following steps are also included:

[0081] A second metal layer is formed on the side of the oxide layer away from the array structure, and the second metal layer is electrically connected to the array structure through a second metal connection layer. The second metal layer and the second metal connection layer are, for example, copper layers. The second metal layer is electrically connected to the second electrode layer (upper electrode) of the memory cell array structure through the second metal connection layer.

[0082] Combine the following Figures 2 to 12 The implementation process of the memory manufacturing method is described in detail. It is understandable that the drawings and the following description are only examples, which are intended to make the process of the memory manufacturing method clearer, and are not intended to limit the scope of protection of this application. In order to more clearly show the hierarchical structure of the memory, Figures 2 to 12 The structures of the memory at various stages of the preparation process are shown in cross-sectional views. Only a small number of memory cells are shown as examples. In actual memory products, the number and arrangement of memory cells can be set as needed and are not limited to those shown in the figures.

[0083] like Figure 2 As shown, corresponding to step S100, after forming the first metal layer 11, an etch stop layer 12 and a first protective layer 13 are sequentially deposited on one side of the first metal layer 11. The first metal layer 11 is a copper layer, the etch stop layer 12 is a SiCN layer, and the first protective layer 13 is a TEOS layer.

[0084] like Figure 3 As shown, a plurality of through holes are formed in the first protection layer 13 and the etching stop layer 12 by etching. Figure 4 As shown, TiN is filled in the through hole to form a first metal connection layer 14 .

[0085] like Figure 5 As shown, corresponding to step S200, a first electrode layer 21, a fixed dielectric 22, and a second electrode layer 23 are sequentially deposited on the side (upper side) of the first protective layer 13 away from the first metal layer 11; wherein the first electrode layer 21 (lower electrode) is electrically connected to the first metal layer 11 through the first metal connection layer 14. The first electrode layer 21 and the second electrode layer 23 can be made of metal materials such as aluminum Al, titanium Ti, tungsten W, etc., and the fixed dielectric 22 can be made of metal oxides with resistive switching properties such as hydrofluoric acid Hf / iron Fe / magnesium Mg as oxide medium.

[0086] like Figure 6 As shown, a memory cell array structure is formed by photolithography, etching and other processes, and the array structure is composed of a plurality of memory cells 20 arranged in an array. Figure 6 Only two storage units are shown as an example, but this is not intended to limit the protection scope of the present application.

[0087] like Figure 7As shown, corresponding to step S300, a second protective layer 31 is formed on the side of the array structure away from the first metal layer 11 by a chemical vapor deposition process. Figure 8 As shown, corresponding to step S300, the thickness of the second protective layer 31 is reduced by sidewall etching technology to obtain a storage unit protective sidewall 32. The second protective layer is, for example, a SiN (silicon nitride) protective layer or a SiCN (silicon carbon nitride) protective layer, and the thickness of the thinned second protective layer, i.e., the storage unit protective sidewall 32, is less than 100A.

[0088] like Fig. 9 As shown, corresponding to step S400, a third protective layer 33 is formed by filling through a chemical vapor deposition process, and the third protective layer 33 has a step structure 34 corresponding to the position between two adjacent storage units 20. Here, the step structure 34 refers to the structure of the portion of the third protective layer 33 formed between two adjacent storage units 20, and the portions on both sides connected to the storage units 20 form a step portion, and a cavity is formed between the two step portions. The third protective layer 33 is, for example, a TEOS protective layer.

[0089] like Fig.10 As shown, corresponding to step S500, a plasma enhanced chemical vapor deposition process is used to deposit an oxide layer 41 on the side of the third protective layer 33 away from the array structure, and an air gap 42 is formed between the oxide layer 41 and the third protective layer 33 at a position corresponding to the step structure. The oxide layer is, for example, a BD2 ultra-low dielectric constant oxide layer. Fig.10 The structure of four storage units 20 is exemplarily shown in the figure. The number and arrangement of the actual storage units 20 can be adjusted as needed and are not limited to those shown in the figure.

[0090] like Fig.11 As shown, a plurality of through holes are formed in the oxide layer 41 by photolithography and etching processes, and the plurality of through holes are aligned with the first metal connection layer 14 in the vertical direction, and the through holes penetrate all the way to expose the upper surface of the second electrode layer 23. Fig.12 As shown, the second metal layer 51 and the second metal connection layer 52 are formed by physical vapor deposition, chemical mechanical polishing and other processes. The second metal layer 51 and the second metal connection layer 52 are, for example, copper layers. The second metal layer 51 is electrically connected to the second electrode layer 23 of the storage unit 20 through the second metal connection layer 52.

[0091] like Fig.12 As shown, the embodiment of the present application further provides a memory, which is obtained by using the preparation method of the memory, and the memory includes:

[0092] A first metal layer 11; the first metal layer 11 is, for example, a copper layer;

[0093] A first protective layer 13 is located on one side of the first metal layer 11; the first protective layer is, for example, a TEOS protective layer; in this embodiment, an etch stop layer 12 is further formed between the first metal layer 11 and the first protective layer 13; the etch stop layer is, for example, a SiCN layer;

[0094] A memory cell array structure is located on a side of the first protective layer 13 away from the first metal layer 11, and the array structure is electrically connected to the first metal layer 11 through a first metal connection layer 14; the memory cell array structure includes a plurality of memory cells 20 arranged in an array; in this embodiment, the memory cell array structure includes a first electrode layer, a fixed dielectric and a second electrode layer 23 deposited sequentially from bottom to top, and the first electrode layer is electrically connected to the first metal layer 11 through the first metal connection layer 14; the first electrode layer and the second electrode layer can be made of metal materials such as aluminum Al, titanium Ti, tungsten W, etc., and the fixed dielectric can be made of metal oxides with resistive switching properties such as hydrofluoric acid Hf / iron Fe / magnesium Mg for oxide medium; the first metal connection layer is, for example, a titanium nitride TiN layer;

[0095] A storage unit protection sidewall 32 is located at a side of the array structure away from the first protection layer 13; the storage unit protection sidewall 32 is, for example, a SiN film or a SiCN film;

[0096] A third protection layer 33 is located on a side of the storage unit protection sidewall 32 away from the array structure, and the third protection layer 33 forms a step structure corresponding to a position between two adjacent storage units; the third protection layer is, for example, a TEOS protection layer;

[0097] An oxide layer 41 is located on a side of the third protective layer 33 away from the array structure, and an air gap 42 is provided between the oxide layer 41 and the third protective layer 33 at a position corresponding to the step structure; the oxide layer is, for example, a BD2 ultra-low dielectric constant oxide layer;

[0098] The second metal layer 51 is located on the side of the oxide layer 41 away from the array structure. The second metal layer 51 is electrically connected to the second electrode layer 23 of the array structure via a second metal connection layer 52. The second metal layer 51 and the second metal connection layer 52 are, for example, copper layers.

[0099] By adopting the memory of the present application, in order to reduce RC delay and leakage, an air gap with a dielectric constant of 1 can be introduced between the metal layers of the memory as an isolation medium between the back-end metal layers and the upper and lower layers, which can effectively reduce the K value of the dielectric layer in the back-end process, thereby reducing RC delay and leakage, improving the overall operating speed and effectively compensating for the shortage of storage erase operation time, effectively improving the product performance of the memory.

[0100] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A method for preparing a memory, characterized in that: include: forming a first metal layer and a first protective layer located on one side of the first metal layer; forming a memory cell array structure on a side of the first protection layer away from the first metal layer, wherein the array structure is electrically connected to the first metal layer via a first metal connection layer; forming a second protective layer on a side of the array structure away from the first metal layer, and reducing the thickness of the second protective layer by sidewall etching technology to obtain a protective sidewall of the storage unit; Filling and forming a third protective layer by a chemical vapor deposition process, wherein the third protective layer has a step structure corresponding to a position between two adjacent storage units; An oxide layer is deposited on a side of the third protective layer away from the array structure, and an air gap is formed between the oxide layer and the third protective layer at a position corresponding to the step structure.

2. The method for preparing a memory according to claim 1, characterized in that: Forming a first metal layer and a first protective layer located on one side of the first metal layer comprises the following steps: forming a first metal layer; Depositing an etch stop layer on one side of the first metal layer; A first protection layer is deposited on a side of the etch stop layer away from the first metal layer.

3. The method for preparing a memory according to claim 1, characterized in that: Forming a memory cell array structure on a side of the first protection layer away from the first metal layer comprises the following steps: Depositing a first electrode layer, a fixed dielectric and a second electrode layer in sequence on a side of the first protective layer away from the first metal layer; The memory cell array structure is formed by photolithography and etching processes.

4. The method for preparing a memory according to claim 1, characterized in that: Forming a second protective layer on a side of the array structure away from the first metal layer, comprising: A second protection layer is formed on a side of the array structure away from the first metal layer by a chemical vapor deposition process.

5. The method for preparing a memory according to claim 1, characterized in that: Depositing an oxide layer on a side of the third protective layer away from the array structure comprises the following steps: A plasma enhanced chemical vapor deposition process is used to deposit an oxide layer on a side of the third protective layer away from the array structure.

6. The method for preparing a memory according to claim 1, characterized in that: The oxide layer is a BD2 ultra-low dielectric constant oxide layer.

7. The method for preparing a memory according to claim 1, characterized in that: Reducing the thickness of the second protective layer includes reducing the thickness of the second protective layer to less than 100 Å.

8. The method for preparing a memory according to claim 1, characterized in that: After forming the air gap at the step structure, the method further includes the following steps: A second metal layer is formed on a side of the oxide layer away from the array structure, and the second metal layer is electrically connected to the array structure through a second metal connection layer.

9. The method for preparing a memory according to claim 1, characterized in that: The first protective layer and the third protective layer are tetraethoxysilane protective layers, and the second protective layer is a silicon nitride protective layer or a silicon carbonitride protective layer.

10. A memory, characterized in that: The method for preparing a memory according to any one of claims 1 to 9 is used, wherein the memory comprises: A first metal layer; A first protective layer, located on one side of the first metal layer; A memory cell array structure, located on a side of the first protection layer away from the first metal layer, the array structure being electrically connected to the first metal layer via a first metal connection layer; A storage unit protection sidewall, located on a side of the array structure away from the first protection layer; A third protection layer is located on a side of the storage unit protection side wall away from the array structure, and the third protection layer has a step structure formed at a position corresponding to a position between two adjacent storage units; an oxide layer, located on a side of the third protective layer away from the array structure, and an air gap is provided between the oxide layer and the third protective layer at a position corresponding to the step structure; The second metal layer is located on a side of the oxide layer away from the array structure, and the second metal layer is electrically connected to the array structure through a second metal connection layer.

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