Semiconductor device and forming method thereof

Abstract

Semiconductor devices and methods of forming the same are provided. A method of the present disclosure includes depositing an aluminum nitride layer over a substrate, processing the aluminum nitride layer to convert a top portion of the aluminum nitride layer to an aluminum oxynitride layer, depositing a III-V semiconductor layer on the aluminum oxynitride layer, and forming a gate structure over the III-V semiconductor layer.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] In semiconductor technology, due to their properties, Group III-V (or III-V) semiconductor compounds are used to form various integrated circuit devices, such as high-power field effect transistors, high-frequency transistors, or high electron mobility transistors (HEMTs). A HEMT is a field effect transistor that uses a junction between two materials with different band gaps (i.e., a heterojunction) as the channel, unlike a metal oxide semiconductor field effect transistor (MOSFET) which typically uses a doped region as the channel. HEMTs have many attractive properties compared to MOSFETs, including high electron mobility and the ability to transmit signals at high frequencies. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: depositing an aluminum nitride layer over a substrate; processing the aluminum nitride layer to convert a top portion of the aluminum nitride layer into an aluminum oxynitride layer; depositing a III-V semiconductor layer on the aluminum oxynitride layer; and forming a gate structure over the III-V semiconductor layer.

[0004] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: depositing a plurality of layers above a substrate, wherein the plurality of layers comprises: a plurality of aluminum nitride layers, and a plurality of aluminum oxynitride layers, interlaced with the plurality of aluminum nitride layers; depositing a III-V semiconductor layer on the aluminum oxynitride layer; and forming a gate structure above the III-V semiconductor layer.

[0005] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a substrate; a multilayer disposed above the substrate, the multilayer comprising a plurality of aluminum nitride layers interlaced with a plurality of aluminum nitride oxide layers; a III-V semiconductor layer located above the multilayer; and a gate structure located above the III-V semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, various features are not drawn to scale and are only used for illustration purposes. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A flow chart is shown of a method of forming a device with improved heat dissipation according to one or more aspects of the present disclosure.

[0008] Figure 2 According to one or more aspects of the present disclosure, Figure 1 Flow chart of a first sub-process of depositing a buffer layer at block 14 of the method in FIG.

[0009] Figure 3 According to one or more aspects of the present disclosure, Figure 1 Flow chart of a second sub-process of depositing a buffer layer at block 14 of the method in FIG.

[0010] Figure 4-Figure 18 The workpiece according to one or more aspects of the present disclosure is shown in Figure 1 Partial cross-sectional views of different operations of the method. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0013] In addition, when "about," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to include numbers within a reasonable range, taking into account the variations inherent in the manufacturing process as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with the manufacture of components with the number associated with it, a number or range of numbers encompasses a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / - 15%. When describing aspects of transistors, the source / drain regions may be referred to individually or collectively as the source or drain, depending on the context.

[0014] A high electron mobility transistor (HEMT) is a solid-state transistor. Typically, HEMTs are fabricated to have an aluminum gallium nitride / gallium nitride (AlGaN / GaN) structure, in which a two-dimensional electron gas (2-DEG) with high electron mobility is formed at the AlGaN / GaN interface. HEMTs are used for high-frequency, high-temperature, and high-power applications. Although HEMTs have grown in high-frequency, high-temperature, and high-power applications, they are subject to self-heating effects due to resistance (R) in the channel. Self-heating effects may accelerate device aging, reduce drain saturation current, and cause various reliability issues. Self-heating effects may increase channel temperature due to Joule heating. When the lattice in the channel heats up and the heat cannot be effectively dissipated, both carrier mobility and electron saturation velocity may decrease due to phonon scattering. HEMTs include one or more buffer layers for contacting the underlying substrate, which may serve as a heat sink for heat dissipation purposes. When the buffer layer has low thermal conductivity, the heat generated by the self-heating effect cannot be effectively dissipated. Therefore, the thermal conductivity of the buffer layer plays an important role in the heat dissipation of the HEMT. Generally speaking, buffer layers with higher crystallinity tend to be better thermal conductors. However, higher crystallinity may also lead to greater electron leakage in the 2-DEG in HEMTs. Therefore, it is desirable to have a low leakage, high thermal conductivity buffer layer in HEMTs.

[0015] The present disclosure provides a multilayer buffer layer to better dissipate the heat of the HEMT without unwanted electron leakage. In one embodiment, a base buffer layer is deposited on a substrate and the base buffer layer is processed to convert the top portion of the base buffer layer into a leakage reduction layer. The base buffer layer may include aluminum nitride and the leakage reduction layer may include aluminum oxynitride. In another embodiment, the buffer layer and the leakage reduction layer are alternately deposited on the substrate to form a multilayer buffer layer. The buffer layer may include aluminum nitride (AlN) or boron nitride (BN). The leakage reduction layer may include aluminum oxynitride (AlON) or gallium nitride (GaN). The base buffer layer or buffer layer is deposited to have good crystallinity to exhibit good thermal conductivity. The leakage reduction layer can control electron leakage. The base buffer layer (or buffer layer) and the leakage reduction layer can be deposited in pairs to have a multilayer structure with good thermal conductivity and low leakage.

[0016] Various aspects of the disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1 A flowchart of a method 10 for forming a semiconductor device according to an embodiment of the present disclosure is included. The operations at block 14 of method 10 may be performed using Figure 2 Subprocess 14A or Figure 3The method 10 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 10. Additional steps may be provided before, during, and after the method 10, and some of the steps described may be replaced, eliminated, or moved for other embodiments of the method. For simplicity, not all steps are described in detail here. The method 10 and the sub-processes 14A and 14B will be described below in conjunction with Figure 4-Figure 18 1 and 2 , which include partial cross-sectional views of a workpiece 200 at different manufacturing stages according to an embodiment of the method 10. To avoid doubt, in all the drawings, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. Since the workpiece 200 will form a semiconductor device after its manufacturing process is completed, the workpiece 200 may be referred to as a semiconductor device 200 or a semiconductor structure 200 according to the context.

[0017] refer to Figure 1 and Figure 4 The method 10 includes block 12, in which a substrate 202 is received. In some embodiments, the substrate 202 may be a silicon substrate, a silicon carbide substrate, or a sapphire substrate. When the substrate 202 is a silicon substrate, the substrate 202 may have a (111) lattice plane. The substrate 202 may be doped to reduce the electron concentration near the top surface of the substrate 202. In some embodiments, the substrate 202 is doped with a p-type dopant, such as boron (B), aluminum (Al), gallium (Ga), indium (In), or boron difluoride (BF 2 ). The p-type dopant may be introduced by ion implantation. To repair damage or defects caused by the ion implantation and activate the p-type dopant, the substrate 202 may be annealed at a temperature of about 800° C. to about 1100° C. The reduced electron concentration allows for a higher operating voltage without damaging the semiconductor device 200.

[0018] In some embodiments not explicitly shown, before the buffer layer is deposited on the substrate 202 at block 14, a seed layer may be deposited over the substrate 202. The seed layer is used to bridge the lattice mismatch between the substrate 202 and the buffer layer. The seed layer may include a single layer or multiple layers. In some embodiments, the seed layer includes aluminum nitride (AlN). The seed layer may be epitaxially deposited on the substrate 202 using metal organic CVD (MOCVD), molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), atomic layer deposition (ALD), or physical vapor deposition (PVD). In order to compensate for the lattice mismatch, the seed layer may include a gradual change in lattice structure, from a lattice structure closer to the substrate 202 to a lattice structure closer to the buffer layer. In some embodiments, the seed layer may be doped with impurities in situ to improve the ability of the seed layer to prevent outward diffusion of the substrate 202. In one embodiment, the seed layer may be doped with carbon (C).

[0019] refer to Figure 1-Figure 3 , Figure 5-Figure 7 and Figure 12-14 , method 10 includes block 14, in which a buffer layer is deposited over substrate 202. The operations at block 14 may be performed according to Figure 2 The first sub-process 14A or Figure 3 The first sub-process 14A and the second sub-process 14B are performed. The first sub-process 14A and the second sub-process 14B both form a multi-layer buffer layer. The first sub-process 14A deposits a base buffer layer and then treats the base buffer layer to convert a top portion of the base buffer layer into a leakage reduction layer. The deposition and treatment can be repeated until a desired thickness is reached. The second sub-process 14B deposits a buffer layer and then deposits a leakage reduction layer on the buffer layer. The deposition of the buffer layer and the leakage reduction layer can be repeated until a desired thickness is reached.

[0020] refer to Figure 2 and Figure 5 , the first sub-process 14A includes a block 102, in which a base buffer layer 204 is deposited over the substrate 202. In some embodiments, the base buffer layer 204 includes aluminum nitride (AlN). The base buffer layer 204 can be deposited using physical vapor deposition (PVD). In the example process, an aluminum target and a nitrogen-containing gas flow (such as nitrogen (N 2 ))Deposit a base buffer layer 204 in a PVD chamber. In some embodiments, the PVD process for depositing the base buffer layer 204 may be pulsed DC, sputtering, or sputtering with a radio frequency (RF) bias. According to the present disclosure, it is desired that the base buffer layer 204 has a high degree of crystallinity so that the base buffer layer 104 exhibits good thermal conductivity. To achieve this, the PVD process at box 102 is performed at a low temperature, for example, between about 20°C and about 200°C, and at a low pressure, for example, between about 1 Torr and about 3 Torr. In some cases, the thermal conductivity of the base buffer layer 204 formed under the above conditions at room temperature may be between about 230 W / mK and about 320 W / mK. It should be noted that some conventional views hold that a buffer layer with a high degree of crystallinity is undesirable because high crystallinity generally results in high electron leakage. In some embodiments, the base buffer layer 204 may have a first thickness T1 measured from the top surface of the substrate 202. In some embodiments, the first thickness T1 may be about Peace The subsequent block 104 forms a leakage reduction layer 206 to reduce electron leakage.

[0021] refer to Figure 2 and Figure 6, the first sub-process 14A includes a block 104 in which a process 300 is performed to convert a top portion of the base buffer layer 204 into a leakage reduction layer 206. In some embodiments, the leakage reduction layer 206 includes aluminum oxynitride (AlON), which can be considered a partially oxidized form of the base buffer layer 204 or an oxygen-doped form of the base buffer layer 204. In one embodiment, the process 300 includes nitrous oxide (N 2 In this embodiment, nitrous oxide (N 2 The nitrous oxide (N 2 O) plasma treatment introduces oxygen into the top portion of the base buffer layer 204 and converts it into the leakage reduction layer 206. In some embodiments, nitrous oxide (N 2 O) is preferably used as a substrate. 2 204. The substrate buffer layer 204 may be treated with a nitrous oxide plasma. The nitrous oxide plasma treatment may include a dual frequency plasma source with a primary high frequency between about 200 MHz and about 600 MHz and a secondary low frequency between about 50 MHz and about 300 MHz. In some cases, the nitrous oxide plasma treatment may last from 1 to about 15 seconds. In another embodiment, the treatment 300 includes an ultraviolet (UV) treatment in an inert gas environment such as argon (Ar), helium (He), or a combination of both. In this embodiment, the UV treatment may remove defects in the substrate buffer layer 204. After the UV treatment, the treated substrate buffer layer 204 is exposed to ambient air, and the oxygen (O 2 ) is doped into the top of the base buffer layer 104 to form the leakage reduction layer 206. In another embodiment, the treatment 300 may include UV treatment and nitrous oxide (N 2 O) plasma treatment. The former removes defects in the base buffer layer 204, while the latter converts the top portion of the base buffer layer 204 into a leakage reduction layer. Compared with the base buffer layer 204 including AlN, the leakage reduction layer 206 including aluminum oxynitride (AlON) is less crystalline and exhibits lower electron leakage. Process 300 can be regarded as an oxygen doping process, and oxygen doping affects the lattice thermal conductivity due to additional phonon scattering. In order to prevent the leakage reduction layer 206 from slowing down the heat conduction too much, the second thickness T2 of the remaining base buffer layer 204 is greater than the third thickness T3 of the leakage reduction layer 106. In some embodiments, the second thickness T2 can be about Peace The third thickness T3 may be between about Peace The base buffer layer 204 and the leakage reduction layer 206 may be collectively referred to as a first buffer layer pair 208 .

[0022] refer to Figure 2 and Figure 7The first sub-process 14A includes a block 106 for determining whether the deposited first buffer layer pair 208 has reached a desired thickness. In the depicted embodiment, the desired thickness is a fourth thickness T4. In some cases, the fourth thickness T4 may be about Peace When the desired thickness is not reached, the operations of boxes 102 and 104 are repeated to form additional first buffer layer pairs 208. In this regard, it can be seen that the operations at boxes 102 and 104 can be viewed as a cycle that can be repeated to reach the desired thickness. In some cases, the cycle including the operations at boxes 102 and 104 can be performed once or repeated 1 to 10 times. The final stack of first buffer layer pairs 208 can be referred to as first multi-layer buffer layers 210. When only one cycle is performed, the first multi-layer buffer layer 210 includes a base buffer layer 204 and a leakage reduction layer 206, and is a first buffer layer pair 208. For illustrative purposes but not limiting the scope of the present disclosure, Figure 7 The illustrated first multi-layer buffer layer 210 includes four (4) first buffer layer pairs 208 .

[0023] refer to Figure 3 and Fig.12 , the second sub-process 14B includes a block 108, where a buffer layer 212 is deposited over the substrate 202. In some embodiments, the buffer layer 212 includes aluminum nitride (AlN) or boron nitride (BN). The buffer layer 212 can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). When the buffer layer 212 includes aluminum nitride, the deposition at block 108 can include using an aluminum-containing precursor and a nitrogen-containing precursor. Example aluminum-containing precursors can include trimethylaluminum (TMA) or triethylaluminum (TEA). Example nitrogen-containing precursors can include ammonia (NH 3 ), tert-butylamine (TBAm), or phenylhydrazine. When the buffer layer 212 includes boron nitride (BN), the deposition at block 108 may include using a single precursor or a combination of a boron-containing precursor and a nitrogen-containing precursor. Examples of single precursors include ammonia borane, borazine, and trimethylamine borane. Examples of boron-containing precursors include boron trifluoride, boron oxide, boron trichloride, trimethylborate (TMB), diborates, or decaborane. Example nitrogen-containing precursors may include ammonia (NH 3), tert-butylamine (TBAm) or phenylhydrazine. According to the present disclosure, it is desirable that the buffer layer 212 has a high degree of crystallinity so that the buffer layer 212 exhibits good thermal conductivity. In some cases, when the buffer layer 212 includes aluminum nitride, its thermal conductivity at room temperature can be between about 230 W / mK and about 320 W / mK, and when it includes boron nitride, its thermal conductivity can be greater than 600 W / mK. As described above, a buffer layer with high crystallinity is considered undesirable by some traditional views because high crystallinity generally leads to high electron leakage. In some embodiments, the buffer layer 212 can have a second thickness T2 measured from the top surface of the substrate 202. In some embodiments, the second thickness T2 can be about Peace The third thickness T3 may be between about Peace The subsequent block 110 forms a leakage reduction layer 214 to reduce electron leakage.

[0024] refer to Figure 3 and Fig.13 , the second sub-process 14B includes a box 110, in which a leakage reduction layer 214 is deposited over the buffer layer 212. In some embodiments, the leakage reduction layer 214 may include aluminum oxynitride (AlON) or gallium nitride (GaN). Unlike the leakage reduction layer 206 formed by the process 300 in the first sub-process 16A, the leakage reduction layer 214 is deposited using ALD or CVD. Because the operations at boxes 108 and 110 are performed using ALD or CVD, the deposition of the buffer layer 212 and the leakage reduction layer 214 can be deposited in the same process chamber without breaking the vacuum. If a different deposition method (such as PVD) is used to deposit one of the buffer layer 212 and the leakage reduction layer 214, the workpiece 200 will have to be moved in and out of the CVD and PVD chambers, resulting in increased process time. When the leakage reduction layer 214 includes aluminum oxynitride, the deposition at box 110 may include an aluminum-containing precursor, an oxygen-containing precursor, and a nitrogen-containing precursor. An example oxygen-containing precursor may include oxygen (O 2 ) or nitrous oxide (N 2 O). Example aluminum-containing precursors may include trimethylaluminum (TMA) or triethylaluminum (TEA). Example nitrogen-containing precursors may include ammonia (NH3), tert-butylamine (TBAm), or phenylhydrazine. When the leakage reduction layer 214 includes gallium nitride, the deposition at block 110 may include a gallium-containing precursor and a nitrogen-containing precursor. Examples of gallium-containing precursors include trimethylgallium (TMG) and triethylgallium (TEG). Examples of nitrogen-containing precursors ... 3 ), tert-butylamine (TBAm) or phenylhydrazine. To prevent the leakage reduction layer 214 from slowing down the heat conduction too much, the second thickness T2 of the buffer layer 212 is greater than the third thickness T3 of the leakage reduction layer 214. In some embodiments, the second thickness T2 may be about Peace The third thickness T3 may be between about Peace The buffer layer 212 and the leakage reduction layer 214 may be collectively referred to as a second buffer layer pair 216 .

[0025] refer to Figure 3 and Fig.14 The second sub-process 14B includes a block 112 for determining whether the deposited second buffer layer pair 216 has reached a desired thickness. In the depicted embodiment, the desired thickness is a fourth thickness T4. In some cases, the fourth thickness T4 may be about Peace When the desired thickness is not reached, the operations of boxes 108 and 110 are repeated to form additional second buffer layer pairs 216. In this regard, it can be seen that the operations at boxes 108 and 110 can be viewed as a cycle that can be repeated to reach the desired thickness. In some cases, the cycle including the operations at boxes 108 and 110 can be performed once or repeated 1 to 10 times. The final stack of second buffer layer pairs 216 can be referred to as second multi-layer buffer layers 218. When only one cycle is performed, the second multi-layer buffer layer 218 includes one buffer layer 212 and one leakage reduction layer 214, and is a second buffer layer pair 216. For illustrative purposes but not limiting the scope of the present disclosure, Fig.13 The illustrated second multi-layer buffer layer 218 includes four (4) second buffer layer pairs 216 .

[0026] The first sub-process 14A and the second sub-process 14B have different properties. The first sub-process 14A deposits the base buffer layer 204 by PVD, and forms the leakage reduction layer 206 by processing the top portion of the base buffer layer 104. The second sub-process 14B deposits the buffer layer 212 and the leakage reduction layer 214 by ALD or CVD. Both the first sub-process 14A and the second sub-process 14B can achieve the expected results. Because the deposition rate of PVD is much higher than that of ALD or CVD, the process time of the first sub-process 14A is shorter than that of the second sub-process 14B. In semiconductor manufacturing, the process time (also known as the takt time) determines the capacity of the process. Generally, a shorter process time can be converted into a lower manufacturing cost. That is, the first sub-process 14A may be more cost-effective than the second sub-process 14B. The second sub-process 14B also has advantages. Because the leakage reduction layer 206 in the first sub-process 14A is formed by processing the base buffer layer 204, the leakage reduction layer 206 is a modified or doped form of the base buffer layer 204. However, since the second sub-process 14B reforms the buffer layer 212 and the leakage reduction layer 214, there may be greater differences in the composition of the buffer layer 212 and the leakage reduction layer 214. For example, when the second sub-process 14B is adopted, the buffer layer 212 may include aluminum nitride (AlN) and the leakage reduction layer 214 may include gallium nitride (GaN), which is not a modified or doped form of aluminum nitride (AIN). Another example is that when the second sub-process 14B is adopted, the buffer layer 212 may include boron nitride (BN) and the leakage reduction layer 214 may include aluminum oxynitride (AlON), which is not a modified or doped form of BN. In other words, compared with the first sub-process 14A, the second sub-process 14B can be used to form a wider variety of buffer layer pairs. In the first example, the second multilayer buffer layer 218 may include a buffer layer 212 formed of crystalline aluminum nitride (AlN) and a leakage reduction layer 214 formed of aluminum oxynitride (AlON). In a second example, the second multi-layer buffer layer 218 may include a buffer layer 212 formed of crystalline boron nitride (BN) and a leakage reduction layer 214 formed of aluminum oxynitride (AlON). In a third example, the second multi-layer buffer layer 218 may include a buffer layer 212 formed of crystalline aluminum nitride (AlN) and a leakage reduction layer 214 formed of gallium nitride (GaN). In a fourth example, the second multi-layer buffer layer 218 may include a buffer layer 212 formed of crystalline boron nitride (BN) and a leakage reduction layer 214 formed of gallium nitride (GaN).

[0027] refer to Figure 1 , Figure 8 and Fig.15, method 10 includes frame 16, wherein a channel layer 220 is deposited over the buffer layer. The channel layer 220 includes a III-V semiconductor. In one embodiment, the channel layer 220 may include gallium nitride (GaN). When the channel layer 220 includes gallium nitride, the channel layer may be deposited using PVD, sputtering epitaxy, metal organic vapor phase epitaxy (MOVPE), metal organic chemical vapor deposition (MOCVD), CVD, or ALD. When the channel layer 220 is deposited using PVD, a high purity gallium nitride sputtering target may be used. When the channel layer 220 is deposited using sputtering epitaxy, the gallium sputtering target may be sputtered with nitrogen plasma. When the channel layer 220 is deposited using MOVPE, MOCVD, CVD, or ALD, the deposition at frame 16 may include a gallium-containing precursor and a nitrogen-containing precursor. Examples of gallium-containing precursors include trimethylgallium (TMG) and triethylgallium (TEG). Examples of nitrogen-containing precursors include ammonia (NH 3 ), tert-butylamine (TBAm) or phenylhydrazine.

[0028] In some alternative embodiments, the channel layer 220 may include aluminum nitride (AlN) or aluminum gallium nitride (AlGaN). When the channel layer 220 includes aluminum nitride, the channel layer may be deposited using PVD, sputtering epitaxy, metal organic vapor phase epitaxy (MOVPE), metal organic chemical vapor deposition (MOCVD), CVD, or ALD. For example, when the channel layer 220 includes aluminum nitride, its deposition may include using an aluminum-containing precursor and a nitrogen-containing precursor. Example aluminum-containing precursors may include trimethylaluminum (TMA) or triethylaluminum (TEA). Example nitrogen-containing precursors may include ammonia (NH 3 ), tert-butylamine (TBAm) or phenylhydrazine. When the channel layer 220 includes aluminum gallium nitride, its deposition may also include the use of a gallium-containing precursor. Examples of gallium-containing precursors include trimethylgallium (TMG) and triethylgallium (TEG). It should be noted that when the channel layer 220 and the barrier layer 230 (described below) both include aluminum gallium nitride, they have different stoichiometric ratios. For example, the channel layer 220 may include more gallium (Ga) and less aluminum (Al) than the barrier layer 230. Figure 8 A channel layer 220 deposited on the first multi-layer buffer layer 210 is shown. Fig.15 A channel layer 220 deposited on the second multi-layer buffer layer 218 is shown.

[0029] refer to Figure 1 , Fig. 9 and Fig.16, method 10 includes block 18, wherein a barrier layer 230 is deposited over channel layer 220. In some embodiments, barrier layer 230 may include aluminum gallium nitride (AlGaN). Barrier layer 230 may be epitaxially grown by MOVPE using an aluminum-containing precursor, a gallium-containing precursor, and a nitrogen-containing precursor. The aluminum-containing precursor may include TMA or TEA. The gallium-containing precursor may include TMG or TEG. The nitrogen-containing precursor may include ammonia (NH 3 ), tert-butylamine (TBAm) or phenylhydrazine. Fig. 9 A barrier layer 230 is shown deposited on a channel layer 220 which is deposited directly on the first multi-layer buffer layer 210 . Fig.16 A barrier layer 230 is shown deposited on the channel layer 220 on the second multi-layer buffer layer 218 .

[0030] refer to Figure 1 , Figure 10-11 and Figure 17-Figure 18 , method 10 includes frame 20, wherein a source contact 240S and a drain contact 240D are formed on the barrier layer 230. In some embodiments, the source contact 240S and the drain contact 240D include tantalum nitride (TaN), nickel (Ni), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), gold (Au), or a combination thereof. The source contact 240S and the drain contact 240D may be deposited separately or simultaneously using PVD, CVD, or MOCVD. In some embodiments, after forming the source contact 240S and the drain contact 240D, annealing is performed to alloy the source contact 240S and the drain contact 240D with the barrier layer 230. Fig.10 and Fig.17 In some embodiments shown, the source contact 240S and the drain contact 240D are disposed directly on the top surface of the barrier layer. Fig.11 and Fig.18 In some alternative embodiments shown, barrier layer 230 is first etched to form a recess in barrier layer 230, and then source contact 240S and drain contact 240D are deposited in the recess. In some embodiments, the recess formed in barrier layer 230 extends completely through barrier layer 230 to expose channel layer 220, and source contact 240S and drain contact 240D contact barrier layer 230 only through their sidewalls. In these embodiments, the bottom surfaces of source contact 240S and drain contact 240D contact channel layer 220.

[0031] refer to Figure 1 , Figure 10-11 and Figure 17-Figure 18, method 10 includes frame 22, wherein a gate structure 250 is formed over barrier layer 230. Although not explicitly shown, gate structure 250 may include more than one layer. In one embodiment, gate structure 250 may include a bonding isolation layer directly on barrier layer 230 and a gate electrode directly on the bonding isolation layer. In some embodiments, the bonding isolation layer may include aluminum oxide or silicon nitride. In some embodiments, the gate electrode may include tantalum nitride (TaN), nickel (Ni), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), gold (Au), or a combination thereof. The bonding isolation layer may be deposited using ALD or CVD. The gate electrode may be deposited using PVD, CVD, or MOCVD.

[0032] After completing the operation of frame 22, a semiconductor device 200 is formed from the workpiece 200, such as Fig.10 , Fig.11 , Fig.17 and Fig.18 As shown. The semiconductor device 200 may be a high electron mobility transistor (HEMT). In some embodiments, the semiconductor device 200 is an enhancement mode HEMT, in which the channel in the channel layer 220 is usually turned off when no bias voltage is applied to the gate structure 250 .

[0033] The present invention provides a multilayer buffer layer for a HEMT. The multilayer buffer layer includes 1 to 10 pairs of crystalline buffer layers and leakage reduction layers. In each pair, the crystalline buffer layer provides thermal conductivity and the leakage reduction layer is used to reduce electron leakage. In one embodiment, a base buffer layer 204 is deposited on a substrate 202 using PVD. At low process pressure and low process temperature, the deposited base buffer layer 204 exhibits crystallinity. The base buffer layer 204 is treated 300 to convert the top portion of the base buffer layer 104 into a leakage reduction layer 206. The treatment 300 may include a nitrous oxide plasma treatment, an ultraviolet treatment, and then exposure to air, or a combination of the above. The treatment 300 introduces oxygen into the lattice at the top of the base buffer layer 204. Due to the introduction of oxygen, the thermal conductivity of the leakage reduction layer 206 is less than the thermal conductivity of the base buffer layer 204. In order to prevent the thermal conductivity of the leakage reduction layer 206 from being reduced too much, its thickness is less than the thickness of the base buffer layer 204. In some embodiments, the base buffer layer 204 includes aluminum nitride (AlN), and the leakage reduction layer 206 includes aluminum oxynitride (AlON) or oxygen-doped aluminum nitride (AlN:O). The first multi-layer buffer layer 210 may include one (1) to ten (10) pairs of the base buffer layer 204 and the leakage reduction layer 206. In another embodiment, the buffer layer 212 and the leakage reduction layer 214 are deposited by ALD or CVD. That is, the leakage reduction layer 214 is not formed by processing a portion of the buffer layer 212. In some embodiments, the buffer layer 212 includes aluminum nitride (AlN) or boron nitride (BN), and the leakage reduction layer 214 includes aluminum oxynitride (AlON) or gallium nitride (GaN). The second multi-layer buffer layer 218 may include one (1) to ten (10) pairs of the buffer layer 212 and the leakage reduction layer 214. The first multi-layer buffer layer 210 or the second multi-layer buffer layer 218 has thermal conductivity and helps to effectively dissipate heat to the substrate 202, thereby slowing down device aging and mitigating thermal performance degradation. The leakage reduction layer in the first multi-layer buffer layer 210 or the second multi-layer buffer layer 218 reduces electron leakage.

[0034] In one example aspect, the present disclosure is directed to a method of forming a semiconductor device. The method includes depositing an aluminum nitride layer over a substrate, processing the aluminum nitride layer to convert a top portion of the aluminum nitride layer into an aluminum oxynitride layer, depositing a III-V semiconductor layer on the aluminum oxynitride layer, and forming a gate structure over the III-V semiconductor layer.

[0035] In some embodiments, the deposition of the aluminum nitride layer includes using physical vapor deposition (PVD). In some embodiments, the treatment includes exposing the aluminum nitride layer to ultraviolet (UV) radiation in the presence of argon (Ar) or helium (He). In some embodiments, the treatment includes using nitrous oxide (N 2O) plasma treating the aluminum nitride layer. In some embodiments, the method further comprises forming a source contact and a drain contact through the III-V semiconductor layer before forming the gate structure. In some embodiments, after forming the source contact and the drain contact, the source contact and the drain contact are in direct contact with the aluminum nitride layer. In some embodiments, the aluminum nitride layer comprises about Peace In some embodiments, the aluminum oxynitride layer includes a thickness of about Peace In some embodiments, the substrate comprises silicon, silicon carbide, or sapphire.

[0036] In another example aspect, the present disclosure is directed to a method of forming a semiconductor device, the method comprising depositing a plurality of layers on a substrate, wherein the plurality of layers comprises a plurality of aluminum nitride layers and a plurality of aluminum oxynitride layers, the plurality of aluminum oxynitride layers being interlaced with the plurality of aluminum nitride layers, depositing a III-V semiconductor layer on the aluminum oxynitride layer, and forming a gate structure over the III-V semiconductor layer.

[0037] In some embodiments, the deposition of the multilayer comprises a plurality of process cycles. Each process cycle in the plurality of process cycles comprises: depositing an aluminum nitride layer over the substrate, and treating the aluminum nitride layer to convert a top portion of the aluminum nitride layer into an aluminum oxynitride layer. In some embodiments, the deposition of the aluminum nitride layer comprises using physical vapor deposition (PVD). In some embodiments, the treating comprises exposing the aluminum nitride layer to ultraviolet (UV) radiation in the presence of argon (Ar) or helium (He). In some embodiments, the treating comprises treating the aluminum nitride layer with nitrous oxide (N 2 O) plasma treating the aluminum nitride layer. In some embodiments, the number of the plurality of aluminum nitride layers is the same as the number of the plurality of aluminum oxynitride layers. In some embodiments, the method further comprises depositing a channel layer over the III-V semiconductor layer before forming the gate structure. The channel layer comprises gallium nitride (GaN), aluminum nitride (AlN), or aluminum gallium nitride (AlGaN). The III-V semiconductor layer comprises aluminum gallium nitride (AlGaN).

[0038] In another example aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, a multilayer disposed over the substrate, a III-V semiconductor layer over the multilayer, and a gate structure over the III-V semiconductor layer, the multilayer including a plurality of aluminum nitride layers interleaved with a plurality of aluminum oxynitride layers.

[0039] In some embodiments, the III-V semiconductor layer includes aluminum gallium nitride (AlGaN). In some embodiments, the thickness of each aluminum nitride layer in the plurality of aluminum nitride layers is greater than the thickness of each aluminum nitride oxide layer in the plurality of aluminum nitride oxide layers. In some embodiments, the thickness of each aluminum nitride layer in the plurality of aluminum nitride layers is about Peace The thickness of each of the plurality of aluminum oxynitride layers is between about Peace between.

[0040] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: depositing an aluminum nitride layer over the substrate; treating the aluminum nitride layer to convert a top portion of the aluminum nitride layer into an aluminum oxynitride layer; depositing a III-V semiconductor layer on the aluminum oxynitride layer; as well as A gate structure is formed over the III-V semiconductor layer.

2. The method according to claim 1, wherein: The depositing of the aluminum nitride layer includes using physical vapor deposition.

3. The method according to claim 1, wherein: The treatment includes exposing the aluminum nitride layer to ultraviolet radiation in the presence of argon (Ar) or helium (He).

4. The method according to claim 1, wherein: The treatment includes treating the aluminum nitride layer with nitrous oxide (N2O) plasma.

5. The method according to claim 1, further comprising: Prior to forming the gate structure, source and drain contacts are formed through the III-V semiconductor layer.

6. The method according to claim 5, wherein: After forming the source contact and the drain contact, the source contact and the drain contact are in direct contact with the aluminum nitride layer.

7. A method of forming a semiconductor device, comprising: Depositing multiple layers over a substrate, wherein the multiple layers include: multiple aluminum nitride layers, and a plurality of aluminum oxynitride layers interleaved with the plurality of aluminum nitride layers; depositing a III-V semiconductor layer on the aluminum oxynitride layer; and A gate structure is formed over the III-V semiconductor layer.

8. The method according to claim 7, in, said deposition of said multiple layers comprises a plurality of process cycles, Wherein, each process cycle in the plurality of process cycles comprises: depositing an aluminum nitride layer over the substrate, and The aluminum nitride layer is processed to convert a top portion of the aluminum nitride layer into an aluminum oxynitride layer.

9. A semiconductor device comprising: substrate; a multilayer disposed over the substrate, the multilayer comprising a plurality of aluminum nitride layers interleaved with a plurality of aluminum oxynitride layers; a III-V semiconductor layer located above the multilayer; as well as A gate structure is located above the III-V semiconductor layer.

10. The semiconductor device according to claim 9, wherein A thickness of each of the plurality of aluminum nitride layers is greater than a thickness of each of the plurality of aluminum oxynitride layers.

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