Vertical p channel type gallium nitride transistor and preparation method thereof

Abstract

The invention discloses a vertical p channel type gallium nitride transistor and a preparation method thereof, and relates to the technical field of transistors, the vertical p channel type gallium nitride transistor comprises a substrate, a buffer layer, a UID-GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, an n-GaN channel layer, a p-GaN ohmic contact layer, an insulating layer, a grid electrode, a lining electrode, a source electrode and a drain electrode from bottom to top; a lining electrode is arranged on the n-GaN channel layer; a source electrode and a drain electrode are respectively arranged on the p-GaN cap layer and the p-GaN ohmic contact layer; the insulating layer covers the p-GaN cap layer, the n-GaN channel layer and the p-GaN ohmic contact layer; the grid electrode covers a part of the insulating layer. The transistor provided by the invention is constructed on a p-GaN / AlGaN / GaN substrate, and an n-GaN / p-GaN homojunction is epitaxially grown on the p-GaN / AlGaN / GaN substrate, so that the structure of the enhanced p-type field effect transistor is realized.

Description

Technical Field

[0001] The present application relates to the field of transistor technology, and in particular to a vertical p-channel gallium nitride transistor and a preparation method thereof. Background Art

[0002] The next major challenge facing GaN power devices is to integrate the driving module with the power p-GaN gate HEMT device to reduce parasitic parameters and improve the high-frequency performance of the circuit. In addition, the use of CMOS logic technology can reduce static power consumption, simplify circuit design and reduce failure rate. However, the physical properties of the GaN material itself make it difficult to obtain a high hole concentration through p-type doping, which seriously affects the development of p-FET. Therefore, research on high-performance GaN-based p-FET is crucial to the construction of all-GaN-based high-speed power integrated circuits.

[0003] At present, the GaN n-FET with mature technology and broad application prospects is the p-GaN gate HEMT device. In order to build a complementary logic circuit with this type of n-FET, the GaN p-FET devices reported so far usually use the p-GaN cap layer of the p-GaN gate HEMT device as the conductive channel of the p-FET. However, since the holes in the p-GaN cap layer are mainly provided by highly doped Mg, a large number of defects are introduced during the doping process, which seriously affects the performance of the p-FET device. In order to realize the E-type p-FET, it is necessary to thin the effective p-GaN channel under the gate to enhance the gate control capability, but the current mainstream methods all have problems with the uniformity and stability of the pFET threshold voltage due to the excessive impact of the manufacturing process fluctuations under the gate on the device performance. Summary of the invention

[0004] The purpose of the present application is to provide a vertical p-channel gallium nitride transistor and a method for preparing the same. The transistor is constructed on a p-GaN / AlGaN / GaN substrate and an n-GaN / p-GaN homojunction is epitaxially grown thereon, thereby greatly reducing the trap and hole mobility reduction problems caused by heavy p-GaN doping.

[0005] To achieve the above objectives, this application provides the following solutions:

[0006] In a first aspect, the present application provides a vertical p-channel gallium nitride transistor, which includes, from bottom to top: a substrate, a buffer layer, a UID-GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, an n-GaN channel layer, a p-GaN ohmic contact layer, an insulating layer, a gate, a liner, a source and a drain;

[0007] The liner is provided on the n-GaN channel layer;

[0008] The source electrode and the drain electrode are respectively disposed on the p-GaN cap layer and the p-GaN ohmic contact layer;

[0009] The insulating layer covers the p-GaN cap layer, the n-GaN channel layer and the p-GaN ohmic contact layer;

[0010] The gate covers a portion of the insulating layer.

[0011] In a second aspect, the present application provides a method for preparing a vertical p-channel gallium nitride transistor, comprising:

[0012] Step 1: Select an epitaxial wafer having formed a substrate, a buffer layer, a UID-GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, an n-GaN channel layer and a p-GaN ohmic contact layer;

[0013] Step 2: Etching the p-GaN cap layer, n-GaN channel layer, and p-GaN ohmic contact layer to expose the contact areas of the source, drain, and substrate electrodes;

[0014] Step 3: Perform mesa isolation on the etched p-GaN cap layer, n-GaN channel layer and p-GaN ohmic contact layer;

[0015] Step 4: Surface treatment of the device with completed mesa isolation;

[0016] Step 5: Annealing to repair damage by Mg diffusion at the source and drain electrodes;

[0017] Step 6: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate n-type ohmic contact metal on the body electrode area window, and anneal at high temperature to form a liner;

[0018] Step 7: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate ohmic contact metal on the source electrode and drain electrode area windows, and anneal at high temperature to form the source and drain;

[0019] Step 8: Depositing an insulating layer on the p-GaN cap layer, the n-GaN channel layer and the p-GaN ohmic contact layer;

[0020] Step 9: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate Schottky contact metal on the gate area window to form a gate, and obtain a prepared vertical p-channel gallium nitride transistor.

[0021] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0022] The present application provides a vertical p-channel gallium nitride transistor and a method for preparing the same. The vertical p-channel gallium nitride transistor includes from bottom to top: a substrate, a buffer layer, a UID-GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, an n-GaN channel layer, a p-GaN ohmic contact layer, an insulating layer, a gate, a liner, a source and a drain; the liner is provided on the n-GaN channel layer; the source and the drain are provided on the p-GaN cap layer and the p-GaN ohmic contact layer respectively; the insulating layer covers the p-GaN cap layer, the n-GaN channel layer and the p-GaN ohmic contact layer; the gate covers part of the insulating layer. The present application is based on the p-GaN / AlGaN / GaN platform, and continues to epitaxially grow an n-GaN / p-GaN homojunction thereon, and realizes an enhanced p-FET based on this structure. This structure uses the epitaxially grown n-GaN layer as a channel, which greatly reduces the trap and hole mobility reduction problems caused by heavy p-GaN doping. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of a three-dimensional structure of a vertical p-channel gallium nitride transistor provided in one embodiment of the present application.

[0025] Figure 2 A cross-sectional view of a cut surface 1 of a vertical p-channel gallium nitride transistor provided by an embodiment of the present application.

[0026] Figure 3 A cross-sectional view of a cut surface 2 of a vertical p-channel gallium nitride transistor provided in one embodiment of the present application.

[0027] Figure 4 A cross-sectional view of a cut surface 3 of a vertical p-channel gallium nitride transistor provided in one embodiment of the present application.

[0028] Figure 5 A cross-sectional view of a cut surface 4 of a vertical p-channel gallium nitride transistor provided in one embodiment of the present application.

[0029] Figure 6 A schematic flow chart of a method for preparing a vertical p-channel gallium nitride transistor provided in one embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0032] Embodiment 1

[0033] like Figure 1 As shown, this embodiment provides a vertical p-channel gallium nitride transistor, which includes, from bottom to top, a substrate 1, a buffer layer 2, a UID-GaN channel layer 3, an AlGaN barrier layer 4, a p-GaN cap layer 5, an n-GaN channel layer 6, a p-GaN ohmic contact layer 7, an insulating layer 8, a gate 9, a liner 10, a source 11 and a drain 12.

[0034] The liner 10 is disposed on the n-GaN channel layer 6 .

[0035] The source electrode 11 and the drain electrode 12 are respectively disposed on the p-GaN cap layer 5 and the p-GaN ohmic contact layer 7 .

[0036] The insulating layer 8 covers the p-GaN cap layer 5 , the n-GaN channel layer 6 and the p-GaN ohmic contact layer 7 .

[0037] The gate 9 covers a portion of the insulating layer 8 .

[0038] Among them, the structure of a p-channel gallium nitride high electron mobility transistor used as a logic circuit and an analog circuit is mainly provided in this embodiment. On the basis of a conventional p-GaN gate HEMT, an n-GaN / pGaN junction is grown on the p-GaN cap layer 5, and the n-GaN in the middle is used to achieve shutdown. Since the device conducts electricity through holes inverted in the n-GaN channel by the gate 9 voltage, it has very good shutdown and withstand voltage characteristics. And since the doped donor energy levels are all achieved through epitaxial growth, the lattice damage introduced by ion implantation is avoided, and a larger current density and higher stability can be achieved.

[0039] Specifically, the structure of a p-channel gallium nitride transistor with high output current and adjustable threshold voltage used in driving, switching and voltage stabilization circuits is as follows: Figures 1 to 5 As shown, Figure 1 A three-dimensional schematic diagram of a vertical p-channel GaN transistor. Figure 2-Figure 5The vertical p-channel GaN transistor is a cross-sectional view of a vertical p-channel GaN transistor under different cut planes. It can be seen that the vertical p-channel GaN transistor includes a substrate 1, a buffer layer 2, a UID-GaN channel layer 3, an AlGaN barrier layer 4, a p-GaN cap layer 5, an n-GaN channel layer 6, a p-GaN ohmic contact layer 7, an insulating layer 8, a gate 9, a liner 10, a source 11, and a drain 12 from bottom to top. The structure is turned off and withstands voltage through the n-GaN channel layer 6 in the middle layer.

[0040] A liner electrode 10 is provided on the n-GaN channel layer 6 , a source electrode 11 and a drain electrode 12 are provided on the p-GaN cap layer 5 and the p-GaN ohmic contact layer 7 , respectively, and the two electrodes are interchangeable, and the gate electrode 9 covers a portion of the insulating layer 8 .

[0041] The substrate 1 is placed at the bottom of the entire structure to play a supporting role, and may be, but is not limited to, a silicon substrate 1 , a sapphire substrate 1 , a silicon carbide (SiC) substrate 1 or a self-supporting gallium nitride substrate 1 .

[0042] The buffer layer 2 is located on the substrate 1 and may be made of, but not limited to, a gallium nitride layer doped with iron (Fe) or carbon (C) or an Al(Ga)N / GaN superlattice structure.

[0043] The UID-GaN channel layer 3 is located above the buffer layer 2 .

[0044] The AlGaN barrier layer 4 is above the UID-GaN channel layer 3 , and generates a two-dimensional electron gas (2DEG) at the interface between the AlGaN barrier layer 4 and the UID-GaN channel layer 3 , on the side close to the UID-GaN channel layer 3 through piezoelectric polarization and spontaneous polarization effects.

[0045] The p-GaN cap layer 5 is located on the AlGaN barrier layer 4. Through the piezoelectric polarization and spontaneous polarization effects at the GaN / AlGaN interface and the p-type doping of the p-GaN cap layer 5 itself, the generation of 2DEG at the AlGaN / GaN interface is suppressed, thereby realizing an enhanced n-FET device. In the present invention, the main function of the p-GaN cap layer 5 is to serve as the substrate 1 and p-type ohmic contact of the p-FET.

[0046] The n-GaN channel layer 6 is located on the p-GaN cap layer 5 and is used for the vertical channel of the pFET.

[0047] The p-GaN ohmic contact layer 7 is located above the n-GaN channel layer 6 and is used for ohmic contact between the source 11 and the drain 12 .

[0048] The insulating layer 8 covers the p-GaN cap layer 5, the n-GaN channel layer 6 and the p-GaN ohmic contact layer 7, and may use but is not limited to silicon nitride (Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), magnesium oxide (MgO) or silicon oxide (SiO2) as the insulating layer 8 material.

[0049] Embodiment 2

[0050] like Figure 6 As shown, this embodiment provides a method for preparing a vertical p-channel gallium nitride transistor, comprising:

[0051] Step 1: Select an epitaxial wafer having formed thereon a substrate 1, a buffer layer 2, a UID-GaN channel layer 3, an AlGaN barrier layer 4, a p-GaN cap layer 5, an n-GaN channel layer 6 and a p-GaN ohmic contact layer 7.

[0052] Step 2: Etch the p-GaN cap layer 5 , the n-GaN channel layer 6 , and the p-GaN ohmic contact layer 7 to expose the contact regions of the source, drain, and substrate 1 electrodes.

[0053] Step 3: Perform mesa isolation on the etched p-GaN cap layer 5 , n-GaN channel layer 6 and p-GaN ohmic contact layer 7 .

[0054] Step 4: Surface treatment of the device with completed mesa isolation.

[0055] Step 5: Annealing to repair damage by Mg diffusion at the source and drain electrodes.

[0056] Step 6: Use electron beam evaporation, thermal evaporation or magnetron sputtering technology to evaporate n-type ohmic contact metal on the body electrode area window, and anneal at high temperature to form the liner 10.

[0057] Step 7: Using electron beam evaporation, thermal evaporation or magnetron sputtering technology, evaporate ohmic contact metal on the source electrode and drain electrode area windows, and anneal at high temperature to form the source 11 and the drain 12.

[0058] Step 8 : depositing an insulating layer 8 on the p-GaN cap layer 5 , the n-GaN channel layer 6 and the p-GaN ohmic contact layer 7 .

[0059] Step 9: Using electron beam evaporation, thermal evaporation or magnetron sputtering technology, evaporate Schottky contact metal on the gate 9 area window to form the gate 9, and obtain a prepared vertical p-channel gallium nitride transistor.

[0060] Specifically, in some embodiments, during the preparation process, first, an epitaxial wafer having a substrate 1, a buffer layer 2, a UID-GaN channel layer 3, an AlGaN barrier layer 4, a p-GaN cap layer 5, an n-GaN channel layer 6, and a p-GaN ohmic contact layer 7 is selected, and then the p-GaN cap layer 5, the n-GaN channel layer 6, and the p-GaN ohmic contact layer 7 are etched to expose the contact area of ​​the source, drain, and substrate 1 electrodes. Next, the mesa isolation is performed, and the isolated device is surface treated, including acid treatment such as HCl, H2SO4+H2O2, BOE, and aqua regia. Then, annealing is performed at the source and drain electrodes through Mg diffusion to repair the damage; in addition, the surface treatment can also be an alkali treatment or an acid-base treatment in turn, such as using TMAH, NH4OH and other treatment methods. Afterwards, an n-type ohmic contact metal is evaporated on the body electrode region window by electron beam evaporation, thermal evaporation or magnetron sputtering process and annealed at high temperature to form a liner 10. At the same time, an ohmic contact metal is evaporated on the source and drain electrode region windows and annealed at high temperature to form a source 11 and a drain 12. Before the ohmic contact, an insulating layer 8 can be deposited, and finally a Schottky contact metal is evaporated on the gate 9 region window to form a gate 9.

[0061] In summary, this application has the following technical effects:

[0062] The p-channel gallium nitride transistor with high output current and adjustable threshold voltage used for logic circuits and analog circuits proposed in this application is based on the p-GaN / AlGaN / GaN platform, on which the n-GaN / p-GaN homojunction is further epitaxially grown, and an enhanced p-FET is realized based on this structure. This structure uses the epitaxially grown n-GaN layer as a channel, thereby greatly reducing the trap and hole mobility reduction problems caused by heavy doping of p-GaN. And the presence of the pn junction can achieve a smaller turn-off current and a larger source-drain withstand voltage. In addition, the effective channel length of the device is determined by the thickness of the n-GaN channel layer 6, so the effective channel length of the gate 9 can be greatly reduced and the device current density can be increased by adjusting the thickness of the n-GaN channel.

[0063] Since the structure is grown epitaxially, it can effectively avoid unnecessary defects introduced by subsequent processes, thereby effectively improving the threshold voltage uniformity and stability of p-FET. In addition, the threshold voltage of the structure is highly controllable, and the Si doping concentration in the n-GaN can be controlled during the epitaxial growth process to directly control the electron concentration in the channel, thereby obtaining different threshold voltages.

[0064] The present application introduces a fourth electrode, the substrate 10, based on the conventional p-FET. In circuit design, the threshold voltage and on-resistance required by the designer can be obtained by changing the substrate 1 voltage, thereby achieving a more flexible circuit design and providing a single chip multi-threshold voltage solution.

[0065] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A vertical p-channel gallium nitride transistor, characterized in that: The vertical p-channel gallium nitride transistor includes, from bottom to top: a substrate, a buffer layer, a UID-GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, an n-GaN channel layer, a p-GaN ohmic contact layer, an insulating layer, a gate, a liner, a source and a drain; The liner is provided on the n-GaN channel layer; The source electrode and the drain electrode are respectively disposed on the p-GaN cap layer and the p-GaN ohmic contact layer; The insulating layer covers the p-GaN cap layer, the n-GaN channel layer and the p-GaN ohmic contact layer; The gate covers a portion of the insulating layer.

2. The vertical p-channel gallium nitride transistor according to claim 1, characterized in that: The substrate is placed at the bottom of the vertical p-channel gallium nitride transistor structure to play a supporting role; the substrate is one of a silicon substrate, a sapphire substrate, a silicon carbide substrate or a self-supporting gallium nitride substrate.

3. The vertical p-channel gallium nitride transistor according to claim 1, characterized in that: The buffer layer covers the substrate, and the buffer layer is composed of a gallium nitride layer doped with iron or carbon or an AlN / GaN super lattice structure.

4. The vertical p-channel gallium nitride transistor according to claim 1, characterized in that: The AlGaN barrier layer covers the UID-GaN channel layer; at the interface between the AlGaN barrier layer and the UID-GaN channel layer, a two-dimensional electron gas is generated on the side close to the UID-GaN channel layer through piezoelectric polarization and spontaneous polarization effects.

5. The vertical p-channel gallium nitride transistor according to claim 1, characterized in that: The p-GaN cap layer covers the AlGaN barrier layer, and the vertical p-channel gallium nitride transistor is used to suppress the generation of 2DEG at the AlGaN / GaN interface through the piezoelectric polarization and spontaneous polarization effects at the GaN / AlGaN interface and the p-type doping of the p-GaN cap layer itself.

6. The vertical p-channel gallium nitride transistor according to claim 1, characterized in that: The n-GaN channel layer is located on the p-GaN cap layer and serves as a vertical channel of the pFET.

7. The vertical p-channel gallium nitride transistor according to claim 1, characterized in that: The p-GaN ohmic contact layer is located above the n-GaN channel layer and is used for ohmic contact between the source and the drain.

8. The vertical p-channel gallium nitride transistor according to claim 1, characterized in that: The insulating layer material of the insulating layer is composed of one of silicon nitride, aluminum nitride, aluminum oxide, magnesium oxide or silicon oxide.

9. A method for preparing a vertical p-channel gallium nitride transistor, characterized in that: include: Step 1: Select an epitaxial wafer having formed a substrate, a buffer layer, a UID-GaN channel layer, an AlGaN barrier layer, a p-GaN cap layer, an n-GaN channel layer and a p-GaN ohmic contact layer; Step 2: Etching the p-GaN cap layer, n-GaN channel layer, and p-GaN ohmic contact layer to expose the contact areas of the source, drain, and substrate electrodes; Step 3: Perform mesa isolation on the etched p-GaN cap layer, n-GaN channel layer and p-GaN ohmic contact layer; Step 4: Surface treatment of the device with completed mesa isolation; Step 5: Annealing to repair damage by Mg diffusion at the source and drain electrodes; Step 6: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate n-type ohmic contact metal on the body electrode area window, and anneal at high temperature to form a liner; Step 7: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate ohmic contact metal on the source electrode and drain electrode area windows, and anneal at high temperature to form the source and drain; Step 8: Depositing an insulating layer on the p-GaN cap layer, the n-GaN channel layer and the p-GaN ohmic contact layer; Step 9: Using electron beam evaporation, thermal evaporation or magnetron sputtering process, evaporate Schottky contact metal on the gate area window to form a gate, and obtain a prepared vertical p-channel gallium nitride transistor.

10. The method for preparing a vertical p-channel gallium nitride transistor according to claim 9, characterized in that: The surface treatment is one of acid treatment, alkali treatment or acid-alkali treatment in turn.

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