Polycrystalline silicon gate thin film structure, semiconductor processing method, wafer and semiconductor integrated circuit

Abstract

The invention discloses a polycrystalline silicon gate thin film structure, a semiconductor processing method, a wafer and a semiconductor integrated circuit. The polycrystalline silicon gate thin film structure comprises a substrate with a floating gate layer; the first polycrystalline silicon layer is arranged on the floating gate layer; the oxide layer is arranged on the first polycrystalline silicon layer, and the oxide layer serves as a stopping layer of chemical mechanical polishing; and the second polycrystalline silicon layer is arranged on the oxide layer, and the second polycrystalline silicon layer serves as an initial layer of chemical mechanical polishing. Therefore, the planarization uniformity of chemical mechanical grinding on the polycrystalline silicon gate film structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a polysilicon gate film structure, a semiconductor processing method, a wafer and a semiconductor integrated circuit. Background Art

[0002] Polysilicon gate is a key component used in transistors. By adding a polysilicon gate film to the gate of the transistor, the performance of the transistor can be improved. The preparation process of the polysilicon gate film usually includes preparing a gate oxide layer on a silicon substrate, and then growing multiple gate layers on the gate oxide layer, and each gate layer is isolated by an insulating layer.

[0003] In the semiconductor device manufacturing process, the flatness of the wafer has a very important impact on the performance of the semiconductor device. In order to improve the flatness of the wafer, it is often necessary to use chemical or physical methods to flatten the polysilicon gate film structure in the wafer. Summary of the invention

[0004] It would be advantageous to provide a mechanism that alleviates, mitigates, or even eliminates one or more of the above-mentioned problems.

[0005] According to some embodiments of the present disclosure, a polysilicon gate film structure is provided, comprising: a substrate with a floating gate layer; a first polysilicon layer arranged on the floating gate layer; an oxide layer arranged on the first polysilicon layer, the oxide layer serving as a stop layer for chemical mechanical polishing; and a second polysilicon layer arranged on the oxide layer, the second polysilicon layer serving as a starting layer for chemical mechanical polishing.

[0006] According to some embodiments of the present disclosure, a semiconductor processing method is provided, which is applied to the polysilicon gate film structure as described above, including: performing a first chemical mechanical polishing operation on the second polysilicon layer to expose the oxide layer from the second polysilicon layer; and removing the oxide layer.

[0007] According to some embodiments of the present disclosure, a wafer is provided, which is obtained by the semiconductor processing method as described above.

[0008] According to some embodiments of the present disclosure, a semiconductor integrated circuit is provided, comprising the wafer as described above.

[0009] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0011] Figures 1A to 1C It is a schematic diagram of the structure of polysilicon gate thin film at various stages in the semiconductor processing process of the prior art;

[0012] Figures 2A to 2C is a schematic diagram of a polysilicon gate film structure at various stages in a semiconductor processing process according to an exemplary embodiment of the present disclosure;

[0013] Figure 3 is a schematic flow chart of a semiconductor processing method according to an exemplary embodiment of the present disclosure;

[0014] Figure 4 is a schematic diagram of a process for removing an oxide layer according to an exemplary embodiment of the present disclosure;

[0015] Figure 5 is a schematic flow chart of a semiconductor processing method according to an exemplary embodiment of the present disclosure;

[0016] Figure 6 is a schematic diagram of a process of removing a portion of a first polysilicon layer according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part without departing from the teaching of the present disclosure.

[0018] Spatially relative terms such as "below," "beneath," "lower," "below," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figure. It will be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as "below other elements or features" or "below other elements or features" or "below other elements or features" will be oriented to "above other elements or features." Therefore, the exemplary terms "below" and "below" can cover both orientations above and below. Terms such as "before" or "before" and "after" or "followed by" can be similarly used, for example, to indicate the order in which light passes through the elements. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used in this article are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between two layers,” it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0019] The terms used herein are only for the purpose of describing a specific embodiment and are not intended to limit the present disclosure. As used herein, the singular forms "one", "one" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the existence of the features, integral bodies, steps, operations, elements and / or parts when used in this specification, but do not exclude the existence of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups or add one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" refers to only A, only B, or both A and B.

[0020] It will be understood that when an element or layer is referred to as being "on another element or layer," "connected to another element or layer," "coupled to another element or layer," or "adjacent to another element or layer," it may be directly on another element or layer, directly connected to another element or layer, directly coupled to another element or layer, or directly adjacent to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on another element or layer," "directly connected to another element or layer," "directly coupled to another element or layer," or "directly adjacent to another element or layer," there are no intermediate elements or layers. However, in no case should "on..." or "directly on..." be interpreted as requiring that one layer completely cover the layer below.

[0021] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the zones of the device and are not intended to limit the scope of the present disclosure.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0023] Polysilicon gate is a key component used in transistors. By adding a polysilicon gate film to the gate of the transistor, the performance of the transistor can be improved. The preparation process of the polysilicon gate film usually includes preparing a gate oxide layer on a silicon substrate, and then growing multiple gate layers on the gate oxide layer, and each gate layer is isolated by an insulating layer. The gate layer is usually made of polysilicon material, and the insulating layer is usually silicon nitride material. Figure 1A As shown, the polysilicon gate film structure includes two gate layers: a first polysilicon layer 120 and a second polysilicon layer 140, both of which are made of polysilicon materials. The material of the insulating layer 130 is silicon nitride (SiN).

[0024] In the current manufacturing process of very large-scale integrated circuits, multi-layer manufacturing technology has become an effective way to improve circuit performance and circuit function complexity. However, the superposition effect of the multi-layer structure will cause ups and downs on the surface of the wafer, and the flattening uniformity is poor. This may cause the performance of the semiconductor device to decline, and may even cause some functions to fail. Therefore, in the semiconductor device manufacturing process, the flattening uniformity of the wafer has a very important impact on the performance of the semiconductor device. In order to improve the flattening uniformity of the wafer, it is often necessary to use chemical or physical methods to flatten the polysilicon gate film structure in the wafer. For example, chemical-mechanical planning (CMP) or etching (Etch) operations can be used to flatten the polysilicon gate film structure. Figure 1B The polysilicon gate film structure is shown after CMP is performed on the second polysilicon layer 140 . Figure 1C The polysilicon gate film structure after the insulating layer 130 is etched is shown. Since polysilicon materials may undergo natural oxidation during the manufacturing process to form oxides such as silicon dioxide (SiO2), this will cause the junction between the gate layer and the insulating layer (i.e., the contact surface between the first polysilicon layer 120 and the insulating layer 130 and the contact surface between the second polysilicon layer 140 and the insulating layer 130) to contain a variety of substances including polysilicon, silicon nitride, oxides, etc. When CMP or etching operations are performed on the junction, due to the complexity of the interface material, the planarization uniformity is poor, such as Figure 1C As shown in FIG. 1 , after the etching operation, there are still multiple high-convex areas on the upper surface of the polysilicon gate film structure. Near these high-convex areas, the film is easily affected by heat, current or mechanical stress, etc., which may cause some functions of the semiconductor device to fail.

[0025] The embodiment of the present disclosure provides a polysilicon gate thin film structure, in which a first polysilicon layer, an oxide layer and a second polysilicon layer are sequentially arranged on a substrate with a floating gate layer. This will reduce the types of substances existing at the junctions between different layers, improve the uniformity of CMP of the polysilicon gate thin film structure, and improve the flatness of the wafer.

[0026] As used herein, the term "substrate" may refer to a substrate of a cut wafer, or may refer to a substrate of an uncut wafer. The term "floating gate layer" may refer to a floating gate prepared in a previous process in a semiconductor manufacturing process, which may include a multilayer structure and multiple shallow trench isolation regions, etc. It should be understood that the term "layer" includes a thin film and should not be interpreted as indicating a vertical or horizontal thickness unless otherwise specified.

[0027] Figure 2AFIG. 1 is a schematic diagram of a polysilicon gate film structure 100 according to an exemplary embodiment of the present disclosure. Figure 2A As shown, the polysilicon gate thin film structure 100 includes a substrate with a floating gate layer 110 , a first polysilicon layer 120 , an oxide layer 150 and a second polysilicon layer 140 .

[0028] The substrate may be any type of semiconductor substrate on an insulator. The substrate includes a floating gate layer 110. It should be understood that although Figure 2A As not shown in FIG. 1 , the floating gate layer 110 may include a multi-layer structure. Figure 2A As shown, in the floating gate layer 110 , there may be a plurality of shallow trench isolation regions 111 . The multi-layer structure in the floating gate layer 110 may be arranged on the shallow trench isolation region 111 .

[0029] The first polysilicon layer 120 is disposed on the floating gate layer 110. In some embodiments, the first polysilicon layer 120 may be deposited on the floating gate layer 110. The thickness of the first polysilicon layer 120 may be designed according to factors such as the function and performance of the semiconductor device, which is not limited in the present disclosure.

[0030] The oxide layer 150 is disposed on the first polysilicon layer 120. The oxide layer 150 serves as a stop layer for chemical mechanical polishing.

[0031] In some embodiments, the material of the oxide layer 150 includes silicon dioxide. Using silicon dioxide to generate the oxide layer 150 can make the types of substances present at the interface between the first polysilicon layer 120 and the oxide layer 150 and the interface between the second polysilicon layer 140 and the oxide layer 150 relatively simple, for example, only polysilicon and silicon dioxide exist.

[0032] In some embodiments, the thickness of the oxide layer 150 is greater than or equal to 200 angstroms and less than or equal to 500 angstroms. By properly setting the thickness of the oxide layer 150, the planarization effect of the polysilicon gate film structure 100 during semiconductor processing can be improved.

[0033] The second polysilicon layer 140 is disposed on the oxide layer 150. The second polysilicon layer 140 serves as a starting layer for chemical mechanical polishing. The thickness of the second polysilicon layer 140 can be designed according to factors such as the function and performance of the semiconductor device, which is not limited in the present disclosure.

[0034] When CMP is performed on the polysilicon gate thin film structure 100, it can start from the second polysilicon layer 140 until the oxide layer 150 is exposed. The second polysilicon layer 140 is gradually polished and flattened during the CMP process. When the second polysilicon layer 140 is polished to a certain extent, the oxide layer 150, which serves as a CMP stop layer, will be exposed.

[0035] Figure 3 FIG. 3 is a flow chart of a semiconductor processing method 300 according to an exemplary embodiment of the present disclosure. The semiconductor processing method 300 is applied to the polysilicon gate film structure 100 described in the above embodiment. Figures 2A to 2C and Figure 3 A semiconductor processing method 300 is described.

[0036] like Figure 3 As shown, the semiconductor processing method 300 includes steps 310 to 320 .

[0037] Step 310, performing a first chemical mechanical polishing operation on the second polysilicon layer 140 to expose the oxide layer 150 from the second polysilicon layer 140. The relevant process parameter settings of the first chemical mechanical polishing operation can be designed according to factors such as the function and performance of the semiconductor device, and the present disclosure does not limit this.

[0038] Step 320 , removing the oxide layer 150 .

[0039] like Figure 2A As shown, in step 310, a first chemical mechanical polishing operation may be performed starting from the upper surface of the second polysilicon layer 140. During the first chemical mechanical polishing process, the second polysilicon layer 140 is gradually polished away. The oxide layer 150 serves as a stop layer for chemical mechanical polishing. When the oxide layer 150 is exposed from the second polysilicon layer 140 (e.g., Figure 2B As shown), the first chemical mechanical polishing operation is stopped, and then step 320 is performed.

[0040] In some embodiments, Figure 4 As shown, step 320 includes step 410 or step 420 .

[0041] In step 410 , a second chemical mechanical polishing operation is performed on the oxide layer 150 .

[0042] The relevant process parameter settings of the second chemical mechanical polishing operation can be designed according to factors such as the function and performance of the semiconductor device. In an example, the relevant process parameter settings of the second chemical mechanical polishing operation can be consistent with the relevant process parameter settings of the first chemical mechanical polishing operation.

[0043] Step 420 , performing a first etching operation on the oxide layer 150 .

[0044] The relevant process parameter settings of the first etching operation can be designed according to factors such as the function and performance of the semiconductor device. In some embodiments, the first etching operation can use an etch back operation to increase the etching depth, thereby forming a more complex three-dimensional structure, effectively improving the three-dimensional structure of the polysilicon gate film, and improving the integration and performance.

[0045] Figure 5 FIG. 3 is another flow chart of a semiconductor processing method 300 according to an exemplary embodiment of the present disclosure. Figure 5 As shown, the semiconductor processing method 300 may further include a step 330 after the step 320 : removing a portion of the first polysilicon layer 120 until the thickness of the polysilicon gate film structure 100 reaches a target thickness.

[0046] In some embodiments, after removing the oxide layer 150, the polysilicon gate thin film structure 100 may still not meet the use requirements, for example, the planarization uniformity of the polysilicon gate thin film structure 100 may not meet the use requirements, the thickness of the polysilicon gate thin film structure 100 may not meet the use requirements, etc. At this time, it is necessary to further remove a portion of the first polysilicon layer 120 until the thickness of the polysilicon gate thin film structure 100 reaches the target thickness. The target thickness can be designed according to factors such as the function and performance of the semiconductor device, and the present disclosure is not limited to this.

[0047] In some embodiments, Figure 6 As shown, step 330 includes step 610 or step 620 .

[0048] Step 610 , performing a third chemical mechanical polishing operation on the first polysilicon layer 120 .

[0049] The process parameters of the third CMP operation may be designed according to the function and performance of the semiconductor device. In an example, the process parameters of the first, second and third CMP operations may be set to be consistent with each other.

[0050] Step 620 , performing a second etching operation on the first polysilicon layer 120 .

[0051] The relevant process parameter settings of the second etching operation can be designed according to factors such as the function and performance of the semiconductor device. The second etching operation can also use a back etching operation. In an example, the relevant process parameter settings of the second etching operation can be consistent with the relevant process parameter settings of the first etching operation.

[0052] In some embodiments, the removal rate of the second polysilicon layer 140 is equal to the removal rate of the first polysilicon layer 120 .

[0053] In this article, the term "removal rate" can also be expressed as "Material Removal Rate (MRR)". "Removal rate" can be used to describe the speed of change of the surface height of the polysilicon gate film structure, which is usually related to parameters such as the relative sliding rate between the film and the polishing pad in CMP and the etching rate in the etching operation.

[0054] In some embodiments, a ratio of a removal rate of the oxide layer 150 to a removal rate of the first polysilicon layer 120 is greater than or equal to 1:1.2 and less than or equal to 1.2:1.

[0055] In an example, the ratio of the removal rate of the oxide layer 150 to the removal rate of the first polysilicon layer 120 is 1:1.

[0056] As can be seen from the above, the type of substance existing at the junction of the oxide layer 150 and the first polysilicon layer 120 is relatively single. Therefore, the removal rate of the oxide layer 150 and the removal rate of the first polysilicon layer 120 can be set to a relatively close value or to the same value, so as to obtain better planarization uniformity and simplify the processing technology.

[0057] By designing and monitoring the removal rates of various materials in each layer, the efficiency of the processing process can be improved while improving the planarization uniformity of the polysilicon gate film structure.

[0058] Figure 2C FIG. 3 shows a polysilicon gate film structure 100 after a semiconductor processing method 300 is performed. Figure 1C By comparison, it can be seen that, compared with the insulating layer 130 made of silicon nitride material in the prior art, the oxide layer 150 can achieve better planarization uniformity.

[0059] The embodiment of the present application provides a wafer. The wafer may include the polysilicon gate film structure 100 as described in the above embodiment. The semiconductor processing method 300 as described in the above embodiment may be used in the process of preparing the wafer.

[0060] An embodiment of the present application also provides a semiconductor integrated circuit, which includes the wafer as described in the above embodiment.

[0061] Although the present disclosure has been illustrated and described in detail in the drawings and in the foregoing description, such illustration and description should be considered illustrative and exemplary rather than restrictive; the present disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure and the appended claims, those skilled in the art will be able to understand and implement variations to the disclosed embodiments when practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps that are not listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A polysilicon gate thin film structure, comprising: A substrate with a floating gate layer; A first polysilicon layer is arranged on the floating gate layer; an oxide layer, disposed on the first polysilicon layer, the oxide layer serving as a stop layer for chemical mechanical polishing; as well as The second polysilicon layer is disposed on the oxide layer, and the second polysilicon layer serves as a starting layer for chemical mechanical polishing.

2. The polysilicon gate film structure according to claim 1, wherein: The material of the oxide layer includes silicon dioxide.

3. The polysilicon gate film structure according to claim 1 or 2, wherein: The thickness of the oxide layer is greater than or equal to 200 angstroms and less than or equal to 500 angstroms.

4. A semiconductor processing method, applied to the polysilicon gate thin film structure according to any one of claims 1 to 3, comprising: performing a first chemical mechanical polishing operation on the second polysilicon layer to expose the oxide layer from the second polysilicon layer; as well as The oxide layer is removed.

5. The semiconductor processing method according to claim 4, wherein: The removing of the oxide layer comprises: performing a second chemical mechanical polishing operation on the oxide layer; or A first etching operation is performed on the oxide layer.

6. The semiconductor processing method according to claim 4, further comprising: After removing the oxide layer, a portion of the first polysilicon layer is removed until the thickness of the polysilicon gate film structure reaches a target thickness.

7. The semiconductor processing method according to claim 6, wherein: The removing a portion of the first polysilicon layer comprises: performing a third chemical mechanical polishing operation on the first polysilicon layer; or A second etching operation is performed on the first polysilicon layer.

8. The semiconductor processing method according to claim 6, wherein: The removal rate of the second polysilicon layer is equal to the removal rate of the first polysilicon layer.

9. The semiconductor processing method according to any one of claims 6 to 8, wherein: A ratio of a removal rate of the oxide layer to a removal rate of the first polysilicon layer is greater than or equal to 1:1.2 and less than or equal to 1.2:

1.

10. The semiconductor processing method according to claim 9, wherein: The ratio of the removal rate of the oxide layer to the removal rate of the first polysilicon layer is 1:

1.

11. A wafer obtained by the semiconductor processing method according to any one of claims 4 to 10.

12. A semiconductor integrated circuit comprising the wafer as claimed in claim 11.

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