A semiconductor structure and its preparation method, and radio frequency power amplifier

Abstract

The present invention discloses a semiconductor structure and a preparation method thereof, and a radio frequency power amplifier. The semiconductor structure includes a substrate and at least one first device and at least one second device arranged on the same side of the substrate, the first device and the second device are connected in series; the first device and the second device connected in series constitute a semiconductor device string, and the devices at both ends of the semiconductor device string are the first device and the second device respectively; the first device is a metal oxide semiconductor field effect transistor, and the second device is a laterally diffused metal oxide semiconductor transistor; the first device includes a first channel region, and the second device includes a second channel region and a drift region, and the first channel region, the second channel region and the drift region are arranged along a first direction, and the drift region is located on the side of the second channel region away from the first channel region. Through the above scheme, the monolithic integration of the first device and the second device can be realized, so that the semiconductor structure has both high withstand voltage and high cut-off frequency characteristics.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof, and a radio frequency power amplifier. Background Art

[0002] The RF power amplifier is an indispensable key component in various wireless communication systems. It is mainly used to amplify the modulated RF signal output by the transceiver to obtain an RF signal that meets the needs of wireless communication. The structure of the RF power amplifier generally includes an input matching module, an output matching module, a bias module, a power supply module, and a semiconductor device. In the prior art, the semiconductor devices in the RF power amplifier cannot meet the requirements of high withstand voltage and high frequency at the same time, which limits the application of the RF power amplifier. Summary of the invention

[0003] The present invention provides a semiconductor structure and a preparation method thereof, and a radio frequency power amplifier, so that the semiconductor structure has both high withstand voltage and high cut-off frequency characteristics, and the radio frequency power amplifier can simultaneously meet the application requirements of high-power scenarios and wide bandwidth ranges.

[0004] In a first aspect, an embodiment of the present invention provides a semiconductor structure suitable for a radio frequency power amplifier, wherein the semiconductor structure includes a substrate and at least one first device and at least one second device disposed on the same side of the substrate, wherein the first device and the second device are connected in series; the first device and the second device connected in series constitute a semiconductor device string, wherein the devices at both ends of the semiconductor device string are the first device and the second device, respectively; the first device is a metal oxide semiconductor field effect transistor, and the second device is a laterally diffused metal oxide semiconductor transistor;

[0005] The first device includes a first channel region, and the second device includes a second channel region and a drift region. The first channel region, the second channel region and the drift region are arranged along a first direction, and the drift region is located on a side of the second channel region away from the first channel region, wherein the first direction is parallel to an extension direction of a plane where the substrate is located.

[0006] In a second aspect, an embodiment of the present invention further provides a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure provided by any embodiment of the present invention. The method for preparing the semiconductor structure includes:

[0007] providing a substrate;

[0008] At least one first device and at least one second device are prepared on the same side of a substrate; the first device and the second device are connected in series, the first device is a metal oxide semiconductor field effect transistor, and the second device is a laterally diffused metal oxide semiconductor transistor; the first device includes a first channel region, the second device includes a second channel region and a drift region, the first channel region, the second channel region and the drift region are arranged along a first direction, and the drift region is located on a side of the second channel region away from the first channel region, wherein the first direction is parallel to an extension direction of a plane where the substrate is located.

[0009] In a third aspect, an embodiment of the present invention further provides a radio frequency power amplifier, comprising: an input matching module, an output matching module, a bias module, a power supply module, and a semiconductor structure provided by any embodiment of the present invention;

[0010] The second device at one end of the semiconductor device string is electrically connected to the output matching module, and the first device at the other end of the semiconductor device string is grounded.

[0011] The semiconductor structure provided by the embodiment of the present invention includes a substrate and at least one first device and at least one second device arranged on the same side of the substrate, the first device and the second device are connected in series; the first device and the second device connected in series constitute a semiconductor device string, and the devices at both ends of the semiconductor device string are respectively the first device and the second device; the first device is a metal oxide semiconductor field effect transistor, and the second device is a laterally diffused metal oxide semiconductor transistor; the first device includes a first channel region, and the second device includes a second channel region and a drift region, the first channel region, the second channel region and the drift region are arranged along a first direction, and the drift region is located on the side of the second channel region away from the first channel region, wherein the first direction is parallel to the extension direction of the plane where the substrate is located. Through the above scheme, the monolithic integration of the first device and the second device can be realized, so that the semiconductor structure has both high withstand voltage and high cut-off frequency characteristics. The RF power amplifier made using the semiconductor structure can simultaneously meet the application requirements of high-power scenarios and wide bandwidth ranges. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of the structure of a radio frequency power amplifier in a related technology provided by an embodiment of the present invention;

[0013] Figure 2 A schematic diagram of the structure of a radio frequency power amplifier in another related technology provided by an embodiment of the present invention;

[0014] Figure 3 A schematic diagram of a semiconductor structure provided by an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of the structure of a radio frequency power amplifier provided by an embodiment of the present invention;

[0016] Figure 5 A layout of a first device and a second device provided in an embodiment of the present invention;

[0017] Figure 6 Another layout of the first device and the second device provided in an embodiment of the present invention;

[0018] Figure 7 A schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention;

[0019] Figure 8 Another layout of the first device and the second device provided in the embodiment of the present invention;

[0020] Fig. 9 Another layout of the first device and the second device provided in the embodiment of the present invention;

[0021] Fig.10 A schematic structural diagram of another semiconductor structure provided by an embodiment of the present invention;

[0022] Fig.11 Another layout of the first device and the second device provided in the embodiment of the present invention;

[0023] Fig.12 Another layout of the first device and the second device provided in the embodiment of the present invention;

[0024] Fig.13 A schematic flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present invention;

[0025] Fig.14 A schematic diagram of the structure of another radio frequency power amplifier provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0027] Figure 1 A schematic diagram of the structure of a radio frequency power amplifier in a related technology provided by an embodiment of the present invention, Figure 2 A schematic diagram of the structure of a radio frequency power amplifier in another related technology provided by an embodiment of the present invention. Figure 1 and Figure 2In the related art, the semiconductor devices in the RF power amplifier are selected from Metal Oxide Semiconductor Field-Effect Transistor (MOSFET), namely MOS tube, or Laterally Diffused Metal Oxide Semiconductor (LDMOS), namely LDMOS tube. The inventors have found that the RF power amplifier prepared by using MOS tube has the risk of breakdown in the application of RF power amplifier due to the limited withstand voltage of MOS tube. Therefore, it can only be applied to small and medium power, which greatly limits the application of RF power amplifier in higher power scenarios. The RF power amplifier prepared by using LDMOS tube, although LDMOS has a higher withstand voltage and is suitable for higher power scenarios, the cut-off frequency of LDMOS tube is low, so it can only be applied to lower frequency application scenarios, which greatly limits the application of RF power amplifier in a wider frequency band.

[0028] Based on the above-mentioned problems of related technologies, the present invention proposes a semiconductor device, which is applied to a radio frequency power amplifier. The semiconductor structure includes a substrate and at least one first device and at least one second device arranged on the same side of the substrate, the first device and the second device are connected in series; the first device and the second device in series constitute a semiconductor device string, and the devices at both ends of the semiconductor device string are the first device and the second device respectively; the first device is a metal oxide semiconductor field effect transistor, and the second device is a laterally diffused metal oxide semiconductor transistor;

[0029] The first device includes a first channel region, and the second device includes a second channel region and a drift region. The first channel region, the second channel region and the drift region are arranged along a first direction, and the drift region is located on a side of the second channel region away from the first channel region, wherein the first direction is parallel to an extension direction of a plane where the substrate is located.

[0030] Through the above scheme, the monolithic integration of the first device and the second device can be achieved, so that the semiconductor structure has both high withstand voltage and high cutoff frequency characteristics. The RF power amplifier made using the semiconductor structure can meet the application requirements of high power scenarios and wide bandwidth range at the same time.

[0031] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Figure 3 A schematic diagram of a semiconductor structure provided by an embodiment of the present invention, Figure 4 A schematic diagram of a radio frequency power amplifier according to an embodiment of the present invention can be found in Figure 3 and Figure 4 In an embodiment of the present invention, a semiconductor structure 100 includes a substrate 10 and at least one first device 20 and at least one second device 30 arranged on the same side of the substrate 10, the first device 20 and the second device 30 are connected in series; the first device 20 and the second device 30 connected in series constitute a semiconductor device string, and the devices at both ends of the semiconductor device string are the first device 20 and the second device 30 respectively; the first device 20 is a metal oxide semiconductor field effect transistor, and the second device 30 is a laterally diffused metal oxide semiconductor transistor; the first device 20 includes a first channel region 201, and the second device 30 includes a second channel region 301 and a drift region 302, the first channel region 201, the second channel region 301 and the drift region 302 are arranged along a first direction X, and the drift region 302 is located on a side of the second channel region 301 away from the first channel region 201, wherein the first direction X is parallel to the extension direction of the plane where the substrate 10 is located.

[0033] like Figure 3 and Figure 4 As shown, the semiconductor structure 100 provided in the embodiment of the present invention includes a substrate 10. The specific type of the substrate 10 is not limited, for example, it can be a silicon substrate, etc., but is not limited thereto. A first device 20 (i.e., a MOS transistor) and a second device 30 (i.e., an LDMOS transistor) are formed on the same side of the substrate 10, and the two devices are arranged in series. Among them, the embodiment of the present invention does not limit the number of the first device 20 and the second device 30 in the same semiconductor structure 100, Figure 3 In the figure, a first device 20 and a first second device 30 are taken as an example, but the present invention is not limited thereto.

[0034] By integrating the first device 20 and the second device 30 into a semiconductor structure 100 , the semiconductor structure 100 has both high withstand voltage and high cutoff frequency characteristics.

[0035] It should be noted that, in the embodiment of the present invention, at least one first device 20 and at least one second device 30 connected in series constitute a semiconductor device string, one end of the semiconductor device string should be the first device 20, and the other end should be the second device 30. In this setting, when the semiconductor structure 100 is connected to other modules in the RF power amplifier, it can be ensured that the first device 20 and the second device 30 are connected to the other modules respectively.

[0036] When the semiconductor structure 100 includes a plurality of first devices 20 and a plurality of second devices 30 , on the basis of ensuring that the devices at both ends of the semiconductor device string are respectively the first devices 20 and the second devices 30 , the arrangement order of the middle first devices 20 and the second devices 30 is not limited.

[0037] For example, Figure 4 For example, the RF power amplifier includes an input matching module 200, an output matching module 300, a bias module 400, a power supply module 500 and a semiconductor structure 100. The semiconductor structure 100 is connected between the input matching module 200 and the output matching module 300. In the semiconductor structure 100, the first device 20 at one end of the semiconductor device string is electrically connected to the input matching module 200 and grounded, and the second device 30 at the other end of the semiconductor device string is electrically connected to the output matching module 300. The RF power amplifier using the semiconductor structure 100 provided by the embodiment of the present invention has the advantages of the high cut-off frequency characteristics of the MOS tube below (i.e., close to the ground end) and the high withstand voltage characteristics of the LDMOS tube above (i.e., close to the output end). Applying the semiconductor structure 100 to the RF power amplifier can enable the RF power amplifier to meet the application requirements of high-power scenarios and wide bandwidth ranges.

[0038] Further, continue to refer to Figure 3 and Figure 4 The first device 20 includes a first channel region 201, and the second device 30 includes a second channel region 301 and a drift region 302. The drift region 302 is the key to the design of the LDMOS tube. The impurity concentration in this region is low, forming a high resistance region. The second channel region 301 and the drift region 302 are adjacent. When the LDMOS tube is connected to a high voltage, the drift region 302 can withstand a higher voltage to ensure the stability of the second device 30.

[0039] Among them, Figure 3 As shown, the first channel region 201, the second channel region 301 and the drift region 302 are all located on the same side of the substrate 10, and the drift region 302 is located on the side of the second channel region 301 away from the first channel region 201 along the first direction X. The first direction X is the horizontal direction in the figure, that is, the extension direction of the substrate 10. In this arrangement, the monolithic integration of the first device 20 and the second device 30 can be achieved, and the first device 20 and the second device 30 can be connected in series.

[0040] Optionally, the embodiment of the present invention does not limit the doping types of the first channel region 201, the second channel region 301 and the drift region 302, and those skilled in the art can set them according to actual needs. For example, taking an N-type MOS transistor and an N-type LDMOS transistor as examples, the first channel region 201, the second channel region 301 and the drift region 302 can all be N-type doped, and the drift region 302 uses a lighter N-type doping.

[0041] The semiconductor structure provided by the embodiment of the present invention includes a substrate and at least one first device and at least one second device arranged on the same side of the substrate, the first device and the second device are connected in series; the first device and the second device connected in series constitute a semiconductor device string, and the devices at both ends of the semiconductor device string are respectively the first device and the second device; the first device is a metal oxide semiconductor field effect transistor, and the second device is a laterally diffused metal oxide semiconductor transistor; the first device includes a first channel region, and the second device includes a second channel region and a drift region, the first channel region, the second channel region and the drift region are arranged along a first direction, and the drift region is located on the side of the second channel region away from the first channel region, wherein the first direction is parallel to the extension direction of the plane where the substrate is located. Through the above scheme, the monolithic integration of the first device and the second device can be realized, so that the semiconductor structure has both high withstand voltage and high cut-off frequency characteristics. The RF power amplifier made using the semiconductor structure can simultaneously meet the application requirements of high-power scenarios and wide bandwidth ranges.

[0042] Optional, you can continue to refer to Figure 3 and Figure 4 The first device 20 further includes a first source region 202, a first drain region 203, a first source electrode 20S and a first drain electrode 20D; along the first direction X, the first source region 202 is located on a side of the first channel region 201 away from the second channel region 301, and the first drain region 203 is located on a side of the first channel region 201 facing the second channel region 301; the first source electrode 20S is located on a side of the first source region 202 away from the substrate 10, and the first drain electrode 20D is located on a side of the first drain region 203 away from the substrate 10. one side; the second device 30 also includes a second source region 303, a second drain region 304, a second source 30S and a second drain 30D. Along the first direction X, the second source region 303 is located on the side of the second channel region 301 away from the drift region 302, the second drain region 304 is located on the side of the drift region 302 away from the second channel region 301, the second source 30S is located on the side of the second source region 303 away from the substrate 10, and the second drain 30D is located on the side of the second drain region 304 away from the substrate 10.

[0043] like Figure 3As shown, the first channel region 201 may include a first source region 202 and a first drain region 203 on both sides along the first direction X, and the first source region 202 and the first drain region 203 are adjacent to the first channel region 201 respectively, and the doping depths of the first channel region 201, the first source region 202 and the first drain region 203 may be similar or the same. Taking an N-type MOS transistor as an example, the first source region 202 and the first drain region 203 may be N-type heavily doped. The source and drain of the first device 20 are respectively a first source 20S and a first drain 20D. In the direction perpendicular to the substrate 10, the first source 20S is located on the side of the first source region 202 away from the substrate 10 and in contact with the first source region 202, and the first drain 20D is located on the side of the first drain region 203 away from the substrate 10 and in contact with the first drain 20D.

[0044] Correspondingly, the second channel region 301 and the drift region 302 may include a second source region 303 and a second drain region 304 on both sides along the first direction X, the second source region 303 is adjacent to the side of the second channel region 301 away from the drift region 302, and the second drain region 304 is adjacent to the side of the drift region 302 away from the second channel region 301. The doping depths of the second channel region 301, the drift region 302, the second source region 303 and the second drain region 304 may be similar or the same. Taking the N-type LDMOS transistor as an example, the second source region 303 and the second drain region 304 may be N-type heavily doped. The source and drain of the second device 30 are respectively a second source 30S and a second drain 30D. Along the direction perpendicular to the substrate 10, the second source 30S is located on the side of the second source region 303 away from the substrate 10 and in contact with the second source region 303, and the second drain 30D is located on the side of the second drain region 304 away from the substrate 10 and in contact with the second drain 30D.

[0045] The source region and the drain region of the first device 20 and the second device 30 are heavily doped so that the two regions have a high electron concentration, thereby providing good electron injection and electron collection capabilities.

[0046] Optional, such as Figure 3 As shown, the distance between the first source region 202 and the first drain region 203 along the first direction X may be smaller than the distance between the second source region 303 and the second drain region 304 along the first direction X, thereby providing sufficient space for the drift region 302 .

[0047] Exemplarily, in some embodiments, the first channel region 201 and the second channel region 301 may be set to have the same length in the first direction X. In this way, the difference between the first device 20 and the second device 30 is only in the setting of the drift region 302 in the second device 30, and the source region, channel region, drain region and other structures of the first device 20 and the second device 30 may be prepared using the same preparation process.

[0048] Further, you can continue to refer to Figure 3The first device 20 further includes a first gate 20G, which is located on a side of the first channel region 201 away from the substrate 10 ; the second device 30 further includes a second gate 30G, which is located on a side of the second channel region 301 away from the substrate 10 .

[0049] The first gate 20G is the control electrode of the first device 20, and the first gate 20G controls the on or off state of the first device 20. The first channel region 201 forms a conductive channel under the control of the gate voltage of the first gate 20G, so that the first source 20S and the first drain 20D are conductive. The second gate 30G is the control electrode of the second device 30, and the second gate 30G controls the on or off state of the second device 30. The second channel region 301 forms a conductive channel under the control of the gate voltage of the second gate 30G, so that the second source 30S and the second drain 30D are conductive.

[0050] The first source 20S, the first drain 20D, the first gate 20G, the second source 30S, the second drain 30D and the second gate 30G are made of conductive materials such as metals. The embodiment of the present invention does not elaborate on or limit the materials and preparation processes of the electrodes.

[0051] Optionally, in an embodiment of the present invention, the first drain region 203 and the second source region 303 are independently spaced apart, and the first drain 20D and the second source 30S are connected; or, the first drain region 203 and the second source region 303 are reused, and the first drain 20D and the second source 30S are reused.

[0052] Figure 5 A layout of a first device and a second device provided in an embodiment of the present invention, Figure 6 Another layout of the first device and the second device provided by an embodiment of the present invention. Figure 6 for Figure 5 The mirror-symmetric design scheme corresponding to the layout design shown, Figure 6 The reference numerals of the various structures are not shown in the figure. Figure 5 As shown. Figure 3 , Figure 5 and Figure 6As shown, in some embodiments, the semiconductor parts of the first device 20 and the second device 30 are independently arranged, that is, the semiconductor regions of the first device 20 and the second device 30 close to each other are relatively independent and not connected to each other, and the semiconductor regions of the first device 20 and the second device 30 close to each other are the first drain region 203 and the second source region 303, and the first drain region 203 and the second source region 303 can be separated by an insulating material. In this arrangement, both semiconductor devices include independently arranged source regions and drain regions. In order to realize the series connection of the first device 20 and the second device 30, the first drain 20D and the second source 30S can be arranged to be connected into an integrated structure, and the first drain 20D and the second source 30S can be prepared at the same time.

[0053] Figure 7 A schematic diagram of another semiconductor structure provided by an embodiment of the present invention, Figure 8 Another layout of the first device and the second device provided in an embodiment of the present invention, Fig. 9 Another layout of the first device and the second device provided in the embodiment of the present invention. Fig. 9 for Figure 8 The mirror-symmetric design scheme corresponding to the layout design shown, Fig. 9 The reference numerals of the various structures are not shown in the figure. Figure 8 As shown. Figure 7-Figure 9 As shown, in other embodiments, some semiconductor parts of the first device 20 and the second device 30 are connected to each other, that is, the semiconductor regions of the first device 20 and the second device 30 that are close to each other are the same region, and the first drain region 203 and the second source region 303 are heavily doped regions, which serve as both the drain region of the first device 20 and the source region of the second device 30. Correspondingly, the first drain 20D and the first source 20S are the same electrode, which serves as both the drain of the first device 20 and the source of the second device 30. In this embodiment, by merging the drain of the MOS tube with the source of the LDMOS tube, the occupied area of ​​the source and drain region (source and drain) can be reduced, thereby reducing the area of ​​the first device 20 and the second device 30, so that the semiconductor structure 100 has a smaller volume. In addition, by reducing the area of ​​the source and drain, the parasitic capacitance of the device can be effectively reduced, thereby improving the device performance.

[0054] Fig.10 A schematic diagram of a semiconductor structure according to another embodiment of the present invention is provided. Fig.11 Another layout of the first device and the second device provided in an embodiment of the present invention, Fig.12 Another layout of the first device and the second device provided in the embodiment of the present invention. Fig.12 for Fig.11 The mirror-symmetric design scheme corresponding to the layout design shown, Fig.12 The reference numerals of the various structures are not shown in the figure. Fig.11 As shown. Figure 10-12 As shown, in some other embodiments, the first device 20 also includes a first source region 202 and a first source electrode 20S, and along the first direction X, the first source region 202 is located on the side of the first channel region 201 away from the second channel region 301; the first source electrode 20S is located on the side of the first source region 202 away from the substrate 10; the second device 30 also includes a second drain region 304 and a second drain electrode 30D, and along the first direction X, the second drain region 304 is located on the side of the drift region 302 away from the second channel region 301, and the second drain electrode 30D is located on the side of the second drain region 304 away from the substrate 10; the first channel region 201 and the second channel region 301 are connected.

[0055] refer to Figure 10-12 In some embodiments of the present invention, the first drain region 203 (first drain 20D) of the first device 20 and the second source region 303 (second source 30S) of the second device 30 can be directly omitted, and the channel regions of the two are directly connected. Figure 4 As shown, since no other structures are connected in the connection path between the first device 20 and the second device 30, eliminating the electrodes connecting the first device 20 and the second device 30 will hardly affect the performance of the device and can further reduce the parasitic capacitance of the device.

[0056] Optional, you can continue to refer to Figure 3 In a possible embodiment, the semiconductor structure 100 further includes a buried oxide layer 40 and a shallow channel isolation layer 50, the buried oxide layer 40 is located on one side surface of the substrate 10; the first source region 202, the first channel region 201 and the first drain region 203 constitute a first semiconductor part of the first device 20, the second source region 303, the second channel region 301, the drift region 302 and the second drain region 304 constitute a second semiconductor part of the second device 30; the first semiconductor part, the second semiconductor part and the shallow channel isolation layer 50 are located on a side of the buried oxide layer 40 away from the substrate 10, and the first semiconductor part, the second semiconductor part and the shallow channel isolation layer 50 are arranged along the first direction X; the shallow channel isolation layer 50 surrounds the first semiconductor part and the second semiconductor part respectively.

[0057] like Figure 3 As shown, in the embodiment of the present invention, the semiconductor structure 100 can be prepared by a Silicon-On-Insulator (SOI) process. The SOI process is compatible with the preparation of MOS transistors and LDMOS transistors, thereby realizing single-chip integration of the first device 20 and the second device 30.

[0058] Specifically, the substrate 10 may be a silicon substrate, on which a buried oxide layer 40 (Buried Oxide, BOX layer) is provided. The entire buried oxide layer 40 covers one side surface of the substrate 10, plays the role of insulation between the device and the silicon substrate, and improves the performance and isolation of active and passive devices. The shallow trench isolation layer 50, the first semiconductor part of the first device 20, and the second semiconductor part of the second device 30 are located on the side surface of the buried oxide layer 40 away from the substrate 10. The shallow trench isolation layer 50, the first semiconductor part and the second semiconductor part are located in the same film layer, and the shallow trench isolation layer 50 (Shallow Trench Isolation, STI layer) surrounds the first semiconductor part, surrounds the first semiconductor part of the first device 20 to form an island, and the shallow trench isolation layer 50 also surrounds the second semiconductor part, surrounds the second semiconductor part of the second device 30 to form an island. The shallow trench isolation layer 50 can play the role of separating the first device 20 and the second device 30.

[0059] The buried oxide layer 40 and the shallow trench isolation layer 50 can both be made of silicon dioxide material, but are not limited thereto.

[0060] Of course, in actual application, the preparation process of the semiconductor structure 100 is not limited to the SOI process, and any process that is compatible with MOS transistors and LDMOS transistors is within the scope of the technical solution protected by the embodiment of the present invention. Optionally, in a possible embodiment, the semiconductor device string includes a first device 20 and a plurality of second devices 30.

[0061] Providing a larger number of second devices 30 in the semiconductor device string can improve the voltage resistance of the semiconductor structure 100; at the same time, providing a first device 20 can ensure that the semiconductor structure 100 has a higher cutoff frequency and ensure the performance of the semiconductor structure 100 in the high frequency band.

[0062] Based on the same concept, an embodiment of the present invention also provides a method for preparing a semiconductor structure, which is used to prepare a semiconductor structure provided by any embodiment of the present invention. The semiconductor structure can refer to Figure 3 . Fig.13 A schematic diagram of a method for preparing a semiconductor structure according to an embodiment of the present invention is provided. Fig.13 , the preparation method of the semiconductor structure comprises the following steps:

[0063] S110 , providing a substrate.

[0064] The specific type of the substrate is not limited, for example, it can be a silicon substrate, etc., but is not limited thereto.

[0065] S120 , preparing at least one first device and at least one second device on the same side of the substrate.

[0066] In which, the first device and the second device are connected in series, the first device is a metal oxide semiconductor field effect transistor, and the second device is a laterally diffused metal oxide semiconductor transistor; the first device includes a first channel region, the second device includes a second channel region and a drift region, the first channel region, the second channel region and the drift region are arranged along a first direction, and the drift region is located on a side of the second channel region away from the first channel region, wherein the first direction is parallel to the extension direction of the plane where the substrate is located.

[0067] The preparation process of the first device and the second device is not limited, and those skilled in the art can set it according to actual needs. Any process that is compatible with MOS tubes and LDMOS tubes is within the scope of the technical solution protected by the embodiments of the present invention.

[0068] Through the above scheme, the monolithic integration of the first device and the second device can be achieved, so that the semiconductor structure has both high withstand voltage and high cutoff frequency characteristics. The RF power amplifier made using the semiconductor structure can meet the application requirements of high power scenarios and wide bandwidth range at the same time.

[0069] Optionally, in some embodiments, after the above (S110), it may also include: preparing a buried oxide layer on the surface of one side of the substrate; preparing a shallow channel isolation layer in a partial area of ​​the buried oxide layer facing away from the substrate; (S120) may be further refined as: preparing a partial structure of the first device and a partial structure of the second device in a partial area of ​​the buried oxide layer facing away from the substrate, the partial structure of the first device and the partial structure of the second device being separated by the shallow channel isolation layer; preparing a first source, a first drain and a first gate that are independent of each other on a side of the partial structure of the first device facing away from the buried oxide layer, and preparing a second source, a second drain and a second gate that are independent of each other on a side of the partial structure of the second device facing away from the buried oxide layer.

[0070] In the embodiment of the present invention, the semiconductor structure can be prepared by SOI process. SOI process is compatible with the preparation of MOS tubes and LDMOS tubes, so as to realize single-chip integration of the first device and the second device.

[0071] Specifically, a buried oxide layer may be prepared on one side of the substrate surface first, and then a shallow channel isolation layer may be prepared on a partial area of ​​the buried oxide layer surface facing away from the substrate side. Along the first direction, the area between adjacent shallow channel isolation layers is the area where the first semiconductor part of the first device and the second semiconductor part of the second device are subsequently set. Furthermore, the first semiconductor part of the first device and the second semiconductor part of the second device may be prepared in the area between adjacent shallow channel isolation layers. The shallow channel isolation layer surrounds the first semiconductor part and the second semiconductor part, respectively, and may play the role of separating the first device and the second device.

[0072] The first semiconductor portion may include a first source region, a first channel region and a first drain region of a first device, and the second semiconductor portion may include a second source region, a second channel region, a drift region and a second drain region of a second device.

[0073] Furthermore, a first source electrode may be prepared on a side of the first source region away from the buried oxide layer, a first gate electrode may be prepared on a side of the first channel region away from the buried oxide layer, a first drain electrode may be prepared on a side of the first drain region away from the buried oxide layer, a second source electrode may be prepared on a side of the second source region away from the buried oxide layer, a second gate electrode may be prepared on a side of the second channel region away from the buried oxide layer, and a second drain electrode may be prepared on a side of the second drain region away from the buried oxide layer. The above electrodes may be prepared in the same or different process steps, which is not limited in the embodiments of the present invention.

[0074] The embodiment of the present invention does not limit the specific preparation method of each structure in the above-mentioned buried oxide layer, shallow trench isolation layer, first device and second device, and any existing preparation method can be selected for preparation.

[0075] The method for preparing a semiconductor structure provided by an embodiment of the present invention includes all technical features and corresponding beneficial effects of the semiconductor structure provided by any embodiment of the present invention, which will not be described in detail here.

[0076] The embodiment of the present invention further provides a radio frequency power amplifier, the structure of which can be referred to as Figure 4 The RF power amplifier includes an input matching module 200, an output matching module 300, a bias module 400, a power supply module 500 and a semiconductor structure 100 provided by any embodiment of the present invention; wherein the second device 30 at one end of the semiconductor device string is electrically connected to the output matching module 300, and the first device 20 at the other end of the semiconductor device string is grounded.

[0077] like Figure 4 As shown, one end of the input matching module 200 is the input end of the RF power amplifier, and the other end of the input matching module 200 is electrically connected to the first gate of the first device 20 in the semiconductor structure 100. The first source of the first device 20 is grounded, and the first drain is electrically connected to the second source of the second device 30. The second drain of the second device 30 is connected to one end of the output matching module 300, and the other end of the output matching module 300 is the output end of the RF power amplifier. The bias module 400 can be electrically connected to the gate of the first device 20 and the gate of the second device 30 respectively. One end of the power supply module 500 is connected to the power supply VCC, and the other end of the power supply module 500 is connected to the second drain of the second device 30 (i.e., the output matching module 300).

[0078] The specific structures of the input matching module, output matching module, bias module and power supply module are not limited and can refer to any prior art. The RF power amplifier made of the semiconductor structure provided by the embodiment of the present invention can meet the application requirements of high power scenarios and wide bandwidth range at the same time.

[0079] The radio frequency power amplifier provided in the embodiment of the present invention has all the technical features and corresponding beneficial effects of the semiconductor structure provided in any embodiment of the present invention, which will not be described in detail here.

[0080] For example, Fig.14 A schematic diagram of the structure of another radio frequency power amplifier provided in an embodiment of the present invention is shown in FIG. Fig.14 As shown, in a possible embodiment, the semiconductor device string includes a first device 20 and a plurality of second devices 30. A larger number of second devices 30 are provided in the semiconductor device string to improve the withstand voltage of the semiconductor structure 100; at the same time, a first device 20 is provided to ensure that the semiconductor structure 100 has a higher cutoff frequency and the performance of the semiconductor structure 100 in the high frequency band is ensured.

[0081] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that: Applicable to a radio frequency power amplifier, the semiconductor structure comprises a substrate and at least one first device and at least one second device arranged on the same side of the substrate, the first device and the second device are connected in series; the first device and the second device connected in series constitute a semiconductor device string, the semiconductor device string comprises one first device and a plurality of second devices; the devices at both ends of the semiconductor device string are the first device and the second device respectively; the first device is a metal oxide semiconductor field effect transistor, and the second device is a laterally diffused metal oxide semiconductor transistor; The first device includes a first channel region, the second device includes a second channel region and a drift region, the first channel region, the second channel region and the drift region are arranged along a first direction, the drift region is located on a side of the second channel region away from the first channel region, wherein the first direction is parallel to an extension direction of a plane where the substrate is located; the first channel region and the second channel region are connected; The first device further includes a first source region, and the second device further includes a second drain region. Along the first direction, the first source region is located on a side of the first channel region away from the second channel region, and the second drain region is located on a side of the drift region away from the second channel region.

2. The semiconductor structure according to claim 1, characterized in that: The first device further includes a first drain region, a first source electrode and a first drain electrode; along the first direction, the first drain region is located on a side of the first channel region facing the second channel region; the first source electrode is located on a side of the first source region facing away from the substrate, and the first drain electrode is located on a side of the first drain region facing away from the substrate; The second device also includes a second source region, a second source electrode and a second drain. Along the first direction, the second source region is located on a side of the second channel region away from the drift region, the second source electrode is located on a side of the second source region away from the substrate, and the second drain electrode is located on a side of the second drain region away from the substrate.

3. The semiconductor structure according to claim 2, characterized in that: The first drain region and the second source region are independently spaced apart, and the first drain electrode and the second source electrode are connected, or; The first drain region and the second source region are multiplexed with each other, and the first drain electrode and the second source electrode are multiplexed with each other.

4. The semiconductor structure according to claim 2, characterized in that: The semiconductor structure further includes a buried oxide layer and a shallow trench isolation layer, wherein the buried oxide layer is located on one side surface of the substrate; The first source region, the first channel region and the first drain region constitute a first semiconductor portion of the first device, and the second source region, the second channel region, the drift region and the second drain region constitute a second semiconductor portion of the second device; The first semiconductor part, the second semiconductor part and the shallow channel isolation layer are located on the side of the buried oxide layer away from the substrate, and the first semiconductor part, the second semiconductor part and the shallow channel isolation layer are arranged along the first direction; the shallow channel isolation layer surrounds the first semiconductor part and the second semiconductor part respectively.

5. The semiconductor structure according to claim 1, characterized in that: The first device further includes a first source electrode, which is located on a side of the first source region away from the substrate; The second device further includes a second drain, and the second drain is located at a side of the second drain region facing away from the substrate.

6. The semiconductor structure according to claim 1, characterized in that The first device further includes a first gate, the first gate being located on a side of the first channel region facing away from the substrate; The second device further includes a second gate, and the second gate is located on a side of the second channel region facing away from the substrate.

7. A method for preparing a semiconductor structure, characterized in that: Used to prepare the semiconductor structure according to any one of claims 1 to 6, the preparation method of the semiconductor structure comprising: providing a substrate; At least one first device and at least one second device are prepared on the same side of the substrate; the first device and the second device are connected in series, the first device is a metal oxide semiconductor field effect transistor, and the second device is a laterally diffused metal oxide semiconductor transistor; the first device includes a first channel region, the second device includes a second channel region and a drift region, the first channel region, the second channel region and the drift region are arranged along a first direction, and the drift region is located on a side of the second channel region away from the first channel region, wherein the first direction is parallel to an extension direction of a plane where the substrate is located.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: After providing the substrate, the method further comprises: Preparing a buried oxide layer on one surface of the substrate; Preparing a shallow trench isolation layer in a partial area of ​​the buried oxide layer away from the substrate; Preparing at least one first device and at least one second device on the same side of the substrate, comprising: A partial structure of the first device and a partial structure of the second device are prepared in a partial area of ​​the buried oxide layer away from the substrate, wherein the partial structure of the first device and the partial structure of the second device are separated by the shallow trench isolation layer; A first source, a first drain and a first gate are prepared independently of each other on the side of the partial structure of the first device away from the buried oxide layer, and a second source, a second drain and a second gate are prepared independently of each other on the side of the partial structure of the second device away from the buried oxide layer.

9. A radio frequency power amplifier, characterized in that: include: An input matching module, an output matching module, a bias module, a power supply module, and a semiconductor structure as described in any one of claims 1 to 6 above; The second device at one end of the semiconductor device string is electrically connected to the output matching module, and the first device at the other end of the semiconductor device string is grounded.

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