Semiconductor device structure and forming method thereof

Abstract

Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, a semiconductor device structure includes a plurality of vertically stacked semiconductor layers, a plurality of internal spacers, each internal spacer disposed between two adjacent semiconductor layers. The semiconductor device structure also includes a source / drain feature in contact with each of the internal spacers, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a capping layer disposed between the source / drain feature and each of the plurality of semiconductor layers.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to a semiconductor device structure and a method for forming the same, and more particularly to a semiconductor device structure and a method for forming the same that can improve the integrity of components. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in the materials and design of integrated circuits (ICs) have created multiple generations of integrated circuits, each with smaller and more complex circuits than the previous generation. In the development of integrated circuits, functional density (e.g., the number of interconnected devices per unit chip area) has generally increased, accompanied by a reduction in geometry (the size of the smallest component (or line) that can be formed using a process). Such a process of geometry reduction generally brings the benefits of improving production efficiency and reducing associated costs. However, such geometry reduction also increases the complexity of processing and manufacturing of integrated circuits. For example, transistors using nanostructured channels have been proposed to improve carrier mobility and drive current in the device. An inner spacer is usually set between the metal gate and the source / drain (S / D) structure to protect the source / drain (S / D) structure from damage that may occur during a subsequent gate replacement process. Although the formation of inner spacers is generally appropriate and sufficient to meet their intended purpose, they are not completely satisfactory in all aspects. Summary of the invention

[0003] Some embodiments of the present disclosure provide a semiconductor device structure. The structure includes a plurality of semiconductor layers stacked vertically, a plurality of internal spacers, each of which is disposed between two adjacent semiconductor layers. The structure also includes a source / drain feature in contact with each of the internal spacers, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a cap layer disposed between the source / drain feature and each of the plurality of semiconductor layers.

[0004] Some embodiments of the present disclosure further provide a semiconductor device structure. This structure includes a plurality of semiconductor layers stacked vertically, a plurality of internal spacers, and each internal spacer is disposed between two adjacent semiconductor layers. This structure also includes a source / drain feature in contact with each internal spacer, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a cap layer separating each of the semiconductor layers from the source / drain feature. A portion of at least one of the semiconductor layers and a portion of the cap layer define a first interface, and a portion of the internal spacers and the source / drain feature define a second interface, and the second interface is offset from the first interface.

[0005] Some embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a semiconductor layer stack above a substrate, the semiconductor layer stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, forming a fin structure from the semiconductor layer stack and the substrate, forming a sacrificial gate structure and a gate spacer above a portion of the fin structure, removing a portion of the fin structure not covered by the sacrificial gate structure and the gate spacer to expose a portion of the substrate, removing an edge portion of the second semiconductor layer to form cavities between adjacent first semiconductor layers, selectively forming a capping layer on an exposed surface of each of the first semiconductor layer and the second semiconductor layer, forming an internal spacer on the capping layer in the cavity, and forming a source / drain component on opposite sides of the sacrificial gate structure and the gate spacer, wherein the source / drain component is in contact with the capping layer and the internal spacer. The method also includes removing the sacrificial gate structure and the plurality of second semiconductor layers to expose a portion of the first semiconductor layer and the capping layer, and forming a gate electrode layer to surround an exposed portion of at least one of the plurality of first semiconductor layers, wherein the gate electrode layer is separated from the internal spacer by the capping layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following detailed description in conjunction with the accompanying drawings of the specification can better understand the content of the embodiments of the present disclosure. It should be emphasized that, according to standard practices in the industry, many components (features) are not drawn to scale. In fact, in order to clearly discuss, the sizes of various components may be arbitrarily increased or reduced.

[0007] Figure 1-6 is a perspective view of various stages of manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

[0008] Figure 7A-17AAccording to some embodiments of the present disclosure, Figure 6 The cross-sectional side view of various stages of the semiconductor device structure is taken along section AA.

[0009] Fig.9E is a cross-sectional side view of a semiconductor device structure according to some other embodiments of the present disclosure.

[0010] Fig.11E and Fig.11F is a cross-sectional side view of a semiconductor device structure according to some other embodiments of the present disclosure.

[0011] Fig.11G and Fig.11H According to some other embodiments of the present disclosure Fig.11F An enlarged schematic diagram of a portion of a semiconductor device structure in FIG.

[0012] Fig.12E and Fig.12F is a cross-sectional side view of a semiconductor device structure according to some other embodiments of the present disclosure.

[0013] Fig.17E and Fig.17F According to some other embodiments of the present disclosure Fig.17A An enlarged schematic diagram of a portion of the semiconductor device structure in FIG.

[0014] Figure 7B-17B According to some embodiments of the present disclosure, Figure 6 The cross-sectional side view of various stages of the semiconductor device structure is taken along the cross section BB.

[0015] Figure 7C-17C According to some embodiments of the present disclosure, Figure 6 Cross-sectional side views of various stages of the semiconductor device structure taken along section CC.

[0016] Figure 7D-17D According to some embodiments of the present disclosure, Figure 6 The cross-sectional side views of various stages of the semiconductor device structure are taken along section DD.

[0017] Description of reference numerals:

[0018] 100: Semiconductor device structure

[0019] 101: Base

[0020] 104: Semiconductor layer stacking

[0021] 106 first semiconductor layer

[0022] 108: Second semiconductor layer

[0023] 112: Fin structure

[0024] 114,119: Grooves

[0025] 116: Ibe

[0026] 118: Insulation material

[0027] 120: Isolation area

[0028] 130: Sacrificial gate structure

[0029] 131: Cavity

[0030] 132: Sacrificial gate dielectric layer

[0031] 134: Sacrificial gate electrode layer

[0032] 136: Mask layer

[0033] 138: Gate spacer

[0034] 143: Overlay

[0035] 143a: First sublayer ( / first part)

[0036] 143b: Second sublayer ( / second part)

[0037] 144: Internal spacer

[0038] 144a: Dielectric layer

[0039] 145a,145b: Gap

[0040] 146: Source / drain component (source epitaxial component / drain epitaxial component)

[0041] 162: Contact Etch Stop Layer

[0042] 164: First interlayer dielectric layer

[0043] 166: Opening

[0044] 180: Gate dielectric layer

[0045] 182: Gate electrode layer

[0046] 184: Silicide layer

[0047] 186: Source / drain contacts

[0048] 187,191: First interface

[0049] 189,193: Second interface

[0050] 190: Replacement gate structure

[0051] T1, T2, T3, T4: thickness

[0052] D1, D2, D3, D4: Concave distance

[0053] AA,BB,CC,DD: Section DETAILED DESCRIPTION

[0054] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present disclosure. Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first component is formed above or located on a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present disclosure may repeat component symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0055] Furthermore, spatially relative terms may be used herein, such as "below," "beneath," "lower," "above," "above," "on," "top," "higher," and other similar terms may be used herein to describe the relationship between an element or component as shown in the figures and other elements or components. Such spatially relative terms include different orientations of the device in use or operation in addition to the orientation shown in the drawings. The device can be rotated to other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptions used herein may also be interpreted based on the rotated orientation.

[0056] Although the embodiments of the present disclosure are discussed in relation to nanostructured channel field effect transistors (FETs), some aspects of the present disclosure may be used for other processes and / or other devices, such as planar FETs, fin field effect transistors (Fin-FETs), horizontal all-around gate (HGAA) FETs, vertical all-around gate (VGAA) FETs, and other suitable devices. Those skilled in the art will readily appreciate that other modifications that may be made are also within the scope of the present disclosure. In the case of a all-around gate (GAA) transistor structure, the all-around gate (GAA) transistor structure may be patterned by any suitable method. For example, one or more optical lithography processes, including double-patterning or multi-patterning, may be used to pattern the structure. Generally speaking, double-patterning or multi-patterning processes combine optical lithography processes with self-aligned processes so that the pitch of the pattern formed is smaller than the pitch that can be obtained using a single, direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can be used to pattern the GAA structure.

[0057] Figures 1 to 17D 1 shows a non-limiting process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that additional embodiments of the method may be Figures 1 to 17D Other steps are provided before, during, and after the processes shown, and some of the steps described below may be replaced or eliminated. The order of the steps / processes is not limited and may be interchanged.

[0058] Figure 1-6 1 is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 can be a semiconductor substrate. The substrate 101 can include a crystalline semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), indium phosphide (InP) or a combination thereof. In one embodiment, the material of the substrate 101 is silicon. The substrate 101 can be doped or undoped. The substrate 101 can be a bulk semiconductor substrate, such as a bulk silicon substrate as a wafer, a silicon-on-insulator (SOI) substrate, a multilayer or gradient substrate or the like.

[0059] The substrate 101 may include a plurality of regions that have been doped with impurities (eg, dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0060] The semiconductor layer stack 104 includes semiconductor layers made of different materials and arranged alternately to form nanosheet channels in a multi-gate device such as a nanosheet channel FET. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108 vertically stacked above the substrate 101. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 can be made of Si and the second semiconductor layer 108 can be made of SiGe. In some examples, the first semiconductor layer 106 can be made of SiGe and the second semiconductor layer 108 can be made of Si. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be other materials or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or a combination of any of the foregoing materials.

[0061] The first semiconductor layer 106 and the second semiconductor layer 108 may be formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the material layers of the semiconductor layer stack 104 may be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0062] The first semiconductor layer 106 or a portion thereof may form a nanosheet channel of the semiconductor device structure 100 in a subsequent manufacturing stage. The term "nanosheet" is used herein to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term also includes elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or rod-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanosheet channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanosheet transistor. This nanosheet transistor may be referred to as a nanowire transistor, a fully wrapped gate (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0063] Each first semiconductor layer 106 may have a thickness in the range of about 5 nm to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 may have a thickness in the range of about 2 nm to about 50 nm. Figure 1 The alternating arrangement shown is for illustrative purposes and is not intended to limit the content beyond the specific description in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of such semiconductor layers is dependent on the predetermined number of channels of the semiconductor device structure 100.

[0064] exist Figure 2In the embodiment of the present invention, the fin structure 112 is formed by a stack of semiconductor layers 104. Each fin structure 112 has an upper portion including a first semiconductor layer 106, a second semiconductor layer 108, and a well portion 116 formed by the substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using multiple patterning operations including optical lithography and etching processes. The aforementioned etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The optical lithography process may include forming a photoresist layer (not shown) above the hard mask layer, exposing the photoresist layer with a pattern, performing post-exposure bake processes, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process may be used to pattern the photoresist layer to form the aforementioned mask element. The etching process forms trenches 114 in the unprotected areas, through the hard mask layer, through the semiconductor layer stack 104 and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 may be etched using dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or a combination thereof.

[0065] exist Figure 3 In the embodiment, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trench 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization step, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon carbide nitride (SiCN), fluorine-doped silicate glass (FSG), a low dielectric constant (low-K) dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0066] exist Figure 4In the embodiment of the present invention, the insulating material 118 is recessed to form an isolation region 120. The recess of the insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. The recess of the insulating material 118 reveals the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with a surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101, or is located below it.

[0067] exist Figure 5 , one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Then, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. The gate spacers 138 may be formed, for example, by conformally depositing one or more layers for the gate spacers 138 and anisotropically etching the one or more layers. Although one sacrificial gate structure 130 is shown, two or more sacrificial gate structures 130 may be disposed along the X-direction in some embodiments.

[0068] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as silicon oxide (SiOx) or a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or a combination of the foregoing materials.

[0069] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 is used as a channel region of the semiconductor device structure 100. The portion of the fin structure 112 exposed on the opposite side of the sacrificial gate structure 130 is the source / drain (S / D) region that defines the semiconductor device structure 100. In some cases, some source / drain (S / D) regions can be shared between multiple transistors. For example, each of the S / D regions can be connected together and implemented as a multifunctional transistor. It should be understood that the source region and the drain region can be used interchangeably because the epitaxial components formed in these regions are substantially the same. The source / drain regions can refer to a source or a drain individually or collectively, depending on the content of the description.

[0070] exist Figure 6 In the embodiment of the present invention, by removing the portion of the fin structure 112 not covered by the sacrificial gate structure 130, the portion of the fin structure 112 in the S / D region (e.g., the region on the opposite side of the sacrificial gate structure 130) is recessed downward to below the top surface of the isolation region 120 (or the insulating region 118). The recessing of the portion of the fin structure 112 can be accomplished by an etching process, such as an isotropic or anisotropic etching process, or further can be selective with respect to one or more crystal planes of the substrate 101. The etching process can be a dry etch, such as RIE, neutral beam etching (NBE), etc., or a wet etch, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) or any suitable etchant. As a result of recessing the portion of the fin structure 112, trenches 119 can be formed in the source / drain (S / D) region.

[0071] Figure 7A-17A According to some embodiments, Figure 6 1 is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100 taken along section AA. Figure 7B-17B According to some embodiments, Figure 6 1 is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100 taken along section BB. Figure 7C-17C According to some embodiments, Figure 6 1 is a cross-sectional side view of various stages of manufacturing the semiconductor device structure 100 taken along section CC. Figure 7D-17D According to some embodiments, Figure 6 The cross-sectional side view of various stages of manufacturing the semiconductor device structure 100 is taken along the cross-sectional view DD of FIG. The cross-sectional view AA is located at the fin structure 112 ( Figure 4) in a plane along the X direction. Section BB is located in a plane perpendicular to section AA and is located in the sacrificial gate structure 130 along the Y direction. Section CC is located in a plane perpendicular to section AA and is located in the source / drain feature 146 ( Fig. 12A The cross section DD is a cross section of the second semiconductor layer 108 in a plane along the X direction.

[0072] exist Figures 8A-8D , edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms a plurality of cavities 131. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of silicon germanium and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 may be selectively etched using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0073] exist Figures 9A-9D In the embodiment of the present invention, after removing the edge portion of each second semiconductor layer 108, a cap layer 143 is selectively formed on the exposed surfaces of the first semiconductor layer 106, the second semiconductor layer 108, and the partially exposed well portion 116 of the substrate 101. The cap layer 143 may be selectively formed using any suitable selective deposition process, such as a cyclic deposition etching (CDE) epitaxial process or a selective etching growth (SEG). As will be discussed in more detail below, the precursors and temperature used to form the cap layer 143 may be controlled to achieve selective growth or preferential growth of the cap layer 143 on the semiconductor surface of the exposed well portion 116 of the substrate 101 above the dielectric surface of the first semiconductor layer 106, the second semiconductor layer 108, and the sacrificial gate structure 130. Alternatively, the capping layer 143 can be first formed entirely on the exposed surface of the semiconductor device structure 100, and then removed from the exposed surface of the sacrificial gate structure 130 by one or more selective etching processes (e.g., plasma treatment or atomic layer etching (ALE)) without damaging the capping layer 143 on the first semiconductor layer 106, the second semiconductor layer 108, and the exposed well portion 116 of the substrate 101.

[0074] In either case, the capping layer 143 acts as an etch stop layer to prevent the chemistry of the etchant (used during the subsequent removal of the second semiconductor layer 108) and / or germanium from penetrating into the subsequently formed inner spacers 144 ( Fig.11A and 11B If the inner spacer 144 is damaged, the etching process for removing the second semiconductor layer 108 may also remove the subsequently formed S / D features 146 ( Fig.13A ). This is because the atomic percentage of germanium of the second semiconductor layer 108 is similar to or lower than the atomic percentage of the material (e.g., SiGe:B) of the S / D component 146. Therefore, the S / D component 146 may be damaged or even completely removed by the etching process. Forming the capping layer 143 between the second semiconductor layer 108 and the subsequent internal spacer 144 can avoid or minimize damage to the internal spacer 144 during the removal of the second semiconductor layer 108, thereby protecting the integrity of the S / D component 146. The combined thickness of the capping layer 143 and the internal spacer 144 can avoid reliability issues such as time dependent dielectric breakdown (TDDB). The capping layer 143 can also reduce (at least 50%) and / or eliminate germanium diffusion (Gediffusion) from the second semiconductor layer 108 during subsequent high temperature processes, thereby enhancing device performance by at least 2% or more.

[0075] The capping layer 143 may be any suitable material capable of withstanding chemical attack during the subsequent removal of the second semiconductor layer 108. The capping layer 143 may be a semiconductor material, such as silicon. In some embodiments, the capping layer 143 is formed of pure silicon (e.g., intrinsic silicon or undoped silicon) or substantially pure silicon (e.g., substantially free of impurities, such as an impurity percentage of less than about 1%). In some embodiments, the capping layer 143 is formed of doped silicon. In the case where the capping layer 143 is doped silicon, a Group III element such as boron may be used as a dopant. In an exemplary embodiment, the capping layer 143 is boron-doped silicon (Si:B). In various embodiments, the dopant concentration of the capping layer 143 may be in the range of from about 1E1017cm -3 To about 5E20cm -3 In the range of, for example, about 3E21cm -3It has been observed that the capping layer 143 formed of boron-doped silicon can effectively block etching chemicals used to remove the second semiconductor layer 108 during the formation of nanostructured channels in a multi-gate device. Therefore, in some embodiments, the internal spacers 144 can be largely protected. Using boron-doped silicon (Si:B) as the capping layer 143 may be advantageous because the boron dopant may change the crystal orientation of the underlying material (e.g., the first semiconductor layer 106 and the wells 107, 109 of the substrate 101) to facilitate subsequent epitaxial S / D features 146 ( Fig.13A )’s growth.

[0076] In addition, the capping layer 143 may be made of a dielectric material such as nitride. Suitable dielectric materials for the capping layer 143 may include, but are not limited to, SiN, SiCN, SiON, SiOCN, or any suitable nitride-based dielectrics. The capping layer 143 may be formed by converting the first semiconductor layer 106, the second semiconductor layer 108, and a portion of the well 106 of the substrate 101 into a nitride layer. For example, a nitridation process such as a rapid thermal nitridation (RTN) process, a high pressure nitridation (HPN) process, or a decoupled plasma nitridation (DPN) process may be performed on the exposed surfaces of the first semiconductor layer 106, the second semiconductor layer 108, and the well 106 of the substrate 101. A portion of the second semiconductor layer 108, such as a surface portion of the second semiconductor layer 108, may be nitrided after the nitridation process. In the case where the second semiconductor layer 108 is SiGe, a surface portion of the second semiconductor layer 108 may be changed into SiGeN.

[0077] In some embodiments that may be combined with any one or more embodiments of the present disclosure, the cover layer 143 may be a multi-layer structure including two or more layers of the materials discussed herein. Fig.9DIn one exemplary embodiment shown, for example, the capping layer 143 may include a first sublayer 143a and a second sublayer 143b disposed between the first sublayer 143a and the second semiconductor layer 108. In the case where the capping layer 143 includes SiN, the first sublayer 143a (now the outer capping layer) of the capping layer 143 may be SiN having a first nitrogen content, and the second sublayer 143b (now the inner capping layer) of the capping layer 143 may be SiN having a nitrogen content lower than the first. That is, the nitrogen content in the capping layer 143 gradually decreases in a direction away from the surface of the nitride layer. This is applicable to the capping layer 143 formed on the first semiconductor layer 106 and the second semiconductor layer 108 and the well 106 of the substrate 101. In the case where the capping layer 143 includes SiN and Si:B, the first sublayer 143a (now the outer capping layer) of the capping layer 143 may be boron-doped silicon having a first nitrogen content, and the second sublayer 143b (now the inner capping layer) of the capping layer 143 may be boron-doped silicon having a second nitrogen content lower than the first nitrogen content. In the case where the capping layer 143 includes a first sublayer of SiN and a second sublayer of pure Si, a multilayer structure can be obtained by nitriding a portion of the pure silicon. In this case, the first sublayer 143a of the capping layer 143 (now the outer capping layer) can be SiN, and the second sublayer 143b of the capping layer 143 (now the inner capping layer) can remain as pure silicon.

[0078] In some embodiments where the capping layer 143 includes silicon (e.g., pure silicon or substantially pure silicon), the selective deposition of the capping layer 143 can be achieved by heating the semiconductor device structure 100 to a temperature of about 400 degrees Celsius to about 600 degrees Celsius, such as about 450 degrees Celsius to about 510 degrees Celsius, and exposing the exposed surface of the semiconductor device structure 100 to a precursor in a reaction chamber (i.e., in situ), the precursor comprising at least one silicon-containing precursor. The gas reaction of the silicon-containing precursor causes silicon to grow on the semiconductor surface (e.g., the exposed surface of the first semiconductor layer 106, the second semiconductor layer 108, and the well 116 of the substrate 101) instead of on the dielectric surface of the sacrificial gate structure 130 (e.g., the mask layer 136 and the gate spacer 138). Suitable silicon-containing precursors may include, but are not limited to, monosilane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10), dimethylsilane ((CH3)2SiH2), trimethylsilane (SiH(CH3)3), dichlorosilane (SiH2Cl2; DCS), trichlorosilane (SiHCl3; TCS), or the like. In one embodiment, the capping layer 143 is formed using a precursor containing SiH4. The formation of the capping layer 143 can be performed in a reaction chamber where epitaxial growth or CVD deposition is mainly performed.

[0079] Additionally or alternatively, the selective deposition of the capping layer 143 can be achieved by heating the semiconductor device structure 100 to a temperature of about 300 degrees Celsius to about 500 degrees Celsius, such as about 360 degrees Celsius to about 420 degrees Celsius, and exposing the exposed surface of the semiconductor device structure 100 to a precursor including at least a silicon-containing precursor (as exemplified above) in a reaction chamber (i.e., in situ) for a short period of time, such as about 3 seconds to about 10 seconds, such as about 5 seconds. In one embodiment, the silicon-containing precursor includes SiH4 and Si2H6. In another embodiment, the silicon-containing precursor includes SiH4. The capping layer 143 is formed comprehensively on the exposed surface of the semiconductor device structure 100, including the exposed dielectric surface of the sacrificial gate structure 130 and the exposed semiconductor surfaces of the first semiconductor layer 106, the second semiconductor layer 108, and the well 116 of the first semiconductor layer 108. Due to the short growth time and the property of silicon to preferentially grow on semiconductor surfaces rather than dielectric surfaces, the amount of capping layer 143 on the dielectric surface of the sacrificial gate structure 130 is much smaller than the amount of capping layer 143 on the semiconductor surfaces of the first semiconductor layer 106, the second semiconductor layer 108, and the well 116 of the substrate 101. Thereafter, the semiconductor device structure 100 is subjected to a treatment process to remove the capping layer 143 from the dielectric surface of the sacrificial gate structure 130, resulting in the selective deposition of the capping layer 143 on the exposed semiconductor surfaces of the first semiconductor layer 106, the second semiconductor layer 108, and the well 116 of the substrate 101. In some embodiments, the gate spacer 138, the sacrificial gate dielectric layer 132, and the optional sacrificial gate electrode layer 134 within the cavity 131 may remain in contact with the capping layer 143, such as Fig.9D shown.

[0080] The treatment process may be an etching process using plasma or material radicals. For example, the treatment process may use reactive species generated by hydrogen-containing gas in situ in the reaction chamber or upstream of the reaction chamber (e.g., from a remote plasma generator). Exemplary reactive species may include hydrogen plasma or neutral radical species, such as hydrogen radicals or hydrogen atoms. In some embodiments, the aforementioned treatment process is a plasma treatment process. The aforementioned plasma treatment may be any suitable plasma process, such as a decoupled plasma process, a remote plasma process, or a combination of the aforementioned. The plasma may be formed by a capacitively coupled plasma (CCP) source or an inductively coupled plasma (ICP) source driven by an RF power generator. In the case of using an ICP source, the plasma treatment may be performed in a remote plasma generator having a chamber wall, a ceiling, and a plasma source power applicator, the plasma source power applicator including a coil antenna disposed above the ceiling and / or around the chamber wall. The plasma source power applicator is coupled to an RF power source through an impedance matching network, which may use a continuous wave RF power generator or a pulsed RF power generator operating at a predetermined duty cycle. The power source ionizes the hydrogen-containing gas supplied to the remote plasma generator. The generated hydrogen ions may be filtered by a grounded showerhead disposed in the remote plasma generator to generate neutral radical species (e.g., hydrogen radicals) before being supplied to a process chamber in which the semiconductor device structure 100 is disposed. In an exemplary embodiment, the decoupled plasma process is formed by an ICP source driven by an RF power generator using a tunable frequency from about 2 MHz to about 13.56 MHz, and the process chamber is operated at a pressure in the range of about 10 mTorr to 1 Torr, a temperature of about 25 degrees Celsius to about 300 degrees Celsius, and a processing time of about 15 seconds to about 1 minute. The RF power generator is operated to provide power between about 50 watts and about 1000 watts, and the output of the RF power generator is controlled by a pulse signal with a duty cycle in the range of about 20% to about 80%.

[0081] In the case where the capping layer 143 comprises boron-doped silicon, the selective deposition of the capping layer 143 may be achieved by a CDE epitaxial process. The CDE epitaxial process may be performed in a process chamber at a temperature in a range between about 300° C. and 800° C., at a pressure in a range between about 1 Torr and 760 Torr, and for a duration in a range between about 20 seconds and 300 seconds. A first portion of the capping layer 143 is formed by exposing the semiconductor device structure 100 to a gas mixture comprising one or more silicon-containing precursors, a p-type dopant gas, and a carrier gas for a first period of time, followed by a selective etch in which the first portion of the capping layer 143 is exposed to an etching gas for a second period of time to selectively remove an amorphous portion or a polycrystalline portion of the capping layer 143 while leaving a crystalline portion of the capping layer 143 intact. A purge gas (e.g., nitrogen) may be flowed through the process chamber between the epitaxial growth and the selective etching. Gases suitable for the silicon-containing precursor may be the gases discussed above. Suitable boron-containing precursors may include, but are not limited to, borane (BH3), diborane (B2H6), boron trichloride (BCl3), triethyl borate (TEB), cycloborazine (B3N3H6) or alkyl-substituted derivatives of cycloborazine, or the like. In the case of using an etching gas (e.g., in a CDE epitaxial process or a SEG process), the deposition process may use one or more etching gases. Suitable etching gases may include, but are not limited to, hydrogen chloride (HCl), chlorine (Cl2), or the like. A diluent / purge gas, such as hydrogen (H2), nitrogen (N2) and / or argon (Ar), may be used with the precursor for forming the capping layer 143. In one embodiment, the capping layer 143 uses a precursor comprising SiH4 and DCS and B2H6. The formation of the capping layer 143 may be performed in a reaction chamber based on epitaxy or CVD. The silicon-containing precursor may be provided at a flow rate in the range of about 10 sccm to about 100 sccm, the dopant gas may be provided at a flow rate in the range of about 50 sccm to about 100 sccm, the carrier gas may be provided at a flow rate in the range of about 0 sccm to about 50,000 sccm, and the purge gas may be provided at a flow rate in the range of about 0 sccm to about 50,000 sccm. The epitaxial growth and selective etching of the CDE epitaxial process are repeated until the desired thickness of the capping layer 143 and the concentration of the above-mentioned dopants are achieved.

[0082] Fig.9EAn alternative embodiment is shown in which a capping layer 143 is formed on the first semiconductor layer 106 and the second semiconductor layer 108 within the cavity 131. In this embodiment, the capping layer 143 may be first deposited on the exposed surfaces of the sacrificial gate structure 130, the first semiconductor layer 106, and the second semiconductor layer 108 using a conformal deposition process such as atomic layer deposition (ALD). Precursors may be selected to make this conformal deposition process a non-selective deposition process, meaning that the capping layer 143 is fully formed on the exposed surfaces of the sacrificial gate structure 130 (e.g., the mask layer 136 and the gate spacers 138), the first semiconductor layer 106, the second semiconductor layer 108, the sacrificial gate dielectric layer 132, and the well 116 of the substrate 101. After forming the capping layer 143, a suitable etching process may be performed such that the capping layer 143 on the exposed surfaces of the semiconductor device structure 100 is etched. Since it is more difficult for the etchant to reach the capping layer 143 in the cavity 131, the etching process can remove the capping layer 143 on the sacrificial gate structure 130, the first semiconductor layer 106, and the well 106 of the substrate 101 at a faster rate than the removal rate of the capping layer 143 on the second semiconductor layer 108. This can result in the entire capping layer 143 on the sacrificial gate structure 130, the first semiconductor layer 106, and the well 106 of the substrate 101 being removed, while slightly removing the capping layer 143 on the first semiconductor layer 106 and the second semiconductor layer 108 in the cavity 131, as shown in FIG. Fig.9E As shown. An exemplary etching process may include exposing the exposed surfaces of the sacrificial gate structure 130, the first semiconductor layer 106, the second semiconductor layer 108, the sacrificial gate dielectric layer 132, and the well 116 of the substrate 101 to fluorine (F) radicals or to a gas mixture including hydrogen fluoride (HF) and ammonia (NH3) at a chamber temperature of about 0°C to about 50°C and a chamber pressure of about 100mTorr to about 500mTorr. In some embodiments, HF and NH3 may flow into the process chamber at a flow rate ratio of about 1 (HF):5 (NH3) to about 1 (HF):10 (NH3).

[0083] In any case, if Fig.9D The capping layer 143 shown may have a thickness of about 3 angstroms. To about 30 angstroms If the thickness is less than about 3 angstroms, The capping layer 143 may not effectively block the etchant used during the removal of the second semiconductor layer 108. On the other hand, if the thickness is greater than 30 angstroms, There may not be enough space to set the subsequently formed internal spacer 144, thereby reducing the effectiveness of the internal spacer 144. In addition, the thicker capping layer 143 may also take up too much space required for the subsequent formation of the metal gate. Due to the depression at the edge of the second semiconductor layer 108, the etching reaction at and / or near the edge area of ​​the second semiconductor layer 108 may be less effective. Therefore, the capping layer 143 in contact with the gate spacer 138 and the sacrificial gate dielectric layer 132 can have a thickness T1, and the capping layer 143 on the second semiconductor layer 108 can have a thickness T2 greater than the thickness T1. In this case, the thickness T2 can be approximately 5% to approximately 20% greater than the thickness T1.

[0084] The capping layer 143 at and / or adjacent to the second semiconductor layer 108 may have a shape according to the contour of the recessed second semiconductor layer 108. Fig.9D In the illustrated embodiment, the capping layer 143 is formed to have a curved profile (e.g., a concave shape) when viewed from the top. In some embodiments, the capping layer 143 may have a square or rectangular shape when viewed from the top, which may vary according to the edge profile of the recessed second semiconductor layer 108.

[0085] exist Figures 10A-10D In the embodiment, a dielectric layer 144a is deposited on the exposed surface of the semiconductor device structure 100. The dielectric layer 144a also fills the cavity 131 ( Fig. 8A ). The dielectric layer 144a may be made of a dielectric material different from the material of the capping layer 143. Suitable materials for the dielectric layer 144a may include, but are not limited to, SiO2, Si3N4, SiC, SiCP, SiON, SiOC, SiCN, SiOCN and / or other suitable materials. Other materials may also be used, such as low-k materials having a dielectric constant value of less than about 3.5. The dielectric layer 144a may be formed by a conformal deposition process (e.g., ALD). The thickness T3 of the dielectric layer 144a adjacent to the first semiconductor layer 106 (and the well 116 of the substrate 101) may be in the range of about 1 nm to about 4 nm, while the thickness T4 of the dielectric layer 144a adjacent to the second semiconductor layer 108 may be in the range of about 2 nm to about 10 nm. In some embodiments, the dielectric layer 144a is a single-layer structure. In some embodiments, the dielectric layer 144a is a multi-layer structure including two or more of the materials discussed herein.

[0086] exist Figures 11A-11D In the process, an etching process is performed so that only a portion of the dielectric layer 144a remains in the cavity 131 ( Fig. 9A) to form the internal spacer 144. The removal process may be any suitable etching process, such as dry etching, wet etching, or a combination thereof. The etching process may be a selective etching process using an etchant that selectively removes the dielectric layer 144a without substantially removing the capping layer 143. Removal of a portion of the dielectric layer 144a may be performed by an anisotropic etching process. During the aforementioned anisotropic etching process, the dielectric layer 144a within the cavity 131 is protected by the first semiconductor layer 106 and the capping layer 143. The remaining second semiconductor layer 108 is covered between the internal spacers 144 along the X direction. Fig.11D As shown, when viewed from the top, the exposed surfaces of the capping layer 143 and the inner spacer 144 within the cavity 131 are substantially coplanar or flush with the sidewall surfaces of the gate spacer 138. In some embodiments, the capping layer 143 on the well 106 of the substrate 101 is also removed.

[0087] Fig.11E According to some embodiments Fig.11A 1 is an enlarged view of a portion of the semiconductor device structure 100 shown in FIG. In this embodiment, the dimension of the inner spacer 144 along the Z direction is greater than the dimension of the second semiconductor layer 108 along the Z direction. Specifically, the capping layer 143 is a continuous layer disposed between the inner spacer 144, the first semiconductor layer 106, the second semiconductor layer 108, and the subsequently formed epitaxial source / drain (S / D) feature 146, and in contact with these layers and features ( Fig. 12A The capping layer 143 extends to separate the first semiconductor layer 106 from the inner spacers 144. Each inner spacer 144 is separated from an adjacent semiconductor layer (eg, the first semiconductor layer 106 and the second semiconductor layer 108) by the capping layer 143.

[0088] Fig.11F Shown based on Fig.9E 1, a schematic diagram of a semiconductor device structure 100 at a stage after forming an internal spacer 144. In some embodiments, the duration of the selective etching process can be controlled so that not only the capping layer 143 on the first surface (i.e., the vertical surface along the Z direction) of the first semiconductor layer 106 is removed, but also a portion of the capping layer 143 on the second surface (i.e., the horizontal surface along the X direction) of the first semiconductor layer 106 is removed. In these embodiments, during the removal of the portion of the dielectric layer 144a, the etchant used can etch both the dielectric 144a and the capping layer 143 within the cavity 131 ( Fig. 9A). The dielectric layer 144a is etched at a first removal rate, and the capping layer 143 is etched at a second removal rate. In some embodiments, the second removal rate is greater than the first removal rate, resulting in a recess distance D1 of the capping layer 143 (measured from the edge of the first semiconductor layer 106 to the edge of the capping layer 143) being greater than a recess distance D2 of the inner spacer 144 (measured from the edge of the first semiconductor layer 106 to the edge of the inner spacer 144), such as Fig.11G As shown. Specifically, the recessed distance D1 can form a gap 145a generally defined by the first semiconductor layer 106, the capping layer 143 and the inner spacer 144. Removing a portion of the capping layer 143 between the inner spacer 144 and the first semiconductor layer 106 results in a substantially C-shaped or U-shaped structure of the capping layer 143 disposed between adjacent first semiconductor layers 106. The remaining portion of the capping layer 143 is in contact with the first semiconductor layer 106, the second semiconductor layer and the inner spacer 144. The gap 145a can then be filled with a source / drain (S / D) feature 146 ( Fig. 12A ).

[0089] In some embodiments, the first removal rate is greater than the second removal rate, resulting in a recess distance D3 of the inner spacer 144 (measured from the edge of the first semiconductor layer 106 to the edge of the inner spacer 144) being greater than a recess distance D4 of the capping layer 143 (measured from the edge of the first semiconductor layer 106 to the edge of the capping layer 143). Fig.11H Similarly, the recessed distance D3 forms a gap 145 b , and the gap 145 b can be generally defined by the cover layer 143 and the inner spacer 144 .

[0090] exist Figures 12A-12DIn the embodiment of the present invention, an epitaxial source / drain (S / D) feature 146 is formed in the source / drain (S / D) region. The epitaxial source / drain (S / D) feature 146 can be grown laterally from the first semiconductor layer 106. The epitaxial source / drain (S / D) feature 146 can include one or more layers of Si, SiP, SiC and SiCP for an n-type FET, or one or more layers of Si, SiGe, Ge for a p-type FET. The epitaxial source / drain (S / D) feature 146 can be formed by an epitaxial growth method using selective epitaxial growth (SEG), CVD, ALD or MBE. The second semiconductor layer 108 below the sacrificial gate structure 130 is separated from the epitaxial source / drain (S / D) feature 146 by an internal spacer 144. The epitaxial source / drain (S / D) features 146 may be grown vertically and horizontally to form facets that may correspond to crystal planes of the material of the first semiconductor layer 106. In some cases, the epitaxial source / drain (S / D) features 146 of a fin structure may be grown and merged with the epitaxial source / drain (S / D) features 146 of an adjacent fin structure, such as Fig. 12C An example is shown.

[0091] The epitaxial source / drain (S / D) components 146 can be source / drain (S / D) regions. For example, one of a pair of epitaxial source / drain (S / D) components 146 located on one side of the sacrificial gate structure 130 can be a source region, and the other of a pair of epitaxial source / drain components 146 located on the other side of the sacrificial gate structure 130 can be a drain region. A pair of source / drain epitaxial components 146 includes a source epitaxial component 146 and a drain epitaxial component 146 connected by multiple channels (i.e., the first semiconductor layer 106). The source / drain regions can refer to a source or a drain individually or collectively, depending on the context. In the present disclosure, source and drain can be used interchangeably and their structures are basically the same.

[0092] In adopting Fig.11F In the case of an embodiment of the present invention, the epitaxial source / drain (S / D) features 146 may also contact the first semiconductor layer 106 , the inner spacer 144 , and a portion of the capping layer 143 . Fig.12E and Fig.12F According to some embodiments, the Fig.11G and Fig.11H 14. The embodiment of the present invention is a stage of the semiconductor device structure 100 after forming the epitaxial source / drain (S / D) feature 146. It can be seen that the epitaxial source / drain (S / D) feature 146 grows to the gap 145a ( Fig.11G ) and gap 145b( Fig.11H) and is in contact with the first semiconductor layer 106, the internal spacer 144 and the capping layer 143.

[0093] exist Figures 13A-13D In the embodiment of the present invention, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the top surface of the sacrificial gate structure 130, the top surface of the insulating material 118, the top surface of the epitaxial source / drain (S / D) feature 146, and the exposed surface of the semiconductor layer stack 104. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbide nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, the like, or a combination of the foregoing materials, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer 164 is formed on the CESL 162 over the semiconductor device structure 100. The material for the first ILD layer 164 may include a compound containing Si, O, C, and / or H, such as silicon oxide, TEOS oxide, SiCOH, and SiOC. Organic materials such as polymers may also be used for the first ILD layer 164. The first ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the first ILD layer 164, the semiconductor device structure 100 may be thermally treated to anneal the first ILD layer 164.

[0094] exist Figures 14A-14D In the embodiment, after forming the first ILD layer 164 , a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed.

[0095] exist Figures 15A-15D, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed in sequence. The removal of the sacrificial gate structure 130 and the second semiconductor layer 108 forms an opening 166 between the gate spacers 138 and between the adjacent first semiconductor layers 106. The first ILD layer 164 protects the epitaxial S / D features 146 during the removal process. The sacrificial gate structure 130 may be removed using plasma dry etching and / or wet etching. First, the sacrificial gate electrode layer 134 may be removed by any suitable process, such as dry etching, wet etching, or a combination of the foregoing, followed by the removal of the sacrificial gate dielectric layer 132, which may also be performed by any suitable process. For example, dry etching, wet etching, or a combination of the foregoing. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacers 138, the first ILD layer 164, the CESL 162, and the capping layer 143.

[0096] The removal of the sacrificial gate structure 130 exposes the first semiconductor layer 106 and the second semiconductor layer 108. The etching process may be any suitable etching process, such as dry etching, wet etching, or a combination of the foregoing. Then, the second semiconductor layer 108 is removed and the capping layer 143 on the inner spacer 144 is exposed. The etching process may be a selective etching process that removes the second semiconductor layer 108 but does not remove the capping layer 143, the gate spacer 138, the first ILD layer 164, the CESL 162, and the first semiconductor layer 106. In the case where the second semiconductor layer 108 is made of SiGe or Ge and the first semiconductor layer 106 is made of Si, the chemistry used in the selective wet etching process removes SiGe while substantially not affecting Si and the dielectric materials of the gate spacer 138, the capping layer 143, the inner spacer 144, the first ILD layer 164, and the CESL 162. In one embodiment, the second semiconductor layer 108 may be removed using a wet etchant, such as but not limited to hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), dry etchants such as fluorine-based (e.g., F2) or chlorine-based gases (e.g., Cl2), or any suitable isotropic etchant. When the etching process is completed, the portion of the first semiconductor layer 106 not covered by the inner spacer 144 and the capping layer 143 is exposed in the opening 166. The capping layer 143 enhances the protection of the inner spacer 144 and prevents the etchant from passing through the inner spacer 144 and damaging the epitaxial S / D features 146.

[0097] exist Figures 16A-16D, replacement gate structures 190 are formed. The replacement gate structures 190 may each include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interfacial layer (IL) (not shown) may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The interfacial layer may also be formed on the exposed surface of the substrate 101. The interfacial layer may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride, silicon oxynitride, oxynitride, or the like) formed by thermal oxidation or chemical oxidation of the first semiconductor layer 106, and / or a dielectric layer (e.g., hafnium silicate). Next, a gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100 (e.g., on the interfacial layer (if any), the sidewalls of the gate spacer 138, the top surface of the first ILD layer 164, the CESL 162, and the capping layer 143). The gate dielectric layer 180 may be formed of a material that is chemically different from the sacrificial gate dielectric layer 132. The gate dielectric layer 180 may include a high-k dielectric material, or be made of a high-k dielectric material, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), or other suitable high-k dielectric materials. The gate dielectric layer 180 may be a conformal layer formed by a conformal process, such as an ALD process, a PECVD process, a molecular beam deposition (MBD) process, the like, or a combination of the foregoing processes. The gate dielectric layer 180 may have a thickness in a range of about 0.3 nm to about 5 nm.

[0098] After forming the interface layer (if any) and the gate dielectric layer 180, a gate electrode layer 182 is formed on the gate dielectric layer 180. The gate electrode layer 182 fills the opening 166 ( Fig.15A) and surrounds a portion of each first semiconductor layer 106. The gate electrode layer 182 includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations of the foregoing materials. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) can be conformally (and sequentially, if more than one layer) deposited between the gate dielectric layer 180 and the gate electrode layer 182. The one or more optional conformal layers can include one or more barrier layers and / or capping layers, and one or more work-function tuning layers. The one or more barrier layers and / or capping layers may include or be tantalum and / or titanium nitride, silicon nitride, carbon nitride and / or aluminum nitride; tungsten nitride, carbon nitride and / or carbide; the like; or a combination of the foregoing materials. The one or more work function adjustment layers may include or be titanium and / or tantalum nitride, silicon nitride, carbon nitride, aluminum nitride, aluminum oxide and / or aluminum carbide; tungsten nitride, carbon nitride and / or carbide; cobalt; platinum; the like; or a combination of the foregoing materials.

[0099] Portions of the gate electrode layer 182, one or more optional conformal layers (if any), and the gate dielectric layer 180 above the top surface of the first ILD layer 164, the top surface of the CESL 162, and the top surface of the gate spacer 138 may be removed by a planarization process, such as by a CMP process. After the CMP process, the top surface of the first ILD layer 164, the top surface of the CESL 162, the top surface of the gate spacer 138, and the top surface of the gate electrode layer 182 are substantially coplanar.

[0100] exist Figures 17A-17DIn the embodiment of the present invention, contact openings are formed through the first ILD layer 164 and the contact etch stop layer (CESL) 162 to expose the epitaxial S / D features 146. Then, a silicide layer 184 is formed on the S / D epitaxial features 146, and source / drain (S / D) contacts 186 are formed in the contact openings on the silicide layer 184. The S / D contacts 186 may include a conductive material, such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. Although not shown, before forming the S / D contacts 186, a barrier layer (e.g., TiN, TaN, or the like) may be formed on the sidewalls of the contact openings.

[0101] After forming the contact opening, a silicide layer 184 is formed on the epitaxial S / D component 146. The silicide layer 184 conductively couples the epitaxial S / D component 146 to the S / D contact 186 subsequently formed in the contact opening. The silicide layer 184 can be formed by depositing a metal source layer above the epitaxial S / D component 146 and performing a rapid thermal annealing process. During the rapid thermal annealing process, a portion of the metal source layer above the epitaxial S / D component 146 reacts with silicon in the epitaxial S / D component 146 to form the silicide layer 184. Then, the unreacted portion of the metal source layer is removed. The silicide layer 184 may include a metal or metal alloy silicide, and the aforementioned metal includes a noble metal, a refractory metal, a rare earth metal, an alloy of the aforementioned metals, or a combination of the aforementioned. Next, a conductive material is formed in the contact opening, and a source / drain (S / D) contact 186 is formed. The conductive material may be made of one or more materials including Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, titanium nitride, and tantalum nitride. Although not shown, a barrier layer (e.g., TiN, TaN, or the like) may be formed on the sidewalls of the contact openings before forming the S / D contacts 186. Then, a planarization process such as CMP is performed to remove excess deposition of the contact material and expose the top surface of the gate electrode layer 182.

[0102] like Fig.17DAs shown, the capping layer 143 between two adjacent semiconductor layers 106 may include a first portion 143a and a second portion 143b. The first portion 143a extends between the inner spacer 144 and the gate dielectric layer 180 and contacts the inner spacer 144 and the gate dielectric layer 180. The second portion 143b is disposed between the inner spacer 144 and the gate spacer 138 and contacts the inner spacer 144 and the gate spacer 138. The second portion 143b of the capping layer 143 is also in contact with the source / drain (S / D) feature. The second portion 143b of the capping layer 143 may have a thickness T1, and the first portion 143a of the capping layer 143 may have a thickness T2 greater than the thickness T1.

[0103] Fig.17E According to some embodiments Fig.17A 1 is an enlarged schematic diagram of a portion of the semiconductor device structure 100 shown in FIG. In this embodiment, the capping layer 143 is a continuous layer disposed between and in contact with the inner spacers 144, the first semiconductor layer 106, the second semiconductor layer 108, and the epitaxial S / D component 146. The capping layer 143 extends to completely separate the first semiconductor layer 106 from the inner spacers 144. Each inner spacer 144 is separated from the first semiconductor layer 106 and the gate dielectric layer 180 by the capping layer 143. A portion of at least one of the first semiconductor layers 106 and a portion of the capping layer 143 define a first interface 187, and a portion of the inner spacer 144 and a portion of the epitaxial S / D component 146 define a second interface 189. In some embodiments, the first interface 187 and the second interface 189 are substantially aligned or coplanar. Some portions of the capping layer 143 extend into the epitaxial S / D component 146.

[0104] Fig.17F According to some embodiments Fig.17A FIG. 1 is an enlarged schematic diagram of a portion of a semiconductor device structure 100 shown in FIG. Fig.17F The embodiment shown in is similar to Fig.17E In the embodiment of the present invention, except that the inner spacer 144 is further recessed to allow a larger amount of the epitaxial S / D component 146 to extend into the area between the adjacent first semiconductor layers 106. Similarly, a portion of at least one of the first semiconductor layers 106 and a portion of the capping layer 143 define a first interface 191, and a portion of the inner spacer 144 and a portion of the epitaxial S / D component 146 define a second interface 193. In some embodiments, the first interface 191 and the second interface 193 are offset from each other (i.e., misaligned). Furthermore, some portions of the capping layer 143 extend into the epitaxial S / D component 146.

[0105] It should be understood that the semiconductor device structure 100 may be further subjected to complementary metal oxide semiconductor (CMOS) processes and / or back-end of line (BEOL) processes to form various components, such as transistors, contacts / vias, interconnect metal layers, dielectric layers, protection layers, etc. The semiconductor device structure 100 may further include backside contacts (not shown) on the back side of the substrate 101, so that the source or drain of the epitaxial S / D component 146 may be connected to a backside power rail (e.g., positive voltage VDD or negative voltage VSS) through the backside contacts.

[0106] Various embodiments or examples described herein provide multiple advantages over the prior art. According to embodiments of the present disclosure, the exposed surfaces of the first semiconductor layer 106 (nanostructure channel layer) and the second semiconductor layer 108 may be covered with a silicon-based capping layer 143 before forming the internal spacer 144 to prevent damage to the S / D components of the nanostructure channel FET caused by the release of the nanowire. The capping layer may reduce or eliminate germanium diffusion through the internal spacer at and / or near the end of the nanostructure channel during high temperature processes. The capping layer may also effectively block the etchant chemicals used during the replacement gate process, thereby protecting the integrity of the epitaxial S / D components.

[0107] One embodiment of the present disclosure is a semiconductor device structure. The structure includes a plurality of semiconductor layers stacked vertically, a plurality of internal spacers, each of which is disposed between two adjacent semiconductor layers. The structure also includes a source / drain feature in contact with each of the internal spacers, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a cap layer disposed between the source / drain feature and each of the plurality of semiconductor layers.

[0108] In some embodiments, according to the semiconductor device structure described above, each of the inner spacers has at least three surfaces in contact with the capping layer and one surface in contact with the source / drain feature.

[0109] In some embodiments, according to the above semiconductor device structure, a gate dielectric layer is further included, which is disposed between the gate electrode layer and each of the semiconductor layers.

[0110] In some embodiments, according to the semiconductor device structure, a portion of the capping layer is disposed between the gate dielectric layer and each of the inner spacers, and contacts the gate dielectric layer and each of the inner spacers.

[0111] In some embodiments, according to the above semiconductor device structure, a gate spacer is further included, contacting the capping layer and a portion of the gate dielectric layer.

[0112] In some embodiments, according to the semiconductor device structure, a portion of the capping layer is disposed between the gate spacer and each of the inner spacers, and is in contact with the gate spacer and each of the inner spacers.

[0113] In some embodiments, according to the semiconductor device structure, a portion of the capping layer is also in contact with the source / drain component.

[0114] In some embodiments, according to the above-mentioned semiconductor device structure, a portion of at least one of the aforementioned semiconductor layers and a portion of the aforementioned covering layer define a first interface, a portion of one of the aforementioned internal spacers and a portion of the source / drain component define a second interface, and the aforementioned first interface is aligned with the aforementioned second interface.

[0115] In some embodiments, according to the above-mentioned semiconductor device structure, a portion of at least one of the aforementioned semiconductor layers and a portion of the aforementioned covering layer define a first interface (first interface), a portion of one of the aforementioned internal spacers and a portion of the source / drain component define a second interface (second interface), and the aforementioned first interface and the aforementioned second interface are offset from each other.

[0116] Another embodiment of the present disclosure is a semiconductor device structure. The structure includes a plurality of semiconductor layers stacked vertically, a plurality of internal spacers, each of which is disposed between two adjacent semiconductor layers. The structure also includes a source / drain feature in contact with each internal spacer, a gate electrode layer surrounding a portion of each of the plurality of semiconductor layers, and a cap layer separating each of the semiconductor layers from the source / drain feature. A portion of at least one of the semiconductor layers and a portion of the cap layer define a first interface, and a portion of the internal spacers and the source / drain feature define a second interface, the second interface being offset from the first interface.

[0117] In some embodiments, according to the above-mentioned semiconductor device structure, a gate dielectric layer is further included between each of the above-mentioned semiconductor layers and the above-mentioned gate electrode layer.

[0118] In some embodiments, according to the semiconductor device structure, the portion of the capping layer is disposed between the gate dielectric layer and each of the inner spacers, and is in contact with the gate dielectric layer and each of the inner spacers.

[0119] In some embodiments, according to the semiconductor device structure, each of the inner spacers has a first side in contact with the capping layer and a second side in contact with the source / drain feature.

[0120] In some embodiments, according to the above semiconductor device structure, a gate spacer is further included, which is in contact with a portion of the gate dielectric layer, wherein another portion of the capping layer is also in contact with the gate spacer.

[0121] In some embodiments, according to the semiconductor device structure, a portion of the gate dielectric layer is disposed between the gate spacer and the gate electrode layer, and is in contact with the gate spacer and the gate electrode layer.

[0122] In some embodiments, according to the semiconductor device structure, a portion of the capping layer extends into the source / drain component.

[0123] In some embodiments, according to the above semiconductor device structure, the capping layer is pure silicon or doped silicon.

[0124] Another embodiment of the present disclosure is a method for forming a semiconductor device structure. The method includes forming a semiconductor layer stack above a substrate, the semiconductor layer stack including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately, forming a fin structure from the semiconductor layer stack and the substrate, forming a sacrificial gate structure and a gate spacer above a portion of the fin structure, removing a portion of the fin structure not covered by the sacrificial gate structure and the gate spacer to expose a portion of the substrate, removing an edge portion of the second semiconductor layer to form cavities between adjacent first semiconductor layers, selectively forming a capping layer on an exposed surface of each of the first semiconductor layer and the second semiconductor layer, forming an internal spacer on the capping layer within the cavity, and forming a source / drain component on opposite sides of the sacrificial gate structure and the gate spacer, wherein the source / drain component is in contact with the capping layer and the internal spacer. The method also includes removing the sacrificial gate structure and the plurality of second semiconductor layers to expose a portion of the first semiconductor layer and the capping layer, and forming a gate electrode layer to surround an exposed portion of at least one of the plurality of first semiconductor layers, wherein the gate electrode layer is separated from the internal spacer by the capping layer.

[0125] In some embodiments, according to the above-mentioned method of forming a semiconductor device structure, it also includes: before forming the aforementioned gate electrode layer, first forming a gate dielectric layer to surround a portion of each of the aforementioned first semiconductor layers, wherein a portion of the aforementioned covering layer is arranged between the aforementioned gate dielectric layer and the aforementioned internal spacer and in contact with the aforementioned gate dielectric layer and the aforementioned internal spacer.

[0126] In some embodiments, according to the above method for forming a semiconductor device structure, the capping layer is pure silicon or doped silicon.

[0127] The above summarizes the components of several embodiments so that those skilled in the art to which the present disclosure belongs can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure belongs should understand that they can easily design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art to which the present disclosure belongs should also understand that such equivalent structures do not deviate from the concept and scope of the present disclosure, and they can make various changes, substitutions and replacements without violating the concept and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be defined as defined by the claims.

Claims

1. A semiconductor device structure, characterized in that: Multiple semiconductor layers are stacked vertically; a plurality of inner spacers, each of the inner spacers being disposed between two adjacent semiconductor layers among the semiconductor layers; a source / drain feature in contact with each of the inner spacers; A gate electrode layer surrounds a portion of each of the semiconductor layers; as well as A capping layer is disposed between the source / drain feature and each of the semiconductor layers. 2 . The semiconductor device structure of claim 1 , wherein each of the inner spacers has at least three surfaces in contact with the capping layer and one surface in contact with the source / drain feature.

3. The semiconductor device structure of claim 1 , further comprising: A gate dielectric layer is disposed between the gate electrode layer and each of the semiconductor layers. 4 . The semiconductor device structure of claim 3 , wherein a portion of the capping layer is disposed between the gate dielectric layer and each of the inner spacers, and contacts the gate dielectric layer and each of the inner spacers.

5. The semiconductor device structure of claim 3, further comprising: A gate spacer contacts the capping layer and portions of the gate dielectric layer. 6 . The semiconductor device structure of claim 5 , wherein a portion of the capping layer is disposed between the gate spacer and each of the inner spacers and contacts the gate spacer and each of the inner spacers. 7 . The semiconductor device structure of claim 6 , wherein a portion of the capping layer also contacts the source / drain feature.

8. A semiconductor device structure, characterized in that: Multiple semiconductor layers are stacked vertically; A plurality of inner spacers, each of the inner spacers being disposed between two adjacent semiconductor layers; a source / drain feature in contact with each of the inner spacers; A gate electrode layer surrounds a portion of each of the semiconductor layers; as well as A capping layer separates each of the semiconductor layers from the source / drain feature, wherein a portion of at least one of the semiconductor layers and a portion of the capping layer define a first interface, and A portion of the inner spacers and the source / drain component define a second interface that is offset from the first interface. 9 . The semiconductor device structure of claim 8 , wherein a portion of the capping layer extends into the source / drain feature.

10. A method for forming a semiconductor device structure, characterized in that: Forming a semiconductor layer stack on a substrate, the semiconductor layer stack comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; forming a fin structure from the semiconductor layer stack and the substrate; forming a sacrificial gate structure and a gate spacer over a portion of the fin structure; removing a portion of the fin structure not covered by the sacrificial gate structure and the gate spacer to expose a portion of the substrate; Removing edge portions of the second semiconductor layers to form a cavity between adjacent first semiconductor layers; selectively forming a capping layer on an exposed surface of each of the first semiconductor layers and the second semiconductor layers; forming an inner spacer on the cover layer within the cavities; forming a source / drain feature on opposite sides of the sacrificial gate structure and the gate spacer, wherein the source / drain feature contacts the capping layer and the inner spacer; Removing the sacrificial gate structure and the second semiconductor layers to expose portions of the first semiconductor layers and the capping layer; as well as A gate electrode layer is formed to surround the exposed portion of at least one of the first semiconductor layers, wherein the gate electrode layer is separated from the inner spacer by the capping layer.

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