Solar cell and photovoltaic module

Abstract

The invention provides a solar cell and a photovoltaic module, and belongs to the technical field of solar cells. The solar cell comprises: a semiconductor substrate having a first surface and a second surface opposite to each other, and a plurality of first side surfaces adjacent between the first surface and the second surface; the passivation contact structure is at least located on a part of the first surface of the semiconductor substrate, and the passivation contact structure comprises an interface passivation layer and a first doped semiconductor layer which are stacked in sequence; wherein in the direction from the first surface to the second surface, the first side face comprises a first area and a second area which are adjacent in sequence, and the first area protrudes in the direction away from the first side face compared with the second area; the first doped semiconductor layer is further located on a part of the surface of the first region, and the first doped semiconductor layer located on the first region and the first doped semiconductor layer located on the first surface are integrally continuous; a portion of the surface of the first region adjacent to the second region is not covered with the first doped semiconductor layer.

Description

Technical Field

[0001] At least one embodiment of the present application relates to a solar cell, and more particularly to a solar cell and a photovoltaic module. Background Art

[0002] In the related art, a solar cell includes an N-type region and a P-type region, and a certain degree of electrical isolation is required between the N-type region and the P-type region. Generally, the N-type region and the P-type region can be separated by processes such as wet etching, but the existing methods are not perfect, and there is still a risk of leakage between the front and back of the solar cell.

[0003] At the same time, during the production and handling process, the edges of the battery are very likely to rub against each other, causing the passivation film to fall off or be scratched, leaving the substrate exposed on the outside. In this case, the surface passivation layer is destroyed, which will weaken the passivation performance of the battery and affect the battery performance. Summary of the invention

[0004] In view of this, it is necessary to provide a solar cell and a photovoltaic module formed by the solar cell in view of the defects of the solar cell in the related art.

[0005] According to an embodiment of one aspect of the present application, a solar cell is provided, including:

[0006] A semiconductor substrate having a first surface and a second surface opposite to each other, and a plurality of first side surfaces adjacent to the first surface and the second surface;

[0007] A passivation contact structure is located at least on a portion of the first surface of the semiconductor substrate, and the passivation contact structure includes an interface passivation layer and a first doped semiconductor layer stacked in sequence;

[0008] In which, in the direction from the first surface to the second surface, the first side surface includes a first region and a second region adjacent to each other in sequence, and the first region protrudes in a direction away from the first side surface compared to the second region; the first doped semiconductor layer is also located on a partial surface of the first region, wherein the first doped semiconductor layer located on the first region is integrally continuous with the first doped semiconductor layer located on the first surface; and a portion of the surface of the first region adjacent to the second region is not covered with the first doped semiconductor layer.

[0009] According to an embodiment of another aspect of the present application, a photovoltaic assembly is provided, comprising the above-mentioned solar cell.

[0010] According to the solar cell provided by the above-mentioned embodiments of the present application, in a direction parallel to the first surface, a first region of at least one first side surface is raised in a direction away from the first side surface compared to the second region, which is beneficial to increase the effective area of ​​the passivation contact structure of the first surface, improve the passivation contact performance of the first surface, improve the carrier collection efficiency, and thus improve the efficiency of the solar cell.

[0011] According to the solar cell provided by the above embodiment of the present application, in the direction parallel to the first surface, the first area of ​​at least one first side surface is raised in the direction away from the first side surface compared to the second area. Since the surface of the raised portion of the first area is at a certain distance from the surface of the first side surface, the electrical isolation between the front and back sides of the battery can be enhanced (the spatial electrical isolation distance between the first surface and the second surface), and the risk of leakage between the front and back sides can be reduced; at the same time, in the process of preparing the electrode, the slurry used to prepare the electrode can also be effectively prevented from leaking and distributing in a larger range on the side of the battery, causing serious damage to the electrical performance of the battery. In addition, due to the protrusion of the first area, the damage to the performance of the solar cell caused by scratches on the solar cell can be reduced.

[0012] According to the solar cell provided by the above embodiment of the present application, the first doped semiconductor layer is also located on a portion of the surface of the first region, which can increase the effective area of ​​the passivation contact structure and improve the carrier collection efficiency while reducing the risk of leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, rather than limiting the present application.

[0014] Figure 1 is a cross-sectional schematic diagram of a solar cell in the related art;

[0015] Figure 2 A partial cross-sectional schematic diagram of a solar cell in the related art;

[0016] Figure 3 A schematic top view of a semiconductor substrate provided in an embodiment of the present application;

[0017] Figure 4 A schematic cross-sectional view of a solar cell provided in an embodiment of the present application;

[0018] Figure 5 A partial cross-sectional schematic diagram of a solar cell provided in an embodiment of the present application;

[0019] Figure 6 A cross-sectional schematic diagram of a solar cell provided in another embodiment of the present application;

[0020] Figure 7 A cross-sectional schematic diagram of a solar cell provided in yet another embodiment of the present application;

[0021] Figure 8 A scanning electron microscope image of a first side of a solar cell provided in yet another embodiment of the present application;

[0022] Fig. 9 A partial cross-sectional schematic diagram of a solar cell provided in yet another embodiment of the present application;

[0023] Fig.10 A scanning electron microscope image of a first side of a solar cell provided in yet another embodiment of the present application;

[0024] Fig.11 A partial cross-sectional schematic diagram of a solar cell provided in yet another embodiment of the present application;

[0025] Fig.12 A cross-sectional schematic diagram of a solar cell provided in yet another embodiment of the present application;

[0026] Fig.13 A schematic cross-sectional view of a back-contact solar cell provided in an embodiment of the present application; and

[0027] Fig.14 A schematic top view of the first surface of a back-contact solar cell provided in an embodiment of the present application.

[0028] Description of reference numerals:

[0029] 1- semiconductor substrate;

[0030] A-first surface;

[0031] B-second surface;

[0032] C-first side;

[0033] C1 - first zone;

[0034] C2 - second area;

[0035] C3 - third area;

[0036] 11- a first semiconductor base;

[0037] 12- a second semiconductor base;

[0038] 13- a third semiconductor base portion;

[0039] d1 - the height of the protrusion of the first area;

[0040] d2-protrusion height of the third area;

[0041] 2-interface passivation layer;

[0042] 3-a first doped semiconductor layer;

[0043] 31- a third doped semiconductor layer;

[0044] 32- a fourth doped semiconductor layer;

[0045] 4-first passivation anti-reflection layer;

[0046] 5-a second doped semiconductor layer;

[0047] 6- second passivation anti-reflection layer;

[0048] 10- a first electrode;

[0049] 20- a second electrode;

[0050] 111-heavily doped semiconductor substrate layer;

[0051] 100-small number of children area;

[0052] 200-multiple sub-areas;

[0053] 300-Isolation area. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. However, the present application can be implemented in different forms and should not be construed as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the application thorough and complete, and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated, and the same reference numerals represent the same elements throughout.

[0055] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "include", "comprising", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0056] In the related art, for example, patent CN202410605390.9 provides a TOPCon battery that improves the risk of leakage of bifacial batteries. The side of the battery substrate has a doped silicon layer retained by plating. The surface of the area exposed outside the doped silicon layer on the side of the silicon substrate is etched by a corrosive solution to prevent the doped silicon layer from remaining on the surface of the area close to the doped silicon layer on the side of the silicon substrate to prevent short circuits. On the side of the silicon substrate, the surface of the area not corresponding to the doped silicon layer can be lower than the surface of the area corresponding to the doped silicon layer to further reduce the leakage risk of doped silicon layers of different doping types.

[0057] Similar to patent CN202410605390.9, such as Figure 1-Figure 2 The solar cell includes: a semiconductor substrate 1, the semiconductor substrate 1 has a first surface A and a second surface B relative to each other, and a first side surface C; an interface passivation layer 2 and a first doped semiconductor layer 3, which are located on the first surface A of the semiconductor substrate 1; and a first passivation anti-reflection layer 4; wherein, in the direction from the first surface A to the second surface B, the first side surface C of the semiconductor substrate includes adjacent first regions C1 and second regions C2, and the first region C1 is protruded in a direction away from the first side surface C compared to the second region C2.

[0058] refer to Figure 2 As shown, the first doped semiconductor layer 3 extends from the first surface A of the semiconductor substrate 1 and covers the first area C1 as a whole. Although the above method suppresses the leakage to a certain extent, the height of the first area C1 protruding relative to the second area C2 is limited, and if the doped silicon layer formed on the second surface B of the solar cell also has a plating retention area on the first side surface C, the risk of leakage is still very high.

[0059] In view of this, it is necessary to provide a solar cell and photovoltaic module to address the technical problems in the related technology that there is a risk of leakage between the front and back sides of the solar cell, and the sides are easily contaminated by metal slurry or scratched during transportation, resulting in reduced battery performance.

[0060] Figure 3 A schematic top view of a semiconductor substrate provided in an embodiment of the present application.

[0061] Figure 4 A schematic cross-sectional view of a solar cell provided in an embodiment of the present application.

[0062] According to an exemplary embodiment of the present application, the present application provides a solar cell, referring to Figure 3 , Figure 4 As shown, including:

[0063] A semiconductor substrate 1, wherein the semiconductor substrate 1 has a first surface A and a second surface B opposite to each other, and a plurality of first side surfaces C adjacent to the first surface A and the second surface B;

[0064] A passivation contact structure, located at least on a portion of the first surface A of the semiconductor substrate 1, the passivation contact structure comprising an interface passivation layer 2 and a first doped semiconductor layer 3 stacked in sequence;

[0065] In which, in the direction from the first surface A to the second surface B, the first side surface C includes a first region C1 and a second region C2 adjacent to each other in sequence, and the first region C1 is protruded in the direction away from the first side surface C compared with the second region C2; the first doped semiconductor layer 3 is also located on a partial surface of the first region C1, wherein the first doped semiconductor layer 3 located on the first region C1 is integrally continuous with the first doped semiconductor layer 3 located on the first surface A; and a portion of the surface of the first region C1 adjacent to the second region C2 is not covered with the first doped semiconductor layer 3.

[0066] That is, in the direction from the first surface A to the second surface B, the semiconductor substrate 1 includes a first semiconductor base portion 11 and a second semiconductor base portion 12 integrally formed with the first semiconductor base portion 11; the first side surface C includes a first region C1 located on the side surface of the first semiconductor base portion 11 and a second region C2 located on the side surface of the second semiconductor base portion 12, and the first region C1 of at least one first side surface C protrudes in a direction away from the first side surface C compared to the second region C2.

[0067] According to an embodiment of the present application, in a cross section parallel to the first surface A, an area of ​​the first semiconductor base portion 11 is greater than an area of ​​the second semiconductor base portion 12 .

[0068] According to an embodiment of the present application, a protrusion height d1 of the first region C1 compared to the second region C2 is 0.5 μm-5 μm, for example, 0.5 μm, 1 μm, 2 μm, or 5 μm, but is not limited to the above values.

[0069] According to an embodiment of the present application, the semiconductor substrate 1 may be a silicon substrate. Alternatively, the semiconductor substrate 1 may be a substrate made of any semiconductor material such as a germanium silicon substrate, a germanium substrate or a gallium arsenide substrate. In addition, the semiconductor substrate 1 may be an N-type semiconductor substrate or a P-type semiconductor substrate. The semiconductor substrate 1 may be a single crystal or a polycrystalline.

[0070] According to an embodiment of the present application, the shape of the semiconductor substrate 1 is a rectangle, and there is a chamfer between two adjacent sides of the rectangle. Figure 3 As shown, the semiconductor substrate 1 includes eight first side surfaces C, for example.

[0071] According to an embodiment of the present application, the passivation contact structure extends from the first surface A of the semiconductor substrate 1 to a partial surface of the first region C1 of at least one first side surface C. The passivation contact structure does not completely cover the first region C1, which can reduce the risk of short circuit caused by the passivation contact structure. In addition, there is a step structure between the first region C1 and the second region C2. On the side wall of the step structure, that is, on the connecting side wall between the first region C1 and the second region C2, there may be a doped region of the substrate. The first doped semiconductor layer 3 is easily in contact with the doped region on the step side wall, resulting in direct contact between the first doped semiconductor layer 3 and the semiconductor substrate 1, causing battery failure. Therefore, setting the first doped semiconductor layer 3 away from the side wall can avoid the above situation.

[0072] According to an embodiment of the present application, in a direction from the first surface A to the second surface B, a distance between the first doped semiconductor layer 3 located on the surface of the first region C1 and the second region C2 is greater than or equal to 1 μm.

[0073] According to an embodiment of the present application, in a direction perpendicular to the first surface A, a distribution width of the first doped semiconductor layer 3 in the first region A is less than 80% of a width of the first region A.

[0074] According to an embodiment of the present application, the ratio of the width of the first region C1 in the direction perpendicular to the first surface A to the thickness of the semiconductor substrate 1 is in the range of 1% to 20%, for example, 1%, 5%, 10%, 15%, 20%, but not limited to the values ​​cited. If the ratio range is too small, it is difficult to achieve the technical effect of increasing the passivation contact structure area and improving the carrier collection efficiency; if the ratio range is too large, the risk of leakage between the first surface A and the second surface B is prone to occur.

[0075] According to an embodiment of the present application, the thickness of the first semiconductor base 11 in a direction perpendicular to the first surface A ranges from 0.5μm to 20μm, for example, it can be 0.5μm, 1μm, 5μm, 10μm, 20μm, but is not limited to the listed values; the thickness of the first semiconductor base 11 in a direction perpendicular to the first surface A is the width of the first region C1 in the direction from the first surface A to the second surface B.

[0076] According to an embodiment of the present application, in a direction parallel to the first surface A, the first region C1 of at least one first side surface C is raised in a direction away from the first side surface C1 compared to the second region C2, which is beneficial to increasing the effective area of ​​the passivation contact structure of the first surface A, improving the passivation contact performance of the first surface A, improving the carrier collection efficiency, and thereby improving the efficiency of the solar cell.

[0077] According to the embodiment of the present application, in the direction parallel to the first surface A, the first region C1 of at least one first side surface C is raised in the direction away from the first side surface C compared to the second region C2. Since the surface of the raised portion of the first region is at a certain distance from the surface of the second region C2, the electrical isolation between the front and back sides of the battery can be enhanced, and the risk of leakage between the front and back sides can be reduced. At the same time, in the process of preparing the electrode, the slurry used to prepare the electrode can also be effectively prevented from leaking and distributing in a larger range on the side of the battery, causing serious damage to the electrical performance of the battery. In addition, due to the protrusion of the first region C1, the damage to the performance of the solar cell caused by scratches on the solar cell can be reduced.

[0078] Since the doping concentration of the doped semiconductor layer is usually large, leakage of the solar cell usually occurs between doped semiconductor layers of different doping types. In the case where the width of the first region C1 in the direction perpendicular to the first surface A is large, the first doped semiconductor layer 3 covering the first region C1 is prone to leakage with the second doped semiconductor layer 5 located on the second surface B.

[0079] By setting the width of the first region C1 to 1%-20% of the thickness of the semiconductor substrate and the first doped semiconductor layer 3 being located on a portion of the surface of the first region C1 , the risk of leakage between the first doped semiconductor 3 and the second surface B is reduced.

[0080] According to the solar cell provided by the above-mentioned embodiment of the present application, the first doped semiconductor layer is located on a partial surface of the first region, which can increase the effective area of ​​the passivation contact structure and improve the carrier collection efficiency while reducing the risk of leakage.

[0081] According to an embodiment of the present application, the solar cell may be a bifacial solar cell, such as a tunneling oxide passivated contact solar cell (Thin Oxide Passivated Contact, TOPCon) or a heterojunction solar cell (Heterojunction with Intrinsic Thin-layer, HJT).

[0082] According to an embodiment of the present application, the interface passivation layer 2 includes one of an intrinsic amorphous silicon layer, a low-doped intrinsic amorphous silicon layer (the doping concentration is lower than that of the first doped semiconductor layer) and a dielectric layer, and the dielectric layer includes but is not limited to silicon oxide, aluminum oxide, doped aluminum oxide, silicon nitride, and silicon carbonitride. The first doped semiconductor layer 3 is at least one of a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, a doped nanocrystalline silicon layer, and a doped amorphous silicon layer.

[0083] According to an embodiment of the present application, the interface passivation layer 2 is, for example, tunneling silicon oxide, and the first doped semiconductor layer 3 is, for example, doped polysilicon.

[0084] According to an embodiment of the present application, the interface passivation layer 2 is, for example, intrinsic amorphous silicon, and the first doped semiconductor layer 3 is, for example, doped amorphous silicon.

[0085] According to an embodiment of the present application, the TOPCon solar cell further includes: a second doped semiconductor layer 5, which is at least located within the second surface B of the semiconductor substrate 1 and serves as an emitter region (emitter) of the TOPCon solar cell; one of the second doped semiconductor layer 5 and the first doped semiconductor layer 3 is N-type, and the other of the second doped semiconductor layer 5 and the first doped semiconductor layer 3 is P-type.

[0086] According to an embodiment of the present application, the TOPCon solar cell further comprises a second passivation anti-reflection layer 6, which is at least located on the surface of the second doped semiconductor layer 5 away from the semiconductor substrate 1. The second passivation anti-reflection layer 6 is used to realize the passivation and anti-reflection functions of the second surface B of the semiconductor substrate 1.

[0087] Figure 5 A schematic partial cross-sectional view of a solar cell provided in an embodiment of the present application.

[0088] According to the embodiments of the present application, reference Figure 5 As shown, a heavily doped semiconductor substrate layer 111 is formed on the surface of the first surface A and the first region C1 of the semiconductor substrate 1. The heavily doped semiconductor substrate layer 111 here can be understood as having a doping concentration greater than the doping concentration of the semiconductor substrate 1 itself. Specifically, since doping elements need to be added in the process of forming the first doped semiconductor layer 3, some of the doping elements will diffuse into the semiconductor substrate 1, so that the concentration of the doping elements in the partial region of the semiconductor substrate 1 close to the first surface A and the first region C1 is greater than the doping concentration of the semiconductor substrate 1. Optionally, the heavily doped semiconductor substrate layer 111 can be located on a partial surface of the first region C1, or on the entire surface of the first region C1.

[0089] Figure 6 A cross-sectional schematic diagram of a solar cell provided in another embodiment of the present application.

[0090] According to the embodiments of the present application, reference Figure 6 As shown, the first region C1 of at least one first side surface C is an inclined surface extending from the side away from the first surface A to the side close to the first surface A in a direction away from the semiconductor substrate 1. In this way, the surface area of ​​the first surface A can be increased, and the area of ​​the passivation contact structure located on the first surface A can be increased, which is beneficial to improving the carrier collection efficiency. In addition, the surface distance of the entire first side surface in a direction perpendicular to the first surface A can be increased, which is more beneficial to the isolation between the first surface A and the second surface B.

[0091] According to an embodiment of the present application, the passivation contact structure extends from the first surface A of the semiconductor substrate 1 to a portion of the surface of the first region C1 of at least one first side surface C.

[0092] According to an embodiment of the present application, the interface passivation layer 2 and the first doped semiconductor layer 3 are also located on a portion of the surface of the first region C1, which can increase the surface area of ​​the passivation contact structure composed of the interface passivation layer 2 and the first doped semiconductor layer 3, improve the carrier collection efficiency, and thereby improve the efficiency of the solar cell.

[0093] According to the embodiment of the present application, the first area C1 is an inclined surface and is relatively flat, which is conducive to depositing a first passivation anti-reflection layer 4 with better film quality on the first side surface C, thereby improving the passivation and anti-reflection effects of the first passivation anti-reflection layer 4.

[0094] According to an embodiment of the present application, the passivation contact structure extends from the first surface A of the semiconductor substrate 1 to a portion of the surface of the first region C1 of at least one first side surface C. The passivation contact structure does not completely cover the first region C1, which can reduce the short circuit risk caused by the passivation contact structure.

[0095] Figure 7 A cross-sectional schematic diagram of a solar cell provided in yet another embodiment of the present application.

[0096] According to the embodiments of the present application, since the first region C1 of at least one first side surface C is an inclined surface extending from the side away from the first surface A to the side close to the first surface A along the direction away from the semiconductor substrate 1, there is no large step between the first region C1 and the second region C2, which is beneficial to improving the passivation effect of the first passivation anti-reflection layer. When considering a better passivation effect, the first doped semiconductor layer 3 can also cover most of the surface of the first region C1, or even cover the entire first region C1.

[0097] Figure 8 A scanning electron microscope image of a first side of a solar cell provided in yet another embodiment of the present application.

[0098] refer to Figure 8 As shown, the first region C1 has a plurality of holes, and the holes are recessed into the semiconductor substrate 1 in a direction parallel to the first surface A.

[0099] According to an embodiment of the present application, the passivation contact structure extends from the first surface A of the semiconductor substrate 1 to a partial surface of the first region C1 of at least one first side surface C. The hole passes through the passivation contact structure and is recessed into the semiconductor substrate 1 in a direction parallel to the first surface A. The first passivation anti-reflection layer 4 is located on the sidewalls and bottom surface of the first region C1 and the hole, so that the hydrogen in the first anti-reflection passivation layer 4 in the hole enters the semiconductor substrate 1, thereby improving the hydrogen passivation effect of the semiconductor substrate 1, thereby improving the efficiency of the solar cell. In general, the first passivation anti-reflection layer 4 may include one or more layers of aluminum oxide, silicon nitride, and silicon oxynitride, such as a stack of aluminum oxide and silicon nitride. A large amount of hydrogen will be introduced when aluminum oxide is deposited, and due to the hole structure, a large amount of hydrogen can enter the semiconductor substrate 1.

[0100] According to an embodiment of the present application, the distribution density of the holes in the area close to the first surface A is smaller than the distribution density in the area close to the second area C2.

[0101] According to the embodiments of the present application, the distribution density of holes in the area close to the first surface A is low, which can reduce the recombination centers of carriers in the area close to the first surface A, reduce the recombination of carriers, and thus improve the carrier collection efficiency.

[0102] According to an embodiment of the present application, the radial dimension of the hole gradually decreases from the surface of the first region C1 to the semiconductor substrate 1 in a direction parallel to the first surface A. In other words, the hole is an inverted pyramid structure extending from the surface of the first region C1 to the semiconductor substrate 1 in a direction parallel to the first surface A.

[0103] According to an embodiment of the present application, the radial dimension of the hole is less than 5 μm, preferably less than 2 μm, and more preferably less than 1 μm; the radial dimension of the hole may be, for example, 4 μm, 3 μm, 2 μm, or 1 μm, but is not limited to the values ​​listed.

[0104] According to the embodiment of the present application, the ratio of the projection area of ​​the hole in the first region A to the surface area of ​​the first region is in the range of 1% to 30%, for example, 1%, 5%, 10%, 20%, 30%, but not limited to the values ​​cited. If the ratio range is too small, it is difficult to achieve the technical effect of improving the passivation effect of the semiconductor substrate and increasing the passivation contact structure area, or the effect is not obvious; if the ratio range is too large, the semiconductor substrate 1 will have too many defects, which is not conducive to the effective collection of carriers.

[0105] According to the embodiment of the present application, the distribution density and radial size of the hole structure in the first region C1 covered by the doped semiconductor layer 3 or the passivation contact structure are smaller than that in the first region C1 not covered by the doped semiconductor layer 3. This can reduce damage to the passivation contact structure.

[0106] Fig. 9 A partial cross-sectional schematic diagram of a solar cell provided in yet another embodiment of the present application.

[0107] Fig.10 A scanning electron microscope image of a first side of a solar cell provided in yet another embodiment of the present application.

[0108] According to the embodiments of the present application, reference Fig. 9 , Fig.10 As shown, the first region C1 has a protruding ridge, and the ridge extends in a direction substantially parallel to the first surface A.

[0109] According to the embodiments of the present application, reference Fig. 9 As shown, the first doped semiconductor layer 3 is also located on a portion of the surface of the first region C1; the first doped semiconductor layer 3 located on the first region C1 is integrally continuous with the first doped semiconductor layer 3 located on the first surface A; and a portion of the surface of the first region C1 adjacent to the second region C2 is not covered with the first doped semiconductor layer 3.

[0110] According to an embodiment of the present application, the first region C1 has raised edges, and the first doped semiconductor layer 3 is located on a partial surface of the first region C1, which can enhance the electrical isolation between the front and back sides of the battery, and when leakage current is controllable, the surface area of ​​the first doped semiconductor layer 3 can be increased, which is beneficial to improving the carrier collection efficiency.

[0111] Fig.11 A partial cross-sectional schematic diagram of a solar cell provided in yet another embodiment of the present application.

[0112] According to the embodiments of the present application, reference Fig.11 As shown, the first region C1 has a raised edge, and the edge extends in a direction substantially parallel to the first surface A, which can increase the surface area of ​​the first region C1. In the case of controllable leakage, the first doped semiconductor layer 3 is completely covered on the first region C1, which can increase the surface area of ​​the first doped semiconductor layer 3, thereby facilitating the improvement of carrier collection efficiency.

[0113] According to an embodiment of the present application, since there is a raised edge on the first area C1 of at least one first side surface C, the edge extends in a direction substantially parallel to the first surface A; that is, a partial area of ​​the first area C1 close to the second area C2 is a slope extending from one side of the second area C2 to one side of the edge along a direction away from the semiconductor substrate 1.

[0114] There may not be a large step between the first region C1 and the second region C2, or even no step, which is conducive to improving the passivation effect of the passivation anti-reflection layer. When considering the passivation effect, the first doped semiconductor layer may also cover most of the surface of the first region C1, or even cover the first region C1 entirely. According to an embodiment of the present application, the second region C2 has a tower base structure, and the width of the first region C1 in a direction perpendicular to the first surface A is smaller than the size of the tower base structure of the second region C2, wherein the size of the tower base structure is defined as the side length or diagonal length of the tower base structure.

[0115] According to an embodiment of the present application, the TOPcon solar cell also includes a first electrode 10, which passes through the first passivation anti-reflection layer 4 and is electrically in contact with the first doped semiconductor layer 3; and a second electrode 20, which passes through the second passivation anti-reflection layer 6 and is electrically in contact with the second doped semiconductor layer 5.

[0116] According to an embodiment of the present application, the distance between the first electrode 10 and the first region C1 in a direction perpendicular to the thickness of the semiconductor substrate 1 (a direction parallel to the first surface A) is greater than or equal to 300 μm. Therefore, in the process of preparing the electrode, the slurry used to prepare the electrode can also be effectively prevented from leaking and distributing in a larger range on the side of the battery, causing serious damage to the electrical performance of the battery.

[0117] According to an embodiment of the present application, the first doped semiconductor layer 3 is one or more of doped polycrystalline silicon, doped amorphous silicon and doped microcrystalline silicon. The first doped semiconductor layer 3 is, for example, doped polycrystalline silicon, the thickness of the doped polycrystalline silicon is usually between 80nm and 500nm, and the doping concentration is usually between 1*10 17 ~1*10 21 atoms / cm 3 . .

[0118] Fig.12 A cross-sectional schematic diagram of a solar cell provided in yet another embodiment of the present application.

[0119] According to the embodiments of the present application, reference Fig.12 As shown, the first side surface C also includes a third area C3 adjacent to the second area C2, and the third area C3 is closer to the second surface B than the second area C2. That is, the above-mentioned solar cell also includes: a third semiconductor base portion 13, which is formed integrally with the second semiconductor base portion 12, and the third semiconductor base portion 13 is closer to the second surface B than the second semiconductor base portion 12.

[0120] According to an embodiment of the present application, the third region C3 is raised in a direction away from the first side surface C compared to the second region C2, and a raised height d2 of the third region C3 is greater than a raised height d1 of the first region C1.

[0121] According to an embodiment of the present application, the protrusion height d2 of the third region C3 is 3 μm to 10 μm, for example, 3 μm, 5 μm, 6 μm, 8 μm, or 10 μm, but is not limited to the above values.

[0122] According to the embodiment of the present application, when the second doped semiconductor layer 5 is formed on the second surface B, the second doped semiconductor layer 5 is plated around the first side surface C. When the second doped semiconductor layer 5 plated around the first side surface C is removed by using an alkali solution, a third region C3 is formed in the region of the first side surface C close to the second surface B, wherein the third region C3 is convex in a direction away from the first side surface C compared to the second region C2, which can increase the spatial electrical isolation distance between the first surface A and the second surface B, and can better avoid the occurrence of leakage on the first side surface of the solar cell; on the other hand, it can effectively prevent the slurry used to prepare the electrode on the second surface B from leaking to the first side surface, thereby avoiding damage to the performance of the battery.

[0123] In addition, the third region C3 is raised in a direction away from the first side surface C compared to the second region C2, which can increase the junction area of ​​the PN junction formed by the semiconductor substrate 1 and the second doped semiconductor layer 5, which is beneficial to improving the photocurrent of the solar cell.

[0124] According to an embodiment of the present application, the solar cell is a solar cell having a single-sided electrode, such as an interdigitated back contact cell (IBC).

[0125] Fig.13 A schematic cross-sectional view of a back-contact solar cell provided in an embodiment of the present application.

[0126] Fig.14 A schematic top view of the first surface of a back-contact solar cell provided in an embodiment of the present application.

[0127] According to an exemplary embodiment of the present application, referring to Fig.13 , Fig.14 As shown, the present application provides a back-contact solar cell.

[0128] According to an embodiment of the present application, an electrode collecting region is provided on the first surface A of the semiconductor substrate 1 , and the electrode collecting region includes a plurality of minority carrier regions 100 and a plurality of majority carrier regions 200 alternately distributed along the second direction, and an isolation region 300 is provided between adjacent minority carrier regions 100 and majority carrier regions 200 .

[0129] According to an embodiment of the present application, the first doped semiconductor layer 3 includes a third doped semiconductor layer 31 and a fourth doped semiconductor layer 32; wherein the third doped semiconductor layer 31 for collecting and deriving minority carriers is arranged in the minority region 100; the fourth doped semiconductor layer 32 for collecting and deriving majority carriers is arranged in the majority region 200, wherein the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 have opposite conductivity types, one of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 is N-type, and the other of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 is P-type. For example, the conductivity type of the third doped semiconductor layer 31 may be N-type, in which case the conductivity type of the fourth doped semiconductor layer 32 is P-type; or, the conductivity type of the third doped semiconductor layer 31 may be P-type, in which case the conductivity type of the fourth doped semiconductor layer 32 is N-type.

[0130] According to the embodiments of the present application, reference Fig.13 , Fig.14 As shown, the plurality of third doped semiconductor layers 31 extend in a first plane parallel to the first surface A in a first direction.

[0131] According to an embodiment of the present application, the plurality of fourth doped semiconductor layers 32 extend in the first direction, and the plurality of third doped semiconductor layers 31 and the plurality of fourth doped semiconductor layers 32 are alternately distributed on the first surface A in a second direction perpendicular to the first direction within the first plane.

[0132] According to an embodiment of the present application, the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 are also located on a portion of the surface of the first region C1 .

[0133] According to an embodiment of the present application, the first doped semiconductor layer 31 located on the minority region 100 at the outermost edge of the semiconductor substrate 1 extends vertically from the first plane to a partial surface of the first area C1 of the first side C; and / or, the second doped semiconductor layer 32 located on the majority region 200 at the outermost edge of the semiconductor substrate 1 extends vertically from the first plane to a partial surface of the first area C1 of the first side C.

[0134] According to the embodiment of the present application, a first interface passivation layer is further formed between the semiconductor substrate 1 and the third doped semiconductor layer 31 , and a second interface passivation layer is further formed between the semiconductor substrate 1 and the fourth doped semiconductor layer 32 .

[0135] According to an embodiment of the present application, the first interface passivation layer and / or the second interface passivation layer includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide and amorphous silicon.

[0136] According to an embodiment of the present application, the first passivation anti-reflection layer 4 of the back contact solar cell is located on the surface of the third doped semiconductor layer 31 and the fourth doped semiconductor layer 32 away from the semiconductor substrate 1 and on the semiconductor substrate 1 of the isolation region 300. The material of the first passivation anti-reflection layer 4 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide and amorphous silicon. The first passivation anti-reflection layer 4 is used to realize the surface passivation and anti-reflection function of the back contact solar cell.

[0137] According to an embodiment of the present application, the above-mentioned back-contact solar cell also includes: a first electrode 10, the first electrode 10 penetrates the first passivation anti-reflection layer 4 and is electrically in contact with the third doped semiconductor layer 31; a second electrode 20, the second electrode 20 penetrates the first passivation anti-reflection layer 4 and is electrically in contact with the fourth doped semiconductor layer 32.

[0138] According to an embodiment of the present application, the width of the first electrode 10 is 5 μm to 600 μm, for example, 5 μm, 10 μm, 100 μm, 500 μm, or 600 μm, but is not limited to the above values.

[0139] According to an embodiment of the present application, the width of the second electrode 20 is 5 μm-600 μm, for example, 5 μm, 10 μm, 100 μm, 500 μm, 600 μm, but is not limited to the above values.

[0140] According to an embodiment of the present application, the material of the first electrode 10 and / or the second electrode 20 includes, but is not limited to, one or more of metals, metal oxides, metal nitrides, metal carbides, and metal sulfides. The first electrode 10 and / or the second electrode 20 may also be other conductive connection materials such as graphene.

[0141] According to an embodiment of the present application, during the electrode preparation process, an electrode slurry is coated on the first passivation anti-reflection layer 4 of the first surface A, and then sintered so that the electrode slurry passes through the first passivation anti-reflection film 4 and forms contact with the doped semiconductor film layer.

[0142] According to an exemplary embodiment of the present application, the present application provides a photovoltaic assembly, including the above-mentioned solar cell.

[0143] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0144] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate (1), the semiconductor substrate (1) having a first surface (A) and a second surface (B) opposite to each other, and a plurality of first side surfaces (C) adjacent to the first surface (A) and the second surface (B); A passivation contact structure, located at least on a portion of the first surface (A) of the semiconductor substrate (1), the passivation contact structure comprising an interface passivation layer (2) and a first doped semiconductor layer (3) stacked in sequence; Wherein, in the direction from the first surface (A) to the second surface (B), the first side surface (C) comprises a first area (C1) and a second area (C2) adjacent to each other in sequence, and the first area (C1) is convex in a direction away from the first side surface (C) compared with the second area (C2); The first doped semiconductor layer (3) is also located on a portion of the surface of the first region (C1), wherein the first doped semiconductor layer (3) located on the first region (C1) is integrally continuous with the first doped semiconductor layer (3) located on the first surface (A); and a portion of the surface of the first region (C1) adjacent to the second region (C2) is not covered with the first doped semiconductor layer (3).

2. The solar cell according to claim 1, characterized in that In the direction from the first surface (A) to the second surface (B), the distance between the first doped semiconductor layer (3) located on the surface of the first region (C1) and the second region (C2) is greater than or equal to 1 μm.

3. The solar cell according to claim 1, characterized in that The ratio of the width of the first region (C1) in a direction perpendicular to the first surface (A) to the thickness of the semiconductor substrate (1) is in a range of 1% to 20%.

4. The solar cell according to claim 1, characterized in that The width of the first region (C1) in a direction perpendicular to the first surface (A) is 0.5 μm to 20 μm.

5. The solar cell according to claim 1, characterized in that: In a direction perpendicular to the first surface (A), a distribution width of the first doped semiconductor layer (3) in the first region (C1) is less than 80% of a width of the first region (C1).

6. The solar cell according to any one of claims 1 to 5, characterized in that: A first region (C1) of at least one of the first side surfaces (C) is an inclined surface extending from a side away from the first surface (A) to a side close to the first surface (A) along a direction away from the semiconductor substrate (1).

7. The solar cell according to any one of claims 1 to 5, characterized in that: The first region (C1) includes edges extending substantially parallel to the first surface (A).

8. The solar cell according to any one of claims 1 to 5, characterized in that: The first region (C1) has a plurality of holes, and the holes are recessed into the semiconductor substrate (1) in a direction parallel to the first surface (A).

9. The solar cell according to claim 8, characterized in that: The distribution density of the holes in the area close to the first surface (A) is smaller than the distribution density in the area close to the second area (C2).

10. The solar cell according to claim 9, characterized in that: The radial dimension of the hole gradually decreases in the direction from the surface of the first region (C1) to the semiconductor substrate (1); And / or, the radial dimension of the hole is less than 5 μm.

11. The solar cell according to any one of claims 1 to 5, characterized in that: Also includes: A second doped semiconductor layer (5), located at least within the second surface (B) of the semiconductor substrate (1); as well as The second passivation anti-reflection layer (6) is at least located on a surface of the second doped semiconductor layer (5) away from the semiconductor substrate (1).

12. The solar cell according to any one of claims 1 to 5, characterized in that: The solar cell is a back contact solar cell, The first doped semiconductor layer (3) comprises a plurality of third doped semiconductor layers (31) and a plurality of fourth doped semiconductor layers (32), wherein the plurality of third doped semiconductor layers (31) and the plurality of fourth doped semiconductor layers (32) are alternately distributed on the first surface (A); Wherein, one of the third doped semiconductor layer (31) and the fourth doped semiconductor layer (32) is of N type, and the other of the third doped semiconductor layer and the fourth doped semiconductor layer is of P type.

13. The solar cell according to any one of claims 1 to 5, characterized in that: Also includes: A first passivation anti-reflection layer (4), at least located on a surface of the passivation contact structure away from the semiconductor substrate (1); A first electrode (10), the first electrode (10) penetrates the first passivation anti-reflection layer (4) and contacts the first doped semiconductor layer (3); Wherein, the distance between the first electrode (10) and the first region (C1) in a direction parallel to the first surface (A) is greater than or equal to 300 μm.

14. The solar cell according to any one of claims 1 to 5, characterized in that: The first side surface (C) further includes a third area (C3) adjacent to the second area (C2), and the third area (C3) is closer to the second surface (B) than the second area (C2); The third region (C3) is protruded in a direction away from the first side surface (C) compared to the second region (C2), and a protruding height of the third region (C3) is greater than a protruding height of the first region (C1).

15. A photovoltaic module, characterized in that: Comprising the solar cell according to any one of claims 1 to 14.

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