A low-inductance packaging structure and packaging method for a power semiconductor module

Abstract

The present invention relates to the technical field of power semiconductor modules, and proposes a low-inductance packaging structure of a power semiconductor module, comprising a substrate and a power semiconductor module unit arranged on the substrate, the power semiconductor module unit is used to form a dual-switch circuit structure capable of reducing inductance, the power semiconductor module unit comprises a plurality of lining plates arranged at intervals on the substrate, adjacent lining plates are connected by a first bonding wire, two connected lining plates are connected with a power terminal group extending out of an outer tube shell, the power terminal group comprises two sub-power terminals which are partially overlapped but not in contact with each other, and are used to generate electromagnetic coupling when the two sub-power terminals conduct currents in different directions to reduce inductance; a low-inductance packaging method of a power semiconductor module is also proposed, which is used to manufacture the low-inductance packaging structure of a power semiconductor module proposed by the present invention. The present invention has the advantages of high reliability, high power density and low inductance.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor modules, and in particular to a low-inductance packaging structure and a packaging method for a power semiconductor module. Background Art

[0002] High-voltage and high-power semiconductor power devices are widely used in high-power power conversion such as rail transportation, smart grid, and high-voltage flexible direct current transmission. The wide application of high-voltage and high-power semiconductor power devices has also put forward higher requirements for them. These requirements continue to push the maximum output current specifications and current density technical limits of fully controlled power devices represented by semiconductor power devices such as insulated gate bipolar transistors.

[0003] The continuous innovation of semiconductor power chip technology and semiconductor device module packaging technology is an important guarantee for improving the performance of semiconductor devices. Packaging technology is particularly important for improving its performance reliability. For such high power requirements, traditional high-voltage and high-power modules usually adopt a single-switch circuit mode. With this circuit structure, when meeting the rapidly increasing system power requirements, it has a great impact on the working temperature of the semiconductor power chip, the withstand voltage design, the thermal stress and electromagnetic stress of the material, and the working temperature of the packaging material, forcing the system design to retain a large design margin, thereby limiting the performance of the power semiconductor.

[0004] In the field of high voltage and high power, the new generation of standardized power semiconductor modules adopts a half-bridge circuit structure to achieve a low-inductance half-bridge package, which is convenient for parallel expansion of capacity and meets the requirements of different power levels. It can provide higher system output power through different connection topologies between modules. From the perspective of the power component system, the same module appearance packaging structure is used for different high voltage levels, which can shorten the development cycle of power components and reduce the R&D, production and end-user application and maintenance costs.

[0005] In order to achieve parallel connection of multiple power modules without derating, there are strict requirements for the current sharing design of the electromagnetic performance inside the module, including improving the consistency of semiconductor chips, optimizing the layout of the metal layer on the surface of the liner, and optimizing the auxiliary terminal interconnection structure to achieve the balance of the main current of multiple chips inside the module and the control signals of power chips in different positions; the position layout of the DC positive / DC negative pole of the module power terminal and the AC end has an important impact on reducing the inductance of the module component to meet the high switching frequency and high current turn-on rate of the power component system. Summary of the invention

[0006] The present invention provides a low-inductance packaging structure and packaging method for a power semiconductor module, which utilizes a novel liner structure layout and combines a novel structural power terminal structure to give full play to the advantages of large-size semiconductor power chips, and utilizes a dual-switch circuit structure to balance losses and reduce inductance, thereby achieving a semiconductor power module packaging structure with low thermal resistance, high power density and high reliability, which can effectively solve the above-mentioned technical problems.

[0007] The low-inductance packaging structure of a power semiconductor module of the present invention comprises a substrate and a power semiconductor module unit arranged on the substrate, wherein the power semiconductor module unit is used to form a dual-switch circuit structure capable of reducing inductance; wherein the power semiconductor module unit comprises a plurality of lining plates arranged at intervals on the substrate, adjacent lining plates being connected by a first bonding wire, two connected lining plates being connected with a power terminal group extending out of an outer tube shell, the power terminal group comprising two sub-power terminals which are partially overlapped but not in contact with each other, and are used to generate electromagnetic coupling when the two sub-power terminals conduct currents in different directions to reduce inductance.

[0008] In one embodiment, an auxiliary terminal group is connected to the liner for introducing a driving signal into the power semiconductor module unit and leading a test signal out to a peripheral system; the auxiliary terminal group extends out of the top of the outer tube shell.

[0009] In one embodiment, a chipset is disposed in the middle region of the liner, the chipset comprising a plurality of power chips connected in parallel; the area of ​​the power chip is N times that of a power chip in a standard module, where N is greater than or equal to 2.

[0010] In one embodiment, the power terminal group also includes an AC power terminal, the sub-power terminal includes a positive power terminal and a negative power terminal, the two connected linings include a first lining plate and a second lining plate, the positive power terminal is connected to the first lining plate, the negative power terminal and the AC power terminal are both connected to the second lining plate, and the positive power terminal, the negative power terminal and the AC power terminal are all arranged in a serpentine structure in the vertical direction.

[0011] In one embodiment, the positive power terminal, the negative power terminal and the AC power terminal are all pre-bent power terminals, the positive power terminal includes a positive mounting portion, one side of the positive mounting portion is connected to a positive first bending portion, the lower side of the positive first bending portion is connected to a positive vertical connecting portion extending to the right, the lower side of the positive vertical connecting portion is sequentially connected to a positive second bending portion, a positive horizontal connecting portion and a positive bottom pin portion, and the positive bottom pin portion is connected to a first liner; the negative power terminal includes a negative mounting portion, the negative mounting portion A negative pole first bending portion is connected to one side, a negative pole vertical connecting portion extending to the left is connected to the lower side of the negative pole first bending portion, a negative pole second bending portion, a negative pole horizontal connecting portion, a negative pole third bending portion and a negative pole bottom pin portion are sequentially connected to the lower side of the negative pole vertical connecting portion, and the negative pole bottom pin portion is connected to the second lining plate; the positive pole second bending portion has the same bending direction as the negative pole second bending portion, the positive pole vertical connecting portion overlaps with the negative pole vertical connecting portion but does not contact, and the positive pole horizontal connecting portion overlaps with the negative pole horizontal connecting portion but does not contact.

[0012] In one embodiment, the dual switch circuit structure includes an upper switch circuit structure and a lower switch circuit structure, the upper switch circuit structure and the lower switch circuit structure form a main current loop, the auxiliary terminal group includes two groups of sub-auxiliary terminals respectively connected to the first lining plate and the second lining plate, and the two groups of sub-auxiliary terminals respectively form an upper switch control loop and a lower switch control loop with the upper switch circuit structure and the lower switch circuit structure.

[0013] In one embodiment, the sub-auxiliary terminals include a gate auxiliary terminal, an emitter auxiliary terminal and a collector auxiliary terminal.

[0014] In one embodiment, the upper switch control circuit includes: a first metal layer, which is constructed in an L-shaped structure and is arranged on the first liner, one side of the first metal layer is close to the first circumferential edge side of the first liner, and the other side of the first metal layer is close to the second circumferential edge side of the first liner; an auxiliary liner, which is arranged outside the first liner and close to the second circumferential edge side of the first liner, and the auxiliary liner is provided with an auxiliary metal layer group; a second metal layer, which is arranged on the first liner and close to the fourth circumferential edge side of the first liner; and a third metal layer, which is arranged on the first liner except for the first metal layer and the second metal layer The chip group on the first substrate is arranged on the third metal layer; the first metal layer, the second metal layer and the third metal layer are arranged at intervals with each other; the first metal layer, the auxiliary metal layer group and the control gate of the power chip arranged on the first substrate are connected in sequence through the second bonding wire, the chip group arranged on the first substrate is arranged on the third metal layer, the power chip and the second metal layer are connected through the third bonding wire, the pin of the gate auxiliary terminal is connected to the first metal layer, the pin of the emitter auxiliary terminal is connected to the second metal layer, and the pin of the collector auxiliary terminal is connected to the third metal layer.

[0015] In one embodiment, the lower switch control circuit includes: an auxiliary lining plate, which is arranged outside the second lining plate and close to the fourth circumferential edge side of the second lining plate, and an auxiliary metal layer group is arranged on the auxiliary lining plate; a fourth metal layer, which is constructed as an L-shaped structure and is arranged on the second lining plate, one side of the fourth metal layer is close to the third circumferential edge side of the second lining plate, and the other side of the fourth metal layer is close to the fourth circumferential edge side of the second lining plate; a fifth metal layer, which is arranged on the second lining plate, one side of the fourth metal layer is close to the second circumferential edge side of the second lining plate, and the other side of the fourth metal layer is close to the third circumferential edge side of the second lining plate; and a sixth metal layer, which is arranged on the In the area on the second substrate except the fourth metal layer and the fifth metal layer, the chip group on the second substrate is arranged on the sixth metal layer; the fourth metal layer, the fifth metal layer and the sixth metal layer are arranged at intervals from each other; the fourth metal layer, the auxiliary metal layer group and the control gate of the power chip arranged on the second substrate are connected in sequence through the second bonding wire, the chip group arranged on the second substrate is arranged on the sixth metal layer, the power chip and the fifth metal layer are connected through the third bonding wire, the pin of the gate auxiliary terminal is connected to the fourth metal layer, the pin of the emitter auxiliary terminal is connected to the fifth metal layer, and the pin of the collector auxiliary terminal is connected to the sixth metal layer.

[0016] In one embodiment, the auxiliary metal layer group includes a plurality of strip metal layers arranged at intervals, and the plurality of strip metal layers are connected in series and connected to a chip resistor.

[0017] In one embodiment, the negative electrode bottom pin portion includes three negative electrode pins arranged at intervals, and the chip group arranged on the second liner includes three power chips.

[0018] In one embodiment, the main current loop includes: a second metal layer, which is arranged on the first backing plate and close to the fourth circumferential edge side of the first backing plate; a third metal layer, which is arranged on the first backing plate except the second metal layer, and the chipset on the first backing plate is arranged on the third metal layer; a fifth metal layer, which is arranged on the second backing plate, one side of the fifth metal layer is close to the second circumferential edge side of the second backing plate, and the other side of the fifth metal layer is close to the third circumferential edge side of the second backing plate; a seventh metal layer, which is arranged on the second backing plate, one side of the seventh metal layer is close to the first circumferential edge side of the second backing plate, The other side of the seventh metal layer is close to the second circumferential edge side of the second liner; the eighth metal layer is arranged on the second liner and close to the second circumferential edge side of the second liner; and the sixth metal layer is arranged on the first liner except the fifth metal layer, the seventh metal layer and the eighth metal layer, and the chipset on the second liner is arranged on the sixth metal layer; the metal layers on the same liner are arranged at intervals; the positive bottom pin portion is connected to the third metal layer, the three negative pins are connected to the fifth metal layer, the seventh metal layer and the eighth metal layer in sequence, and the pin of the AC power terminal is connected to the sixth metal layer.

[0019] In one embodiment, the positive bottom pin portion includes two positive pins, and a first pin bending portion and a second pin bending portion are respectively arranged between the positive horizontal connecting portion and the two positive pins, and a compensation section is arranged between the first pin bending portion and the second pin bending portion. The compensation section is used to reduce the stress caused by the vibration of the positive power terminal, and the bottoms of the two positive pins are connected to the third metal layer, and the spacing between the two positive pins is greater than the preset distance.

[0020] In one embodiment, the metal layer is made of copper, aluminum or a metal that can be used as a semiconductor surface coating.

[0021] In one embodiment, the power chip includes a first chip and a second chip, and the first chip and the second chip are connected together via a fourth bonding wire.

[0022] In one embodiment, the chip group is disposed on the backing plate by pressure silver sintering, pressureless silver sintering or copper sintering.

[0023] In one embodiment, when there are multiple power semiconductor module units, the multiple power semiconductor module sub-units are connected in parallel.

[0024] In one embodiment, it further includes: an outer tube shell, which is tightly connected to the substrate and forms a potting area between the two, and the power semiconductor module unit is located in the potting area; and a potting material, which is insulated and fills the potting area.

[0025] In one embodiment, the liner is a ceramic liner.

[0026] In one embodiment, when there are multiple power semiconductor module units, the multiple power semiconductor module sub-units are connected in parallel.

[0027] The present invention also provides a low-inductance packaging method for a power semiconductor module, which is used to manufacture the low-inductance packaging structure for a power semiconductor module described in any one of the above embodiments.

[0028] The present invention provides a power semiconductor module low inductance packaging structure and packaging method. Compared with the prior art, the power semiconductor module low inductance packaging structure provided by the present invention has at least the following beneficial effects:

[0029] ① The present invention adopts a dual-switch circuit structure. Through electromagnetic balance and structural optimization of the entire main current loop, the resistance and inductance of the upper switch and lower switch loops in the power semiconductor module can be made consistent, thereby reducing the electromagnetic oscillation of the entire main current loop during the current switching process, thereby achieving loss balance of the upper and lower switches and improving the reliability of the entire packaging structure.

[0030] ② The present invention adopts a novel asymmetric structure and overlapping sub-power terminals, so that the two sub-power terminals overlap with a large area. The magnetic flux generated by the two power terminals in the switching stage is in opposite directions, and a large proportion of cancellation is formed after electromagnetic coupling, thereby reducing the overall inductance of the two sub-power terminals, thereby reducing the inductance of the entire module and improving the mechanical performance and reliability of the entire packaging structure.

[0031] ③ The structures of the positive power terminal and the negative power terminal themselves are designed to meet the requirements of high current balance and vibration relief, providing a structure for inductance balance and vibration stress relief, thereby further improving the reliability of the packaging structure.

[0032] ④ Through the precise optimization design between the positive power terminal pin, the negative power terminal pin and the lining, the electromagnetic balance of the main current between multiple parallel power chips is effectively achieved. At the same time, the upper and lower switch control loop balance is used to achieve the balance of the turn-on transient overshoot current when multiple power chips are connected in parallel, ensuring the transient working characteristics and reliability of the module.

[0033] ⑤ Two large-area high-mechanical-property ceramic liners are connected to replace the traditional four-liner structure, while increasing the effective area of ​​the main current loop metal layer on the upper surface of the ceramic liners, replacing the traditional power chip supporting separate metal layer design. On the basis of ensuring the metal layer area required for each control circuit, the liner layout is greatly optimized, effectively reducing the process complexity, reducing the number of metal layers, and then reducing the use of bonding wires, saving process costs, and improving production efficiency.

[0034] ⑥ Compared with the standard module, the effective area of ​​the third metal layer and the sixth metal layer of the present invention is increased, and the source area of ​​the power chip is increased geometrically, so that the total number of chips on a single substrate is reduced by at least 1 / 3 compared with the traditional size chips. At the same time, the current density can be improved, and the current level of the power chip is increased exponentially. The overall thermal resistance of the power semiconductor module sub-unit will be reduced by more than 15%, thereby improving the reliability of the packaging structure, simplifying the production process, and improving production efficiency.

[0035] ⑦ The power terminal of the present invention connects DC current and AC current, and at the same time clearly separates the DC end and the AC end of the half-bridge circuit, which is convenient for achieving inductance cancellation of the main current loop, effectively reducing the overall stray inductance of the power semiconductor module, optimizing the switching characteristics of the semiconductor device, and thus improving the overall reliability of the power semiconductor module.

[0036] ⑧The present invention provides a plurality of power semiconductor module units, and the plurality of power semiconductor module units are connected in parallel to form power semiconductor modules of different power levels and topological structures, thereby forming a series of large-area power semiconductor modules and a standardized power semiconductor module production platform.

[0037] The low-inductance packaging method for a power semiconductor module provided by the present invention also has the above-mentioned beneficial effects because it packages the above-mentioned low-inductance packaging structure of the power semiconductor module. At the same time, the ultrasonic bonding terminals provide higher reliability than terminals formed by welding and sintering processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Hereinafter, the present invention will be described in more detail based on embodiments and with reference to the accompanying drawings.

[0039] Figure 1 It is a schematic structural diagram of the low-inductance packaging structure substrate of the power semiconductor module and the power semiconductor module unit after being assembled;

[0040] Figure 2 It is a schematic structural diagram of the low inductance packaging structure substrate and liner of the power semiconductor module of the present invention after being assembled;

[0041] Figure 3 It is a schematic structural diagram of the positive power terminal and the negative power terminal of the low inductance packaging structure of the power semiconductor module of the present invention after being overlapped;

[0042] Figure 4 It is a structural schematic diagram of the positive power terminal of the low inductance packaging structure of the power semiconductor module of the present invention;

[0043] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale.

[0044] Reference numerals:

[0045] 1-substrate, 10-substrate mounting hole, 11-housing fastening hole, 12-first bonding wire, 13-second bonding wire, 14-third bonding wire, 15-fourth bonding wire, 2-liner, 20-first liner, 200-first metal layer, 201-second metal layer, 202-third metal layer, 21-second liner, 210-fourth metal layer, 211-fifth metal layer, 212-sixth metal layer, 213-seventh metal layer, 214-eighth metal layer, 22-auxiliary liner, 220-auxiliary metal layer, 221-chip resistor, 3-power terminal group, 30-positive power terminal, 300-positive mounting portion, 301-positive first bending portion, 302-positive vertical connecting portion, 303-positive first Two bending parts, 304-positive horizontal connection part, 3040-first pin bending part, 3041-second pin bending part, 305-positive bottom pin part, 3050-positive pin, 306-compensation section, 31-negative power terminal, 310-negative mounting part, 311-negative first bending part, 312-negative vertical connection part, 313-negative second bending part, 314-negative horizontal connection part, 315-negative bottom pin part, 3150-negative pin, 32-AC power terminal, 4-auxiliary terminal group, 40-gate auxiliary terminal, 41-emitter auxiliary terminal, 42-collector auxiliary terminal, 5-chip group, 50-power chip, 500-first chip, 501-second chip. DETAILED DESCRIPTION

[0046] The present invention will be further described below in conjunction with the accompanying drawings.

[0047] Please refer to Figure 1The low inductance packaging structure of a power semiconductor module of the present invention comprises a substrate 1 and a power semiconductor module unit arranged on the substrate 1; the power semiconductor module unit is used to form a dual switch circuit structure that can reduce inductance, and the power semiconductor module unit comprises a plurality of lining plates 2 arranged at intervals on the substrate 1, wherein two oppositely arranged lining plates 2 are connected by a first bonding wire 12, and a power terminal group 3 extending out of an outer tube shell is connected to the two connected lining plates 2, and the power terminal group 3 comprises two overlapping but non-contacting sub-power terminals.

[0048] Please refer to Figure 1 Specifically, in one example, all the linings 2 are connected with auxiliary terminal groups 4 for introducing drive signals into the power semiconductor module unit and leading out test signals to the peripheral system; the auxiliary terminal groups 4 extend out of the top of the outer tube shell.

[0049] Please refer to Figure 2 Specifically, in one example, a chipset 5 is disposed in the middle area of ​​the liner 2, and the chipset 5 includes a plurality of power chips 50 connected in parallel with each other; the power chip 50 is N times the area of ​​the power chip in the standard module, and N is greater than or equal to 2.

[0050] Specifically, it should be noted that the area of ​​the large-size power chip described in the present invention is a relative concept, not a description of the absolute size. For different voltage levels and power semiconductor power materials, the power chips have certain differences in absolute area, which is not simply reflected in the same absolute size. For example, the active area of ​​the chip used in the current silicon-based high-voltage and high-power module is about one square centimeter, and the corresponding large-size power chip active area is at least two square centimeters or more; the active area of ​​the medium and low voltage power chip is 1.5-2 square centimeters, and the active area of ​​the corresponding large-size power chip is 3-4 square centimeters or more; for the currently used wide bandgap power chips, such as silicon carbide chips, due to the defects of silicon carbide materials and the current process difficulties, more than a dozen square millimeters is the usual area under the current technical conditions, and the silicon carbide active area described in the present invention is at the level of 0.5 to several square centimeters.

[0051] Specifically, it should be noted that, in power module products of the same size, the operating thermal resistance of the power module can be reduced by significantly increasing the active area of ​​the power chip and selecting a thinner substrate with high mechanical performance and high reliability, and the operating junction temperature of the power chip can be reduced under the same power loss conditions, so as to increase the output current rating, increase the output power of the power module, and thus improve the reliability of the module.

[0052] Please refer to Figure 1In one example, the power terminal group 3 includes two sub-power terminals and an AC power terminal 32, the two sub-power terminals are a positive power terminal 30 and a negative power terminal 31, the two connected lining plates 2 are respectively a first lining plate 20 and a second lining plate 21, the positive power terminal 30 is connected to the first lining plate 20, the negative power terminal 31 and the AC power terminal 32 are both connected to the second lining plate 21, the positive power terminal 30, the negative power terminal 31 and the AC power terminal 32 are all arranged in a serpentine structure in the vertical direction, and the positive power terminal 30 and the negative power terminal 31 are arranged opposite to each other and overlapped in multiple places but not in contact, so as to generate electromagnetic coupling to reduce inductance when the two conduct currents in different directions.

[0053] Please refer to Figure 3 and Figure 4 , further, in a preferred example, the positive power terminal 30, the negative power terminal 31 and the AC power terminal 32 are all pre-bent power terminals, the positive power terminal 30 includes a positive mounting portion 300, one side of the positive mounting portion 300 is connected to a positive first bending portion 301, the lower side of the positive first bending portion 301 is connected to a positive vertical connecting portion 302 extending to the right, the lower side of the positive vertical connecting portion 302 is sequentially connected to a positive second bending portion 303, a positive horizontal connecting portion 304 and a positive bottom pin portion 305, and the positive pin 3050 is connected to the first liner 20; the negative power terminal 31 includes a negative mounting portion 310, a negative mounting portion A negative first bending portion 311 is connected to one side of 310, a negative vertical connecting portion 312 extending to the left is connected to the lower side of the negative first bending portion 311, a negative second bending portion 313, a negative horizontal connecting portion 314, a negative third bending portion and a negative bottom pin portion 315 are sequentially connected to the lower side of the negative vertical connecting portion 312, and the negative pin 3150 is connected to the second lining plate 21; the positive second bending portion 303 and the negative second bending portion 313 have the same bending direction, the positive vertical connecting portion 302 and the negative vertical connecting portion 312 are arranged opposite to each other and overlap but do not touch, and the positive horizontal connecting portion 304 and the negative horizontal connecting portion 314 are arranged opposite to each other and overlap but do not touch.

[0054] Specifically, it should be noted that the positive vertical connection part 302 and the negative vertical connection part 312, the positive horizontal connection part 304 and the negative horizontal connection part 314 are arranged to overlap each other, and the magnetic flux generated by the two power terminals is in opposite directions. Compared with the standard terminal, there is a larger area of ​​electromagnetic coupling area, which can form a large-scale offset, thereby reducing the overall inductance of the two sub-power terminals, thereby reducing the inductance of the entire module and improving the mechanical performance and reliability of the entire packaging structure. At the same time, the position and structure of each bending part and the mounting part are set to meet high current balance and vibration relief, provide a structure for inductance balance and vibration stress relief, thereby further improving the reliability of the packaging structure.

[0055] Please refer to Figure 1 and Figure 2 Specifically, in one example, the dual switch circuit structure includes an upper switch circuit structure and a lower switch circuit structure, the upper switch circuit structure and the lower switch circuit structure form a main current loop, the auxiliary terminal group 4 includes two groups of sub-auxiliary terminals respectively connected to the first liner 20 and the second liner 21, and the two groups of sub-auxiliary terminals respectively form an upper switch control loop and a lower switch control loop with the upper switch circuit structure and the lower switch circuit structure.

[0056] Specifically, it should be noted that by adopting a dual-switch circuit structure, through electromagnetic balance and structural optimization of the entire main current loop, the resistance and inductance of the upper switch and lower switch loops in the power semiconductor module can be made consistent, thereby reducing the electromagnetic oscillation of the entire main current loop during the current switching process, thereby achieving loss balance of the upper and lower switches and improving the reliability of the entire packaging structure.

[0057] Please refer to Figure 1 and Figure 2 In one example, the sub-auxiliary terminals include a gate auxiliary terminal 40 , an emitter auxiliary terminal 41 and a collector auxiliary terminal 42 .

[0058] Please refer to Figure 1 and Figure 2, further, in a preferred example, the upper switch control loop includes: a first metal layer 200, which is constructed as an L-shaped structure and is arranged on the first liner 20, one side of the first metal layer 200 is close to the first circumferential edge side of the first liner 20, and the other side of the first metal layer 200 is close to the second circumferential edge side of the first liner 20; an auxiliary liner 222, which is arranged outside the first liner 20 and close to the second circumferential edge side of the first liner 20, and the auxiliary metal layer 220 group is arranged on the auxiliary liner 222; a second metal layer 201, which is arranged on the first liner 20 and close to the fourth circumferential edge side of the first liner 20; and a third metal layer 202, which is arranged on the first liner 20 except the first metal layer 200 and the second metal layer 201 In the area outside the first substrate 20, the chip group 5 on the first substrate 20 is arranged on the third metal layer 202; the first metal layer 200, the second metal layer 201 and the third metal layer 202 are arranged at intervals from each other; the first metal layer 200, the auxiliary metal layer 220 group and the control gate of the power chip 50 arranged on the first substrate 20 are connected in sequence through the second bonding wire 13, the chip group 5 arranged on the first substrate 20 is arranged on the third metal layer 202, the power chip 50 and the second metal layer 201 are connected through the third bonding wire 14, the pin of the gate auxiliary terminal 40 is connected to the first metal layer 200, the pin of the emitter auxiliary terminal 41 is connected to the second metal layer 201, and the pin of the collector auxiliary terminal 42 is connected to the third metal layer 202.

[0059] Specifically, it should be noted that the effective areas of the third metal layer 202 and the sixth metal layer 212 are increased, and at the same time, the source region area of ​​the power chip 50 is increased exponentially, so that the total number of chips on a single substrate is reduced by at least 1 / 3 relative to chips of traditional size, and at the same time, the current density can be increased. The current levels of the power chip 50 are increased exponentially, and the overall thermal resistance of the power semiconductor module sub-unit will be reduced by more than 15%, thereby improving the reliability of the packaging structure, simplifying the production process, and improving production efficiency.

[0060] Please refer to Figures 1 to 4, further, in a preferred example, the lower switch control circuit includes: an auxiliary liner 222, which is arranged outside the second liner 21 and close to the fourth circumferential edge side of the second liner 21, and an auxiliary metal layer 220 group is arranged on the auxiliary liner 222; a fourth metal layer 210, which is constructed as an L-shaped structure and is arranged on the second liner 21, one side of the fourth metal layer 210 is close to the third circumferential edge side of the second liner 21, and the other side of the fourth metal layer 210 is close to the fourth circumferential edge side of the second liner 21; a fifth metal layer 211, which is arranged on the second liner 21, one side of the fourth metal layer 210 is close to the second circumferential edge side of the second liner 21, and the other side of the fourth metal layer 210 is close to the third circumferential edge side of the second liner 21; and a sixth metal layer 212, which is arranged on the second liner 2 1, except for the fourth metal layer 210 and the fifth metal layer 211, the chip group 5 on the second substrate 21 is arranged on the sixth metal layer 212; the fourth metal layer 210, the fifth metal layer 211 and the sixth metal layer 212 are arranged at intervals from each other; the fourth metal layer 210, the auxiliary metal layer 220 group and the control gate of the power chip 50 arranged on the second substrate 21 are connected in sequence through the second bonding wire 13, the chip group 5 arranged on the second substrate 21 is arranged on the sixth metal layer 212, the power chip 50 and the fifth metal layer 211 are connected through the third bonding wire 14, the pin of the gate auxiliary terminal 40 is connected to the fourth metal layer 210, the pin of the emitter auxiliary terminal 41 is connected to the fifth metal layer 211, and the pin of the collector auxiliary terminal 42 is connected to the sixth metal layer 212.

[0061] Specifically, it should be noted that auxiliary small lining plates are added around the main lining plates to assist in completing the circuit connection of the control loop, improve the effective utilization rate of the main lining plates, and improve the power density of the module.

[0062] Specifically, the first substrate 20 and the second substrate 21 are respectively connected through two groups of auxiliary terminal groups 4. On the first substrate 20, the gate auxiliary terminal 40, the first metal layer 200, the auxiliary metal layer 220, the third metal layer 202, the chip group 5, the second metal layer 201, and the emitter auxiliary terminal 41 constitute an upper switch control loop. The control current is transmitted through the gate auxiliary terminal 40, and then passes through the first metal layer 200, the auxiliary metal layer 220 and the third metal layer 202 in sequence until it is transmitted to the chipset 5 and controls the changes in the internal components of the power chip 50, thereby controlling the on and off of the upper switch circuit structure. Finally, the control current is output from the second metal layer 201 and the emitter auxiliary terminal 41 in sequence. On the second substrate 21, the gate auxiliary terminal 40, the fourth metal layer 210, the auxiliary metal layer 220, the sixth metal layer 212, the chipset 5, the fifth metal layer 211, and the emitter auxiliary terminal 41 constitute an upper switch control loop. Similarly, the control current is transmitted through the gate auxiliary terminal 40, and then sequentially passes through the fourth metal layer 210, the auxiliary metal layer 220 and the sixth metal layer 212 until it reaches the chipset 5 and controls the change of the internal components of the power chip 50, thereby controlling the on and off of the lower switch circuit structure. Finally, the control current is sequentially output by the fifth metal layer 211 and the emitter auxiliary terminal 41. At the same time, the two collector auxiliary terminals 42 are respectively connected to the third metal layer 202 and the sixth metal layer 212, and are used to provide reference signals to the upper switch control loop and the lower switch control loop respectively.

[0063] Specifically, it should be noted that by utilizing the upper and lower switch control loops to balance each other, the transient overshoot current when multiple power chips 50 are connected in parallel is balanced, thereby ensuring the transient working characteristics and reliability of the module.

[0064] Please refer to Figure 2 Furthermore, in one example, the auxiliary metal layer 220 group includes a plurality of strip metal layers arranged at intervals, and the plurality of strip metal layers are connected in series and connected to the chip resistor 221 .

[0065] Specifically, it should be noted that welding or sintering the chip resistor 221 on the auxiliary liner 22 can effectively reduce gate oscillation and improve the reliability of the power module when the chip is turned on and off.

[0066] Please refer to Figure 1 and Figure 2 In one example, the negative electrode bottom pin portion 315 includes three negative electrode pins 3150 arranged at intervals, and the chip group 5 arranged on the second substrate 21 includes three power chips 50 .

[0067] Please refer to Figures 1 to 4, further, in one example, the main current loop includes: a second metal layer 201, which is arranged on the first liner 20 and close to the fourth circumferential edge side of the first liner 20; a third metal layer 202, which is arranged on the first liner 20 except the second metal layer 201, and the chipset 5 on the first liner 20 is arranged on the third metal layer 202; a fifth metal layer 211, which is arranged on the second liner 21, one side of the fifth metal layer 211 is close to the second circumferential edge side of the second liner 21, and the other side of the fifth metal layer 211 is close to the third circumferential edge side of the second liner 21; a seventh metal layer 213, which is arranged on the second liner 21, one side of the seventh metal layer 213 is close to the first circumferential edge side of the second liner 21, and the seventh metal layer 213 is close to the third circumferential edge side of the second liner 21. The other side of the seventh metal layer 213 is close to the second circumferential edge side of the second liner 21; the eighth metal layer 214 is arranged on the second liner 21 and close to the second circumferential edge side of the second liner 21; and the sixth metal layer 212 is arranged on the first liner 20 except the fifth metal layer 211, the seventh metal layer 213 and the eighth metal layer 214, and the chipset 5 on the second liner 21 is arranged on the sixth metal layer 212; the metal layers on the same liner 2 are arranged at intervals; the positive bottom pin portion 305 is connected to the third metal layer 202, the three negative pins 3150 are connected to the fifth metal layer 211, the seventh metal layer 213 and the eighth metal layer 214 in sequence, and the pin of the AC power terminal 32 is connected to the sixth metal layer 212.

[0068] Specifically, the main current loop includes a direct current loop and an alternating current loop, wherein the direct current loop includes a positive power terminal 30, a third metal layer 202, a chipset 5 arranged on the first liner 20, a second metal layer 201, a sixth metal layer 212, a chipset 5 arranged on the second liner 21, a fifth metal layer 211, a seventh metal layer 213 and an eighth metal layer 214 connected in parallel, and a negative power terminal 31. The direct current first flows into the third metal layer 202 from the positive bottom pin portion 305 of the positive power terminal 30, and then passes through the chipset 5 arranged on the first liner 20, the second metal layer 201, the sixth metal layer 212, the chipset 5 arranged on the second liner 21, and the fifth metal layer 211, the seventh metal layer 213 and the eighth metal layer 214 connected in parallel in sequence, and then is connected through three negative pins 3150 respectively connected to the fifth metal layer 211, the seventh metal layer 213 and the eighth metal layer 214, and finally flows out from the negative power terminal 31. The AC current loop includes an AC power terminal 32, a sixth metal layer 212, a chipset 5 disposed on the second liner 21, a fifth metal layer 211, a seventh metal layer 213 and an eighth metal layer 214 connected in parallel, and a negative power terminal 31. The AC current first flows from the AC power terminal 32 into the sixth metal layer 212, and then sequentially passes through the chipset 5 disposed on the second liner 21 and the fifth metal layer 211, the seventh metal layer 213 and the eighth metal layer 214 connected in parallel, and then is connected through three negative pins 3150 respectively connected to the fifth metal layer 211, the seventh metal layer 213 and the eighth metal layer 214, and finally flows out from the negative power terminal 31. Therefore, the power terminal of the present invention connects the DC current and the AC current, realizes the clear separation of the DC end and the AC end of the half-bridge circuit, facilitates the inductance offset of the main current loop, effectively reduces the overall stray inductance of the power semiconductor module, optimizes the switching characteristics of the semiconductor device, and thus improves the overall reliability of the power semiconductor module.

[0069] Specifically, it should be noted that in the above-mentioned examples, the third metal layer 202 and the sixth metal layer 212 respectively fill the remaining areas of the first liner 20 and the second liner 21. At the same time, the present invention adopts two large-area high-mechanical property ceramic liners to be connected to replace the traditional four-liner structure, thereby further increasing the effective area of ​​the main current loop metal layer (the third metal layer 202 and the sixth metal layer 212) on the upper surface of the ceramic liners, replacing the traditional power chip 50 with a separate metal layer design, and greatly optimizing the liner layout on the basis of ensuring the metal layer area required for each control circuit, effectively reducing the process complexity, reducing the number of metal layers, and thereby reducing the use of bonding wires, saving process costs, and improving production efficiency.

[0070] Please refer to Figure 4Further, in one example, the positive bottom pin portion 305 includes two asymmetric positive pins 3050, and a first pin bending portion 3040 and a second pin bending portion 3041 are respectively arranged between the positive horizontal connecting portion 304 and the two positive pins 3050, and a compensation section 306 is arranged between the first pin bending portion 3040 and the second pin bending portion 3041, and the compensation section 306 is used to reduce the stress caused by the vibration of the positive power terminal 31, and the bottoms of the two positive pins 3050 are respectively connected to the third metal layer 202, and the spacing between the two positive pins 3050 is greater than a preset distance, for example, the preset distance is the spacing between the fifth metal layer 211 and the eighth metal layer 214.

[0071] Specifically, it should be noted that two asymmetric positive pins 3050 are connected to different positions of the first liner 20 with a certain distance between them. When current flows, the current can be transmitted to the third metal layer 202 more quickly to ensure the balance of inductance and resistance on the third metal layer 202, thereby ensuring the current balance between the power chips 50 inside the module. The first pin bend 3040, the second pin bend 3041 and the compensation section 306 can effectively reduce the stress caused by the vibration of the main power terminal during processes such as ultrasonic bonding and welding and actual working conditions.

[0072] In one example, the metal layer is made of copper, aluminum, or a metal that can be used as a semiconductor surface coating.

[0073] Specifically, it should be noted that the metal layer is usually composed of a copper layer or an aluminum layer, and the metal layer is usually 0.2-0.8 mm; different metal coatings are added to the surface of the metal layer to adapt to welding, sintering and other processes, and the thickness of the metal coating is 2-10 microns.

[0074] In one example, the material and thickness of the substrate 1 are selected according to different application environments, and the substrate 1 is provided with a substrate mounting hole 10 and a housing fastening hole 11 .

[0075] Specifically, it should be noted that the thermal-mechanical properties of the substrate 1 material must comprehensively consider the module production and manufacturing process and the actual operating conditions of the entire module. In addition, the thermal conductivity of the material is also a key factor. In order to reduce the cost of the substrate 1, the present invention adopts Figure 2The substrate mounting hole 10 and the housing fastening hole 11 are shown. This kind of substrate 1 preformed via is formed in one step during the substrate 1 manufacturing process, and does not require the traditional mechanical drilling via solution, which effectively reduces the fixing cost of the substrate 1 and improves the reliability of the substrate 1. The thickness of the substrate 1 is usually 3-6 mm, and different metal coatings are used on the surface of the substrate 1 to adapt to the welding or sintering process. The coating thickness is generally 5-20 microns. The thickness of the substrate 1 used in the present invention is 25% thinner than the thickness of the traditional module substrate 1, which effectively reduces the thermal resistance of the module itself and ensures high thermal-mechanical performance.

[0076] In an example, the power chip 50 includes a first chip 500 and a second chip 501 , and the first chip 500 and the second chip 501 are connected together through a fourth bonding wire 15 .

[0077] In one example, the chip group 5 is disposed on the substrate 2 by pressure silver sintering, pressureless silver sintering or copper sintering.

[0078] In one example, it also includes: an outer tube shell, which is tightly connected to the substrate 1 and forms a potting area between the two, and the power semiconductor module unit is located in the potting area; and a potting material, which is insulated and fills the potting area.

[0079] In one example, the liner 2 is a ceramic liner.

[0080] Specifically, it should be noted that the high-voltage ceramic layer in the middle is made of aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc. The thickness of the ceramic layer material is usually 0.3-1.5 mm, depending on the voltage requirements and different materials. In order to meet the needs of large currents, the metal layer on the upper surface of the ceramic lining is thickened to reduce the on-resistance and reduce the loss introduced by the package. At the same time, the module in the present invention selects a thin ceramic lining material with stronger thermomechanical properties and insulation capabilities to achieve a power semiconductor module with high voltage resistance, low thermal resistance, and high mechanical properties.

[0081] In one example, when there are multiple power semiconductor module units, the multiple power semiconductor module sub-units are connected in parallel.

[0082] Specifically, it should be noted that multiple power semiconductor module units are connected in parallel to form power semiconductor modules of different power levels and topological structures, thereby forming a series of large-area power semiconductor modules and a standardized power semiconductor module production platform.

[0083] Specifically, in one example, ultrasonic bonding is used to connect the bonding wires to the metal layer, the bonding wires to the chip, and the pins to the metal layer.

[0084] Specifically, it should be noted that ultrasonic bonding can improve the reliability of terminal bonding compared with welding and other methods. At the same time, the terminal bonding point can be flexibly designed to fully utilize the space inside the module to achieve parallel balanced operation of the devices.

[0085] The low-inductance packaging method for a power semiconductor module of the present invention is used to manufacture the low-inductance packaging structure for a power semiconductor module described in any one of the above examples.

[0086] In the description of the present invention, it is necessary to understand that the terms "upper", "lower", "bottom", "top", "front", "back", "inside", "outside", "left", "right", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0087] Although the present invention has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced by equivalents without departing from the scope of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A low inductance packaging structure for a power semiconductor module, characterized in that: It includes a substrate and a power semiconductor module unit arranged on the substrate, wherein the power semiconductor module unit is used to form a dual switch circuit structure capable of reducing inductance; The dual switch circuit structure comprises an upper switch circuit structure and a lower switch circuit structure, wherein the upper switch circuit structure and the lower switch circuit structure form a main current loop, and the auxiliary terminal group comprises two groups of sub-auxiliary terminals respectively connected to the first lining plate and the second lining plate, and the two groups of sub-auxiliary terminals respectively form an upper switch control loop and a lower switch control loop with the upper switch circuit structure and the lower switch circuit structure; The power semiconductor module unit comprises a plurality of liner plates arranged at intervals on the substrate, adjacent liner plates are connected by first bonding wires, two connected liner plates are connected with a power terminal group extending out of the outer tube shell, the power terminal group comprises two sub-power terminals which are partially overlapped but not in contact with each other, and are used to generate electromagnetic coupling when the two sub-power terminals conduct currents in different directions to reduce inductance; The power terminal group further includes an AC power terminal, and the sub-power terminal includes a positive power terminal and a negative power terminal. The two connected lining plates include a first lining plate and a second lining plate, the positive power terminal is connected to the first lining plate, the negative power terminal and the AC power terminal are both connected to the second lining plate, and the positive power terminal, the negative power terminal and the AC power terminal are all arranged in a serpentine structure in the vertical direction; The positive power terminal, the negative power terminal and the AC power terminal are all pre-bent power terminals, the positive power terminal comprises a positive mounting portion, one side of the positive mounting portion is connected to a positive first bending portion, the lower side of the positive first bending portion is connected to a positive vertical connecting portion extending to the right, the lower side of the positive vertical connecting portion is sequentially connected to a positive second bending portion, a positive horizontal connecting portion and a positive bottom pin portion, and the positive bottom pin portion is connected to a first liner; The negative power terminal comprises a negative mounting portion, one side of the negative mounting portion is connected to a negative first bending portion, the lower side of the negative first bending portion is connected to a negative vertical connecting portion extending to the left, the lower side of the negative vertical connecting portion is sequentially connected to a negative second bending portion, a negative horizontal connecting portion, a negative third bending portion and a negative bottom pin portion, and the negative bottom pin portion is connected to a second liner; The bending directions of the positive electrode second bending portion and the negative electrode second bending portion are the same, the positive electrode vertical connecting portion and the negative electrode vertical connecting portion are overlapped but not in contact, and the positive electrode horizontal connecting portion and the negative electrode horizontal connecting portion are overlapped but not in contact.

2. The power semiconductor module low inductance packaging structure according to claim 1, characterized in that: The lining plate is connected with an auxiliary terminal group for introducing a driving signal into the power semiconductor module unit and leading a test signal out to a peripheral system; the auxiliary terminal group extends out of the top of the outer tube shell.

3. The low inductance packaging structure of a power semiconductor module according to claim 1, characterized in that: A chipset is arranged in the middle area of ​​the liner, and the chipset includes Multiple power chips connected in parallel; The power chip has an area N times that of a power chip in a standard module, where N is greater than or equal to 2.

4. The low inductance packaging structure of a power semiconductor module according to claim 1, characterized in that: The sub-auxiliary terminals include a gate auxiliary terminal, an emitter auxiliary terminal and a collector auxiliary terminal.

5. The low inductance packaging structure of a power semiconductor module according to claim 4, characterized in that: The upper switch control loop comprises: A first metal layer is constructed in an L-shaped structure and is disposed on the first lining plate, one side of the first metal layer is close to a first circumferential edge side of the first lining plate, and the other side of the first metal layer is close to a second circumferential edge side of the first lining plate; an auxiliary lining plate, which is arranged outside the first lining plate and close to the second circumferential edge side of the first lining plate, and an auxiliary metal layer group is arranged on the auxiliary lining plate; A second metal layer is disposed on the first liner and close to the peripheral edge of the first liner; and A third metal layer is arranged on a region of the first substrate except the first metal layer and the second metal layer, and the chipset on the first substrate is arranged on the third metal layer; The first metal layer, the second metal layer and the third metal layer are arranged at intervals with each other; the first metal layer, the auxiliary metal layer group and the control gate of the power chip arranged on the first substrate are connected in sequence through the second bonding wire, the chip group arranged on the first substrate is arranged on the third metal layer, the power chip and the second metal layer are connected through the third bonding wire, the pin of the gate auxiliary terminal is connected to the first metal layer, the pin of the emitter auxiliary terminal is connected to the second metal layer, and the pin of the collector auxiliary terminal is connected to the third metal layer.

6. The low inductance packaging structure of a power semiconductor module according to claim 4, characterized in that: The lower switch control loop comprises: An auxiliary lining plate, which is arranged outside the second lining plate and close to the peripheral edge of the second lining plate, and an auxiliary metal layer group is arranged on the auxiliary lining plate; a fourth metal layer, which is constructed in an L-shaped structure and is disposed on the second lining plate, wherein one side of the fourth metal layer is close to the third circumferential edge side of the second lining plate, and the other side of the fourth metal layer is close to the fourth circumferential edge side of the second lining plate; a fifth metal layer disposed on the second lining plate, one side of the fourth metal layer being close to the second circumferential edge side of the second lining plate, and the other side of the fourth metal layer being close to the third circumferential edge side of the second lining plate; and A sixth metal layer is disposed on a region of the second substrate except the fourth metal layer and the fifth metal layer, and the chipset on the second substrate is disposed on the sixth metal layer; The fourth metal layer, the fifth metal layer and the sixth metal layer are arranged at intervals with each other; the fourth metal layer, the auxiliary metal layer group and the control gate of the power chip arranged on the second substrate are connected in sequence through the second bonding wire, the chip group arranged on the second substrate is arranged on the sixth metal layer, the power chip and the fifth metal layer are connected through the third bonding wire, the pin of the gate auxiliary terminal is connected to the fourth metal layer, the pin of the emitter auxiliary terminal is connected to the fifth metal layer, and the pin of the collector auxiliary terminal is connected to the sixth metal layer.

7. The low inductance packaging structure of a power semiconductor module according to claim 5 or 6, characterized in that: The auxiliary metal layer group includes a plurality of strip metal layers arranged at intervals, and the plurality of strip metal layers are connected in series and are connected to a chip resistor.

8. The low inductance packaging structure of a power semiconductor module according to claim 1, characterized in that: The negative electrode bottom pin portion includes three negative electrode pins arranged at intervals, and the chip group arranged on the second liner includes three power chips.

9. The low inductance packaging structure of a power semiconductor module according to claim 8, characterized in that: The main current loop comprises: A second metal layer is disposed on the first lining plate and is close to the peripheral edge of the first lining plate; A third metal layer is arranged on a region of the first substrate except the second metal layer, and the chipset on the first substrate is arranged on the third metal layer; a fifth metal layer disposed on the second lining plate, one side of the fifth metal layer being close to the second circumferential edge side of the second lining plate, and the other side of the fifth metal layer being close to the third circumferential edge side of the second lining plate; A seventh metal layer is disposed on the second lining plate, one side of the seventh metal layer is close to the first circumferential edge side of the second lining plate, and the other side of the seventh metal layer is close to the second circumferential edge side of the second lining plate; An eighth metal layer is disposed on the second liner plate and is close to a second circumferential edge side of the second liner plate; and A sixth metal layer is disposed on a region of the first substrate excluding the fifth metal layer, the seventh metal layer and the eighth metal layer, and the chipset on the second substrate is disposed on the sixth metal layer; The metal layers on the same liner are spaced apart from each other; the positive electrode bottom pin is connected to the third metal layer, the three negative electrode pins are connected to the fifth metal layer, the seventh metal layer and the eighth metal layer in sequence, and the pin of the AC power terminal is connected to the sixth metal layer.

10. The low inductance packaging structure of a power semiconductor module according to claim 9, characterized in that: The positive bottom pin portion includes two positive pins, a first pin bending portion and a second pin bending portion are respectively arranged between the positive horizontal connecting portion and the two positive pins, a compensation section is arranged between the first pin bending portion and the second pin bending portion, and the compensation section is used to reduce the stress caused by the vibration of the positive power terminal, the bottoms of the two positive pins are connected to the third metal layer, and the spacing between the two positive pins is greater than the preset distance.

11. The low inductance packaging structure of a power semiconductor module according to any one of claims 1 to 6 or 8 to 10, characterized in that: The lining plate is a ceramic lining plate.

12. The low inductance packaging structure of a power semiconductor module according to any one of claims 1 to 6 or 8 to 10, characterized in that: When there are multiple power semiconductor module units, the multiple power semiconductor module sub-units are connected in parallel.

13. A low inductance packaging method for a power semiconductor module, characterized in that: The method is used for manufacturing the low-inductance packaging structure of a power semiconductor module as claimed in any one of claims 1 to 12.

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