Display panel and manufacturing method thereof

Abstract

The present invention discloses a display panel and a method for manufacturing the same. The display panel includes: at least one light-emitting unit; the light-emitting unit includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in sequence; and a reflective cavity structure; the reflective cavity structure is located on the sidewall of the light-emitting unit and includes a first dielectric layer, a first metal layer, a second dielectric layer, and a third dielectric layer stacked in sequence. The third dielectric layer is located on the side of the first dielectric layer away from the light-emitting unit. The refractive index of the first dielectric layer decreases in a direction from the first dielectric layer to the third dielectric layer, and the refractive index of the second dielectric layer is greater than that of the third dielectric layer. The present invention can improve the luminous efficiency of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a method for preparing the same. Background Art

[0002] With advancements in display technology, micro-light-emitting diodes (Micro LEDs) are becoming the core of next-generation display technology due to their advantages such as high brightness, low power consumption, and long lifespan. However, current Micro LED display panels face high costs and complex manufacturing processes during mass production. Furthermore, due to limitations in light energy utilization, traditional light-emitting diode (LED) display panels cannot fully utilize the high brightness characteristics of Micro LEDs. Therefore, improving light energy utilization and, therefore, the brightness of Micro LED display panels while ensuring mass production and cost control has become a key challenge for the industry. Summary of the Invention

[0003] The present invention provides a display panel and a manufacturing method thereof, which can improve the luminous efficiency of the display panel.

[0004] According to one aspect of the present invention, there is provided a display panel, comprising:

[0005] At least one light-emitting unit; the light-emitting unit comprises a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in sequence;

[0006] A reflective cavity structure; the reflective cavity structure is located on the side wall of the light-emitting unit, and the reflective cavity structure includes a first dielectric layer, a first metal layer, a second dielectric layer, and a third dielectric layer arranged in a stacked manner, wherein the third dielectric layer is located on a side of the first dielectric layer away from the light-emitting unit; the refractive index of the first dielectric layer decreases along the direction from the first dielectric layer to the third dielectric layer, and the refractive index of the second dielectric layer is greater than the refractive index of the third dielectric layer.

[0007] Optionally, the first dielectric layer includes a plurality of dielectric sub-layers, and the plurality of dielectric sub-layers are stacked;

[0008] Along the direction from the first dielectric layer to the third dielectric layer, the refractive index difference between adjacent dielectric sub-layers is 0.2-0.5.

[0009] Optionally, the display panel further includes:

[0010] A transparent conductive layer; the transparent conductive layer is located on a side of the second semiconductor layer away from the first semiconductor layer;

[0011] a reflector structure; the reflector structure is located on a side of the transparent conductive layer away from the first semiconductor layer; the reflector structure includes a plurality of refractive units, each refractive unit includes a fourth dielectric layer and a fifth dielectric layer; the fifth dielectric layer is located on a side of the fourth dielectric layer away from the transparent conductive layer; the refractive index of the fourth dielectric layer is greater than the refractive index of the fifth dielectric layer;

[0012] The reflective cavity structure is at least located on the side wall of the quantum well layer, the side wall of the second semiconductor layer, the side wall of the transparent conductive layer and the side wall of the reflective mirror structure.

[0013] Optionally, at least part of the sidewalls of the light-emitting units are inclined sidewalls;

[0014] The angle between the inclined sidewall and the surface of the first semiconductor layer adjacent to the quantum well layer is 65 degrees to 85 degrees.

[0015] Optionally, the display panel further includes:

[0016] a first insulating layer, the first insulating layer being located on a side of the reflector structure away from the first semiconductor layer; the first insulating layer covering the reflector structure, the reflective cavity structure, and the exposed first semiconductor layer; the first insulating layer comprising a first wiring groove and a first through hole, the first wiring groove being connected to the first through hole, the first through hole extending from the bottom of the first wiring groove to the transparent conductive layer; each light-emitting unit corresponding to one first wiring groove and one first through hole; the width of the first wiring groove in a first direction being greater than the width of the first through hole in the first direction, the first direction being perpendicular to the direction from the first semiconductor layer to the second semiconductor layer;

[0017] A first seed layer and a second metal layer are arranged in the first wiring groove and the first through hole; the second metal layer is located on the side of the first seed layer away from the first insulating layer, and the first seed layer covers the side wall of the first through hole and the bottom and side wall of the first wiring groove.

[0018] Optionally, the display panel further includes:

[0019] A driving substrate, a wiring layer, and a second insulating layer are stacked in sequence; the driving substrate is located on a side of the second insulating layer away from the light-emitting unit;

[0020] The wiring layer includes at least one wiring unit; each wiring unit corresponds to a light-emitting unit;

[0021] The second insulating layer includes a second wiring groove and a second through hole, the second wiring groove is connected to the second through hole, and the second through hole extends from the bottom of the second wiring groove to the wiring unit; each wiring unit corresponds to a second wiring groove and a second through hole; the width of the second wiring groove in the first direction is greater than the width of the second through hole in the first direction;

[0022] A second seed layer and a third metal layer are provided in the second wiring trench and the second through hole; the third metal layer is located on a side of the second seed layer away from the second insulating layer, and the second seed layer covers the sidewall of the second through hole and the bottom and sidewall of the second wiring trench;

[0023] The surface of the first insulating layer away from the first semiconductor layer contacts the surface of the second insulating layer away from the driving substrate, the surface of the first seed layer away from the first semiconductor layer contacts the surface of the second seed layer away from the driving substrate, and the surface of the second metal layer away from the first semiconductor layer contacts the surface of the third metal layer away from the driving substrate; the vertical projection of the first seed layer on the driving substrate coincides with the vertical projection of the second seed layer on the driving substrate, and the vertical projection of the second metal layer on the driving substrate coincides with the vertical projection of the third metal layer on the driving substrate.

[0024] According to another aspect of the present invention, there is provided a method for preparing a display panel, comprising:

[0025] forming at least one light-emitting unit; the light-emitting unit comprises a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in sequence;

[0026] A reflective cavity structure is formed on the sidewall of each light-emitting unit; the reflective cavity structure includes a first dielectric layer, a first metal layer, a second dielectric layer, and a third dielectric layer arranged in a stacked manner, wherein the third dielectric layer is located on a side of the first dielectric layer away from the light-emitting unit; the refractive index of the first dielectric layer gradually decreases in a direction from the first dielectric layer to the third dielectric layer, and the refractive index of the second dielectric layer is greater than the refractive index of the third dielectric layer.

[0027] Optionally, at least one light-emitting unit is formed, including:

[0028] forming a first semiconductor sublayer;

[0029] forming a quantum well sublayer on one side of the first semiconductor layer;

[0030] forming a second semiconductor sublayer on a side of the quantum well sublayer away from the first semiconductor sublayer;

[0031] forming a transparent conductive sublayer on a side of the second semiconductor sublayer away from the first semiconductor sublayer;

[0032] The quantum well sublayer, the second semiconductor sublayer, the transparent conductive sublayer and at least a portion of the first semiconductor sublayer are etched to form a first semiconductor layer, a quantum well layer, a second semiconductor layer, and at least one light-emitting unit and a transparent conductive layer.

[0033] Optionally, after forming at least one light-emitting unit, the method further includes:

[0034] forming a photoresist layer on a side of the second semiconductor layer away from the first semiconductor layer; the photoresist layer exposes a surface of the transparent conductive layer away from the first semiconductor layer;

[0035] A reflector structure is formed on a side of the transparent conductive layer away from the first semiconductor layer; the reflector structure includes a plurality of refractive units, each of which includes a fourth dielectric layer and a fifth dielectric layer; the fifth dielectric layer is located on a side of the fourth dielectric layer away from the transparent conductive layer; and the refractive index of the fourth dielectric layer is greater than the refractive index of the fifth dielectric layer.

[0036] The photoresist layer is removed.

[0037] Optionally, after forming the reflective cavity structure on the sidewall of each light-emitting unit, the method further includes:

[0038] forming a first insulating sublayer on a side of the reflector structure away from the first semiconductor layer; the first insulating sublayer covers the reflector structure, the reflective cavity structure and the exposed first semiconductor layer;

[0039] The first insulating sublayer is etched to form a first insulating layer, a first wiring trench, and a first through hole; the first wiring trench is connected to the first through hole, and the first through hole extends from the bottom of the first wiring trench to the transparent conductive layer; each light-emitting unit corresponds to a first wiring trench and a first through hole; the width of the first wiring trench in a first direction is greater than the width of the first through hole in the first direction, and the first direction is perpendicular to the direction from the first semiconductor layer to the second semiconductor layer;

[0040] forming a first seed layer in the first wiring groove and the first through hole; the first seed layer covers the side wall of the first through hole and the bottom and side wall of the first wiring groove;

[0041] forming a second metal layer on a side of the first seed layer away from the first insulating layer; the second metal layer is located in the first wiring groove and the first through hole;

[0042] forming a driving substrate;

[0043] forming a patterned layer on one side of the driving substrate;

[0044] forming a wiring sublayer on a side of the patterned layer away from the driving substrate;

[0045] The patterned layer is removed to form a wiring layer; the wiring layer includes at least one wiring unit; each wiring unit corresponds to a light-emitting unit;

[0046] forming a second insulating sublayer on a side of the wiring layer away from the driving substrate;

[0047] The second insulating sublayer is etched to form a second insulating layer, a second wiring groove, and a second through hole; the second wiring groove is connected to the second through hole, and the second through hole extends from the bottom of the first wiring groove to the wiring unit; each wiring unit corresponds to a second wiring groove and a second through hole; the width of the second wiring groove in the first direction is greater than the width of the second through hole in the first direction;

[0048] forming a second seed layer in the second wiring groove and the second through hole; the second seed layer covers the side wall of the second through hole and the bottom and side wall of the second wiring groove;

[0049] forming a third metal layer on a side of the second seed layer away from the second insulating layer; the third metal layer is located in the second wiring groove and the second through hole;

[0050] Through a hybrid bonding process, the surface of the first insulating layer away from the first semiconductor layer contacts the surface of the second insulating layer away from the driving substrate, the surface of the first seed layer away from the first semiconductor layer contacts the surface of the second seed layer away from the driving substrate, and the surface of the second metal layer away from the first semiconductor layer contacts the surface of the third metal layer away from the driving substrate; the vertical projection of the first seed layer on the driving substrate coincides with the vertical projection of the second seed layer on the driving substrate, and the vertical projection of the second metal layer on the driving substrate coincides with the vertical projection of the third metal layer on the driving substrate.

[0051] The display panel provided by the technical solution of the embodiment of the present invention includes: at least one light-emitting unit; the light-emitting unit includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in sequence; a reflective cavity structure; the reflective cavity structure is located on the sidewall of the light-emitting unit, and the reflective cavity structure includes a first dielectric layer, a first metal layer, a second dielectric layer, and a third dielectric layer stacked in sequence, with the third dielectric layer located on the side of the first dielectric layer away from the light-emitting unit; the refractive index of the first dielectric layer decreases along the direction from the first dielectric layer to the third dielectric layer, and the refractive index of the second dielectric layer is greater than the refractive index of the third dielectric layer. By providing a reflective cavity structure, the embodiment of the present invention can reflect a light beam back and forth within the reflective cavity structure, effectively increasing the travel length of the light within the cavity, improving light intensity and photon utilization efficiency, and improving color purity and spectral control, thereby improving the luminous efficiency of the display panel.

[0052] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 It is a structural schematic diagram of a display panel provided by an embodiment of the present invention.

[0055] Figure 2 This is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present invention.

[0056] Figure 3 yes Figure 2 A detailed flow chart included in S110.

[0057] Figure 4-Figure 23 It is a schematic diagram of the intermediate structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "first," "second," and the like in the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0060] An embodiment of the present invention provides a display panel, Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, with reference to Figure 1 The display panel includes: at least one light emitting unit 10; the light emitting unit 10 includes a first semiconductor layer 11, a quantum well layer 12 and a second semiconductor layer 13 which are stacked in sequence.

[0061] A reflective cavity structure 20; the reflective cavity structure 20 is located on the side wall of each light-emitting unit 10, and the reflective cavity structure 20 includes a first dielectric layer 21, a first metal layer 22, a second dielectric layer 23, and a third dielectric layer 24 arranged in a stacked manner. The third dielectric layer 24 is located on the side of the first dielectric layer 21 away from the light-emitting unit 10; the refractive index of the first dielectric layer 21 decreases along the direction from the first dielectric layer 21 to the third dielectric layer 24, and the refractive index of the second dielectric layer 23 is greater than the refractive index of the third dielectric layer 24.

[0062] The size of the light-emitting unit 10 includes but is not limited to the size of commonly used micro-display chips, such as 5 μm×5 μm and 3 μm×3 μm. At least one light-emitting unit 10 may include any one of a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit. In other embodiments, different processes may be used to make at least some of the light-emitting units 10 emit different colors, thereby realizing full-color display of the display panel. Figure 1 The light-emitting unit in FIG is a cross-sectional view. Figure 1 The shape of the top view of the light emitting unit 10 may include a rectangle, a circle, a triangle, or any other polygon. The first semiconductor layer 11 may be an N-type gallium nitride layer, and the second semiconductor layer 13 may be a P-type gallium nitride layer. Alternatively, the first semiconductor layer 11 may be a P-type gallium nitride layer, and the second semiconductor layer 13 may be an N-type gallium nitride layer. Figure 1 At least two light-emitting units 10 share the first semiconductor layer 11, and each light-emitting unit 10 corresponds to a quantum well layer 12 and a second semiconductor layer 13. Figure 1 This is only an example of a display panel structure; alternatively, at least two light-emitting units 10 may not share the first semiconductor layer 11. Each light-emitting unit 10 may correspond to a first semiconductor layer 11, a quantum well layer 12 and a second semiconductor layer 13. The first semiconductor layers 11 of all light-emitting units 10 are electrically connected by providing a whole transparent conductive layer on the surface of the first semiconductor layer 11 of each light-emitting unit 10.

[0063] Specifically, the reflective cavity structure 20 includes a first dielectric layer 21, a first metal layer 22, a second dielectric layer 23 and a third dielectric layer 24 that are stacked. The refractive index of the first dielectric layer 21 decreases along the direction from the first dielectric layer 21 to the third dielectric layer 24, and can reflect light. Exemplarily, the first dielectric layer may include multiple dielectric sublayers, and the refractive index of the dielectric sublayer farther away from the light-emitting unit 10 is lower, and the refractive index difference between adjacent dielectric sublayers is 0.2-0.5. The thickness of the first metal layer 22 can be 45nm-55nm, for example, 50nm can be selected. The first metal layer 22 is a very thin metal layer that can reflect light. The refractive index of the second dielectric layer 23 is greater than the refractive index of the third dielectric layer 24, and can reflect light passing through the first metal layer 22.

[0064] The reflective cavity structure 20 can reflect the light beam back and forth in the reflective cavity structure 20 by setting the first dielectric layer 21, the first metal layer 22, the second dielectric layer 23 and the third dielectric layer 24, thereby effectively increasing the travel length of the light in the cavity. The accumulation of multiple reflections can greatly increase the light intensity, especially at a specific wavelength, resonance can be formed, which can further enhance the light signal; and through the design of the reflective cavity structure 20, the photon utilization efficiency can be greatly improved by multiple reflections, superposition and enhancement of photons in the reflective cavity structure 20 under the premise of limited light source power or no additional input power, without generating a standing wave effect; the reflective cavity structure 20 can enhance light of a specific wavelength through interference and resonance effects, so that the Micro LED display panel has a narrower spectral emission and improves color purity; for display applications, especially high-resolution Micro LED display panels, it helps to improve color expression and contrast and enhance spectral control; conventional Bragg reflectors (DBRs) are more dependent on the periodic arrangement of materials and mainly play a filtering role, and cannot play a resonance enhancement role.

[0065] The display panel provided by the technical solution of the embodiment of the present invention includes: at least one light-emitting unit 10; the light-emitting unit 10 includes a first semiconductor layer 11, a quantum well layer 12, and a second semiconductor layer 13 stacked in sequence; and a reflective cavity structure 20. The reflective cavity structure 20 is located on the sidewall of each light-emitting unit 10 and includes a first dielectric layer 21, a first metal layer 22, a second dielectric layer 23, and a third dielectric layer 24 stacked in sequence. The third dielectric layer 24 is located on the side of the first dielectric layer 21 away from the light-emitting unit 10. The refractive index of the first dielectric layer 21 decreases along the direction from the first dielectric layer 21 to the third dielectric layer 24, and the refractive index of the second dielectric layer 23 is greater than the refractive index of the third dielectric layer 24. By providing the reflective cavity structure 20, the embodiment of the present invention can reflect a light beam back and forth within the reflective cavity structure 20, effectively increasing the travel length of the light within the cavity, improving light intensity and photon utilization efficiency, and enhancing color purity and spectral control, thereby improving the luminous efficiency of the display panel.

[0066] Optional, reference Figure 1 The first dielectric layer 21 includes a plurality of dielectric sublayers, which are stacked. In the direction from the first dielectric layer 21 to the third dielectric layer 24 , the refractive index difference between adjacent dielectric sublayers is 0.2-0.5.

[0067] Wherein, the thickness of each dielectric sublayer is 70nm-80nm; illustratively, Figure 1The light emitting unit 10 includes three dielectric sublayers, namely the first dielectric sublayer A1, the second dielectric sublayer A2 and the third dielectric sublayer A3. The first dielectric sublayer A1 is closest to the light emitting unit 10, so the refractive index of the first dielectric sublayer A1 is set to the highest, and the refractive index of the second dielectric sublayer A2 and the third dielectric sublayer A3 decreases in sequence, which can increase the travel length of light and improve the light intensity and light extraction efficiency.

[0068] Optionally, the display panel further includes: a transparent conductive layer 30 ; the transparent conductive layer 30 is located on a side of the second semiconductor layer 13 away from the first semiconductor layer 11 .

[0069] A reflector structure; the reflector structure is located on the side of the transparent conductive layer 30 away from the first semiconductor layer 11; the reflector structure includes a plurality of refractive units 40, each refractive unit 40 includes a fourth dielectric layer 41 and a fifth dielectric layer 42; the fifth dielectric layer 42 is located on the side of the fourth dielectric layer 41 away from the transparent conductive layer 30; the refractive index of the fourth dielectric layer 41 is greater than the refractive index of the fifth dielectric layer 42; the reflective cavity structure is located at least on the sidewalls of the quantum well layer 12, the sidewalls of the second semiconductor layer 13, the sidewalls of the transparent conductive layer 30 and the sidewalls of the reflector structure.

[0070] Among them, the material of the transparent conductive layer 30 can be indium tin oxide (ITO), and the reflector structure is a structure of alternatingly deposited high and low refractive indices, which can be arranged according to a certain period to form a Bragg reflection grating structure. The reflector structure can reflect light of a specific wavelength, and the reflectivity can reach more than 99%; by setting a reflector structure on the top of the light-emitting unit 10 and setting a reflective cavity structure on the side wall, the overall light output efficiency of the light-emitting unit 10 can be increased by 1.5-1.8 times.

[0071] Optional, reference Figure 1 , at least part of the sidewall of the light emitting unit is an inclined sidewall; the angle B between the inclined sidewall and the surface of the first semiconductor layer adjacent to the quantum well layer is 65 degrees to 85 degrees.

[0072] Among them, the side walls of at least part of the light-emitting units are inclined side walls, and the first semiconductor layer 11, the quantum well layer 12 and the second semiconductor layer 13 can be etched through an etching process, so that the side walls of the quantum well layer 12, the side walls of the second semiconductor layer 13 and part of the side walls of the first semiconductor layer 11 form inclined side walls; the angle B between the inclined side walls and the surface of the first semiconductor layer adjacent to the quantum well layer is 65 degrees to 85 degrees, which can cooperate with the reflective cavity structure 20 to improve the light intensity and photon utilization efficiency, improve the color purity and spectrum control, and thus improve the luminous efficiency of the display panel.

[0073] Optional, reference Figure 1The display panel also includes: a first insulating layer 50, which is located on the side of the reflector structure away from the first semiconductor layer 11; the first insulating layer 50 covers the reflector structure, the reflective cavity structure 20 and the exposed first semiconductor layer 11; the first insulating layer 50 includes a first wiring groove 51 and a first through hole 52, the first wiring groove 51 is connected to the first through hole 52, and the first through hole 52 passes through the bottom of the first wiring groove 51 to the transparent conductive layer 30; each light-emitting unit 10 corresponds to a first wiring groove 51 and a first through hole 52; the width of the first wiring groove 51 in the first direction X is greater than the width of the first through hole 52 in the first direction X, and the first direction X is perpendicular to the direction of the first semiconductor layer 11 pointing to the second semiconductor layer 13.

[0074] A first seed layer 61 and a second metal layer 71 are arranged in the first wiring groove 51 and the first through hole 52; the second metal layer 71 is located on the side of the first seed layer 61 away from the first insulating layer 50, and the first seed layer 61 covers the side walls of the first through hole 52 and the bottom and side walls of the first wiring groove 51.

[0075] Among them, the material of the first insulating layer 50 includes but is not limited to silicon oxide, nitrogen oxide and low dielectric constant material. Exemplarily, the material of the first insulating layer 50 can be SiO2, Si3N4 or SiCO, etc.; the first insulating layer 50 covers the reflector structure, the reflective cavity structure 20 and the exposed first semiconductor layer 11, and the exposed first semiconductor layer 11 refers to the first semiconductor layer 11 that is not covered by the reflective cavity structure 20 and the quantum well layer 12. The first wiring groove 51 and the first through-hole 52 can be formed in the first insulating layer 50 through a dual damascene process, two photolithography and etching steps; the material of the second metal layer 71 can be a metal material; the material of the first seed layer 61 can include tantalum (Ta), tantalum nitride (TaN), titanium (Ti) or titanium nitride (TiN), or a combination of several materials; the first seed layer 61 can play the role of conducting electricity, promoting metal growth, improving adhesion, preventing diffusion and regulating crystal structure, and is a key step in achieving a uniform and stable metal interconnection structure; by setting the width of the first wiring groove 51 in the first direction X to be greater than the width of the first through-hole 52 in the first direction X, the size of the second metal layer 71 in the first wiring groove 51 can be larger, which can improve the quality of electrical connection during subsequent metal bonding, so that it can be used in high performance and high density.

[0076] Optional, reference Figure 1 The display panel also includes: a driving substrate 80, a wiring layer 90 and a second insulating layer 100 stacked in sequence; the driving substrate 80 is located on a side of the second insulating layer 100 away from the light-emitting unit 10; the wiring layer 90 includes at least one wiring unit 91; each wiring unit 91 corresponds to one light-emitting unit 10.

[0077] The second insulating layer 100 includes a second wiring groove 101 and a second through hole 102. The second wiring groove 101 is connected to the second through hole 102. The second through hole 102 passes through the bottom of the second wiring groove 101 to the wiring unit 91; each wiring unit 91 corresponds to a second wiring groove 101 and a second through hole 102; the width of the second wiring groove 101 in the first direction X is greater than the width of the second through hole 102 in the first direction X.

[0078] A second seed layer 62 and a third metal layer 72 are arranged in the second wiring groove 101 and the second through hole 102; the third metal layer 72 is located on the side of the second seed layer 62 away from the second insulating layer 100, and the second seed layer 62 covers the side wall of the second through hole 102 and the bottom and side wall of the second wiring groove 101.

[0079] The surface of the first insulating layer 50 away from the first semiconductor layer 11 contacts the surface of the second insulating layer 100 away from the driving substrate 80, the surface of the first seed layer 61 away from the first semiconductor layer 11 contacts the surface of the second seed layer 62 away from the driving substrate 80, and the surface of the second metal layer 71 away from the first semiconductor layer 11 contacts the surface of the third metal layer 72 away from the driving substrate; the vertical projection of the first seed layer 61 on the driving substrate 80 coincides with the vertical projection of the second seed layer 62 on the driving substrate 80, and the vertical projection of the second metal layer 71 on the driving substrate 80 coincides with the vertical projection of the third metal layer 72 on the driving substrate 80.

[0080] Among them, the material of the second insulating layer 100 includes but is not limited to silicon oxide, nitride oxide and low dielectric constant material. Exemplarily, the material of the second insulating layer 100 can be SiO2, Si3N4 or SiCO; the second insulating layer 100 covers the wiring unit 91 and the driving substrate 80 not covered by the wiring unit 91, and can form a second wiring groove 101 and a second through-hole 102 in the second insulating layer 100 through a dual damascene process, two photolithography and etching. The material of the third metal layer 72 can be the same as that of the second metal layer 71; the material of the second seed layer 62 can include tantalum (Ta), tantalum nitride (TaN), titanium (Ti) or titanium nitride (TiN), or a combination of several materials; the second seed layer 62 has the same function as the first seed layer 61; by setting the width of the second wiring groove 101 in the first direction X to be greater than the width of the second through-hole 102 in the first direction X, the size of the second metal layer 71 in the first wiring groove 51 can be larger, which can improve the electrical connection quality during subsequent metal bonding, so that it can be used in high performance and high density.

[0081] Hybrid bonding can be used to ensure that the surface of the first insulating layer 50 away from the first semiconductor layer 11 contacts the surface of the second insulating layer 100 away from the drive substrate 80, the surface of the first seed layer 61 away from the first semiconductor layer 11 contacts the surface of the second seed layer 62 away from the drive substrate 80, and the surface of the second metal layer 71 away from the first semiconductor layer 11 contacts the surface of the third metal layer 72 away from the drive substrate. The vertical projection of the first seed layer 61 on the drive substrate 80 overlaps with the vertical projection of the second seed layer 62 on the drive substrate 80, and the vertical projection of the second metal layer 71 on the drive substrate 80 overlaps with the vertical projection of the third metal layer 72 on the drive substrate 80. Hybrid bonding technology, as a chip interconnect method, excels in increasing device density and reducing parasitic resistance and capacitance, and is particularly important for improving photoelectric efficiency.

[0082] An embodiment of the present invention provides a method for manufacturing a display panel based on the above embodiments, which is used to manufacture the display panel described in any of the above embodiments. Figure 2 is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present invention, with reference to Figure 2 , the preparation method comprises:

[0083] S110, forming at least one light-emitting unit; the light-emitting unit includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in sequence.

[0084] S120. Form a reflective cavity structure on the side wall of each light-emitting unit; the reflective cavity structure includes a first dielectric layer, a first metal layer, a second dielectric layer, and a third dielectric layer that are stacked, and the third dielectric layer is located on a side of the first dielectric layer away from the light-emitting unit; the refractive index of the first dielectric layer gradually decreases in a direction from the first dielectric layer to the third dielectric layer, and the refractive index of the second dielectric layer is greater than the refractive index of the third dielectric layer.

[0085] The embodiment of the present invention forms a reflective cavity structure, which can reflect the light beam back and forth within the reflective cavity structure, effectively increasing the travel length of the light in the cavity, improving light intensity and photon utilization efficiency, improving color purity and spectral control, and thus improving the luminous efficiency of the display panel.

[0086] Optionally, based on the above embodiment, Figure 3 yes Figure 2 A detailed flow chart included in S110, refer to Figure 3 The embodiment of the present invention further refines S110, specifically, S110, forming at least one light-emitting unit, as follows:

[0087] S111 , forming a first semiconductor sublayer.

[0088] S112 , forming a quantum well sublayer on one side of the first semiconductor layer.

[0089] S113 , forming a second semiconductor sublayer on a side of the quantum well layer away from the first semiconductor layer.

[0090] S114 , forming a transparent conductive sublayer on a side of the second semiconductor layer away from the first semiconductor layer.

[0091] S115 , etching the quantum well sublayer, the second semiconductor sublayer, the transparent conductive sublayer, and at least a portion of the first semiconductor sublayer to form a first semiconductor layer, a quantum well layer, a second semiconductor layer, and a transparent conductive layer.

[0092] Among them, the specific process method is the same as the subsequent method.

[0093] Figure 4-Figure 23 is a schematic diagram of the intermediate structure of a display panel provided by an embodiment of the present invention, with reference to Figure 4-Figure 23 , the preparation method comprises:

[0094] S210 , providing a substrate.

[0095] Among them, reference Figure 4 The substrate 01 may be a silicon-based substrate or a sapphire-based substrate but is not limited to the above two types.

[0096] S220 , forming a buffer layer on one side of the substrate.

[0097] Among them, reference Figure 4 The material of the buffer layer 02 may be at least one of gallium nitride (GaN), aluminum nitride (AlN) or aluminum gallium nitride (AlGaN).

[0098] S230 , forming a first semiconductor sub-layer.

[0099] Among them, reference Figure 4 , a first semiconductor sublayer 03 may be formed on a side of the buffer layer 02 away from the substrate 01. The first semiconductor sublayer 03 may be N-GaN.

[0100] S240 , forming a quantum well sublayer on one side of the first semiconductor layer.

[0101] Among them, reference Figure 4 , a quantum well sublayer 04 may be formed on the side of the first semiconductor sublayer 03 away from the substrate 01 .

[0102] S250 , forming a second semiconductor sublayer on a side of the quantum well sublayer away from the first semiconductor sublayer.

[0103] Among them, reference Figure 4A second semiconductor sublayer 05 can be formed on the side of the quantum well sublayer 04 away from the first semiconductor sublayer 03 through an epitaxial growth process. The second semiconductor sublayer 05 can be P-GaN. The substrate 01, buffer layer 02, first semiconductor sublayer 03, quantum well sublayer 04, and second semiconductor sublayer 05 form a gallium nitride epitaxial wafer. The gallium nitride epitaxial wafer can be 4 inches, 6 inches, 8 inches, or 12 inches in size.

[0104] S260 , forming a transparent conductive sublayer on a side of the second semiconductor sublayer away from the first semiconductor sublayer.

[0105] Among them, reference Figure 5 , a transparent conductive sub-layer 06 can be formed on the side of the second semiconductor sub-layer 05 away from the first semiconductor sub-layer 03 by a sputtering process.

[0106] S270, etching the quantum well sublayer, the second semiconductor sublayer, the transparent conductive sublayer and at least part of the first semiconductor sublayer to form a first semiconductor layer, a quantum well layer, a second semiconductor layer, and at least one light-emitting unit and a transparent conductive layer.

[0107] Among them, reference Figure 6 The first semiconductor sublayer 03, the quantum well sublayer 04, the second semiconductor sublayer 05 and the transparent conductive sublayer 06 can be etched through an etching process, so that the side walls of the quantum well sublayer 04, the second semiconductor sublayer 05, the transparent conductive sublayer 06 and part or all of the first semiconductor sublayer 03 are inclined side walls, and the angle between the inclined side wall and the surface of the first semiconductor layer 11 adjacent to the quantum well layer 12 is 65 degrees to 85 degrees; the angle of the inclined side wall is designed to cooperate with the subsequent reflection enhancement cavity.

[0108] S280 , forming a photoresist layer on a side of the second semiconductor layer away from the first semiconductor layer; the photoresist layer exposes a surface of the transparent conductive layer away from the first semiconductor layer.

[0109] Among them, reference Figure 7 A photoresist layer 07 is formed on the side of the second semiconductor layer 13 away from the first semiconductor layer 11, and the light-emitting unit is wrapped and protected by the photoresist layer 07; the photoresist layer 07 covers the sidewalls of the quantum well layer 12, the sidewalls of the second semiconductor layer 13, and the sidewalls of the transparent conductive layer 30.

[0110] S290. Form a reflector structure on a side of the transparent conductive layer away from the first semiconductor layer; the reflector structure includes a plurality of refractive units, each refractive unit includes a fourth dielectric layer and a fifth dielectric layer; the fifth dielectric layer is located on a side of the fourth dielectric layer away from the transparent conductive layer; the refractive index of the fourth dielectric layer is greater than the refractive index of the fifth dielectric layer.

[0111] Among them, reference Figure 7A reflector structure is formed on the side of the transparent conductive layer 30 away from the first semiconductor layer 11. Fourth dielectric layers 41 and fifth dielectric layers 42 with high and low refractive indices are alternately deposited on top of the transparent conductive layer 30 and arranged at a certain period to form a Bragg reflection grating structure, which reflects light of a specific wavelength with a reflectivity of more than 99%.

[0112] S300 , removing the photoresist layer.

[0113] S310. Form a reflective cavity structure on the side wall of each light-emitting unit; the reflective cavity structure includes a first dielectric layer, a first metal layer, a second dielectric layer, and a third dielectric layer that are stacked, and the third dielectric layer is located on a side of the first dielectric layer away from the light-emitting unit; the refractive index of the first dielectric layer gradually decreases in a direction from the first dielectric layer to the third dielectric layer, and the refractive index of the second dielectric layer is greater than the refractive index of the third dielectric layer.

[0114] Among them, reference Figure 8 A first dielectric layer 21 can be deposited on the side wall of the light-emitting unit 10. The first dielectric layer 21 includes a first dielectric sublayer A1, a second dielectric sublayer A2, and a third dielectric sublayer A3. Thin films of materials with a gradient refractive index are sequentially deposited on the side wall of the light-emitting structure. The refractive index is high near the light-emitting unit 10 and decreases gradually outward. The refractive index difference is within a range of 0.2 to 0.5. The refractive index of the first dielectric sublayer A1 is greater than that of the second dielectric sublayer A2, and the refractive index of the second dielectric sublayer A2 is greater than that of the third dielectric sublayer A3. A first metal layer 22 is then deposited. The first metal layer 22 is a metal thin film layer. After that, two layers of dielectric films with high and low refractive indices are alternately deposited on the first metal layer 22 to form a second dielectric layer 23 and a third dielectric layer 24, thereby completing the preparation of the sidewall reflection cavity structure 20.

[0115] S320, forming a first insulating sublayer on a side of the reflector structure away from the first semiconductor layer; the first insulating sublayer covers the reflector structure, the reflective cavity structure and the exposed first semiconductor layer.

[0116] Among them, reference Figure 9 , forming a first insulator layer 081 by a deposition process; Figure 10 The step above the first insulator layer 081 is smoothed by chemical mechanical polishing (CMP) to form the first insulator layer 082 .

[0117] S330, etching the first insulating sublayer to form a first insulating layer, a first wiring groove and a first through hole; the first wiring groove is connected to the first through hole, and the first through hole passes through the bottom of the first wiring groove to the transparent conductive layer; each light-emitting unit corresponds to a first wiring groove and a first through hole; the width of the first wiring groove in the first direction is greater than the width of the first through hole in the first direction, and the first direction is perpendicular to the direction of the first semiconductor layer pointing to the second semiconductor layer.

[0118] Among them, reference Figure 11 , the first wiring groove 51 and the first insulator second layer 083 are formed by one-time photolithography and etching; Figure 12 , and then a single photolithography and etching process is performed to form the first through-hole 52, thereby forming the shape of the first insulating layer 50. Through the "dual damascene process," after two photolithography and etching steps, the first wiring trench 51 and the first through-hole 52 are formed in the same layer of insulating material, completing the conductive metal and metal wiring in one go. In the process of preparing the first wiring trench 51 and the first through-hole 52, a dual damascene (trench-first) process is adopted. First, the first wiring trench 51 is patterned and etched, and then the first through-hole 52 is defined and etched. The specific steps are as follows: first, a first photolithography is performed on the first insulating sublayer to define the position of the first wiring trench 51; the first wiring trench 51 is etched to form the first wiring trench 51; a second photolithography is performed to define the position of the first through-hole 52; and the first through-hole 52 is etched to facilitate the subsequent formation of a vertical electrical connection.

[0119] Specifically, the advantages of the trench-first process are: wiring trench etching is easier. Since the wiring trench is defined and etched first, the structure of the entire first insulating sublayer is more complete, which makes the shape and sidewall quality of the wiring trench easier to control, especially in high-density designs; the wiring trench is more closely integrated with the through-hole structure. Etching the wiring trench first can better match the structure of the through-hole, especially in tiny process nodes, which can improve the electrical connection quality of the wiring trench and the through-hole.

[0120] S340 , forming a first seed layer in the first wiring trench and the first through hole; the first seed layer covers the sidewalls of the first through hole and the bottom and sidewalls of the first wiring trench.

[0121] Among them, reference Figure 13 The first seed layer 61 can be deposited by physical sputtering. The material for the first seed layer 61 can be tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination of these materials. The first seed layer 61 primarily serves to conduct electricity, promote metal growth, enhance adhesion, prevent diffusion, and regulate crystal structure. It is a key step in achieving a uniform and stable metal interconnect structure.

[0122] S350 , forming a second metal layer on a side of the first seed layer away from the first insulating layer; the second metal layer is located in the first wiring groove and in the first through hole.

[0123] Among them, reference Figure 14 , a second metal layer 71 is formed through a metal filling and CMP process.

[0124] S360: forming a driving substrate.

[0125] S370 , forming a patterned layer on one side of the driving substrate.

[0126] Among them, reference Figure 15 , a patterned layer 09 is formed on one side of the driving substrate 80 through a photolithography process.

[0127] S380 , forming a wiring sublayer on a side of the patterned layer away from the driving substrate.

[0128] Among them, reference Figure 16 , metal is deposited by electron beam deposition process to form wiring sublayer 010.

[0129] S390, removing the patterned layer to form a wiring layer; the wiring layer includes at least one wiring unit; each wiring unit corresponds to a light-emitting unit.

[0130] Among them, reference Figure 17 The patterned layer is removed by lift-off to form a wiring layer 90. The wiring layer 90 is a redistribution layer (RDL) circuit. The driving substrate 80 includes a driving circuit. The redistribution layer (RDL) circuit can realize the interconnection between the transparent conductive electrode and the driving circuit.

[0131] Specifically, redistribution layer (RDL) technology tightly connects the driver substrate to the transparent conductive electrodes of the light-emitting units. This wiring layer achieves electrical interconnection through processes such as thin-film deposition and photolithography, helping to reduce production complexity and costs. This wiring layer 90 simplifies traditional wiring structures, improves signal transmission stability and efficiency, and reduces losses and space waste in traditional wiring processes.

[0132] S400 , forming a second insulating sublayer on a side of the wiring layer away from the driving substrate.

[0133] Among them, reference Figure 18 , a second insulating sublayer 011 is formed through a deposition process.

[0134] S410. Etch the second insulating sublayer to form a second insulating layer, a second wiring groove and a second through hole; the second wiring groove is connected to the second through hole, and the second through hole passes through the bottom of the first wiring groove to the wiring unit; each wiring unit corresponds to a second wiring groove and a second through hole; the width of the second wiring groove in the first direction is greater than the width of the second through hole in the first direction.

[0135] Among them, reference Figure 19 , a second wiring groove 101 and a second insulator layer 012 are formed by one photolithography and etching; Figure 20 , and then a second through hole 102 is formed by photolithography and etching, thereby forming the shape of the second insulating layer 100.

[0136] S420 , forming a second seed layer in the second wiring trench and in the second through hole; the second seed layer covers the sidewalls of the second through hole and the bottom and sidewalls of the second wiring trench.

[0137] Among them, reference Figure 21 The second seed layer 62 may be deposited by physical sputtering, and the material of the second seed layer 62 is the same as that of the first seed layer 61 .

[0138] S430 , forming a third metal layer on a side of the second seed layer away from the second insulating layer; the third metal layer is located in the second wiring groove and the second through hole.

[0139] Among them, reference Figure 22 , a third metal layer 72 is formed by a metal filling and CMP process.

[0140] S440. Through a hybrid bonding process, the surface of the first insulating layer away from the first semiconductor layer is in contact with the surface of the second insulating layer away from the driving substrate, the surface of the first seed layer away from the first semiconductor layer is in contact with the surface of the second seed layer away from the driving substrate, and the surface of the second metal layer away from the first semiconductor layer is in contact with the surface of the third metal layer away from the driving substrate; the vertical projection of the first seed layer on the driving substrate coincides with the vertical projection of the second seed layer on the driving substrate, and the vertical projection of the second metal layer on the driving substrate coincides with the vertical projection of the third metal layer on the driving substrate.

[0141] Among them, reference Figure 23 The hybrid bonding process can achieve hybrid bonding with higher packaging density and better performance than traditional packaging by bonding the upper light-emitting unit 10 and the lower driving substrate 80 in the form of metal material-metal material and insulating material-insulating material. The metal material can be copper (Cu).

[0142] Specifically, hybrid-bonding technology, as an emerging chip interconnection method, excels in increasing device density, reducing parasitic resistance and capacitance, and is particularly important for improving photoelectric efficiency. The mass production packaging method currently commonly used on the market is to eutectic weld the electrodes of the light-emitting unit to the metal contact points on the driver substrate. It can form a strong welding connection at a relatively low temperature and is characterized by its good mechanical stability; however, it has problems such as high welding temperature, high contact resistance, insufficient thermal management capabilities, uneven welding layers, and mechanical fatigue, which limit its use in high-performance and high-density applications. With increasing performance requirements, technologies such as hybrid bonding are gradually becoming alternatives to eutectic bonding, especially in scenarios that require higher efficiency and better thermal management.

[0143] The embodiment of the present invention adopts a hybrid bonding process, which can have the following advantages: reduced resistance loss; hybrid bonding technology greatly reduces resistance and signal transmission losses through direct copper-copper connection. It enables the display panel to be driven with higher efficiency, improving the overall brightness. Compact structural design: Because hybrid bonding technology can achieve higher integration, the close combination of the light-emitting unit and the driving circuit reduces the distance of signal transmission, thereby reducing delay and energy loss. This compactness helps smaller light sources achieve higher brightness. Excellent thermal management: hybrid bonding technology can more effectively manage heat and improve heat dissipation performance, which is crucial for improving the brightness of the display panel and extending its service life, because excessively high temperatures will reduce the luminous efficiency of the light-emitting unit. Improved photoelectric conversion efficiency: By reducing interface defects and poor contact, hybrid bonding technology can improve photoelectric conversion efficiency, which means that under the same input current, the light-emitting unit can emit stronger light.

[0144] S450 , removing the buffer layer and the substrate.

[0145] Among them, reference Figure 1 , Figure 1 for Figure 23 The structure of the substrate 01 and the buffer layer 02 is removed.

[0146] The method for manufacturing a display panel provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the display panel described in any embodiment of the present invention.

[0147] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0148] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: at least one light-emitting unit; The light emitting unit includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in sequence; Reflective cavity structure; The reflective cavity structure is located on a side wall of the light-emitting unit, and includes a first dielectric layer, a first metal layer, a second dielectric layer, and a third dielectric layer that are stacked. The third dielectric layer is located on a side of the first dielectric layer away from the light-emitting unit. The refractive index of the first dielectric layer decreases along a direction from the first dielectric layer to the third dielectric layer, and the refractive index of the second dielectric layer is greater than the refractive index of the third dielectric layer. The first dielectric layer includes a plurality of dielectric sub-layers, and the plurality of dielectric sub-layers are stacked; Along the direction from the first dielectric layer to the third dielectric layer, the refractive index difference between adjacent dielectric sublayers is 0.2-0.5; The thickness of the first metal layer is 45 nm-55 nm.

2. The display panel according to claim 1, wherein: Also includes: a transparent conductive layer; The transparent conductive layer is located on a side of the second semiconductor layer away from the first semiconductor layer; reflector structure; The reflector structure is located on a side of the transparent conductive layer away from the first semiconductor layer; the reflector structure includes a plurality of refractive units, each of which includes a fourth dielectric layer and a fifth dielectric layer; The fifth dielectric layer is located on a side of the fourth dielectric layer away from the transparent conductive layer; the refractive index of the fourth dielectric layer is greater than the refractive index of the fifth dielectric layer; The reflective cavity structure is at least located on a side wall of the quantum well layer, a side wall of the second semiconductor layer, a side wall of the transparent conductive layer, and a side wall of the reflective mirror structure.

3. The display panel according to claim 1, wherein: At least part of the sidewalls of the light-emitting unit are inclined sidewalls; An angle between the inclined sidewall and a surface of the first semiconductor layer adjacent to the quantum well layer is 65 degrees to 85 degrees.

4. The display panel according to claim 2, wherein: Also includes: a first insulating layer, wherein the first insulating layer is located on a side of the reflector structure away from the first semiconductor layer; The first insulating layer covers the reflector structure, the reflective cavity structure, and the exposed first semiconductor layer; the first insulating layer includes a first wiring groove and a first through hole, the first wiring groove is connected to the first through hole, and the first through hole extends from the bottom of the first wiring groove to the transparent conductive layer; each light-emitting unit corresponds to a first wiring groove and a first through hole; the width of the first wiring groove in the first direction is greater than the width of the first through hole in the first direction, and the first direction is perpendicular to the direction from the first semiconductor layer to the second semiconductor layer; A first seed layer and a second metal layer are arranged in the first wiring groove and the first through hole; the second metal layer is located on the side of the first seed layer away from the first insulating layer, and the first seed layer covers the side wall of the first through hole and the bottom and side wall of the first wiring groove.

5. The display panel according to claim 4, wherein: Also includes: A driving substrate, a wiring layer, and a second insulating layer are stacked in sequence; the driving substrate is located on a side of the second insulating layer away from the light-emitting unit; The wiring layer includes at least one wiring unit; each wiring unit corresponds to a light-emitting unit; The second insulating layer includes a second wiring groove and a second through hole, the second wiring groove is connected to the second through hole, and the second through hole extends from the bottom of the second wiring groove to the wiring unit; each wiring unit corresponds to a second wiring groove and a second through hole; the width of the second wiring groove in the first direction is greater than the width of the second through hole in the first direction; A second seed layer and a third metal layer are provided in the second wiring trench and the second through hole; the third metal layer is located on a side of the second seed layer away from the second insulating layer, and the second seed layer covers the sidewall of the second through hole and the bottom and sidewall of the second wiring trench; A surface of the first insulating layer away from the first semiconductor layer contacts a surface of the second insulating layer away from the drive substrate, a surface of the first seed layer away from the first semiconductor layer contacts a surface of the second seed layer away from the drive substrate, and a surface of the second metal layer away from the first semiconductor layer contacts a surface of the third metal layer away from the drive substrate; A vertical projection of the first seed layer on the driving substrate coincides with a vertical projection of the second seed layer on the driving substrate, and a vertical projection of the second metal layer on the driving substrate coincides with a vertical projection of the third metal layer on the driving substrate.

6. A method for preparing a display panel, characterized in that: include: forming at least one light-emitting unit; The light emitting unit includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in sequence; A reflective cavity structure is formed on the sidewall of each light-emitting unit; the reflective cavity structure includes a first dielectric layer, a first metal layer, a second dielectric layer, and a third dielectric layer arranged in a stacked manner, wherein the third dielectric layer is located on a side of the first dielectric layer away from the light-emitting unit; the refractive index of the first dielectric layer gradually decreases along a direction from the first dielectric layer to the third dielectric layer, and the refractive index of the second dielectric layer is greater than the refractive index of the third dielectric layer; The first dielectric layer includes a plurality of dielectric sub-layers, and the plurality of dielectric sub-layers are stacked; Along the direction from the first dielectric layer to the third dielectric layer, the refractive index difference between adjacent dielectric sublayers is 0.2-0.5; The thickness of the first metal layer is 45 nm-55 nm.

7. The method for manufacturing a display panel according to claim 6, wherein: At least one light emitting unit is formed, comprising: forming a first semiconductor sublayer; forming a quantum well sublayer on one side of the first semiconductor layer; forming a second semiconductor sublayer on a side of the quantum well sublayer away from the first semiconductor sublayer; forming a transparent conductive sublayer on a side of the second semiconductor sublayer away from the first semiconductor sublayer; The quantum well sublayer, the second semiconductor sublayer, the transparent conductive sublayer and at least a portion of the first semiconductor sublayer are etched to form a first semiconductor layer, a quantum well layer, a second semiconductor layer, and at least one light-emitting unit and a transparent conductive layer.

8. The method for manufacturing a display panel according to claim 7, wherein: After forming at least one light-emitting unit, the method further includes: forming a photoresist layer on a side of the second semiconductor layer away from the first semiconductor layer; wherein the photoresist layer exposes a surface of the transparent conductive layer away from the first semiconductor layer; A reflector structure is formed on a side of the transparent conductive layer away from the first semiconductor layer; the reflector structure includes a plurality of refractive units, each of which includes a fourth dielectric layer and a fifth dielectric layer; the fifth dielectric layer is located on a side of the fourth dielectric layer away from the transparent conductive layer; and the refractive index of the fourth dielectric layer is greater than the refractive index of the fifth dielectric layer. The photoresist layer is removed.

9. The method for manufacturing a display panel according to claim 8, wherein: After the reflective cavity structure is formed on the sidewall of each light-emitting unit, the method includes: forming a first insulating sublayer on a side of the reflector structure away from the first semiconductor layer; the first insulating sublayer covers the reflector structure, the reflective cavity structure and the exposed first semiconductor layer; The first insulating sublayer is etched to form a first insulating layer, a first wiring trench, and a first through hole; the first wiring trench is connected to the first through hole, and the first through hole extends from the bottom of the first wiring trench to the transparent conductive layer; each light-emitting unit corresponds to a first wiring trench and a first through hole; the width of the first wiring trench in a first direction is greater than the width of the first through hole in the first direction, and the first direction is perpendicular to the direction from the first semiconductor layer to the second semiconductor layer; forming a first seed layer in the first wiring groove and the first through hole; the first seed layer covers the sidewall of the first through hole and the bottom and sidewall of the first wiring groove; forming a second metal layer on a side of the first seed layer away from the first insulating layer; the second metal layer is located in the first wiring groove and the first through hole; forming a driving substrate; forming a patterned layer on one side of the driving substrate; forming a wiring sublayer on a side of the patterned layer away from the driving substrate; Removing the patterned layer to form a wiring layer; the wiring layer includes at least one wiring unit; each wiring unit corresponds to a light-emitting unit; forming a second insulating sublayer on a side of the wiring layer away from the driving substrate; The second insulating sublayer is etched to form a second insulating layer, a second wiring trench, and a second through hole; the second wiring trench is connected to the second through hole, and the second through hole extends from the bottom of the first wiring trench to the wiring unit; each wiring unit corresponds to a second wiring trench and a second through hole; the width of the second wiring trench in the first direction is greater than the width of the second through hole in the first direction; forming a second seed layer in the second wiring groove and the second through hole; the second seed layer covers the sidewall of the second through hole and the bottom and sidewall of the second wiring groove; forming a third metal layer on a side of the second seed layer away from the second insulating layer; the third metal layer is located in the second wiring groove and the second through hole; Through a hybrid bonding process, the surface of the first insulating layer away from the first semiconductor layer contacts the surface of the second insulating layer away from the driving substrate, the surface of the first seed layer away from the first semiconductor layer contacts the surface of the second seed layer away from the driving substrate, and the surface of the second metal layer away from the first semiconductor layer contacts the surface of the third metal layer away from the driving substrate; the vertical projection of the first seed layer on the driving substrate coincides with the vertical projection of the second seed layer on the driving substrate, and the vertical projection of the second metal layer on the driving substrate coincides with the vertical projection of the third metal layer on the driving substrate.

Images