Integrated circuit device and manufacturing method thereof

Abstract

The invention provides a method of manufacturing an integrated circuit device. The method includes depositing a first layer of hard mask material over a layer of dielectric material; etching the first layer of hard mask material, the etched first layer of hard mask material including an etched portion having a first lateral dimension; depositing a second layer of hard mask material over the first layer of hard mask material; etching at least a portion of the second layer of hard mask material while allowing a remaining portion of the hard mask material to leave to expose a portion of the layer of dielectric material having a second lateral dimension less than the first lateral dimension; and etching a trench into the layer of dielectric material at the exposed portion of the layer of dielectric material.

Description

Technical Field

[0001] The present invention relates to an integrated circuit device and a method for manufacturing the same. Background Art

[0002] Each successive generation of integrated circuit (IC) technology is associated with one or more increasing metrics (e.g., number of logic gates, transistors, etc. per IC device). Such metrics are therefore associated with a corresponding reduction in the minimum "critical dimension," or feature width, or "node" achievable with a particular IC process technology. The minimum critical dimension is in turn based on the accuracy and precision of the photolithography masks and other materials used in the relevant node. Summary of the invention

[0003] The present invention is directed to a method of manufacturing an integrated circuit device. The method includes depositing a first layer of hard mask material over a layer of dielectric material. The method also includes etching the first layer of hard mask material, the etched first layer of hard mask material including an etched portion having a first lateral dimension. The method also includes depositing a second layer of hard mask material over the first layer of hard mask material. The method also includes etching at least a portion of the second layer of hard mask material while allowing a remaining portion of the hard mask material to remain to expose a portion of the layer of dielectric material having a second lateral dimension that is less than the first lateral dimension. The method also includes etching a trench into the layer of dielectric material at the exposed portion of the layer of dielectric material.

[0004] The present invention is also directed to a method of manufacturing an integrated circuit device. The method includes depositing a first layer of hard mask material on at least one dielectric layer. The method also includes depositing a photoresist material on the first layer of hard mask material. The method also includes patterning the photoresist material to form a plurality of first pores, each of the plurality of first pores having a first lateral dimension. The method also includes etching the first layer of hard mask material using the photoresist material, the etched first layer of hard mask material including a plurality of second pores, each of the plurality of second pores having a first lateral dimension. The method also includes removing the photoresist material; and depositing a second layer of hard mask material on the first layer of hard mask material to form: a barrier located on the at least one dielectric layer and lining an inner wall of each of the plurality of second pores; and a fill layer located on the at least one dielectric layer and within the barrier of each of the plurality of second pores, the fill layer having a second lateral dimension less than the first lateral dimension. The method also includes etching at least a portion of the second layer of hard mask material while allowing a remaining portion of the hard mask material to be left to remove the fill layer and expose a portion of the at least one dielectric layer within the barrier of each of the plurality of second apertures. The method also includes etching a plurality of trenches through the at least one dielectric layer at the exposed portions of the at least one dielectric layer.

[0005] The present invention is also directed to an integrated circuit device. The integrated circuit device includes: a first electrode; at least one dielectric layer located above the first electrode; and a capacitor structure located above the at least one dielectric layer and the first electrode. The capacitor structure includes: a hard mask material; a horizontal structure located above the hard mask material and including a first conductive layer, an insulating layer, and a second conductive layer located above the at least one dielectric layer; and a plurality of pillars extending from the horizontal structure through the hard mask material and the at least one dielectric layer to the first electrode, and each of the plurality of pillars includes an inner region including the second conductive layer, a middle region including the insulating layer, and an outer region including the first conductive layer. The integrated circuit device also includes a second electrode located above and contacting the second conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A Schematic side views of some embodiments of metal-insulator-metal (MIM) capacitor structures having reduced critical dimensions obtained using a self-aligned mask according to the present disclosure are shown.

[0007] Figure 1B Schematic plan views of some embodiments of three-dimensional (3D) MIM capacitor structures according to the present disclosure are shown, the 3D MIM capacitor structures having reduced critical dimensions obtained using a self-aligned mask.

[0008] Figure 1C Schematic plan views of some embodiments of two-dimensional (2D) MIM capacitor structures with reduced critical dimensions obtained using a self-aligned mask according to the present disclosure are illustrated.

[0009] Figure 2 A side view of some embodiments of an IC device including a MIM capacitor structure having a reduced critical dimension obtained using a self-aligned mask according to the present disclosure is shown.

[0010] FIG. 3A to FIG. 3N Figures illustrate side views of some embodiments of IC devices at various stages of fabrication including MIM capacitor structures having reduced critical dimensions achieved using self-aligned masks according to the present disclosure.

[0011] Figure 4 A method of forming an IC device including a MIM capacitor structure having a reduced critical dimension obtained using a self-aligned mask is illustrated in accordance with some embodiments.

[0012] Figure 5 Figure 2 is a side view of some embodiments of an IC device having a logic section and a capacitor section and including a MIM capacitor structure with reduced critical dimensions obtained using a self-aligned mask according to the present disclosure.

[0013] Figure 6 A method of forming an IC device including features having reduced critical dimensions obtained using a self-aligned mask is illustrated in accordance with some embodiments. DETAILED DESCRIPTION

[0014] The present disclosure provides many different embodiments or examples of different components for implementing the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first component on or on a second component may include an embodiment in which the first component and the second component are formed to be in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component, thereby making the first component and the second component not in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed.

[0015] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0016] The lower limit of the critical dimension that can be achieved in an IC device is usually limited by the specific IC node used to manufacture the device. This lower limit may then affect various properties of the electrical or electronic components created in the device. For example, as described below in conjunction with Figures 1A to 1C As mentioned above, in the case of two-dimensional (2D) or three-dimensional (3D) metal-insulator-metal (MIM) capacitors, the critical dimension determines the width of each "column" or extension of the capacitor. Therefore, a larger critical dimension reduces the number of columns that can be implemented in a capacitor within a specific footprint, and therefore reduces the maximum capacitance that can be achieved.

[0017] To address these issues, the present disclosure provides some embodiments of a method for manufacturing an IC device having one or more components with reduced critical dimensions obtained using a self-aligned mask. In some embodiments, a first layer of hard mask material can be deposited on a dielectric material layer. The first layer of hard mask material can then be etched, and the etched portion can have a first lateral dimension. A second layer of hard mask material can then be deposited on the first layer. At least a portion of the second layer of hard mask material can then be etched to expose a portion of the dielectric material layer having a second lateral dimension, and the second lateral dimension is smaller than the first lateral dimension. A groove can then be etched in the dielectric material layer where the exposed portion of the dielectric material is.

[0018] Thus, some embodiments using this method can provide features such as the resulting trench described above, which can have a second lateral dimension that represents a critical dimension that is smaller than the first lateral dimension of the etched portion of the hard mask material layer. In some embodiments, the reduced critical dimension can improve or enhance some characteristics of a component of an IC device (e.g., a 3D MIM capacitor).

[0019] Figure 1ASchematic side views of some embodiments of a MIM capacitor structure 100 having a reduced critical dimension 108 obtained using a self-aligned mask according to the present disclosure are illustrated. The MIM capacitor structure 100 includes a first conductive layer 102A, an insulating layer 104, and a second conductive layer 102B that serve as a metal layer, an insulator layer, and a metal layer of the MIM capacitor structure 100, respectively. In addition, the MIM capacitor structure 100 using layers 102A, 104, and 102B includes a horizontal body 105 and a plurality of pillars 106 extending downwardly from the horizontal body 105. Additionally, a first layer 302a and a second layer 302b of a hard mask material may be located below the horizontal body 105 and may be used to produce a reduced critical dimension 108, as described in more detail below.

[0020] In some embodiments, the reduced critical dimension 108 results in narrower pillars 106, which in turn allows a greater number of pillars 106 to be used within a particular footprint of the MIM capacitor structure 100 (e.g., as defined by the length of the horizontal body 105). Figure 1A Where three pillars 106 are depicted in FIG. 1 , a critical dimension larger than the reduced critical dimension 108 may allow for two pillars 106 to be present in the MIM capacitor structure 100 .

[0021] Figure 1B A schematic plan view of some embodiments of a 3D MIM capacitor structure 100A having a reduced critical dimension 108 obtained using a self-aligned mask according to the present disclosure is illustrated. The 3D MIM capacitor structure 100A, viewed from below, includes nine pillars 106 formed on a surface of the first conductive layer 102A extending through the first layer 302a and the second layer 302b of the hard mask material, presenting a 2D (3×3) array. Within the array, each pillar 106 may exhibit a reduced critical dimension 108 in two dimensions, such as Figure 1B Thus, a larger array of pillars 106 (eg, a 3×3 array) may be implemented compared to a smaller array of pillars 106 (eg, a 2×2 array) to which devices having larger critical dimensions may be limited.

[0022] Figure 1CA schematic plan view of some embodiments of a 2D MIM capacitor structure 100B having a reduced critical dimension 108 obtained using a self-aligned mask according to the present disclosure is illustrated. The 2D MIM capacitor structure 100B, viewed from below, includes three elongated pillars 106 in a single row formed on a surface of a first conductive layer 102A extending through a first layer 302a and a second layer 302b of a hard mask material. Within the row, each pillar 106 may exhibit a reduced critical dimension 108 in one dimension, such as Figure 1C Thus, a greater number (eg, three) of pillars 106 may be used than a device with a larger critical dimension may be limited to a smaller number (eg, two) of pillars 106 .

[0023] Figure 2 FIG. 2 is a side view of an IC device 200 according to some embodiments of the present disclosure, the IC device 200 including a MIM capacitor structure 100 having a reduced critical dimension 108 obtained using a self-aligned mask. Figure 2 and FIG. 3A to FIG. 3N The discussion is directed to a MIM capacitor structure 100 having a reduced critical dimension 108, but in other embodiments, other IC structures (eg, any other capacitor or non-capacitor structure) may still benefit from the reduced critical dimension.

[0024] The IC device 200 may include a substrate 201 (eg, a silicon substrate) on which a plurality of dielectric layers 204, 206, and 208 may be disposed. Figure 2 As shown, the first dielectric layer 204 is disposed on the substrate 201, and the first dielectric layer 204 may have a first electrode 202 disposed therein, and other multiple dielectric layers 204, 206, and 208 may be disposed on the first electrode 202. In some embodiments, each of the dielectric layers 204, 206, and 208 may include one or more dielectric materials, including, but not limited to, silicon oxide (SiO x ) (e.g., silicon oxide (SiO2)), silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, or the like. For example, dielectric layer 204 may include silicon oxide, dielectric layer 206 may include silicon carbide, and dielectric layer 208 may include silicon nitride. Furthermore, although Figure 2 A specific arrangement and thickness of dielectric layers 204 , 206 , and 208 are depicted, but other arrangements and thicknesses are possible in other embodiments.

[0025] Disposed within dielectric layers 204, 206, and 208 is a MIM capacitor structure 100 having a horizontal body 105 and pillars 106 extending from the horizontal body 105. Figure 2 Three pillars 106 are shown in the figure, but two or more such pillars 106 may be used in other embodiments. In addition, one end of each pillar 106 may contact the first electrode 202, so that the first electrode 202 can provide an electrical connection for the MIM capacitor structure 100.

[0026] In some embodiments, located below the horizontal body 105 and between the pillars 106 is a layer of hard mask material 302 including a first layer 302a and a second layer 302b used to trench in the dielectric layers 204, 206, and 208 to form the pillars 106. Furthermore, in some embodiments, as described in more detail below, the hard mask material 302 is self-aligned in response to a broad or "blanket" etch operation.

[0027] As above combined Figure 1A As discussed, the horizontal body 105 and the pillars 106 each include three layers forming a MIM structure: a first conductive layer 102A, an insulating layer 104, and a second conductive layer 102B. Overall, the horizontal body 105 and the pillars 106 maintain the layered structure of the first conductive layer 102A, the insulating layer 104, and the second conductive layer 102B, so that the length of each pillar 106 contributes significantly to the total capacitance value of the MIM capacitor structure 100. As such, the width of each pillar 106, which is determined by the reduced critical dimension 108, affects the number of pillars 106 that can be employed within the footprint of the horizontal body 105, thereby affecting the capacitance value of the MIM capacitor structure 100.

[0028] Also like Figure 2 As shown, the dielectric cap layer 210 is disposed above the second conductive layer 102B of the horizontal body 105. In addition, a dielectric spacer 211 may be disposed above the insulating layer 104 and surround the dielectric cap layer 210 and the second conductive layer 102B. In some embodiments, the dielectric cap layer 210 and the dielectric spacer 211 may be made of the same dielectric material (e.g., silicon nitride), but other dielectric materials may still be used in other embodiments.

[0029] In some embodiments, the second electrode 212 may contact the second conductive layer 102B. The second electrode 212 may include a conductive material, such as copper, a copper alloy, another metal, or another conductive material. Moreover, in some embodiments, the second electrode 212 may have a wider upper portion and a narrower lower portion. The narrower lower portion may extend through the dielectric cap layer 210 to contact the second conductive layer 102B.

[0030] The first electrode 202 and the second electrode 212 can be used as two electrical connections of the MIM capacitor structure 100 of the IC device 200. In some embodiments, the MIM capacitor structure 100 can be used as a component in a digital or analog circuit, such as a bypass or decoupling capacitor (e.g., for a direct current (DC) voltage such as a power supply voltage). In addition, since the reduced critical dimension 108 corresponds to the width of the pillar 106, a greater number of pillars 106 (e.g., three instead of two) can be used, thereby increasing the capacitance value without increasing the footprint of the MIM capacitor structure 100 (e.g., represented by the length and width of the horizontal body 105).

[0031] FIG. 3A to FIG. 3N Figures show IC devices at various stages of manufacture (e.g., Figure 2 200) wherein the IC device has a reduced critical dimension obtained using a self-aligned mask. FIG. 3A to FIG. 3N Described as a series of actions, it should be understood that these actions are not restrictive, because in other embodiments, the order of actions can still be changed, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described in the figure can be omitted in whole or in part.

[0032] Figure 3A A first electrode 202 is shown with a plurality of dielectric layers 204, 206, and 208 disposed thereon. In some embodiments, a substrate 201 (e.g., a silicon substrate) may support a first dielectric layer 204 within which the first electrode 202 may be formed, followed by subsequent formation of additional dielectric layers 204, 206, and 208. Figure 3A As shown, relatively thin structures of dielectric layers 206 and 208 may be formed in an alternating manner between thicker structures of dielectric layer 204, although many other structures and formation orders may be used to utilize dielectric layers 204, 206, and / or 208. As noted above, in some embodiments, each of dielectric layers 204, 206, and 208 may include one or more dielectric materials including, but not limited to, silicon oxide, silicon nitride, and silicon carbide. For example, dielectric layer 204 may include silicon oxide, dielectric layer 206 may include silicon carbide, and dielectric layer 208 may include silicon nitride, although other materials and combinations are possible.

[0033] A first layer of hard mask material 302 may be formed (e.g., deposited) over dielectric layers 204, 206, and 208. In some embodiments, the first layer of hard mask material 302 may include, but is not limited to, a metal (e.g., aluminum (Al), titanium nitride (TiN), or another metal or metal alloy) or a dielectric material (e.g., silicon nitride (SiN), silicon carbide (SiC), or another dielectric material).

[0034] A layer of photoresist material 304 may then be formed (eg, deposited) over the first layer of hard mask material 302. Figure 3A The photoresist material layer 304 may include a positive photoresist material. However, in other embodiments, a negative photoresist material may also be used for the photoresist material layer 304 .

[0035] A mask 305 can be positioned over the photoresist material layer 304, and the mask 305 can include an opening feature having a first lateral dimension 301. In some embodiments, the first lateral dimension 301 can be a minimum critical dimension that can be directly obtained by the mask 305. Thereafter, light 306 (e.g., ultraviolet (UV) light) can be directed onto the mask 305, which can allow portions of the light 306 to strike portions of the photoresist material layer 304 corresponding to the opening features of the mask 305. Thereafter, a developer can be used to remove portions of the photoresist material layer 304 exposed to the light 306, thereby producing a plurality of first apertures 312, each aperture 312 having the first lateral dimension 301, such as Figure 3B drawn.

[0036] Figure 3C Removal (e.g., etching) of a plurality of second apertures 314 of the first layer 302a of the hard mask material 302 is illustrated, wherein the plurality of second apertures 314 are associated with the plurality of first apertures 312 of the photoresist material layer 304. Each of the plurality of second apertures 314 has a first lateral dimension 301 associated with the photoresist material layer 304.

[0037] Figure 3D The photoresist material layer 304 is shown removed after creating the second plurality of apertures 314. The desired second lateral dimension 108 to be produced in association with each of the second plurality of apertures 314 is also depicted.

[0038] Figure 3EThe second layer 302b of the hard mask material 302 is shown formed (e.g., deposited) over the first layer 302a of the hard mask material 302. In some embodiments, the second layer 302b of the hard mask material 302 is formed on the upper surface and sidewalls of the first layer 302a of the hard mask material 302. In some embodiments, the formation of the second layer 302b results in the formation of a barrier 307 over the underlying dielectric layer (e.g., the uppermost dielectric layer 204) for each of the plurality of second apertures 314. The barrier 307 is also located within the inner wall of its associated aperture. A fill layer 316 is also generated from the formation of the second layer 302b of the hard mask material 302 within the barrier 307 of each of the plurality of second apertures 314 and over the underlying dielectric layer. In some embodiments, the width of the fill layer 316 within the barrier 307 is associated with the second lateral dimension 108. In some embodiments, the barrier 307 and the fill layer 316 of each of the plurality of second apertures 314 are formed due to a reduced level of conformity with the first layer 302a of the hard mask material 302. In some embodiments, the material of the second layer 302b of the hard mask material 302 can be the same as the hard mask material of the first layer 302a. In other embodiments, the second layer 302b of the hard mask material 302 can have a different material than the first layer 302a of the hard mask material 302.

[0039] Figure 3F The diagram shows removing (e.g., etching) at least a portion of the hard mask material 302 (e.g., a portion of the second layer 302b of the hard mask material 302) to remove at least the fill layer 316 of each of the plurality of second apertures 314, thereby exposing a portion of the underlying dielectric layer (e.g., the uppermost dielectric layer 204) within the barrier 307 associated with each of the plurality of second apertures 314. In some embodiments, this removal can be a "full" etch of the entire area occupied by the second layer 302b of the hard mask material 302. In some embodiments, this etching results in the exposed area of ​​the underlying dielectric layer having a width of the second lateral dimension 108, which can also be referred to as a width relative to the second lateral dimension 108. Figure 3C The first lateral dimension 301 of the embodiment of the present invention is a critical dimension 108 that is reduced from the first lateral dimension 301. In some embodiments, the second lateral dimension 108 can be 35% to 65% smaller than the first lateral dimension 301, 50% smaller than the first lateral dimension 301, or other similar values.

[0040] Figure 3GA plurality of trenches 310 are shown removed (e.g., etched) through one or more of the plurality of dielectric layers 204, 206, and 208 at the exposed portions of the uppermost dielectric layer. In some embodiments, the plurality of trenches 310 define locations where pillars 106 will subsequently be formed for the MIM capacitor structure 100. Moreover, in some embodiments, the etching of the plurality of trenches 310 terminates at the first electrode 202. In some embodiments, such etching may also remove additional portions of the first layer 302a of the hard mask material 302, thereby reducing the thickness of the remaining hard mask material 302.

[0041] Figure 3H The first conductive layer 102A is shown formed (e.g., deposited) over the remaining hard mask material 302 and extending into the plurality of trenches 310. In some embodiments, the formation of the first conductive layer 102A is performed with significant conformality such that the first conductive layer 102A is formed along the plurality of trenches 310 and extends to the first electrode 202. In other embodiments, the remaining hard mask material 302 may be removed before forming the first conductive layer 102A over the uppermost dielectric layer 204 and the plurality of trenches 310.

[0042] Fig. 3I The insulating layer 104 is formed (e.g., deposited) on the first conductive layer 102A. In some embodiments, the insulating layer 104 may extend into the plurality of trenches 310. In some embodiments, the insulating layer 104 is formed with significant conformality, so that the insulating layer 104 completely covers the first conductive layer 102A in the plurality of trenches 310.

[0043] Figure 3J The second conductive layer 102B is shown formed (e.g., deposited) over the insulating layer 104, including extending into and filling the plurality of trenches 310. In some embodiments, the formation of the second conductive layer 102B may be performed with significant conformality to facilitate the filling of the plurality of trenches 310. Furthermore, in some embodiments, the formation of the second conductive layer 102B may result in a substantially flat surface provided by the second conductive layer 102B.

[0044] Figure 3K The second conductive layer 102B, the insulating layer 104, the first conductive layer 102A, and portions of the hard mask material 302 are removed (eg, etched) to form a horizontal body (eg, Figure 2 In some embodiments, the second conductive layer 102B is etched to expose a peripheral portion of the insulating layer 104.

[0045] Figure 3LThe figure shows that a dielectric capping layer 210 is formed (e.g., deposited) on the second conductive layer 102B and dielectric spacers 211 are formed on the insulating layer 104 and around the dielectric capping layer 210. In some embodiments, the dielectric capping layer 210 and the dielectric spacers 211 are formed simultaneously. Moreover, in some embodiments, the dielectric capping layer 210 and the dielectric spacers 211 may include the same dielectric material (e.g., silicon nitride). In some embodiments, the dielectric capping layer 210 and the dielectric spacers 211 are formed conformally relative to the second conductive layer 102B and the insulating layer 104 to cover the corresponding materials.

[0046] Figure 3M At least one additional dielectric layer (e.g., one or more dielectric layers 204, 206, and / or 208) is shown formed (e.g., deposited) over the previous top dielectric layer 204, dielectric cap layer 210, and dielectric spacers 211. In some embodiments, the additional dielectric layers include two dielectric layers 204 and an intermediate dielectric layer 208. However, other numbers and other combinations of dielectric layers 204, 206, and / or 208 may be used in other embodiments.

[0047] Figure 3N The second electrode 212 is shown formed (e.g., etched and deposited) through at least one additional dielectric layer and the dielectric cap layer 210 to contact the second conductive layer 102B. In some embodiments, a wide upper region is etched, and a narrower lower region extending through the dielectric cap layer 210 to the second conductive layer 102B is etched. A conductive material such as a metal (e.g., copper), a metal alloy, or another conductive material may then be deposited in the etched region to form the second electrode 212. Thus, the first electrode 202 and the second electrode 212 may serve as contact points for the MIM capacitor structure 100 to be used by other circuits within the IC device 200. As noted above, because the self-aligned hard mask material 302 facilitates the formation of a reduced critical dimension 108, more pillars 106 can be used for the MIM capacitor structure 100, so that the capacitance may be increased.

[0048] Figure 4 FIG. 1 illustrates forming an IC device (eg, Figure 2 The method 400 of the IC device 200 includes a MIM capacitor structure (eg, a MIM capacitor structure having a reduced critical dimension 108) obtained using a self-aligned mask. Figure 2MIM capacitor structure 100). Although this method and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that the present disclosure is not limited to the illustrated order or actions. Therefore, in some embodiments, these actions can be performed in an order different from the order shown, and / or can be performed simultaneously. In addition, in some embodiments, the illustrated actions or events can be subdivided into multiple actions or events, which can be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events can be omitted, and other unillustrated actions or events can be included.

[0049] In some embodiments, actions 402 to 426 may correspond to, for example, FIG. 3A to FIG. 3N In action 402, for example, at least one dielectric layer (e.g., one or more dielectric layers 204, 206, and 208) may be deposited on a first electrode (e.g., first electrode 202). In addition, in some embodiments, as Figure 3A As shown, the first electrode can be formed on a substrate (eg, substrate 201) and a lowermost dielectric layer (eg, Figure 3A At act 404, a first layer of hard mask material (e.g., Figure 3A At act 406, a photoresist material (e.g., photoresist material layer 304) is deposited over the first layer of hard mask material. At act 408, the photoresist material is patterned (e.g., using Figure 3A to form a plurality of first apertures (eg, Figure 3B A plurality of first pores 312). Figure 3A and Figure 3B Cross-sectional views corresponding to some embodiments of actions 402 to 408 are shown.

[0050] At act 410, a first layer of hard mask material is etched using a photoresist material, wherein the etched first layer of hard mask material includes a plurality of second apertures (e.g., Figure 3C In some embodiments, each of the plurality of second pores has a first lateral dimension (eg, first lateral dimension 301). Figure 3C A cross-sectional view corresponding to some embodiments of act 410 is shown.

[0051] At act 412, the photoresist material may be removed. Figure 3D A cross-sectional view corresponding to some embodiments of act 412 is shown.

[0052] At act 414, a second layer of hard mask material (e.g., Figure 3E In some embodiments, the second layer of hard mask material 302 forms a barrier lining the inner wall of each of the plurality of second pores over the at least one dielectric layer (e.g., Figure 3E ), and forming a filling layer (e.g., a barrier 307) on at least one dielectric layer within the barrier of each of the plurality of second apertures. Figure 3E In some embodiments, the fill layer has a second lateral dimension (e.g., Figure 3E The second lateral dimension 108). Figure 3E A cross-sectional view corresponding to some embodiments of act 414 is shown.

[0053] At act 416, at least a portion of the second layer of hard mask material is etched while allowing a portion of the hard mask material to remain. In some embodiments, the etching removes the fill layer to expose a portion of at least one dielectric layer within the barrier of each of the plurality of second apertures. Moreover, in some embodiments, the exposed portion of the at least one dielectric layer has a second lateral dimension. In some embodiments, the etching can be characterized as an overall or "full" etching of the hard mask material. Figure 3F A cross-sectional view corresponding to some embodiments of act 416 is shown.

[0054] At act 418, a plurality of trenches (eg, Figure 3G A plurality of grooves 310). Figure 3G A cross-sectional view corresponding to some embodiments of act 418 is shown.

[0055] At act 420, a first conductive layer (eg, Figure 3H The first conductive layer 102A is formed on the hard mask material. In some embodiments, the first conductive layer extends into the plurality of trenches to contact the first electrode. In addition, in some embodiments, since the first conductor is formed in a manner that is significantly conformal to the hard mask material and the plurality of dielectric layers, the first conductive layer can line the plurality of trenches and extend to the first electrode. Figure 3H A cross-sectional view corresponding to some embodiments of act 420 is shown.

[0056] At act 422, an insulating layer (e.g., Fig. 3I An insulating layer 104 is formed over the first conductive layer and extends into the plurality of trenches. In some embodiments, the insulating layer is formed with significant conformality to the first conductive layer. Fig. 3IA cross-sectional view corresponding to some embodiments of act 422 is shown.

[0057] At act 424, a second conductive layer (eg, Figure 3J The second conductive layer 102B may be formed to have significant conformality with the insulating layer to facilitate the filling of the plurality of trenches 310. Moreover, in some embodiments, the second conductive layer may present a substantially flat upper surface. Figure 3J A cross-sectional view corresponding to some embodiments of act 424 is shown.

[0058] At act 426, a second electrode (eg, Figure 3N The second electrode 212 of the embodiment of the present invention is provided to contact the second conductive layer. Therefore, in some embodiments, the first electrode and the second electrode can be used as contact points for contacting the MIM capacitor structure. In addition, since the self-aligned hard mask material described above is conducive to reducing the critical dimension 108, the MIM capacitor structure can use more pillars, thereby increasing the resulting capacitance.

[0059] Figure 5 FIG. 5 is a side view of an IC device 500 according to some embodiments of the present disclosure, wherein the IC device 500 has a logic section 500A and a capacitor section 500B, wherein the capacitor section 500B includes a MIM capacitor structure 100 having a reduced critical dimension 108 obtained using a self-aligned mask. In some embodiments, the MIM capacitor structure 100 is disposed in a plurality of dielectric layers 204, 206, and 208, such as Figure 2 In some embodiments, the first dielectric layer 204a may surround the upper portion of the plurality of pillars, and the second dielectric layer 204b may be disposed above the first dielectric layer 204a and surround the horizontal portion of the MIM capacitor structure 100. In some embodiments, the first dielectric layer 204a may include an upper surface laterally outside of the hard mask material 302. In some embodiments, the first dielectric layer 204a may be recessed below the bottom of the hard mask material 302 such that the second dielectric layer 204b extends below the bottom of the hard mask material 302.

[0060] In some embodiments, as previously discussed, the hard mask material 302 may include a first layer 302a of the hard mask material 302 and a second layer 302b of the hard mask material 302 disposed along the sidewalls of the first layer 302a. In some embodiments, the first layer 302a may include or be the same material as the second layer 302b. In other embodiments, the first layer 302a may include and / or be a different material than the second layer 302b. In some embodiments, the second layer 302b of the hard mask material 302 may have rounded outer corners facing the MIM capacitor structure 100.

[0061] In some embodiments, the same multiple dielectric layers 204, 206 and 208 may be used in a logic segment 500A, which may include one or more electronic circuits, including, for example, a transistor 501, which may be connected to other components (e.g., a MIM capacitor structure 100) in either or both of the logic segment 500A and the capacitor segment 500B via one or more through-holes 503 and a connecting metal structure 502.

[0062] Although incorporating specific electrical components (e.g. Figure 2 The MIM capacitor structure 100 of FIG. 1 illustrates the reduced critical dimensions resulting from the self-aligned hard mask material, but other components or structures of an IC device may also benefit from the application of the same principles. To this end, Figure 6 A method 600 of forming an IC device including features having reduced critical dimensions obtained using a self-aligned mask is illustrated in accordance with some embodiments. Such features may be used in any type of structure in an IC device to improve some characteristic or aspect of the structure.

[0063] At act 602, a first layer of a hard mask material (e.g., Figure 3A The first layer 302a of the hard mask material 302 is formed on the dielectric material layer (eg, Figure 3A In action 604, a photoresist material (e.g., Figure 3A In action 606, the photoresist material is patterned (e.g., using Figure 3A to remove a first lateral dimension (eg, Figure 3B A portion of the first lateral dimension 301) (e.g., Figure 3B one of the plurality of first pores 312). Figure 3A and Figure 3B Cross-sectional views corresponding to some embodiments of actions 602 to 606 are shown.

[0064] At act 608 , the first layer of hard mask material is etched using the photoresist material, wherein the etched first layer of hard mask material includes an etched portion (eg, one of the plurality of second apertures 314 ) having a first lateral dimension. Figure 3C A cross-sectional view corresponding to some embodiments of act 608 is shown.

[0065] At act 610, the photoresist material may be removed. Figure 3D A cross-sectional view corresponding to some embodiments of act 610 is shown.

[0066] At act 612, a second layer of hard mask material (eg, Figure 3E In some embodiments, the second layer of hard mask material 302 forms a barrier lining the inner wall of the etched portion over at least one dielectric layer (e.g., Figure 3E and forming a fill layer (e.g., a barrier 307) within the barrier over the layer of dielectric material. Figure 3E In some embodiments, the fill layer has a second lateral dimension (e.g., Figure 3E The second lateral dimension 108). Figure 3E A cross-sectional view corresponding to some embodiments of act 612 is shown.

[0067] At act 614, at least a portion of the second layer of hard mask material is etched while allowing a portion of the hard mask material to remain. In some embodiments, the etching removes the fill layer and exposes a portion of at least one dielectric layer within the barrier. Moreover, in some embodiments, the exposed portion of at least one dielectric layer has a second lateral dimension. In some embodiments, the etching can be characterized as a full etching of the hard mask material. Figure 3F A cross-sectional view corresponding to some embodiments of act 614 is shown.

[0068] At act 616, trenches (eg, Figure 3G In some embodiments, the trenches may then be used (e.g., filled with semiconductor, conductive, insulating, and / or dielectric materials) to provide features with reduced critical dimensions. In some embodiments, the etching of the trenches may terminate at the conductive structure (e.g., Figure 3G The first electrode 202). Figure 3G A cross-sectional view corresponding to some embodiments of act 616 is shown.

[0069] Some embodiments relate to a method comprising: depositing a first layer of hard mask material over a layer of dielectric material; etching the first layer of hard mask material, the etched first layer of hard mask material comprising an etched portion having a first lateral dimension; depositing a second layer of hard mask material over the first layer of hard mask material; etching at least a portion of the second layer of hard mask material while allowing a remaining portion of the hard mask material to remain to expose a portion of the layer of dielectric material having a second lateral dimension that is less than the first lateral dimension; and etching a trench into the layer of dielectric material at the exposed portion of the layer of dielectric material.

[0070] In some embodiments, the second lateral dimension is about half the first lateral dimension. In some embodiments, depositing the second layer of hard mask material is performed with reduced conformality to the first layer of hard mask material. In some embodiments, the method further comprises: continuing to etch the trench through a plurality of dielectric layers, wherein the layer of dielectric material is disposed over the plurality of dielectric layers. In some embodiments, the method further comprises: terminating the etching of the trench at a conductive structure, wherein the layer of dielectric material is disposed over the conductive structure. In some embodiments, the method further comprises: removing a remaining portion of the hard mask material.

[0071] Some embodiments relate to another method. The method includes: depositing a first layer of hard mask material over at least one dielectric layer; depositing a photoresist material over the first layer of hard mask material; patterning the photoresist material to form a plurality of first apertures, each of the plurality of first apertures having a first lateral dimension; etching the first layer of hard mask material using the photoresist material, the etched first layer of hard mask material including a plurality of second apertures, each of the plurality of second apertures having a first lateral dimension; removing the photoresist material; and depositing a second layer of hard mask material over the first layer of hard mask material. Depositing the second layer forms: a barrier over the at least one dielectric layer and lining an inner wall of each of the plurality of second apertures; and a fill layer over the at least one dielectric layer and within the barrier of each of the plurality of second apertures, the fill layer having a second lateral dimension less than the first lateral dimension. The method also includes: etching at least a portion of the second layer of hard mask material while allowing a remaining portion of the hard mask material to be left to remove the fill layer and expose a portion of at least one dielectric layer within the barrier of each of the plurality of second pores; and etching a plurality of trenches through the at least one dielectric layer at the exposed portion of the at least one dielectric layer.

[0072] In some embodiments, the method further comprises: depositing at least one dielectric layer on the first electrode before depositing the first layer of hard mask material; forming a first conductive layer on the hard mask material, the first conductive layer extending into the plurality of trenches to contact the first electrode; forming an insulating layer on the first conductive layer and extending into the plurality of trenches; forming a second conductive layer on the insulating layer and filling the plurality of trenches; and forming a second electrode on the second conductive layer, the second electrode contacting the second conductive layer. In some embodiments, the method further comprises: forming a dielectric cap layer on the second conductive layer, wherein the second electrode extends through the dielectric cap layer to the second conductive layer. In some embodiments, the method further comprises: forming a dielectric spacer on the insulating layer and surrounding the dielectric cap layer and the second conductive layer. In some embodiments, the plurality of trenches are arranged in a two-dimensional array in plan view. In some embodiments, the plurality of trenches are arranged in a one-dimensional array in plan view. In some embodiments, each of the plurality of trenches is rectangular in plan view. In some embodiments, the second lateral dimension is approximately half of the first lateral dimension. In some embodiments, depositing the second layer of hard mask material is performed with reduced conformality to the first layer of hard mask material.

[0073] Some embodiments relate to an IC device. The IC device includes: a first electrode; at least one dielectric layer located above the first electrode; and a capacitor structure located above the at least one dielectric layer and the first electrode. The capacitor structure includes: a hard mask material; a horizontal structure located above the hard mask material and including a first conductive layer, an insulating layer, and a second conductive layer located above the at least one dielectric layer; and a plurality of pillars extending from the horizontal structure through the hard mask material and the at least one dielectric layer to the first electrode, each of the plurality of pillars including an inner region including the second conductive layer, a middle region including the insulating layer, and an outer region including the first conductive layer. The IC device also includes a second electrode located above and contacting the second conductive layer.

[0074] In some embodiments, the plurality of cylinders are arranged as a two-dimensional array in a plan view. In some embodiments, the plurality of cylinders are arranged as a one-dimensional array in a plan view. In some embodiments, each of the plurality of cylinders is rectangular in a plan view. In some embodiments, each of the plurality of cylinders is square in a plan view.

[0075] It should be understood that in this written description and in the claims below, the terms "first", "second", "third", etc. are merely general identifiers used for ease of description to distinguish different components in one figure or a series of figures. By themselves, these terms do not imply any temporal order or structural proximity of these components, and are not intended to describe corresponding components in different illustrated embodiments and / or non-illustrated embodiments. For example, the "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to the "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to the "first dielectric layer" in non-illustrated embodiments.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing an integrated circuit device, comprising: depositing a first layer of hard mask material over the layer of dielectric material; etching the first layer of the hard mask material, the etched first layer of the hard mask material comprising an etched portion having a first lateral dimension; depositing a second layer of the hard mask material over the first layer of the hard mask material; etching at least a portion of the second layer of the hard mask material while allowing a remaining portion of the hard mask material to remain to expose a portion of the layer of the dielectric material having a second lateral dimension that is less than the first lateral dimension; as well as Trenches are etched into the layer of dielectric material at exposed portions of the layer of dielectric material.

2. The method according to claim 1, characterized in that The second lateral dimension is approximately half of the first lateral dimension.

3. The method according to claim 1, characterized in that Depositing the second layer of the hard mask material is performed with reduced conformality to the first layer of the hard mask material.

4. The method according to claim 1, characterized in that Also includes: The etching of the trench is terminated at a conductive structure, wherein the layer of the dielectric material is disposed over the conductive structure.

5. A method of manufacturing an integrated circuit device, comprising: depositing a first layer of a hard mask material over at least one dielectric layer; depositing a photoresist material over the first layer of the hard mask material; patterning the photoresist material to form a first plurality of apertures, each of the first plurality of apertures having a first lateral dimension; etching the first layer of the hard mask material using the photoresist material, the etched first layer of the hard mask material comprising a plurality of second apertures, each of the plurality of second apertures having the first lateral dimension; removing the photoresist material; depositing a second layer of the hard mask material over the first layer of the hard mask material to form: a barrier disposed on the at least one dielectric layer and lining an inner wall of each of the plurality of second apertures; as well as a fill layer located above the at least one dielectric layer and within the barrier of each of the plurality of second apertures, the fill layer having a second lateral dimension that is smaller than the first lateral dimension; etching at least a portion of the second layer of the hard mask material while allowing a remaining portion of the hard mask material to remain to remove the fill layer and expose a portion of the at least one dielectric layer within the barrier of each of the plurality of second apertures; as well as A plurality of trenches are etched through the at least one dielectric layer at exposed portions of the at least one dielectric layer.

6. The method according to claim 5, characterized in that Also includes: depositing the at least one dielectric layer over the first electrode before depositing the first layer of the hard mask material; forming a first conductive layer on the hard mask material, the first conductive layer extending into the plurality of trenches to contact the first electrode; forming an insulating layer on the first conductive layer and extending into the plurality of trenches; forming a second conductive layer on the insulating layer and filling the plurality of trenches; as well as A second electrode is formed on the second conductive layer, wherein the second electrode contacts the second conductive layer.

7. The method according to claim 6, characterized in that Also includes: A dielectric capping layer is formed on the second conductive layer, wherein the second electrode extends through the dielectric capping layer to reach the second conductive layer.

8. The method according to claim 7, characterized in that Also includes: A dielectric spacer is formed on the insulating layer and surrounds the dielectric cap layer and the second conductive layer.

9. An integrated circuit device, characterized in that: include: a first electrode; at least one dielectric layer, located on the first electrode; A capacitor structure is located on the at least one dielectric layer and the first electrode, and the capacitor structure includes: Hard mask materials; a horizontal structure located above the hard mask material and comprising a first conductive layer, an insulating layer, and a second conductive layer located above the at least one dielectric layer; and a plurality of pillars extending from the horizontal structure through the hard mask material and the at least one dielectric layer to the first electrode, each of the plurality of pillars comprising an inner region including the second conductive layer, a middle region including the insulating layer, and an outer region including the first conductive layer; and The second electrode is located on the second conductive layer and contacts the second conductive layer.

10. The integrated circuit device according to claim 9, characterized in that The plurality of pillars are arranged in a two-dimensional array in a plan view.

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