Preparation method of shallow trench isolation structure and semiconductor device

Abstract

The invention provides a preparation method of a shallow trench isolation structure and a semiconductor device, and the preparation method comprises the following steps: providing a substrate which comprises a substrate and a patterned hard mask layer on the substrate; depositing a hard mask oxide layer on the substrate, wherein the hard mask oxide layer covers the surface of the hard mask layer and the side wall and the bottom wall of the pattern; etching the substrate to form a plurality of first grooves corresponding to the patterns on the hard mask layer, wherein the first grooves extend to the substrate, and hard mask oxide layers are reserved on the side walls of the patterns of the hard mask layer; removing the hard mask oxide layer on the side wall of the pattern of the hard mask layer through wet etching to form a second groove; forming a liner oxide layer on the side wall and the bottom wall of the second groove; filling the second groove; removing the hard mask layer; and growing a sacrificial oxide layer in the active region. According to the preparation method of the shallow trench isolation structure, the unfilled corner problem of shallow trench isolation can be reduced, the electric leakage of a semiconductor device is improved, and the overall performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field related to semiconductor devices, and in particular to a method for preparing a shallow trench isolation structure and a semiconductor device. Background Art

[0002] In recent years, many commercial complementary metal oxide semiconductor (CMOS) device suppliers have replaced the local oxidation isolation (LOCOS) isolation technology with the shallow trench isolation (STI) technology of advanced submicron technology. This is because the shallow trench isolation is planar with the silicon surface and is not subject to lateral erosion, so it does not form the bird's beak structure in the local oxidation isolation technology of silicon. Shallow trench isolation is also not affected by the field oxide thinning inherent in narrow local oxidation isolation of silicon. Although the use of shallow trench isolation in deep submicron technology has many advantages over the use of local oxidation isolation of silicon, due to the widespread use of narrow width devices in system-on-chip (SoC) designs, the geometric effect of the divot at the corner where the shallow trench isolation structure STI intersects with the active area AA makes the parasitic transistor turn on at a lower voltage than the main transistor. When the transistor width decreases, the contribution of the parasitic transistor to the overall performance of the main transistor increases, resulting in a lower threshold voltage (Vth) and higher saturation current (Idsat) of the semiconductor device. This effect is also known as the Invers Narrow Width Effect (INWE). Therefore, the size control of the divot of shallow trench isolation has become an urgent problem to be solved.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0004] In view of the problems in the prior art, the purpose of the present invention is to provide a method for preparing a shallow trench isolation structure and a semiconductor device, which can reduce the corner chip problem of shallow trench isolation, improve the leakage of semiconductor devices and enhance the overall performance of semiconductor devices.

[0005] A first aspect of the present invention provides a method for preparing a shallow trench isolation structure, the method comprising the following steps:

[0006] Providing a substrate, the substrate comprising a base plate and a patterned hard mask layer on the base plate;

[0007] Depositing a hard mask oxide layer on the substrate, the hard mask oxide layer covering the surface of the hard mask layer and the sidewalls and bottom walls of the pattern;

[0008] Etching the substrate to form a plurality of first trenches corresponding to the pattern on the hard mask layer, wherein the first trenches extend to the substrate and the hard mask oxide layer is retained on the sidewalls of the pattern of the hard mask layer;

[0009] Wet etching to remove the hard mask oxide layer on the sidewall of the pattern of the hard mask layer to form a second trench;

[0010] forming a liner oxide layer on the sidewalls and bottom wall of the second trench;

[0011] filling the second trench;

[0012] removing the hard mask layer;

[0013] A sacrificial oxide layer is grown on the active area.

[0014] According to a first aspect of the present invention, a self-aligned dry etching process is used to etch the substrate to form a plurality of first trenches corresponding to the pattern on the hard mask layer.

[0015] According to the first aspect of the present invention, a liner oxide layer is formed on the sidewalls and bottom wall of the second trench by using an in-situ steam oxidation process.

[0016] According to a first aspect of the present invention, a sacrificial oxide layer is grown in an active area using an in-situ steam oxidation process.

[0017] According to the first aspect of the present invention, the hard mask layer includes an oxide layer and a nitride layer sequentially stacked on the substrate.

[0018] According to the first aspect of the present invention, the oxide layer is a silicon oxide layer, and the nitride layer is a silicon nitride layer.

[0019] According to the first aspect of the present invention, the step of removing the hard mask layer comprises the following steps:

[0020] removing the nitride layer using a phosphoric acid solution; and

[0021] The oxide layer is removed using a dilute hydrofluoric acid solution.

[0022] According to the first aspect of the present invention, the thickness of the hard mask oxide layer is between 5 nanometers and 20 nanometers.

[0023] According to the first aspect of the present invention, the preparation method further comprises the following steps:

[0024] forming a well region by using an ion implantation process;

[0025] The sacrificial oxide layer is removed.

[0026] A second aspect of the present invention provides a semiconductor device, the semiconductor device comprising a shallow trench isolation structure, and the shallow trench isolation structure is obtained by using the preparation method.

[0027] Compared with the existing process, the preparation method of the shallow trench isolation structure of the present invention saves the pull-back step in the preparation of the shallow trench isolation structure by adding the etching steps of the hard mask layer and the deposition steps of the hard mask oxide layer, thereby avoiding the consumption of the height of the hard mask layer caused by the pull-back step, and making it easier to adjust the height of the step at that location, thereby reducing the corner defect problem of the shallow trench isolation, improving the leakage of the semiconductor device and improving the overall performance of the semiconductor device; further, the etching self-aligned dry etching process of the hard mask layer can utilize the dry etching technology to etch the oxide (Oxide, such as silicon dioxide SiO 2 ) has the advantage that the etching (or reaction) rate is much higher than that of silicon (Silicon), and the preparation method of the present invention does not require the addition of a mask plate (Mask), thereby saving preparation costs and reducing product defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0029] Figure 1 A flowchart of a method for preparing a shallow trench isolation structure according to an embodiment of the present invention; and

[0030] Figures 2 to 11 The schematic diagram is a structural diagram of a substrate after each step of a method for preparing a shallow trench isolation structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0032] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0033] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0034] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0035] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0036] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0037] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0038] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0039] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.

[0040] The following further describes the method for preparing the shallow trench isolation structure and the semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. It can be understood that the various specific embodiments are not intended to limit the protection scope of the present invention.

[0041] Figure 1 The flowchart of a method for preparing a shallow trench isolation structure according to an embodiment of the present invention is as follows. Specifically, a method for preparing a shallow trench isolation structure includes the following steps:

[0042] Step S100: providing a substrate, the substrate comprising a substrate 1 and a patterned hard mask layer on the substrate 1, Figure 2; The substrate can be determined according to the structure of the target semiconductor device, and the substrate 1 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 10 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc. The substrate can be N-type or P-type.

[0043] The hard mask layer in step S100 may include an oxide layer 21 and a nitride layer 22 sequentially stacked on the substrate 1. Further, the oxide layer may be a silicon oxide layer with a thickness between 100 angstroms and 200 angstroms, and the nitride layer may be a silicon nitride layer with a thickness between 1000 angstroms and 2000 angstroms. After the hard mask layer is deposited on the substrate, a photoresist may be coated on the surface of the hard mask layer and the photoresist layer may be exposed and developed to obtain a patterned photoresist layer; after obtaining the patterned photoresist layer, a dry etching process (Dry Etch), such as reactive ion etching (Reactive Ion Etch, RIE) and other processes may be used to form a pattern including a plurality of grooves C on the hard mask layer, the pattern determines the area to be etched, and the grooves C correspond to the position of the shallow trench isolation structure to be obtained later, so the size of the groove C may be determined according to the width of the target shallow trench isolation structure to be obtained.

[0044] In the process of etching the oxide layer 21 and the nitride layer 22, the dry etching process uses different gas combinations and etching parameters. For example, for the etching of the nitride layer 22, chlorine-containing or fluorine-containing gases can be used; for the etching of the oxide layer 21, gases such as fluorocarbons can be used, and the active fluorine ions generated by the plasma react chemically with silicon oxide to remove the oxide layer 21. It should be noted that in the process of etching the hard mask layer, due to the unevenness of the etching process, over-etching, etc., the size or shape of the active area (Active Area, AA) may change, thereby reducing the effective area of ​​the active area (Loss AA).

[0045] After step S100, after removing the photoresist or other organic residues on the surface of the substrate, step S200 is performed: depositing a hard mask oxide layer 3 on the substrate, the hard mask oxide layer 3 covers the surface of the hard mask layer (nitride layer 22) and the sidewalls and bottom walls of the pattern (trench C), and the sidewalls and bottom walls of the pattern (trench C) are respectively formed by the hard mask oxide layer 3A and the hard mask oxide layer 3B, see Figure 3 In this step, the hard mask oxide layer 3 may be a silicon oxide layer deposited by a chemical vapor deposition process, such as a hard mask oxide layer 3 deposited by plasma enhanced chemical vapor deposition (PECVD). The thickness of the deposited hard mask oxide layer 3 may be determined based on the width of the active area AA and the width of the notch obtained from the empirical value of the semiconductor structure. Preferably, the thickness of the hard mask oxide layer is between 5 nanometers and 20 nanometers. For example, when the width of the notch is 40nm, the thickness of the hard mask oxide layer 3 may be between 5-10 nanometers.

[0046] After obtaining the hard mask oxide layer 3, step S300 is performed: etching the substrate to form a plurality of first trenches T corresponding to the pattern on the hard mask layer, the first trenches T extending to the substrate 1 and the sidewalls of the pattern of the hard mask layer retain the hard mask oxide layer 3A, Figure 4 . Step S300 can be obtained by using a self-aligned dry etching process, which is mainly based on the principle of selective etching of patterns and materials defined by photolithography. The self-aligned dry etching process has higher precision, so that the pattern can be transferred to the substrate more accurately. The etching in step S300 can be regarded as a physical etching process, or an anisotropic etching process. For example, a reactive plasma etching process (Reactive Ion Etching, RIE) can be used to use the active ions in the plasma to react chemically with the etched material, and at the same time remove the material by physical bombardment, that is, the plasma has a large energy and a low gas density, and the etching of the film is promoted by the physical bombardment of the charged ions on the etched surface, that is, the etching mainly occurs in a direction perpendicular to the surface of the etched film, which is also called anisotropic plasma etching. The side walls of the grooves etched in this way are close to vertical or have a slope of less than 90°. More specifically, for example, when the substrate 1 is a silicon substrate, when etching the silicon material, an etching gas containing fluorine (F) elements, such as carbon tetrafluoride (CF 4 ) or nitrogen trifluoride (NF 3 ), these gases decompose in a plasma state to produce fluoride ions, which react with silicon to form volatile silicon tetrafluoride (SiF 4), thereby etching a partial thickness of the substrate, and due to the selectivity of the etching, the oxide on the sidewall of the pattern (trench C) can be well retained, forming a first trench T with a hard mask oxide layer 3A on both sides of the trench C.

[0047] Then, step S400 is performed: the hard mask oxide layer 3A on the sidewall of the hard mask layer pattern is removed by wet etching to form a second trench T1. Figure 5 When the hard mask oxide layer 3A is a silicon oxide layer, the wet etching solution may be a hydrofluoric acid (HF) solution, and the concentration, temperature and etching time of the hydrofluoric acid solution may be determined according to the desired rate and target effect of etching the hard mask oxide layer 3A. After step S400, a step S is formed at the corner where the shallow trench isolation structure STI intersects with the active area AA.

[0048] Step S500: forming a liner oxide layer 4 on the sidewalls and bottom wall of the second trench T1. Figure 6 . In one embodiment, step S550 may form a liner oxide layer 4 on the sidewalls and bottom wall of the second trench T1 using an in-situ steam generation (ISSG) process. The ISSG process grows oxide by reacting silicon with water vapor at high temperature. In this process, water vapor decomposes on the silicon surface, and the generated oxygen atoms combine with silicon atoms to form silicon dioxide. Compared with the traditional thermal oxidation process, the ISSG process has a higher oxidation rate and better oxide layer quality, and can grow a thicker oxide layer in a shorter time. The ISSG process can provide a uniform supply of water vapor, so that the oxidation reaction on the surface of the active area AA is carried out more uniformly. Even at the corners of the active area (AA) in the shallow trench isolation (STI) process, since water vapor can fully reach, the growth of the oxide layer will not be locally restricted, so that a more rounded shape can be naturally formed, reducing the appearance of missing corners, thereby avoiding the electric field caused by the missing corners to be concentrated at the tip, thereby causing leakage, and improving the reliability and yield of semiconductor devices.

[0049] In step S600: filling the second trench T1 to form a shallow trench isolation filling T2, see Figure 7 Specifically, in step S600, a high aspect ratio (HARP) process capable of effectively filling a trench with a high aspect ratio may be used to fill silicon dioxide in the second trench T1. The HARP process is an improved sub-atmospheric pressure chemical vapor deposition (SACVD) technology. 3 / TEOS (ozone / ethyl orthosilicate) method to obtain a higher deposition rate. At the same time, by adjusting the HARP process parameters such as gas flow, reaction temperature, pressure and plasma power, the generated SiO2 A bottom-up filling method is implemented in the trench, which can avoid premature closure at the top of the trench, thereby reducing the formation of voids, achieving good device isolation effect of the shallow trench, and reducing leakage and interference between adjacent devices. After filling the second trench T1, the second trench T1 filled with silicon dioxide is planarized by chemical-mechanical polishing (CMP), and the chemical-mechanical polishing is performed to the hard mask layer (nitride layer 21).

[0050] After obtaining the shallow trench isolation filling T2, step S700 is performed: removing the hard mask layer; as described above, when the hard mask layer includes an oxide layer 21 and a nitride layer 22 sequentially stacked on the substrate 1, the step of removing the hard mask layer in step S700 includes the following steps:

[0051] S701: Use phosphoric acid solution to remove the nitride layer 22, see Figure 8 ;

[0052] S702: Use dilute hydrofluoric acid solution to remove the oxide layer 21, see Fig. 9 .

[0053] After step S702, the active area AA is exposed, and step S800 is performed: a sacrificial oxide layer (SACoxide) 5 is grown in the active area. Fig.10 Similarly, in this step, the ISSG process can be used to in-situ grow a sacrificial oxide layer 5 on the active area AA, and the sacrificial oxide layer 5 is a silicon dioxide layer. The sacrificial oxide layer 5 is used as a hard mask layer for the ion implantation process when forming the well region, and its thickness is usually between tens of nanometers and hundreds of nanometers. The specific thickness depends on factors such as process requirements and subsequent processes.

[0054] In some other embodiments, the preparation method further comprises the following steps:

[0055] Step S900: Use ion implantation process to form a well region (not shown in the figure). In this step, photolithography is used to define the pattern of the well region on the sacrificial oxide layer 5. Through exposure and development of photoresist, the area where the impurity ions do not need to be implanted is covered with photoresist for protection, and the exposed area is the well region to be implanted later. Different impurity ions are implanted, and the electrical properties of the formed well region are also different. For example, phosphorus (P) ion implantation forms an N well, and boron (B) ion implantation forms a P well.

[0056] After the ion implantation is completed, step S910 is finally performed: removing the sacrificial oxide layer 5. Fig.11 In this step, a dilute hydrofluoric acid solution may be used to remove the sacrificial oxide layer 5 .

[0057] The present invention also provides a semiconductor device, which includes a shallow trench isolation structure, such as a complementary metal oxide semiconductor device (CMOS integrated circuit), wherein the shallow trench isolation structure is used to isolate adjacent transistors to prevent current leakage between them, thereby improving the performance and reliability of the device. The shallow trench isolation structure is obtained by the preparation method.

[0058] Compared with the existing process, the preparation method of the shallow trench isolation structure of the present invention saves the pull-back step in the preparation of the shallow trench isolation structure by adding the etching steps of the hard mask layer and the deposition steps of the hard mask oxide layer, thereby avoiding the consumption of the height of the hard mask layer caused by the pull-back step, and making it easier to adjust the height of the step at that location, thereby reducing the corner defect problem of the shallow trench isolation, improving the leakage of the semiconductor device and improving the overall performance of the semiconductor device; further, the etching self-aligned dry etching process of the hard mask layer can utilize the dry etching technology to etch the oxide (Oxide, such as silicon dioxide SiO 2 ) has the advantage that the etching (or reaction) rate is much higher than that of silicon (Silicon), and the preparation method of the present invention does not require the addition of a mask plate (Mask), thereby saving preparation costs and reducing product defects.

[0059] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0060] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a shallow trench isolation structure, characterized in that: The preparation method comprises the following steps: Providing a substrate, the substrate comprising a base plate and a patterned hard mask layer on the base plate; Depositing a hard mask oxide layer on the substrate, the hard mask oxide layer covering the surface of the hard mask layer and the sidewalls and bottom walls of the pattern; Etching the substrate to form a plurality of first trenches corresponding to the pattern on the hard mask layer, wherein the first trenches extend to the substrate and the hard mask oxide layer is retained on the sidewalls of the pattern of the hard mask layer; Wet etching to remove the hard mask oxide layer on the sidewall of the pattern of the hard mask layer to form a second trench; forming a liner oxide layer on the sidewalls and bottom wall of the second trench; filling the second trench; removing the hard mask layer; A sacrificial oxide layer is grown on the active area.

2. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The substrate is etched using a self-aligned dry etching process to form a plurality of first trenches corresponding to the pattern on the hard mask layer.

3. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: An in-situ steam oxidation process is used to form a liner oxide layer on the sidewalls and bottom wall of the second trench.

4. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: An in-situ steam oxidation process is used to grow a sacrificial oxide layer in the active area.

5. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The hard mask layer includes an oxide layer and a nitride layer sequentially stacked on the substrate.

6. The method for preparing a shallow trench isolation structure according to claim 5, characterized in that: The oxide layer is a silicon oxide layer, and the nitride layer is a silicon nitride layer.

7. The method for preparing a shallow trench isolation structure according to claim 6, characterized in that: The step of removing the hard mask layer comprises the following steps: removing the nitride layer using a phosphoric acid solution; and The oxide layer is removed using a dilute hydrofluoric acid solution.

8. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The hard mask oxide layer has a thickness of 5 nanometers to 20 nanometers.

9. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The preparation method further comprises the following steps: forming a well region by using an ion implantation process; The sacrificial oxide layer is removed.

10. A semiconductor device, characterized in that: The semiconductor device comprises a shallow trench isolation structure, and the shallow trench isolation structure is obtained by using the preparation method described in any one of claims 1 to 9.

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