Display panel, display control method thereof and display device

Abstract

The invention provides a display panel, a display control method thereof and a display device, and belongs to the technical field of display. In the display panel, a plurality of first driving units (031) included in a first driving circuit (03) can output gate driving signals based on starting signals provided by coupled first starting lines. And a plurality of second driving units (041) included in the second driving circuit (04) can output a gate driving signal based on a starting signal provided by a coupled second starting line. The first gating units (032) can control the connection and disconnection between the corresponding first driving units (031) and a part of pixels based on enable signals provided by the coupled first enable lines. The second gating unit (042) can control the connection and disconnection between the corresponding second driving unit (041) and the other part of pixels based on an enable signal provided by a coupled second enable line. Therefore, flexible refresh of pixels in different areas in the display area can be realized by flexibly setting the enable signal and the start signal, and the refresh rates for different areas can be different, that is, partition frequency conversion can be realized, so that the power consumption is reduced.

Description

Display panel, display control method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display control method thereof, and a display device. Background Art

[0002] Low temperature polycrystalline silicon oxide (LTPO) display products are gaining increasing market attention due to their ability to achieve low-frequency display and thus save display power consumption.

[0003] In related technologies, LTPO display products generally include: a substrate, multiple rows of pixels located on the substrate, each row including multiple columns of pixels, and an array substrate row driver (GOA) circuit that drives the multiple pixels to emit light. The GOA circuit includes multiple cascaded GOA units, and the multiple GOA units are coupled to the multiple rows of pixels on the substrate in a one-to-one correspondence via multiple gate lines. The GOA circuit is used to transmit gate drive signals to the multiple rows of pixels row by row, thereby achieving row-by-row scanning and refreshing, thereby lighting up the multiple rows of pixels row by row.

[0004] However, due to the limitations of the coupling and layout of the GOA circuit and pixels, only full-screen refresh is currently possible (i.e., the refresh rate is the same in different areas of the full screen), and split-screen refresh is not possible for different areas. The refresh flexibility is poor, which in turn causes the display product to have higher operating power consumption.

[0005] Summary of the Invention

[0006] Provided are a display panel, a display control method thereof, and a display device. The technical solution is as follows:

[0007] In one aspect, a display panel is provided, comprising:

[0008] a substrate having a display area and a peripheral area at least partially surrounding the display area;

[0009] A plurality of pixels arranged in an array are located in the display area;

[0010] A first driving circuit is located in the peripheral area, the first driving circuit comprising: a plurality of first driving units connected in cascade, and a plurality of first gating units corresponding one-to-one to the plurality of first driving units;

[0011] a second driving circuit located in the peripheral area, the second driving circuit comprising: a plurality of second driving units connected in cascade, and a plurality of second gating units corresponding one-to-one to the plurality of second driving units;

[0012] Wherein, at least one first driving unit and at least one second driving unit are respectively located on both sides of the substrate in the pixel row direction, each first gating unit and the corresponding first driving unit are located on the same side of the substrate, and each second gating unit and the corresponding second driving unit are located on the same side of the substrate;

[0013] Furthermore, each first driving unit is coupled to a portion of pixels in at least one row of pixels through a corresponding first gating unit; the first gating unit is further coupled to a first enable line and is used to control the on / off switching of the first driving unit and the portion of pixels based on a first enable signal provided by the first enable line; the plurality of first driving units are further coupled to a first enable line and are used to output a first gate driving signal based on a first enable signal provided by the first enable line;

[0014] Each second driving unit is coupled to another part of the pixels in the at least one row of pixels through a corresponding second gating unit; the second gating unit is also coupled to a second enable line, and is used to control the on and off of the second driving unit and the another part of the pixels based on a second enable signal provided by the second enable line; the multiple second driving units are also coupled to a second turn-on line, and are used to output a second gate driving signal based on a second turn-on signal provided by the second turn-on line.

[0015] Optionally, the plurality of first driving units are all located on a first side of the two sides; and the plurality of second driving units are all located on a second side of the two sides.

[0016] Optionally, among the plurality of first drive units, a portion of the first drive units are located on a first side of the two sides, and the remaining first drive units except the portion of the first drive units are located on a second side of the two sides;

[0017] Among the plurality of second driving units, a portion of the second driving units are located on a first side of the two sides, and the remaining second driving units except the portion of the second driving units are located on a second side of the two sides.

[0018] Optionally, each first driving unit is coupled to a portion of pixels in a row of pixels through a corresponding first gating unit;

[0019] Among the plurality of first driving units, each first driving unit coupled to pixels in even rows is located on the first side, and each first driving unit coupled to pixels in odd rows is located on the second side.

[0020] Optionally, each second driving unit is coupled to another part of pixels in a row of pixels through a corresponding second gating unit;

[0021] Among the plurality of second driving units, each second driving unit coupled to pixels in even rows is located on the first side, and each second driving unit coupled to pixels in odd rows is located on the second side.

[0022] Optionally, the first driving units and the second driving units located on the first side are arranged in sequence of one first driving unit and one second driving unit in the direction of the pixel columns;

[0023] The first driving units and the second driving units located on the second side are arranged in sequence of one second driving unit and one first driving unit in the direction of pixel columns.

[0024] Optionally, each first driving unit is coupled to a first driving line through a corresponding first gating unit, and the first driving line is coupled to the portion of pixels; each second driving unit is coupled to a second driving line through a corresponding second gating unit, and the second driving line is coupled to the other portion of pixels; and the multiple first driving units are cascaded through the first driving line; and the multiple second driving units are cascaded through the second driving line.

[0025] Optionally, when the plurality of first driving units are all located on a first side of the two sides, and the plurality of second driving units are all located on a second side of the two sides, the first driving line and the second driving line are independent of each other.

[0026] Optionally, among the multiple first drive units, a portion of the first drive units are located on the first side of the two sides, and the remaining first drive units except the portion of the first drive units are located on the second side of the two sides; and among the multiple second drive units, a portion of the second drive units are located on the first side of the two sides, and the remaining second drive units except the portion of the second drive units are located on the second side of the two sides:

[0027] In addition to being coupled to pixels, the first driving line also runs through the display area and cascades the first driving unit located on the first side and the first driving unit located on the second side;

[0028] In addition to being coupled to the pixels, the second driving line also runs through the display area and cascades the second driving unit located on the first side and the second driving unit located on the second side;

[0029] Furthermore, the first driving line and the second driving line coupled to the same row of pixels overlap in the display area.

[0030] Optionally, a portion of the first drive line used for coupling pixels and a portion used for cascading the first drive unit are located in different layers; a portion of the second drive line used for coupling pixels and a portion used for cascading the second drive unit are located in different layers; and overlapping portions of the first drive line and the second drive line are located in different layers.

[0031] Optionally, the pixel includes: a gate metal layer, an insulating layer, and a source / drain metal layer stacked in sequence on one side of the substrate;

[0032] Among them, in the first driving line, the portion for coupling the pixel is located in the same layer as the gate metal layer, the portion for cascading the first driving unit is located in the same layer as the source / drain metal layer, and the portion for coupling the pixel and the portion for cascading the first driving unit are connected through a via hole penetrating the insulating layer;

[0033] In the second driving line, the portion for coupling pixels is located in the same layer as the gate metal layer, the portion for cascading the second driving unit is located in the same layer as the source / drain metal layer, and the portion for coupling pixels and the portion for cascading the second driving unit are connected through vias passing through the insulating layer.

[0034] Optionally, the substrate includes:

[0035] A left display area and a right display area arranged along the pixel row direction from the first column of pixels to the last column of pixels, the left display area including the portion of pixels, and the right display area including the other portion of pixels;

[0036] An upper display area and a lower display area are arranged along the pixel column direction from the first row of pixels to the last row of pixels, and each of the upper display area and the lower display area includes at least one row of pixels.

[0037] Optionally, the refresh rate of the upper display area is greater than or equal to the refresh rate of the lower display area.

[0038] Optionally, the left display area and the right display area have the same area and include the same number of pixels; and / or, the upper display area and the lower display area have the same area and include the same number of pixels.

[0039] Optionally, among the plurality of first gating units and the plurality of second gating units, the gating units located on the same side of the substrate share a same enable line.

[0040] Optionally, the first gating unit includes: a first gating switch tube; the second gating unit includes: a second gating switch tube;

[0041] The gate of the first gate switch tube is coupled to the first enable line, the first electrode of the first gate switch tube is coupled to the corresponding first driving unit, and the second electrode of the first gate switch tube is coupled to the part of pixels;

[0042] A gate of the second gate switch tube is coupled to the second enable line, a first electrode of the second gate switch tube is coupled to the corresponding second driving unit, and a second electrode of the second gate switch tube is coupled to the other part of pixels.

[0043] Optionally, each first driving unit is coupled to a portion of pixels in at least one row of pixels, close to the first gating unit, through a corresponding first gating unit; each second driving unit is coupled to another portion of pixels in at least one row of pixels, close to the second gating unit, through a corresponding second gating unit; and the pixels in the portion of pixels are adjacent to each other, and the pixels in the other portion of pixels are adjacent to each other.

[0044] Optionally, the display panel includes: a low-temperature polycrystalline silicon oxide (LTPO) display panel.

[0045] In another aspect, a display control method is provided for controlling the display panel according to the above aspect; the method comprising:

[0046] Determining refresh requirements of different areas in a display area of ​​the substrate, the different areas including a left area and a right area arranged along a pixel row direction, and / or an upper area and a lower area arranged along a pixel column direction, the refresh requirements being used to indicate whether a refresh is required and a refresh frequency;

[0047] In response to the frame synchronization signal, a first enable signal is transmitted to the first enable line coupled to the plurality of first gating units based on the refresh requirement, and a second enable signal is transmitted to the second enable line coupled to the plurality of second gating units; the first enable signal of the first potential is used to instruct the first gating unit to control the corresponding first driving unit to be turned on and the coupled part of pixels, and the first enable signal of the second potential is used to instruct the first gating unit to control the corresponding first driving unit to be disconnected from the coupled part of pixels; the second enable signal of the first potential is used to instruct the second gating unit to control the corresponding second driving unit to be turned on and the coupled other part of pixels, and the second enable signal of the second potential is used to instruct the second gating unit to control the corresponding second driving unit to be disconnected from the coupled other part of pixels;

[0048] In response to a frame synchronization signal, transmitting a first start signal to a first start line coupled to the plurality of first driving units, and transmitting a second start signal to a second start line coupled to the plurality of second driving units; the first start signal is used to instruct the plurality of first driving units to output a first gate driving signal, and the second start signal is used to instruct the plurality of second driving units to output a second gate driving signal;

[0049] When the first gating unit controls the first driving unit and a portion of the coupled pixels to be turned on, the first driving unit transmits the first gate driving signal to the portion of pixels;

[0050] When the second gating unit controls the second driving unit and another portion of pixels coupled thereto to be turned on, the second driving unit transmits the second gate driving signal to the another portion of pixels.

[0051] In another aspect, a display device is provided, comprising: a driver chip, and the display panel according to the above aspect;

[0052] The driving chip is coupled to a signal line coupled to a circuit in the display panel and is used to provide a signal to the signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] FIG1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0055] FIG2 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0056] FIG3 is a schematic structural diagram of another display panel provided in an embodiment of the present disclosure based on FIG1 ;

[0057] FIG4 is a schematic structural diagram of another display panel provided in an embodiment of the present disclosure based on FIG2 ;

[0058] FIG5 is a schematic diagram of a film structure of a pixel provided by an embodiment of the present disclosure;

[0059] FIG6 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present disclosure based on FIG4 ;

[0060] FIG7 is a schematic diagram of a display area division of a substrate provided by an embodiment of the present disclosure;

[0061] FIG8 is a schematic diagram of a circuit structure of a driving unit and a gating unit provided in an embodiment of the present disclosure;

[0062] FIG9 is a schematic diagram of a circuit structure of a pixel provided by an embodiment of the present disclosure;

[0063] FIG10 is a flow chart of a display control method provided by an embodiment of the present disclosure;

[0064] FIG11 is a signal timing diagram provided by an embodiment of the present disclosure based on the structure of FIG1 ;

[0065] FIG12 is a signal timing diagram provided by an embodiment of the present disclosure based on the structure of FIG2 ;

[0066] FIG13 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0068] It should be noted that the transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode, and the drain is referred to as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is designated as the control electrode, which can also be referred to as the gate, the signal input end is designated as the source electrode, and the signal output end is designated as the drain electrode. Furthermore, the switching transistors used in the embodiments of the present disclosure can include either a P-type switching transistor or an N-type switching transistor. A P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, while an N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. Furthermore, multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two state variables and do not imply that the first potential or the second potential has a specific value throughout the text.

[0069] As consumers pursue the ultimate power consumption of display products, LTPO display panels have been designed. Due to the special nature of the material, it can achieve low-frequency display, with a minimum of 1 Hz, which can reduce power consumption and meet users' demand for low power consumption. Of course, it is not limited to this. Now many manufacturers have further proposed the design of partition frequency conversion based on low-frequency display. Among them, partition frequency conversion refers to: dividing the display area of ​​a display panel into multiple areas, and setting different refresh rates for each area. In this way, local refresh areas can be updated, and local areas that do not need to be refreshed can be maintained, achieving more intelligent refresh, thereby saving more power. However, the existing partition frequency conversion design can only control the minimum refresh area to an entire row, that is, the display area can only be divided into multiple areas according to pixel rows, each area includes at least one row of pixels, and the upper and lower areas including at least one row of pixels are partitioned and refreshed.

[0070] On this basis, the embodiment of the present disclosure takes into account further reduction of the refresh area, with the purpose of being more power-saving and intelligent, and proposes a partition frequency conversion design that can realize both upper and lower partitioning and left and right partitioning (that is, dividing the area into units of pixel columns).

[0071] FIG1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. As shown in FIG1 , the display panel includes:

[0072] Substrate 01. The substrate 01 has a display area A1 and a peripheral area B1 that at least partially surrounds the display area A1. As shown in Figure 1, in the substrate 01 shown therein, the peripheral area B1 partially surrounds the display area A1 and is located on the left and right sides of the display area A1. Of course, in some other embodiments, the peripheral area B1 may also be located on the upper side and / or lower side of the display area A1. Alternatively, the peripheral area B1 may also surround the display area A1, that is, the display area A1 is surrounded by the GOA area. The disclosed embodiment does not limit the positional relationship between the peripheral area B1 and the display area A1.

[0073] Multiple pixels 02 arranged in an array. The multiple pixels 02 are located in the display area A1. The array arrangement may refer to the multiple pixels 02 being arranged in the pixel row direction X1 and the pixel column direction Y1 as shown in FIG1 , that is, the display panel may include multiple rows and columns of pixels as shown in FIG1 .

[0074] The first driving circuit 03 is located in the peripheral area B1 and includes a plurality of first driving units 031 connected in cascade, and a plurality of first gating units 032 corresponding to the plurality of first driving units 031 on a one-to-one basis.

[0075] The second driving circuit 04 is located in the peripheral area B1 and includes a plurality of cascaded second driving units 041 and a plurality of second gating units 042 corresponding to the plurality of second driving units 041 .

[0076] It should be noted that, taking the first drive circuit 03 as an example, with reference to FIG1 , a one-to-one correspondence between multiple first drive units 031 and multiple first gating units 032 may mean that: each first drive unit 031 corresponds to a first gating unit 032, and different first drive units 031 correspond to different first gating units 032. Also, a cascade connection of multiple first drive units 031 may mean that: two (also referred to as two poles) first drive units 031 are coupled to each other, and the latter first drive unit 031 operates under the drive of the previous first drive unit 031. Moreover, the two first drive units 031 coupled to each other here may be adjacent as shown in FIG1 , or they may not be adjacent. The relevant description of the second drive circuit 04 is similar, and will not be repeated in detail in the present embodiment.

[0077] Based on the above coupling, with continued reference to FIG1 , it can be seen that the at least one first driving unit 031 and the at least one second driving unit 041 described in the embodiment of the present disclosure can be located on both sides of the substrate 01 in the pixel row direction X1. That is, as shown in FIG1 , there are one or more first GOA units 031 and second GOA units 041 located on the left and right sides of the display area A1, respectively. Furthermore, each first gating unit 032 and the corresponding first driving unit 031 can be located on the same side of the substrate 01, and each second gating unit 042 and the corresponding second driving unit 041 can be located on the same side of the substrate 01.

[0078] Each first driving unit 031 is coupled to a portion of pixels 02 in at least one row of pixels 02 via a corresponding first gating unit 032. Each first gating unit 032 is also coupled to a first enable line GE1 and is configured to control the switching between the first driving unit 031 and the portion of pixels 02 based on a first enable signal provided by the first enable line GE1. The plurality of first driving units 031 are also coupled to a first turn-on line STV1 and are configured to output a first gate driving signal based on a first turn-on signal provided by the first turn-on line STV1.

[0079] For example, each first driving unit 031 shown in FIG1 is coupled to a portion of pixels 02 in a row of pixels 02 via a corresponding first gating unit 032. Furthermore, the first gating unit 032 can control the first driving unit 031 to be conductive with the coupled portion of pixels 02 when the potential of the first enable signal provided by the first enable line GE1 is a first potential, thereby enabling the first gate driving signal output by the first driving unit 031 to be further transmitted to the portion of pixels 02, thereby implementing a refresh scan of the portion of pixels 02 and driving the portion of pixels 02 to emit light. Furthermore, the first gating unit 032 can control the first driving unit 031 to be disconnected from the coupled portion of pixels 02 when the potential of the first enable signal provided by the first enable line GE1 is a second potential, thereby preventing the first gate driving signal output by the first driving unit 031 from being transmitted to the portion of pixels 02. In other words, the first gating unit 032 can effectively control whether the first gate driving signal output by the first driving unit 031 enters the pixels 02 based on the potential of the first enable signal.

[0080] Optionally, in the embodiment of the present disclosure, the first potential may be an effective potential, the second potential may be an ineffective potential, and the first potential may be a high potential relative to the second potential. Of course, in some other embodiments, the first potential may also be a low potential relative to the second potential.

[0081] Each second driving unit 041 is coupled to another portion of pixels 02 in at least one row of pixels 02 via a corresponding second gating unit 042. Each second gating unit 042 is also coupled to a second enable line GE2 and is configured to control the switching between the second driving unit 041 and another portion of pixels 02 based on a second enable signal provided by the second enable line GE2. The plurality of second driving units 041 are also coupled to a second turn-on line STV2 and are configured to output a second gate driving signal based on a second turn-on signal provided by the second turn-on line STV2.

[0082] For example, each second driving unit 041 shown in FIG1 is coupled to another portion of pixels 02 in a row of pixels 02 via a corresponding second gating unit 042. The second gating unit 042 can control the second driving unit 041 to be conductive with the coupled portion of pixels 02 when the potential of the second enable signal provided by the second enable line GE2 is a first potential, thereby enabling the second gate driving signal output by the second driving unit 041 to be further transmitted to the coupled portion of pixels 02, thereby achieving refresh scanning of the coupled portion of pixels 02 and driving the coupled portion of pixels 02 to emit light. Furthermore, the second gating unit 042 can control the second driving unit 041 to be disconnected from the coupled portion of pixels 02 when the potential of the second enable signal provided by the second enable line GE2 is a second potential, thereby preventing the second gate driving signal output by the second driving unit 041 from being transmitted to the coupled portion of pixels 02. That is, the second gating unit 042 can effectively control whether the second gate driving signal output by the second driving unit 041 enters the pixel 02 based on the potential of the second enable signal.

[0083] That is, in the display panel described in the embodiment of the present disclosure, for each row of pixels 02, a portion (which may be one or more) of the pixels 02 can be coupled to a corresponding first driving unit 031 through a first gating unit 032; and another portion of the pixels 02 other than the portion of the pixels 02 can be coupled to a corresponding second driving unit 041 through a second gating unit 042. In other words, for multiple pixels 02 located in the same row, they can be divided into two parts in the pixel row direction X1 and respectively coupled to different driving units to receive different gate drive signals. In addition, the first gating unit 032 can control the on / off of the first driving unit 031 and a portion of the pixels 02 in the row of pixels 02 based on the received first enable signal; the second gating unit 042 can control the on / off of the second driving unit 041 and another portion of the pixels 02 in the row of pixels 02 based on the received second enable signal. In other words, the first gating unit 032 and the second gating unit 042 can control the on / off of the corresponding driving unit and the pixels 02 based on different enable signals provided by different enable lines. Furthermore, the first drive unit 031 can output a first gate drive signal based on the received first turn-on signal; and the second drive unit 041 can output a second gate drive signal based on the received second turn-on signal. In other words, the first drive unit 031 and the second drive unit 041 can output gate drive signals based on different turn-on signals provided by different turn-on lines. In this way, by flexibly setting the turn-on signal and the enable signal and matching the coupling relationship, flexible and intelligent refresh of the pixels 02 in the upper, lower, left and right different areas of the display area A1 can be achieved, and different refresh rates can be provided for the refresh of different areas, thereby achieving the purpose of frequency division design and achieving the purpose of saving more power. In addition, by arranging the first drive unit 031 and the second drive unit 041 on the left and right sides of the display area A1 respectively, it can also be beneficial to the narrow frame design of the display device, thereby laying the foundation for a full-screen design.

[0084] It should be noted that, since the first driving unit 031 and the second driving unit 041 are both used to output gate driving signals, in the embodiment of the present disclosure, the first driving unit 031 and the second driving unit 041 can also be referred to as GOA units described in the above embodiment. Correspondingly, the first driving circuit 03 including the first driving unit 031 and the second driving circuit 04 including the second driving unit 041 can be referred to as GOA circuits.

[0085] In summary, embodiments of the present disclosure provide a display panel. The display panel includes a substrate having a display area and a peripheral area, a plurality of pixels located in the display area, and a first drive circuit and a second drive circuit located in the peripheral area. The first drive circuit includes a plurality of first drive units and a plurality of first gating units in a one-to-one correspondence. The second drive circuit includes a plurality of second drive units and a plurality of second gating units in a one-to-one correspondence. The plurality of first drive units are cascaded and coupled to a first enable line, and are also coupled to a portion of pixels in a row of pixels through corresponding first gating units. The plurality of second drive units are cascaded and coupled to a second enable line, and are also coupled to another portion of pixels in the row of pixels through corresponding second gating units. The first gating units are also coupled to a first enable line. The second gating units are also coupled to a second enable line. The plurality of first drive units are capable of outputting a first gate drive signal based on a first enable signal provided by the first enable line. The plurality of second drive units are capable of outputting a second gate drive signal based on a second enable signal provided by the second enable line. The first gating units are capable of controlling the switching of the corresponding first drive units and a portion of pixels based on a first enable signal provided by the first enable line. The second gating unit can control the switching of the corresponding second driving unit and another portion of pixels based on the second enable signal provided by the second enable line. This allows flexible setting of the enable and turn-on signals to achieve flexible refresh of pixels in different areas of the display, such as the top, bottom, left, or right. Furthermore, different refresh rates can be set for different areas, enabling zone-specific frequency conversion, thereby reducing power consumption and achieving intelligent power saving.

[0086] Optionally, it can be seen from Figure 1 that in the disclosed embodiment, each first driving unit 031 can be coupled to a portion of pixels 02 in at least one row of pixels 02, close to the first gating unit 032, through the corresponding first gating unit 032. Furthermore, each second driving unit 041 can be coupled to another portion of pixels 02 in at least one row of pixels 02, close to the second gating unit 042, through the corresponding second gating unit 042. Furthermore, the individual pixels 02 in a portion of pixels 02 can be adjacent to each other, and the individual pixels 02 in another portion of pixels 02 can be adjacent to each other. In this way, for a plurality of pixels 02 located in the same row, they can be divided into two parts, left and right, in the pixel row direction X1, thereby realizing a left-right frequency division design. In addition, it can also facilitate layout and wiring, saving manufacturing costs.

[0087] Optionally, referring to FIG. 1 , it can be seen that, among the plurality of first drive units 031, the first first drive unit 031 coupled to the first row of pixels 02 from top to bottom in the pixel column direction Y1 can be coupled to the first turn-on line STV1, and each of the first drive units 031 other than the first first drive unit 031 can be sequentially coupled to the adjacent previous-stage first drive unit 031. Similarly, among the plurality of second drive units 041, the first second drive unit 041 coupled to the first row of pixels 02 from top to bottom in the pixel column direction Y1 can be coupled to the second turn-on line STV2, and each of the second drive units 041 other than the first second drive unit 041 can be sequentially coupled to the adjacent previous-stage second drive unit 041. In this way, wiring and layout can be further facilitated, saving manufacturing costs.

[0088] Optional, as an optional implementation:

[0089] As shown in FIG1 , the first drive circuit 03 includes multiple first drive units 031 on the first side of the two sides. The second drive circuit 04 includes multiple second drive units 041 on the second side of the two sides. That is, of the two sides in the pixel row direction X1, one side may include multiple first drive units 031 in cascade connection, and the other side may include multiple second drive units 041 in cascade connection.

[0090] Optionally, with reference to Figure 1, the first side recorded in the embodiment of the present disclosure may refer to the left side of the display area A1, and the second side may refer to the right side of the display area A1. On this basis, combined with the coupling method of Figure 1, the multiple first driving units 031 located on the left side of the display area A1 can drive the pixels in the left half of the display area A1. The multiple second driving units 041 located on the right side of the display area A1 can drive the pixels in the right half of the display area A1. Left and right bilateral driving is achieved, laying the foundation for frequency division design. Of course, in some other embodiments, the first side may also refer to the right side of the display area A1, and correspondingly, the second side may refer to the left side of the display area A1.

[0091] However, after testing, it was found that the optional implementation shown in Figure 1 is prone to process fluctuations or loading differences. To this end, the embodiment of the present disclosure also proposes another layout method.

[0092] Alternatively, as another implementation option:

[0093] Referring to the structural schematic diagram of another display panel shown in FIG2 , it can be seen that among the multiple first drive units 031, a portion (which may be one or more) of the first drive units 031 may be located on the first side (e.g., the left side) of the two sides, and the remaining first drive units 031 excluding the portion of the first drive units 031 may be located on the second side (e.g., the right side) of the two sides. Similarly, among the multiple second drive units 041, a portion (which may be one or more) of the second drive units 041 may be located on the first side of the two sides, and the remaining second drive units 041 excluding the portion of the second drive units 041 may be located on the second side of the two sides.

[0094] Compared with an optional implementation method shown in Figure 1, this other optional implementation method can also realize left and right bilateral driving, and can also make the first gate drive signal and the second gate drive signal both transmitted throughout the entire row. It is no longer a simple left and right partition physically, and the left and right split screen phenomenon is not easy to occur.

[0095] Alternatively, with continued reference to FIG2 , it can be seen that each first driving unit 031 can be coupled to a portion of pixels 02 in a row of pixels 02 via a corresponding first gating unit 032. On this basis, among the plurality of first driving units 031, the first driving units 031 coupled to pixels 02 in even rows (i.e., row 2, row 4, row 6, ...) can be located on the first side, and the first driving units 031 coupled to pixels 02 in odd rows (i.e., row 1, row 3, row 5, ...) can be located on the second side.

[0096] 2 , it can be seen that each second driving unit 041 can be coupled to another portion of pixels 02 in a row of pixels 02 via a corresponding second gating unit 042. On this basis, among the plurality of second driving units 041, the second driving units 041 coupled to the pixels 02 in even rows can be located on the first side, and the second driving units 041 coupled to the pixels 02 in odd rows can be located on the second side.

[0097] That is, the first drive units 031 coupled to the odd-numbered rows of pixels 02 and the first drive units 031 coupled to the even-numbered rows of pixels 02 can be alternately arranged on the left and right sides in the pixel row direction X1. Furthermore, the second drive units 041 coupled to the odd-numbered rows of pixels 02 and the second drive units 041 coupled to the even-numbered rows of pixels 02 can be alternately arranged on both sides in the row direction. Furthermore, the first drive units 031 coupled to the odd-numbered rows of pixels 02 and the second drive units 041 coupled to the even-numbered rows of pixels 02 can be located on the same side (e.g., the left side); and the first drive units 031 coupled to the even-numbered rows of pixels 02 and the second drive units 041 coupled to the odd-numbered rows of pixels 02 can be located on the same side (e.g., the right side).

[0098] Accordingly, based on this, and continuing to refer to FIG. 2 , it can be seen that the first drive units 031 and the second drive units 041 located on the first side can be arranged in the order of one first drive unit 031 and one second drive unit 041 in the pixel column direction Y1. The first drive units 031 and the second drive units 041 located on the second side can be arranged in the order of one second drive unit 041 and one first drive unit 031 in the pixel column direction Y1. This can also facilitate layout, simplify wiring, and thus reduce manufacturing costs.

[0099] Of course, in some other embodiments, each adjacent row of pixels 02 may be grouped together, with each first drive unit 031 coupled to the same group located on the same side, and each first drive unit 031 coupled to adjacent groups located on the left and right sides, respectively. The same applies to the layout of the second drive units 041. In other words, when configuring multiple first drive units 031 and multiple second drive units 041, with some located on the first side and others on the second side, the layout is not limited to that shown in FIG. 2 .

[0100] Optionally, referring to FIG. 1 and FIG. 2 , it can be seen that among the plurality of first gating units 032 and the plurality of second gating units 042 located on the same side of the substrate 01, the gating units can share the same enable line. In other words, they are coupled to the same enable line. This can further simplify wiring and save costs.

[0101] Optionally, taking GOA1 as an example, identifying the first driver unit 031, MS1 as an example, identifying the first selection unit 032, and GOA2 as an example, identifying the second driver unit 041, and MS2 as an example, FIG3 shows a schematic structural diagram of another display panel based on the structure shown in FIG1 , and FIG4 shows a schematic structural diagram of another display panel based on the structure shown in FIG2 . Furthermore, FIG3 and FIG4 both schematically illustrate 10 first driver units GOA1-1 to GOA1-10 and corresponding 10 first selection units MS1-1 to MS1-10, and also schematically illustrate 10 second driver units GOA2-1 to GOA2-10 and corresponding 10 second selection units MS2-1 to MS2-10.

[0102] 3 and 4 , it can be seen that each first drive unit 031 (e.g., GOA1-1) can be coupled to the first drive line G1 through the corresponding first gating unit 032 (e.g., MS1-1), and the first drive line G1 can be coupled to a portion of the pixels 02. Each second drive unit 041 (e.g., GOA2-1) can be coupled to the second drive line G2 through the corresponding second gating unit 042 (e.g., MS2-1), and the second drive line G2 can be coupled to another portion of the pixels 02. Moreover, multiple first drive units 031 can be cascaded through the first drive line G1. Multiple second drive units 041 can be cascaded through the second drive line G2. Accordingly, each first drive unit 031 can transmit a first gate drive signal and a cascade signal through the first drive line G1. Similarly, each second drive unit 041 can transmit a second gate drive signal and a cascade signal through the second drive line G2.

[0103] And, as an optional implementation:

[0104] Referring to Figure 3 , when the plurality of first drive units 031 are located on the first of two sides, and the plurality of second drive units 041 are located on the second of two sides, the first drive line G1 and the second drive line G2 can be independent of each other. That is, they are not connected to each other. In other words, pixels 02 in the same row can be coupled to the two drive units via two drive lines.

[0105] As another optional implementation:

[0106] Referring to FIG4 , among the plurality of first drive units 031, a portion of the first drive units 031 is located on the first side of the two sides, while the remaining first drive units 031 are located on the second side of the two sides. Among the plurality of second drive units 041, a portion of the second drive units 041 is located on the first side of the two sides, while the remaining second drive units 041 are located on the second side of the two sides. In addition to coupling to pixels 02, the first drive line G1 may also pass through the display area A1, cascading the first drive unit 031 on the first side and the first drive unit 031 on the second side. In addition to coupling to pixels 02, the second drive line G2 may also pass through the display area A1, cascading the second drive unit 041 on the first side and the second drive unit 041 on the second side. Furthermore, the first drive line G1 and the second drive line G2 coupled to the same row of pixels 02 may overlap in the display area A1.

[0107] Optionally, the portion G11 of the first drive line G1 used for coupling to the pixel 02 and the portion G12 used for cascading the first drive unit 031 can be located on different layers. The portion G21 of the second drive line G2 used for coupling to the pixel 02 and the portion G22 used for cascading the second drive unit 041 can be located on different layers. Furthermore, the overlapping portion of the first drive line G1 and the second drive line Gate (see overlapping region C1) can be located on different layers.

[0108] Optionally, first referring to FIG. 5 , it can be seen that the pixel 02 described in the embodiment of the present disclosure may include: a gate metal layer GATE, an insulating layer J1 and a source / drain metal layer SD, which are located on one side of the substrate 01 and stacked in sequence.

[0109] For example, the gate metal layer GATE, insulating layer J1, and source / drain metal layer SD shown in FIG5 can be stacked sequentially in a direction away from the substrate 01. Furthermore, the pixel 02 can further include: a buffer layer BUFFER and an active layer ACT, which are located between the substrate 01 and the gate metal layer GATE and stacked sequentially in a direction away from the substrate 01. Based on FIG5 , referring to FIG6 , which shows a partial structural diagram of a display panel, it can be seen that:

[0110] In the first driving line G1, the portion G11 used for coupling the pixel 02 can be located on the same layer as the gate metal layer GATE, and the portion G12 used for cascading the first driving unit 031 can be located on the same layer as the source-drain metal layer SD, and the portion G11 used for coupling the pixel 02 and the portion G12 used for cascading the first driving unit 031 can be switched through a via (not shown in the figure) passing through the insulating layer J1.

[0111] In addition, in the second driving line G2, the portion G21 used for coupling the pixel 02 can be located on the same layer as the gate metal layer GATE, and the portion G22 used for cascading the second driving unit 041 can be located on the same layer as the source and drain metal layer SD, and the portion G21 used for coupling the pixel 02 and the portion G22 used for cascading the second driving unit 041 can be switched through a via (not shown in the figure) passing through the insulating layer J1.

[0112] In the overlapping region C1 , in the overlapping portion of the first driving line G1 and the second driving line G2 , one may be located in the same layer as the gate metal layer GATE, and the other may be located in the same layer as the source / drain metal layer SD.

[0113] That is, based on the layout of Figure 2, the crossover lines in the left and right areas of display area A1 can select the gate metal layer GATE and the source / drain metal layer SD. In some embodiments, the pixel may include two source / drain metal layers SD1 and SD2 stacked in sequence. Accordingly, the crossover lines here can also select the source / drain metal layer SD1 and / or the source / drain metal layer SD2. For example, as described in the above embodiment, the crossover line coupled to pixel 02 can select the gate metal layer GATE, and the crossover line not coupled to pixel 02 can select the source / drain metal layer SD1.

[0114] It should be noted that being located in the same layer may refer to: a film layer for forming a specific pattern is formed using the same film-forming process, and then the film layer is patterned using the same mask through a single patterning process to form a layer structure. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and are formed through the same patterning process. In this way, manufacturing processes and manufacturing costs can be saved, and manufacturing efficiency can be improved.

[0115] Alternatively, referring to FIG5 , it can be seen that a row of pixels 02 described in the embodiment of the present disclosure may include red (R) pixels 02, green (G) pixels 02, and blue (B) pixels. Of course, in some other embodiments, pixels of other colors, such as white pixels, may also be included.

[0116] Alternatively, referring to FIG. 5 , it can be seen that, in the pixel column direction Y1, the multiple columns of pixels 02 described in the embodiment of the present disclosure can also be coupled to multiple data lines S1 in a one-to-one correspondence and configured to receive data signals transmitted from the data lines S1. Each pixel 02 can emit light based on the received gate drive signal and data signal.

[0117] Continuing with reference to FIG3 and FIG4 , as well as FIG7 , which shows a schematic diagram of a substrate 01 , it can be seen that the substrate 01 described in the embodiments of the present disclosure may include: a left display area A11 and a right display area A12 arranged along the pixel row direction X1, from the first column of pixels 02 to the last column of pixels 02. The left display area A11 may include a portion of the pixels 02 in a row of pixels 02, and the right display area A12 may include another portion of the pixels 02 in a row of pixels 02. As described in the above embodiments, the portion of pixels 02 herein refers to the pixels 02 in a row of pixels 02 coupled to the first drive unit 031; the other portion of pixels 02 refers to the pixels 02 in a row of pixels 02 coupled to the second drive unit 041. That is, the first drive unit 031 may couple to multiple pixels 02 in the left display area A11 and drive the pixels 02 in the left display area A11 to emit light. The second drive unit 041 may couple to multiple pixels 02 in the right display area A12 and drive the pixels 02 in the right display area A12 to emit light. In this way, left and right frequency division design can be realized.

[0118] Furthermore, referring to FIG7 , in addition to being divided into the left display area A11 and the right display area A12, the substrate 01 may further include an upper display area and a lower display area arranged along the pixel column direction Y1 from the first row of pixels 02 to the last row of pixels 02. Each of the upper display area and the lower display area may include at least one row of pixels 02. For example, FIG7 identifies the upper display area that is divided into the left display area A11 as A11-1, and the lower display area as A11-2. The upper display area that is divided into the right display area A12 is identified as A12-1, and the lower display area is identified as A12-2.

[0119] Optionally, based on the layout shown in Figures 2 and 4, considering the reliable cascade transmission of the first driving unit 031 and the second driving unit 041, the embodiment of the present disclosure can also set the refresh rate (frames rate, FR) of the upper display area to be greater than the refresh rate of the lower display area.

[0120] For example, in Figure 7, in the left display area A11, the refresh rate FR1 of the upper display area A11-1 can be greater than or equal to the refresh rate FR3 of the lower display area A11-2; in the right display area A12, the refresh rate FR2 of the upper display area A12-1 can be greater than or equal to the refresh rate FR4 of the lower display area A12-2.

[0121] Of course, in the left display area A11 and the right display area A12, the refresh rates FR1 and FR2 of the upper display area A11-1 and A12-1 may be independent of each other, and the refresh rates FR3 and FR4 of the lower display area A11-2 and A12-2 may be independent of each other.

[0122] Optionally, in an embodiment of the present disclosure, in conjunction with Figure 7, the areas of the left display area A11 and the right display area A12 can be the same, and the number of pixels 02 included can be the same. And / or, the areas of the upper display area (A11-1 and A12-1) and the lower display area (A11-2 and A12-2) can be the same, and the number of pixels 02 included can be the same. That is, during frequency division driving, the left and right frequency division areas can be the same, and / or, the upper and lower frequency division areas can be the same. In this way, uniform frequency division driving can be achieved to ensure a better display effect.

[0123] Of course, in some other embodiments, the left and right frequency division areas may also be different according to different customer needs. For example, the area of ​​the left display area A11 may be 2 / 3 of the overall area of ​​the display area A1; correspondingly, the area of ​​the right display area A12 may be 1 / 3 of the overall area of ​​the display area A1. That is, a 2 / 3 frequency division may be set on the left and a 1 / 3 frequency division may be set on the right. In addition, the upper and lower frequency division areas may also be different. Of course, the refresh rates of the upper and lower frequency divisions may also be different. For example, the refresh rate of the upper display area may be 120Hz, and the refresh rate of the lower display area may be 30Hz.

[0124] Optionally, FIG8 is a simplified circuit diagram provided by an embodiment of the present disclosure. Referring to FIG8 , it can be seen that the first gating unit 032 described in the embodiment of the present disclosure may include: a first gating switch tube MS-T1. The second gating unit 042 includes: a second gating switch tube MS-T2.

[0125] The gate of the first gate switch transistor MS-T1 can be coupled to the first enable line GE1, the first electrode of the first gate switch transistor MS-T1 can be coupled to the corresponding first driving unit 031, and the second electrode of the first gate switch transistor MS-T1 can be coupled to a portion of the pixels 02. The first gate switch transistor MS-T1 can be configured to turn on when the potential of the first enable signal provided by the first enable line GE1 is a first potential, thereby connecting the first driving unit 031 to the pixels 02, thereby causing the first driving unit 031 to transmit the first gate drive signal to the pixels 02. Furthermore, the first gate switch transistor MS-T1 can be configured to turn off when the potential of the first enable signal provided by the first enable line GE1 is a second potential, thereby disconnecting the first driving unit 031 from the pixels 02.

[0126] The gate of the second gate switch transistor MS-T2 can be coupled to the second enable line GE2, the first electrode of the second gate switch transistor MS-T2 can be coupled to the corresponding second driving unit 041, and the second electrode of the second gate switch transistor MS-T2 can be coupled to another portion of the pixels 02. The second gate switch transistor MS-T2 can be configured to turn on when the potential of the second enable signal provided by the second enable line GE2 is a first potential, thereby connecting the second driving unit 041 to the pixels 02, thereby causing the second driving unit 041 to transmit the second gate driving signal to the pixels 02. Furthermore, the second gate switch transistor MS-T2 can be configured to turn off when the potential of the second enable signal provided by the second enable line GE2 is a second potential, thereby disconnecting the second driving unit 041 from the pixels 02.

[0127] Optionally, the display panel described in the embodiments of the present disclosure may include the LTPO display panel described in the above embodiments. For example, taking the LTPO display panel as an example, FIG9 shows a schematic structural diagram of a pixel included therein. As shown in FIG9 , pixel 02 may include pixel circuit 021 and light-emitting element L1. Furthermore, pixel circuit 021 may have an 8T1C structure, i.e., include eight transistors T1 to T8 and one capacitor C1.

[0128] The gate of transistor T1 can be coupled to the reset terminal N-Reset, the first electrode of transistor T1 can be coupled to the first initial terminal Vinit1, and the second electrode of transistor T1 can be coupled to node N3. Transistor T1 can be configured to turn on when the potential of the reset signal provided by the reset terminal N-Reset is a first potential, thereby connecting the first initial terminal Vinit1 to node N3, thereby allowing the first initial signal provided by the first initial terminal Vinit1 to be transmitted to node N3, thereby resetting node N3. Furthermore, transistor T1 can be configured to turn off when the potential of the reset signal provided by the reset terminal N-Reset is a second potential, thereby disconnecting the first initial terminal Vinit1 from node N3.

[0129] The gate of transistor T2 can be coupled to the gate signal terminal Gate_N, the first electrode of transistor T2 can be coupled to node N3, and the second electrode of transistor T2 can be coupled to node N1. Transistor T2 can be configured to turn on when the potential of the gate drive signal provided by the gate signal terminal Gate_N is a first potential, thereby connecting node N1 to node N3. Furthermore, transistor T2 can be configured to turn off when the potential of the gate drive signal provided by the gate signal terminal Gate_N is a second potential, thereby disconnecting node N1 from node N3.

[0130] The gate of transistor T3 may be coupled to node N1, the first electrode of transistor T3 may be coupled to node N2, and the second electrode of transistor T1 may be coupled to node N3. Transistor T3 may be configured to transmit a light-emitting drive signal to node N3 based on the potential of node N1 and the potential of node N2. Transistor T3 may also be referred to as a drive transistor.

[0131] The gate of transistor T4 can be coupled to the gate signal terminal Gate_P, the first electrode of transistor T4 can be coupled to the data signal terminal Vdata, and the second electrode of transistor T4 can be coupled to node N2. Transistor T4 can be configured to turn on when the potential of the gate drive signal provided by the gate signal terminal Gate_P is a first potential, so that the data signal terminal Vdata is conductively connected to node N2, thereby allowing the data signal provided by the data signal terminal Vdata to be transmitted to node N2. On the basis that both transistor T2 and transistor T3 are conductive, the data signal transmitted to node N2 can be further written to node N1 via transistor T3 and transistor T2. Furthermore, transistor T4 can be configured to turn off when the potential of the gate drive signal provided by the gate signal terminal Gate_P is a second potential, so that the data signal terminal Vdata is disconnected from node N2.

[0132] The gate of the transistor T5 can be coupled to the emission control terminal EM, the first electrode of the transistor T5 can be coupled to the driving power supply terminal VDD, and the second electrode of the transistor T5 can be coupled to the node N2. The transistor T5 can be configured to turn on when the potential of the emission control signal provided by the emission control terminal EM is a first potential, thereby connecting the driving power supply terminal VDD to the node N2, thereby allowing the driving power signal provided by the driving power supply terminal VDD to be transmitted to the node N2. Furthermore, the transistor T5 can be configured to turn off when the potential of the emission control signal provided by the emission control terminal EM is a second potential, thereby disconnecting the driving power supply terminal VDD from the node N2.

[0133] The gate of transistor T6 can be coupled to the light-emission control terminal EM, the first electrode of transistor T6 can be coupled to node N3, and the second electrode of transistor T6 can be coupled to the first electrode of light-emitting element L1. Transistor T6 can be configured to turn on when the potential of the light-emission control signal provided by the light-emission control terminal EM is at a first potential, thereby conducting between node N3 and the first electrode of light-emitting element L1, thereby enabling a signal (e.g., a light-emitting drive signal) transmitted to node N3 to be transmitted to the first electrode of light-emitting element L1. Furthermore, transistor T6 can be configured to turn off when the potential of the light-emission control signal provided by the light-emission control terminal EM is at a second potential, thereby decoupling node N3 from the first electrode of light-emitting element L1. Furthermore, the second electrode of light-emitting element L1 can be coupled to a pull-down power supply terminal VSS. Light-emitting element L1 can emit light in response to a voltage difference between a signal received by the first electrode of transistor T6 and a pull-down power supply signal provided by the pull-down power supply terminal VSS to which the second electrode is coupled.

[0134] Optionally, one of the first electrode and the second electrode of the light emitting element L1 may be an anode and the other may be a cathode. For example, in reference 9 , the first electrode is an anode and the second electrode is a cathode.

[0135] The gate of transistor T7 can be coupled to the reset terminal P-Reset, the first electrode of transistor T7 can be coupled to the second initial terminal Vinit2, and the second electrode of transistor T7 can be coupled to the first electrode of light-emitting element L1. Transistor T7 can be configured to turn on when the potential of the reset signal provided by the reset terminal P-Reset is a first potential, thereby connecting the second initial terminal Vinit2 to the first electrode of light-emitting element L1, thereby allowing the second initial signal provided by the second initial terminal Vinit2 to be transmitted to the first electrode of light-emitting element L1, thereby resetting the first electrode of light-emitting element L1. Furthermore, transistor T7 can be configured to turn off when the potential of the reset signal provided by the reset terminal P-Reset is a second potential, thereby disconnecting the second initial terminal Vinit2 from the first electrode of light-emitting element L1.

[0136] The gate of transistor T8 can be coupled to the reset terminal H-Reset, the first electrode of transistor T8 can be coupled to the third initial terminal Vinit3, and the second electrode of transistor T8 can be coupled to node N2. Transistor T8 can be configured to turn on when the potential of the reset signal provided by the reset terminal H-Reset is a first potential, thereby connecting the third initial terminal Vinit3 to the node N2, thereby allowing the third initial signal provided by the third initial terminal Vinit3 to be transmitted to the node N2, thereby resetting the node N2. Furthermore, transistor T8 can be configured to turn off when the potential of the reset signal provided by the reset terminal H-Reset is a second potential, thereby disconnecting the third initial terminal Vinit3 from the node N2.

[0137] One end of the capacitor C1 may be coupled to the node N1 , and the other end of the capacitor C1 may be coupled to the driving power supply terminal VDD. The capacitor C1 may be used to store the potential of the node N1 based on a driving power signal provided by the driving power supply terminal VDD.

[0138] Furthermore, the transistor T2 coupled to the gate signal terminal Gate_N can be an N-type transistor made of an oxide material; the transistor T4 coupled to the gate signal terminal Gate_P can be a P-type transistor made of low-temperature polysilicon (LTPS). Thus, the display panel is called an LTPO panel. It should be noted that the transistor material here can refer to the material of the active layer included in the transistor.

[0139] In addition, in conjunction with Figures 3 and 4 above, the first drive line G1 and the second drive line G2 can both be coupled to the gate signal terminal Gate_N coupled to the transistor T2 included in the pixel circuit 021 in the pixel 02. Accordingly, the first turn-on line STV1 and the second turn-on line STV2 can both be labeled NSTV. Here, N represents an N-type transistor, which correspondingly represents an embodiment in which the first potential is a high potential and the second potential is a low potential. Of course, in some embodiments, it is not limited to coupling the gate signal terminal Gate_N. For example, the first drive line G1 and the second drive line G2 can also be coupled to the gate signal terminal Gate_P coupled to the transistor T4 included in the pixel circuit 02. That is, the first drive unit 031 and the second drive unit 041 can only act on the transistor T2, or can act on both the transistor T2 and the transistor T4. In addition, the data line S1 can both be coupled to the data signal terminal Vdata coupled to the transistor T4 included in the pixel circuit 021 in the pixel 02.

[0140] It should be noted that the pixel circuit 021 is not limited to the 8T1C structure shown in Figure 9. For example, in some other embodiments, the pixel circuit 021 may not include the transistor T8 and may be a 7T1C structure.

[0141] In summary, embodiments of the present disclosure provide a display panel. The display panel includes a substrate having a display area and a peripheral area, a plurality of pixels located in the display area, and a first drive circuit and a second drive circuit located in the peripheral area. The first drive circuit includes a plurality of first drive units and a plurality of first gating units in a one-to-one correspondence. The second drive circuit includes a plurality of second drive units and a plurality of second gating units in a one-to-one correspondence. The plurality of first drive units are cascaded and coupled to a first enable line, and are also coupled to a portion of pixels in a row of pixels through corresponding first gating units. The plurality of second drive units are cascaded and coupled to a second enable line, and are also coupled to another portion of pixels in the row of pixels through corresponding second gating units. The first gating units are also coupled to a first enable line. The second gating units are also coupled to a second enable line. The plurality of first drive units are capable of outputting a first gate drive signal based on a first enable signal provided by the first enable line. The plurality of second drive units are capable of outputting a second gate drive signal based on a second enable signal provided by the second enable line. The first gating units are capable of controlling the switching of the corresponding first drive units and a portion of pixels based on a first enable signal provided by the first enable line. The second gating unit can control the switching of the corresponding second driving unit and another portion of pixels based on the second enable signal provided by the second enable line. This allows flexible setting of the enable and turn-on signals to achieve flexible refresh of pixels in different areas of the display, such as the top, bottom, left, or right. Furthermore, different refresh rates can be set for different areas, enabling zone-specific frequency conversion, thereby reducing power consumption and achieving intelligent power saving.

[0142] FIG10 is a flow chart of a display control method provided by an embodiment of the present disclosure, which can be used to control the display panel described in the above embodiment. As shown in FIG10 , the method includes:

[0143] Step 1001: Determine refresh requirements of different areas in a display area of ​​a substrate.

[0144] Among them, in the embodiment of the present disclosure, different areas may include a left area and a right area arranged along the pixel row direction X1, and / or, an upper area and a lower area arranged along the pixel column direction Y1, and the refresh requirement can be used to indicate whether a refresh is required and the refresh frequency. For example, in conjunction with Figure 7, the left area may refer to the left display area A11, and the right area may refer to the right display area A12. Furthermore, the upper area may refer to the upper display areas A11-1 and A12-1, and the lower area may refer to the lower display areas A11-2 and A12-2.

[0145] Optionally, the display control method described in the embodiments of the present disclosure may be applied to a driver chip included in a display device, also known as a driver integrated circuit (DIC).

[0146] The DIC can be coupled to a host access point (AP). The DIC can directly determine refresh requirements, i.e., determine the positions of the left and right refresh zones and the top and bottom refresh zones of the display area. Alternatively, the DIC can receive data signals from the AP and determine refresh requirements by comparing the real-time data signals received with the data signals of the previous frame.

[0147] Step 1002 : In response to a frame synchronization signal, transmit a first enable signal to first enable lines coupled to a plurality of first gating units based on a refresh requirement, and transmit a second enable signal to second enable lines coupled to a plurality of second gating units.

[0148] In which, the first enable signal of the first potential can be used to instruct the first selection unit to control the corresponding first driving unit and a part of the coupled pixels to be turned on; the first enable signal of the second potential can be used to instruct the first selection unit to control the corresponding first driving unit and a part of the coupled pixels to be disconnected.

[0149] Similarly, the second enable signal of the first potential can be used to instruct the second selection unit to control the corresponding second driving unit to be turned on with another part of the coupled pixels; the second enable signal of the second potential can be used to instruct the second selection unit to control the corresponding second driving unit to be disconnected with another part of the coupled pixels.

[0150] Optionally, after determining the refresh requirement, the DIC can further respond to the frame synchronization signal Vsync to generate a first enable signal and a second enable signal based on the refresh requirement, and output them to the first enable line GE1 and the second enable line GE2, respectively. The frame synchronization signal Vsync is used to indicate the start of a frame scan.

[0151] Step 1003 : In response to the frame synchronization signal, transmit a first start signal to first start lines coupled to the plurality of first driving units, and transmit a second start signal to second start lines coupled to the plurality of second driving units.

[0152] The first start-up signal may be used to instruct the plurality of first driving units to output the first gate driving signal, and the second start-up signal may be used to instruct the plurality of second driving units to output the second gate driving signal.

[0153] Optionally, the DIC may further generate a first start signal and a second start signal in response to the frame synchronization signal Vsync, and transmit the first start signal and the second start signal to the first start line STV1 and the second start line STV2 respectively.

[0154] In the embodiment of the present disclosure, when the first gating unit controls the first driving unit to be turned on with a portion of the coupled pixels, the first driving unit can transmit a first gate driving signal to the portion of the pixels to drive the portion of the pixels to emit light. When the second gating unit controls the second driving unit to be turned on with another portion of the coupled pixels, the second driving unit can transmit a second gate driving signal to the other portion of the pixels to drive the other portion of the pixels to emit light.

[0155] Alternatively, taking the case where the first potential is a high potential and the second potential is a low potential, FIG11 shows a timing diagram based on the structures shown in FIG1 and FIG3 , and FIG12 shows another timing diagram based on the structures shown in FIG2 and FIG4 . Referring to FIG11 and FIG12 , it can be seen that after the frame synchronization signal Vsync arrives, the first enable signal provided by the first enable line GE1 can be pulled low or high starting in any row, and the second enable signal provided by the second enable line GE2 can be pulled low or high starting in any row.

[0156] Specifically, when the first enable signal is pulled high, that is, when the potential of the first enable signal is high, the first gating unit 032 can control the first driving unit 031 to be connected to a portion of the pixels 02 coupled thereto based on the high-potential first enable signal, so that the first driving unit 031 transmits the first gate driving signal to the portion of the pixels 02, thereby achieving refresh scanning of the portion of the pixels 02. When the first enable signal is pulled low, that is, when the potential of the first enable signal is low, the first gating unit 032 can control the first driving unit 031 to be disconnected from the portion of the pixels 02 coupled thereto based on the high-potential first enable signal, so that the first driving unit 031 cannot transmit the first gate driving signal to the portion of the pixels 02, thereby not performing refresh scanning on the portion of the pixels 02, and the portion of the pixels 02 can remain in the state of the most recent frame.

[0157] The same applies to the second enable signal. When the second enable signal is pulled high, that is, when the potential of the second enable signal is high, the second selection unit 042 can control the second driving unit 041 to be connected to another portion of the pixels 02 coupled thereto based on the high-potential second enable signal, so that the second driving unit 041 transmits the first gate driving signal to the another portion of the pixels 02, thereby achieving refresh scanning of the another portion of the pixels 02. When the second enable signal is pulled low, that is, when the potential of the second enable signal is low, the second selection unit 042 can control the second driving unit 041 to be disconnected from the another portion of the pixels 02 coupled thereto based on the high-potential second enable signal, so that the second driving unit 041 cannot transmit the first gate driving signal to the another portion of the pixels 02, thereby not refreshing and scanning the another portion of the pixels 02, and the another portion of the pixels 02 can remain in the state of the most recent frame.

[0158] Therefore, by flexibly setting the first enable signal and the second enable signal, intelligent refresh of different areas of the display area, such as the upper, lower, left and right areas, can be achieved, thereby realizing frequency division driving.

[0159] In summary, an embodiment of the present disclosure provides a display control method. In this method, a plurality of first drive units can output a first gate drive signal based on a first turn-on signal provided by a first turn-on line. A plurality of second drive units can output a second gate drive signal based on a second turn-on signal provided by a second turn-on line. The first gating unit can control the on-off of the corresponding first drive unit and a portion of pixels based on the first enable signal provided by the first enable line. The second gating unit can control the on-off of the corresponding second drive unit and another portion of pixels based on the second enable signal provided by the second enable line. In this way, by flexibly setting the enable signal and the turn-on signal, it is possible to achieve flexible refresh of pixels in different areas of the upper, lower, left or right of the display area, and the refresh rate for different areas can be different, that is, partition frequency conversion can be achieved, thereby reducing power consumption and achieving the purpose of intelligent power saving.

[0160] FIG13 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. As shown in FIG13 , the display device includes: a driver chip DIC and a display panel 00 as described in the above embodiment.

[0161] The driving chip DIC is coupled to the signal lines coupled to the circuits in the display panel 00 and is used to provide signals to the signal lines.

[0162] For example, the driver chip DIC can be coupled to a first start line STV1 coupled to a first driver unit 031 included in a first driver circuit 03, a first enable line GE1 coupled to a first selection unit 032 included in the first driver circuit 03, a second start line STV2 coupled to a second driver unit 041 included in a second driver circuit 04, and a second enable line GE2 coupled to a second selection unit 042 included in the second driver circuit 04 in the display panel 00. The driver chip DIC is configured to provide a first start signal to the first start line STV1, a second start signal to the second start line STV2, a first enable signal to the first enable line GE1, and a second enable signal to the second enable line GE2.

[0163] Optionally, the display device described in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone (e.g., a foldable mobile phone capable of left-right split-screen operation), a tablet computer, a flexible display device, a television, or a monitor. Taking a mobile phone as an example, the solution described in the embodiments of the present disclosure can also achieve a left-right split-screen design when the mobile phone is rotated, providing high driving flexibility.

[0164] It should be noted that the terms used in the embodiments of the present disclosure are intended to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0165] For example, in the embodiments of the present disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0166] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0167] "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0168] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0169] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0170] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display panel, comprising: a substrate having a display area and a peripheral area at least partially surrounding the display area; A plurality of pixels arranged in an array are located in the display area; A first driving circuit is located in the peripheral area, and the first driving circuit includes: a plurality of first driving units connected in cascade, and a plurality of first gating units corresponding to the plurality of first driving units one by one; A second driving circuit is located in the peripheral area, the second driving circuit comprising: a plurality of second driving units connected in cascade, and a plurality of second gating units corresponding to the plurality of second driving units one by one; Wherein, at least one first driving unit and at least one second driving unit are respectively located on both sides of the substrate in the pixel row direction, each first gating unit and the corresponding first driving unit are located on the same side of the substrate, and each second gating unit and the corresponding second driving unit are located on the same side of the substrate; Furthermore, each first driving unit is coupled to a portion of pixels in at least one row of pixels through a corresponding first gating unit; the first gating unit is also coupled to a first enable line, and is used to control the on and off of the first driving unit and the portion of pixels based on a first enable signal provided by the first enable line; the plurality of first driving units are also coupled to a first enable line, and are used to output a first gate driving signal based on a first enable signal provided by the first enable line; Each second driving unit is coupled to another part of the pixels in the at least one row of pixels through a corresponding second gating unit; the second gating unit is also coupled to a second enable line, and is used to control the on and off of the second driving unit and the another part of the pixels based on a second enable signal provided by the second enable line; the multiple second driving units are also coupled to a second start-up line, and are used to output a second gate driving signal based on a second start-up signal provided by the second start-up line.

2. The display panel according to claim 1, wherein: The plurality of first driving units are all located on a first side of the two sides; and the plurality of second driving units are all located on a second side of the two sides.

3. The display panel according to claim 1, wherein: Among the plurality of first drive units, a portion of the first drive units are located on a first side of the two sides, and the remaining first drive units except the portion of the first drive units are located on a second side of the two sides; Among the plurality of second drive units, a portion of the second drive units are located on a first side of the two sides, The remaining second driving units except for the part of the second driving units are located on the second side of the two sides.

4. The display panel according to claim 3, wherein: Each first driving unit is coupled to a portion of pixels in a row of pixels through a corresponding first gating unit; Among the plurality of first driving units, each first driving unit coupled to the pixels in even rows is located at the first side, and each first driving unit coupled to the pixels in odd rows is located at the second side.

5. The display panel according to claim 3 or 4, wherein: Each second driving unit is coupled to another part of pixels in a row of pixels through a corresponding second gating unit; Among the plurality of second driving units, each second driving unit coupled to the pixels in even rows is located at the first side, and each second driving unit coupled to the pixels in odd rows is located at the second side.

6. The display panel according to claim 5, wherein: The first driving units and the second driving units located on the first side are arranged in sequence in the direction of the pixel columns in the order of one first driving unit and one second driving unit; The first driving units and the second driving units located on the second side are arranged in sequence in the direction of the pixel columns in the order of one second driving unit and one first driving unit.

7. The display panel according to any one of claims 1 to 6, wherein: Each first driving unit is coupled to a first driving line through a corresponding first gating unit, and the first driving line is coupled to the part of pixels; each second driving unit is coupled to a second driving line through a corresponding second gating unit, and the second driving line is coupled to the other part of pixels; and the plurality of first driving units are cascaded through the first driving line; The plurality of second driving units are cascade-connected through the second driving line.

8. The display panel according to claim 7, wherein: When the plurality of first driving units are all located on a first side of the two sides, and the plurality of second driving units are all located on a second side of the two sides, the first driving line and the second driving line are independent of each other.

9. The display panel according to claim 7, wherein: When, among the plurality of first drive units, a portion of the first drive units are located on the first side of the two sides, and the remaining first drive units except the portion of the first drive units are located on the second side of the two sides; and when, among the plurality of second drive units, a portion of the second drive units are located on the first side of the two sides, and the remaining second drive units except the portion of the second drive units are located on the second side of the two sides: In addition to being coupled to the pixels, the first driving line also runs through the display area and cascades the first driving unit located on the first side and the first driving unit located on the second side; In addition to being coupled to the pixels, the second driving line also runs through the display area and cascades the second driving unit located on the first side and the second driving unit located on the second side; Furthermore, the first driving line and the second driving line coupled to the same row of pixels overlap in the display area.

10. The display panel according to claim 9, wherein: The portion of the first driving line used for coupling the pixel and the portion used for cascading the first driving unit are located in different layers; the portion of the second driving line used for coupling the pixel and the portion used for cascading the second driving unit are located in different layers; Furthermore, overlapping portions of the first driving line and the second driving line are located in different layers.

11. The display panel according to claim 10, wherein: The pixel comprises: a gate metal layer, an insulating layer and a source-drain metal layer which are located on one side of the substrate and are stacked in sequence; Among them, in the first driving line, a portion for coupling pixels and the gate metal layer are located in the same layer, a portion for cascading the first driving unit and the source-drain metal layer are located in the same layer, and the portion for coupling pixels and the portion for cascading the first driving unit are switched through a via hole penetrating the insulating layer; In the second driving line, the portion for coupling pixels is located in the same layer as the gate metal layer, the portion for cascading the second driving unit is located in the same layer as the source and drain metal layer, and the portion for coupling pixels and the portion for cascading the second driving unit are switched through vias passing through the insulating layer.

12. The display panel according to any one of claims 1 to 11, wherein: The substrate comprises: A left display area and a right display area arranged along the pixel row direction from the first column of pixels to the last column of pixels, the left display area including the part of pixels, and the right display area including the other part of pixels; An upper display area and a lower display area are arranged along the pixel column direction from the first row of pixels to the last row of pixels, and each of the upper display area and the lower display area includes at least one row of pixels.

13. The display panel according to claim 12, wherein: The refresh rate of the upper display area is greater than or equal to the refresh rate of the lower display area.

14. The display panel according to claim 12, wherein: The left display area and the right display area have the same area and include the same number of pixels; And / or, the upper display area and the lower display area have the same area and include the same number of pixels.

15. The display panel according to any one of claims 1 to 14, wherein: Among the plurality of first gating units and the plurality of second gating units, the gating units located at the same side of the substrate share a same enable line.

16. The display panel according to any one of claims 1 to 15, wherein: The first gating unit includes: a first gating switch tube; the second gating unit includes: a second gating switch tube; The gate of the first gate switch tube is coupled to the first enable line, the first electrode of the first gate switch tube is coupled to the corresponding first driving unit, and the second electrode of the first gate switch tube is coupled to the part of pixels; The gate of the second gate switch tube is coupled to the second enable line, the first electrode of the second gate switch tube is coupled to the corresponding second driving unit, and the second electrode of the second gate switch tube is coupled to the other part of pixels.

17. The display panel according to any one of claims 1 to 16, wherein: Each first driving unit is coupled to a portion of pixels in at least one row of pixels, close to the first gating unit, through a corresponding first gating unit; each second driving unit is coupled to another portion of pixels in at least one row of pixels, close to the second gating unit, through a corresponding second gating unit; and the pixels in the portion of pixels are adjacent to each other, and the pixels in the other portion of pixels are adjacent to each other.

18. The display panel according to any one of claims 1 to 17, wherein: The display panel includes: a low temperature polycrystalline silicon oxide (LTPO) display panel.

19. A display control method, for controlling the display panel according to any one of claims 1 to 18; the method comprising: Determining refresh requirements of different areas in a display area of ​​a substrate, the different areas including a left area and a right area arranged along a pixel row direction, and / or an upper area and a lower area arranged along a pixel column direction, the refresh requirements being used to indicate whether refresh is required and a refresh frequency; In response to the frame synchronization signal, based on the refresh requirement, transmitting a first enable signal to a first enable line coupled to the plurality of first gating units, and transmitting a second enable signal to a second enable line coupled to the plurality of second gating units; The first enable signal of the first potential is used to instruct the first gating unit to control the corresponding first driving unit to be turned on with a part of the coupled pixels, and the first enable signal of the second potential is used to instruct the first gating unit to control the corresponding first driving unit to be disconnected from a part of the coupled pixels; the second enable signal of the first potential is used to instruct the second gating unit to control the corresponding second driving unit to be turned on with another part of the coupled pixels, and the second enable signal of the second potential is used to instruct the second gating unit to control the corresponding second driving unit to be disconnected from another part of the coupled pixels; In response to the frame synchronization signal, a first start signal is transmitted to a first start line coupled to the plurality of first driving units, and a second start signal is transmitted to a second start line coupled to the plurality of second driving units; the first start signal is used to instruct the plurality of first driving units to output a first gate driving signal, and the second start signal is used to instruct the plurality of second driving units to output a second gate driving signal; When the first gating unit controls the first driving unit and a part of the coupled pixels to be turned on, the first driving unit transmits the first gate driving signal to the part of the pixels; When the second gating unit controls the second driving unit and another part of the coupled pixels to be turned on, the second driving unit transmits the second gate driving signal to the another part of the pixels.

20. A display device, comprising: A driving chip, and a display panel as claimed in any one of claims 1 to 18; The driving chip is coupled to a signal line coupled to a circuit in the display panel and is used to provide a signal to the signal line.

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