Semiconductor device, electronic device, and manufacturing method

Abstract

The present disclosure relates to: a semiconductor device in which leakage and shrinkage of an exclusion region can be reduced; an electronic device; and a manufacturing method. A semiconductor device according to the present disclosure is provided with: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip and provided with a PN junction portion in a depth direction by forming an N-type well in a surface of a P-type substrate or by forming a P-type well in a surface of an N-type substrate; and a through electrode disposed in a through hole penetrating the substrate. The through electrode is disposed by arranging a thermal oxide film or a ferroelectric film having insulating properties with respect to at least the PN junction portion along the inner wall surface of the through hole. The present technology can be applied, for example, to a stacked CMOS image sensor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, an electronic apparatus and a manufacturing method, and particularly to a semiconductor device, an electronic apparatus and a manufacturing method capable of reducing leakage and narrowing a forbidden zone. Background Art

[0002] In recent years, in various semiconductor devices, the development of three-dimensional stacking technology to achieve higher functions by increasing the scale of circuits installed in one chip has been actively promoted. For example, a stacked complementary metal oxide semiconductor (CMOS) image sensor has been developed in which a sensor chip, a memory chip, and a logic chip are stacked by using three-dimensional stacking technologies such as bumps, through silicon vias (TSVs), and Cu-Cu bonding. In addition, a wafer-on-wafer (WoW) structure in which a semiconductor wafer is bonded to another semiconductor wafer using TSVs, a chip-on-wafer (CoW) structure in which a semiconductor wafer is bonded to a semiconductor chip using TSVs, and the like have been proposed.

[0003] In this way, in a semiconductor device in which two or more layers are multilayered by using a three-dimensional stacking technology, since the front surface side and the rear surface side of a chip are connected, it is considered to use TSV penetrating a semiconductor substrate and to use miniaturized TSV (n-TSV).

[0004] In addition, in a normal semiconductor device, the front surface is covered with an N-type or P-type semiconductor (diffusion layer, well, etc.), and a PN junction is formed in the depth direction from the surface, such as a PN junction between an N-type diffusion layer and a P-type well or a PN junction between a P-type diffusion layer and an N-type well.

[0005] For example, as disclosed in Patent Document 1, in the case of using a large number of miniaturized TSVs in a semiconductor device having a three-dimensional stacked structure, a design is made in a layout in which the miniaturized TSVs penetrate (vertically) a semiconductor substrate forming a PN junction in a depth direction.

[0006] Reference List

[0007] Patent Literature

[0008] Patent Document 1: International Patent Publication No. 2019 / 087764 Summary of the invention

[0009] Problems to be solved by the present invention

[0010] In addition, it is known that defects are generated on the semiconductor substrate by plasma etching in the processing of TSV holes. Therefore, in the case where the depletion layer formed in the PN junction in the semiconductor substrate around the TSV contacts the TSV, the leakage current increases through the defects generated during the processing. For example, this leakage can be reduced by providing a forbidden zone (KoZ) that separates the TSV from the depletion layer caused by the PN junction. However, in the future, when miniaturized TSVs are used in large quantities and designs are made in the layout of connecting chips at arbitrary positions, it is necessary to consider setting a forbidden zone as a constraint. Therefore, it is necessary to reduce leakage and shrink the forbidden zone.

[0011] The present disclosure has been made in view of such circumstances, and makes it possible to reduce leakage and shrink the exclusion area.

[0012] Solution to the problem

[0013] According to one aspect of the present disclosure, a semiconductor device includes: a first semiconductor chip; a second semiconductor chip, which is stacked on the first semiconductor chip and has a PN junction portion in a depth direction by forming an N-type well on the front surface of a P-type substrate or forming a P-type well on the front surface of an N-type substrate; and a through-electrode, which is arranged in a through hole penetrating the substrate, wherein the through-electrode is configured so that a first insulating film having insulating properties at least for the PN junction portion is arranged along the inner wall surface of the through hole.

[0014] According to one aspect of the present disclosure, an electronic device includes a semiconductor device, which includes a first semiconductor chip; a second semiconductor chip, which is stacked on the first semiconductor chip and has a PN junction portion in a depth direction by forming an N-type well on the front surface of a P-type substrate or forming a P-type well on the front surface of an N-type substrate; and a through-electrode, which is arranged in a through hole penetrating the substrate, wherein the through-electrode is configured so that a first insulating film that has insulating properties at least for the PN junction portion is arranged along the inner wall surface of the through hole.

[0015] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device includes: forming a through hole penetrating a substrate of a second semiconductor chip stacked on a first semiconductor chip, wherein the second semiconductor chip is provided with a PN junction portion in a depth direction by forming an N-type well on a front surface of a P-type substrate or forming a P-type well on a front surface of an N-type substrate; and forming a through electrode, wherein the through electrode has a configuration in which a first insulating film having insulating properties at least for the PN junction portion is provided along an inner wall surface of the through hole.

[0016] In one aspect of the present disclosure, a through hole and a through electrode are formed by forming an N-type well on the front surface of a P-type substrate or a P-type well on the front surface of an N-type substrate, the through hole penetrates the substrate of a second semiconductor chip stacked on a first semiconductor chip and is provided with a PN junction portion in a depth direction, and the through electrode has a configuration in which a first insulating film having at least insulating properties for the PN junction portion is provided along the inner wall surface of the through hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 : is a diagram showing a configuration example of a first embodiment of a through-electrode of a semiconductor device to which the present technology is applied.

[0018] Figure 2 It is a diagram for describing a step of forming a through electrode.

[0019] Figure 3 : is a diagram showing a modification example of the through electrode.

[0020] Figure 4 is a cross-sectional view showing a first configuration example of a semiconductor device.

[0021] Figure 5 is a cross-sectional view showing a second configuration example of the semiconductor device.

[0022] Figure 6 is a cross-sectional view showing a third configuration example of the semiconductor device.

[0023] Figure 7 is a cross-sectional view showing a fourth configuration example of the semiconductor device.

[0024] Figure 8 is a cross-sectional view showing a fifth configuration example of the semiconductor device.

[0025] Fig. 9 is a cross-sectional view showing a sixth configuration example of the semiconductor device.

[0026] Fig.10 is a cross-sectional view showing a seventh configuration example of the semiconductor device.

[0027] Fig.11 is a cross-sectional view showing an eighth configuration example of the semiconductor device.

[0028] Fig.12 is a cross-sectional view showing a ninth configuration example of the semiconductor device.

[0029] Fig.13 It is a diagram for explaining a method for manufacturing a semiconductor device.

[0030] Fig.14 The diagrams illustrate a method for manufacturing a semiconductor device.

[0031] Fig.15 It is a diagram for explaining a method for manufacturing a semiconductor device.

[0032] Fig.16 It is a diagram showing a configuration example of a second embodiment of a through-electrode of a semiconductor device to which the present technology is applied.

[0033] Fig.17 It is a diagram for describing a step of forming a through electrode.

[0034] Fig.18 : is a diagram showing a modification example of the through electrode.

[0035] Fig.19 is a cross-sectional view showing a tenth configuration example of the semiconductor device.

[0036] Fig. 20 is a cross-sectional view showing an eleventh configuration example of the semiconductor device.

[0037] Fig.21 is a cross-sectional view showing a twelfth configuration example of the semiconductor device.

[0038] Fig. 22 is a cross-sectional view showing a thirteenth configuration example of the semiconductor device.

[0039] Fig.23 is a cross-sectional view showing a fourteenth configuration example of the semiconductor device.

[0040] Fig.24 is a cross-sectional view showing a fifteenth configuration example of the semiconductor device.

[0041] Fig.25 is a cross-sectional view showing a sixteenth configuration example of the semiconductor device.

[0042] Fig.26 is a cross-sectional view showing a seventeenth configuration example of the semiconductor device.

[0043] Fig. 27 is a cross-sectional view showing an eighteenth configuration example of the semiconductor device.

[0044] Fig.28 It is a diagram for explaining a method for manufacturing a semiconductor device.

[0045] Fig.29 The diagrams illustrate a method for manufacturing a semiconductor device.

[0046] Fig.30 It is a diagram for explaining a method for manufacturing a semiconductor device.

[0047] Fig.31The diagrams illustrate a method for manufacturing a semiconductor device.

[0048] Fig.32 is a block diagram showing a configuration example of an imaging device.

[0049] Fig.33 is a diagram showing a usage example using an image sensor. DETAILED DESCRIPTION

[0050] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the accompanying drawings.

[0051] <First Configuration Example of Through Electrodes>

[0052] Figure 1 : is a diagram showing a configuration example of a through electrode according to a first embodiment used in a semiconductor device to which the present technology is applied.

[0053] like Figure 1 As shown, the through electrode 11 is provided to penetrate the semiconductor layer 21 .

[0054] The wiring layer 22 is stacked on the front surface of the semiconductor layer 21, and the metal line 23 is provided in the wiring layer 22. The insulating film 24 is stacked on the back surface of the semiconductor layer 21. The semiconductor layer 21 is configured such that the deep N well layer 32 and the N well layer 33 are formed on the P substrate 31, which is a P-type silicon substrate, so that the depletion layer 34 is provided at the PN junction portion where the P substrate 31 and the deep N well layer 32 are combined in the depth direction.

[0055] The through electrode 11 is formed by stacking a ferroelectric film 41, an insulating film 42, and a barrier metal 43 along the inner wall surface of a TSV hole formed in a manner of penetrating the semiconductor layer 21 from the back side of the semiconductor layer 21 to the wiring 23, and then embedding a conductor 44. That is, the through electrode 11 penetrates the semiconductor layer 21, and is formed so that at least one end of the through electrode 11 is connected to an internal circuit (for example, Figure 4 Wiring 23 which is a part of the logic circuit of the logic chip 112).

[0056] The ferroelectric film 41 is a structure including a ferroelectric and having a negative or positive fixed charge, is a spontaneously polarized charged film, and forms a hole accumulation layer. As shown in the figure, on the inner wall surface of the TSV hole, the ferroelectric film 41 is stacked outside the surface of the semiconductor layer 21, and the ferroelectric film 41 has a length that at least covers the depletion layer 34 on the PN junction. For example, the ferroelectric film 41 includes BaTiO3 (barium titanate), Pb(Zr,Ti)O3, BiFeO3, SrBi2Ta2O9, (Bi,La)4Ti3O12, etc. as perovskite-type oxides. Alternatively, the ferroelectric film 41 may include a high-k ferroelectric (for example, FE-HfO2, Zr, etc.). In addition, the ferroelectric film 41 is composed of a single layer or a multilayer.

[0057] The insulating film 42 is stacked on the ferroelectric film 41 and is, for example, a film containing oxygen such as a SiO2 film or a SiON film. The insulating film 42 is formed simultaneously with the insulating film 24.

[0058] The barrier metal 43 is, for example, a metal film for preventing metal atoms constituting the conductor 44 from diffusing into the insulating film 42 .

[0059] The conductor 44 is made of metal such as copper.

[0060] The through electrode 11 is configured in this manner, and the ferroelectric film 41 has insulating properties for the depletion layer 34 provided at least in the PN junction portion, and thus it is possible to reduce leakage in the depletion layer 34 caused by defects generated during the processing of the TSV hole. In addition, since the hole accumulation layer is formed by the ferroelectric film 41, it is possible to separate the depletion layer 34 from the peripheral portion of the through electrode 11, thereby being able to reduce the blocking area.

[0061] Therefore, by using the through-electrode 11 having such a configuration in a semiconductor device, low power consumption can be achieved while reducing leakage. In addition, for example, in a design using a large number of miniaturized through-electrodes 11, since the restricted area can be reduced, a layout that connects chips at any position (e.g., at a narrow pitch) can be provided.

[0062] Will refer to Figure 2 The step of forming the through-electrode 11 is described.

[0063] First, if Figure 2 As shown in the first part of FIG. 1 , a TSV hole 51 penetrating the semiconductor layer 21 is formed so that the wiring 23 opens from the back side of the semiconductor layer 21 .

[0064] Then, if Figure 2 As shown in the second part of FIG. 5 , the ferroelectric film 41 is formed on the inner wall surface of the TSV hole 51 .

[0065] Then, if Figure 2As shown in the third part of FIG. 4 , the insulating film 42 is formed to be stacked on the ferroelectric film 41, and the insulating film 24 is formed on the rear surface of the semiconductor layer 21. Furthermore, the barrier metal 43 is stacked on the insulating film 42 and the wiring 23.

[0066] Afterwards, if Figure 1 As shown, the conductor 44 is embedded in the TSV hole 51 to form the through electrode 11 .

[0067] Figure 3 2 is a diagram showing a modified example of the through-electrode 11 .

[0068] Figure 3 The through electrode 11a shown is formed by stacking an insulating film 45 of a different type from the insulating film 42 between the ferroelectric film 41 and the insulating film 42. That is, the through electrode 11a has a structure formed of two layers of the insulating film 42 and the insulating film 45. Of course, the through electrode 11a may also have a structure formed of a multilayer film of more than two layers.

[0069] <Configuration Example of Semiconductor Device>

[0070] Will refer to Figures 4 to 12 A semiconductor device using the through-electrode 11 is described.

[0071] Figure 4 is a cross-sectional view showing a first configuration example of a semiconductor device.

[0072] Figure 4 A semiconductor device 101 having a three-layer structure bonded with bonding surfaces indicated by a dot-dash line is shown. The semiconductor device 101 has a three-layer structure in which a sensor chip 111 is provided in a first layer, logic chips 112a and 112b are provided in a second layer, and a logic chip 113 is provided in a third layer, and has a configuration called a multi-chip. For example, the sensor chip 111 is an imaging element such as a CMOS image sensor, and the logic chips 112a and 112b and the logic chip 113 include a signal processing circuit (logic circuit, memory, etc.) for performing signal processing on an image captured by the sensor chip 111.

[0073] Then, the semiconductor device 101 is configured such that the through electrode 11 is provided to penetrate the semiconductor layer 21 of the logic chip 112b. Figure 1 As described, the semiconductor device 101 can reduce leakage in the depletion layer 34 of the PN junction portion and narrow the forbidden zone.

[0074] Note that Figures 5 to 12 In each configuration example shown, Figure 4 The same configurations as those of the semiconductor device 101 in FIG. 1 are given the same reference numerals, and a detailed description thereof will be omitted.

[0075] Figure 5 is a cross-sectional view showing a second configuration example of the semiconductor device.

[0076] Figure 5 A semiconductor device 101A having a three-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101A has a three-layer structure in which a sensor chip 111 is provided in a first layer, a logic chip 112A is provided in a second layer, and a logic chip 113A is provided in a third layer, and has a configuration called F2F in which the front surface side of the sensor chip 111 and the front surface side of the logic chip 112A are bonded.

[0077] Then, the semiconductor device 101A is configured so that the through electrode 11 is provided to penetrate the semiconductor layer 21 of the logic chip 112A. Therefore, the semiconductor device 101A can reduce the leakage in the depletion layer 34 of the PN junction part and narrow the forbidden area, as shown in FIG. Figure 1 described.

[0078] Figure 6 is a cross-sectional view showing a third configuration example of the semiconductor device.

[0079] Figure 6 A semiconductor device 101B having a three-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101B has a three-layer structure in which a sensor chip 111 is provided in a first layer, a logic chip 112B is provided in a second layer, and a logic chip 113B is provided in a third layer, and has a configuration called F2B in which the front surface side of the sensor chip 111 and the rear surface side of the logic chip 112B are bonded.

[0080] Then, the semiconductor device 101B is provided with the through electrode 11 so as to penetrate the semiconductor layer 21 of the logic chip 112B. Therefore, the semiconductor device 101B can reduce the leakage in the depletion layer 34 of the PN junction part and narrow the forbidden area, as shown in FIG. Figure 1 described.

[0081] Figure 7 is a cross-sectional view showing a fourth configuration example of the semiconductor device.

[0082] Figure 7 A semiconductor device 101C having a double-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101C has a double-layer structure in which a sensor chip 111 is provided in a first layer and a logic chip 112C is provided in a second layer, and has a configuration called a monolithic chip in which the logic chip 112C is provided in a wiring layer of a logic chip 114C.

[0083] Then, the semiconductor device 101C is configured such that the through electrode 11 is provided to penetrate the semiconductor layer 21 of the logic chip 114C. Therefore, the semiconductor device 101C can reduce the leakage in the depletion layer 34 of the PN junction part and narrow the forbidden area, as shown in FIG. Figure 1 described.

[0084] Figure 8 is a cross-sectional view showing a fifth configuration example of the semiconductor device.

[0085] Figure 8 A semiconductor device 101D having a double-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101D has a double-layer structure in which a sensor chip 111 is provided in a first layer and a logic chip 112D is provided in a second layer, and has a configuration called a backside bump in which a bump 121 is provided on the backside side of the logic chip 112D.

[0086] Then, the semiconductor device 101D is configured such that the through electrode 11 is provided as an electrode connected to the bump 121 inside the semiconductor layer 21 of the logic chip 112D and penetrates at least Figure 1 Therefore, the semiconductor device 101D can reduce the leakage in the depletion layer 34 of the PN junction and narrow the forbidden zone, as shown in FIG. Figure 1 described.

[0087] Fig. 9 is a cross-sectional view showing a sixth configuration example of the semiconductor device.

[0088] Fig. 9 A semiconductor device 101E having a three-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101E has a three-layer structure in which a memory chip 115E is provided in a first layer, a memory chip 116E is provided in a second layer, and a logic chip 113E is provided in a third layer, and has a configuration called multi-level memory / logic. Note that the semiconductor device 101E may be mounted on a supporting substrate (not shown) with a bump 121 provided on the back side of the logic chip 113E interposed therebetween. Of course, the semiconductor device 101E may have a layered structure of three or more layers.

[0089] Then, the semiconductor device 101E is configured such that the through electrode 11 is configured to pass through the semiconductor layer 21 of each of the memory chip 115E, the memory chip 116E, and the logic chip 113E and is connected to the bump 121. Therefore, the semiconductor device 101E can reduce the leakage in the depletion layer 34 of the PN junction part and narrow the forbidden area, as shown in FIG. Figure 1 described.

[0090] Fig.10is a cross-sectional view showing a seventh configuration example of the semiconductor device.

[0091] Fig.10 A semiconductor device 101F having a double-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101F has a double-layer structure in which a memory chip 115F is provided in a first layer and a logic chip 112F is provided in a second layer, and has a configuration in which a wiring 122 for power supply is provided in a wiring layer of the logic chip 112F.

[0092] Then, the semiconductor device 101F is configured such that the through electrode 11 is provided to penetrate the semiconductor layer 21 of the memory chip 115F. Furthermore, the semiconductor device 101F is configured such that the through electrode 11 is provided as an electrode connected to the wiring 122 inside the semiconductor layer 21 of the logic chip 112F and penetrates at least Figure 1 Therefore, the semiconductor device 101F can reduce the leakage in the depletion layer 34 of the PN junction and narrow the forbidden zone, as shown in FIG. Figure 1 described.

[0093] Fig.11 is a cross-sectional view showing an eighth configuration example of the semiconductor device.

[0094] Fig.11 A semiconductor device 101G having a single-layer structure is shown. The semiconductor device 101G has a so-called monolithic configuration in which a logic chip 112G is provided in a wiring layer of a logic chip 114G.

[0095] Then, the semiconductor device 101G is configured such that the through electrode 11 is provided to penetrate the semiconductor layer 21 of the logic chip 114G. Therefore, the semiconductor device 101G can reduce the leakage in the depletion layer 34 of the PN junction part and narrow the forbidden area, as shown in FIG. Figure 1 described.

[0096] Fig.12 is a cross-sectional view showing a ninth configuration example of the semiconductor device.

[0097] Fig.12 A semiconductor device 101H having a single-layer structure is shown. The semiconductor device 101H includes a logic chip 112H. Note that the semiconductor layer 21 of the logic chip 112H has a thickness of several μm or less.

[0098] Then, the semiconductor device 101H is configured such that the through electrode 11 is provided to penetrate the semiconductor layer 21 of the logic chip 112H, and the through electrode 11 is connected to the electrode connected to the bump 121. Therefore, the semiconductor device 101H can reduce the leakage in the depletion layer 34 of the PN junction part and narrow the forbidden area, as shown in FIG. Figure 1 described.

[0099] As described above, the through-electrode 11 to which the present technology is applied can be applied to imaging element chips such as the semiconductor devices 101 to 101D, signal processing chips such as the semiconductor devices 101E to 101H, and the like.

[0100] <Method for manufacturing semiconductor device>

[0101] Will refer to Figures 13 to 15 describe Figure 5 A method for manufacturing a semiconductor device 101A.

[0102] In the first step, if Fig.13 As shown in the upper part of the sensor chip 111 and the semiconductor layer 21 on which the wiring layer 22 is stacked is prepared by another process. Then, the layers are stacked by Cu-Cu bonding using the Cu pad 123 provided on the front surface side of the sensor chip 111 and the Cu pad 124 provided on the front surface side of the wiring layer 22.

[0103] In the second step, if Fig.13 As shown in the lower part of FIG. 2 , a TSV hole 51 penetrating the semiconductor layer 21 is formed so that the wiring 23 opens from the back side of the semiconductor layer 21 . Then, a ferroelectric film 41 is formed on the inner wall surface of the TSV hole 51 .

[0104] In the third step, if Fig.14 As shown in the upper part of FIG. 5 , the conductor 44 is embedded in the TSV hole 51 to form the through electrode 11. Note that although not shown, as described above with reference to FIG. Figure 2 As described above, before the conductor 44 is buried, the insulating film 42 and the barrier metal 43 are formed in the TSV hole 51 .

[0105] In the fourth step, if Fig.14 As shown in the lower part of FIG. 1 , an insulating film 24 is formed on the back surface of the semiconductor layer 21, and a Cu pad 125 is buried in a part of the insulating film 24 to be connected to the through electrode 11. In this way, the logic chip 112A is formed.

[0106] In the fifth step, if Fig.15 As shown, the logic chip 112A and the logic chip 113A prepared by another process are Cu-Cu bonded and stacked. Thereafter, a color filter, an on-chip lens, etc. are formed on the rear surface side of the sensor chip 111 to manufacture the semiconductor device 101A, as shown in FIG. Figure 5 as shown in .

[0107] The above steps make it possible to manufacture the semiconductor device 101A having a three-layer structure in which the sensor chip 111 , the logic chip 112A, and the logic chip 113A are stacked and the logic chip 112A and the logic chip 113A are connected by using the through-electrode 11 .

[0108] <Second Configuration Example of Through Electrodes>

[0109] Fig.16 is a diagram showing a configuration example of a second embodiment of a through electrode used in a semiconductor device to which the present technology is applied. Fig.16 In the through electrode 11-2 shown in FIG. Figure 1 The same configuration as that of the through-electrode 11 in FIG. 1 is denoted by the same reference symbols, and a detailed description thereof will be omitted.

[0110] like Fig.16 As shown, the through electrode 11 - 2 is provided to penetrate the semiconductor layer 21 - 2 .

[0111] The semiconductor layer 21-2 is configured such that an N-well layer 33 is formed on a P-substrate 31 which is a P-type silicon substrate, so that a depletion layer 34 is provided at a PN junction portion where the P-substrate 31 is joined to the N-well layer 33. In addition, an element isolator (shallow trench isolation (STI)) 35 for isolating an element is provided on the front surface of the semiconductor layer 21-2, and the through electrode 11-2 is provided to penetrate the element isolator 35.

[0112] The through electrode 11-2 has Figure 1 The through electrode 11 is different in structure in that the thermal oxide film 46 is formed inside the surface of the inner wall surface of the semiconductor layer 21-2 in the TSV hole, and the TSV hole is formed to penetrate the semiconductor layer 21-2 from the back side of the semiconductor layer 21-2 to the wiring 23. That is, Figure 1 The through electrode 11 has a structure in which a ferroelectric film 41 is stacked on the front surface of the inner wall surface of the TSV hole, but the through electrode 11-2 has a structure in which a thermal oxidation film 46 is formed on the inner side of the surface of the inner wall surface of the semiconductor layer 21-2 by performing thermal oxidation treatment after the TSV hole is formed.

[0113] Then, the insulating film 42 and the barrier metal 43 are stacked on the front surface of the inner wall surface of the TSV hole, and the conductor 44 is buried, thereby forming the through electrode 11 - 2 .

[0114] The thermal oxide film 46 is formed by, for example, changing the silicon itself on the front surface of the semiconductor layer 21-2 into a silicon oxide film by heating oxidation in a thermal oxidation process. In addition, the thermal oxide film 46 is provided only on a portion of the semiconductor layer 21-2 on the inner wall surface of the TSV hole and is provided at a position deeper than the element spacer 35.

[0115] The through electrode 11-2 is configured in this manner, and the thermal oxide film 46 has an insulating property for the depletion layer 34 provided at least in the PN junction portion, and thus it is possible to reduce leakage in the depletion layer 34 caused by defects generated during the processing of the TSV hole. In addition, by the thermal oxide film 46, the number of defects in the depletion layer 34 around the through electrode 11-2 can be reduced, so that the forbidden area can be narrowed.

[0116] Therefore, by using a through electrode 11-2 having such a configuration in a semiconductor device, low power consumption can be achieved with reduced leakage, and a layout in which chips are connected at arbitrary positions (e.g., at narrow pitches) can be provided in a design using a large number of miniaturized through electrodes 11-2.

[0117] Will refer to Fig.17 The step of forming the through-electrode 11 - 2 is described.

[0118] First, if Fig.17 As shown in the first part of FIG. 1 , a TSV hole 52 penetrating the semiconductor layer 21 - 2 is formed so that the wiring 23 is opened through the element isolator 35 from the back side of the semiconductor layer 21 - 2 .

[0119] Then, if Fig.17 As shown in the second part of FIG. 1 , a thermal oxidation film 46 is formed on the inner side of the inner wall surface of the semiconductor layer 21 - 2 by performing a thermal oxidation treatment.

[0120] Then, if Fig.17 As shown in the third part of FIG. 4 , the insulating film 42 is formed to be stacked on the thermal oxide film 46, and the insulating film 24 is formed on the rear surface of the semiconductor layer 21 - 2. In addition, the barrier metal 43 is stacked on the insulating film 42 and the wiring 23.

[0121] Afterwards, if Fig.16 As shown, the conductor 44 is embedded in the TSV hole 51 to form the through-electrode 11 - 2 .

[0122] Fig.18 11 - 2 is a diagram showing a modified example of the through-electrode 11 - 2 .

[0123] Fig.18 The through electrode 11a-2 shown in A is formed by stacking an insulating film 45 of a different type from the insulating film 42 between the thermal oxidation film 46 and the insulating film 42. That is, the through electrode 11a-2 has a two-layer film configuration of the insulating film 42 and the insulating film 45. Of course, the through electrode 11-2 may also adopt a multi-layer film structure of more than two layers.

[0124] Fig.18The through electrode 11 b - 2 shown in FIG. 1B has a length at least covering the depletion layer 34 and has a configuration in which the thermal oxide film 46 b is partially formed. That is, in order to reduce leakage of the depletion layer 34 , the thermal oxide film 46 b only needs to be formed to at least cover the depletion layer 34 .

[0125] <Configuration Example of Semiconductor Device>

[0126] Will refer to Figures 19 to 27 A semiconductor device using the through-electrode 11 - 2 is described.

[0127] Fig.19 is a cross-sectional view showing a tenth configuration example of the semiconductor device.

[0128] Fig.19 A semiconductor device 101-2 having a three-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101-2 has a three-layer structure in which a sensor chip 111 is provided in a first layer, logic chips 112a and 112b-2 are provided in a second layer, and a logic chip 113 is provided in a third layer, and has a configuration called a multi-chip. For example, the sensor chip 111 includes an imaging element such as a CMOS image sensor, and the logic chips 112a and 112b-2 and the logic chip 113 include a signal processing circuit (logic circuit, memory, etc.) for performing signal processing on an image captured by the sensor chip 111.

[0129] Then, the semiconductor device 101-2 is configured such that the through electrode 11-2 is set to penetrate the semiconductor layer 21-2 of the logic chip 112b-2. Therefore, the semiconductor device 101-2 can reduce the leakage in the depletion layer 34 of the PN junction part and reduce the forbidden area, as shown in FIG. Fig.16 As described.

[0130] Note that Figures 20 to 27 In each of the configuration examples shown in Fig.19 The same configurations as those of the semiconductor device 101 - 2 in FIG. 1 are given the same reference numerals, and a detailed description thereof will not be repeated.

[0131] Fig. 20 is a cross-sectional view showing an eleventh configuration example of the semiconductor device.

[0132] Fig. 20A semiconductor device 101A-2 having a three-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101A-2 has a three-layer structure in which a sensor chip 111 is provided in a first layer, a logic chip 112A-2 is provided in a second layer, and a logic chip 113A is provided in a third layer, and has a configuration called F2F in which the front surface side of the sensor chip 111 and the front surface side of the logic chip 112A-2 are bonded.

[0133] Then, the semiconductor device 101A-2 is configured such that the through electrode 11-2 is set to penetrate the semiconductor layer 21-2 of the logic chip 112A-2. Therefore, the semiconductor device 101A-2 can reduce the leakage in the depletion layer 34 of the PN junction part and reduce the forbidden area, as shown in FIG. Fig.16 described.

[0134] Fig.21 is a cross-sectional view showing a twelfth configuration example of the semiconductor device.

[0135] Fig.21 A semiconductor device 101B-2 having a three-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101B-2 has a three-layer structure in which a sensor chip 111 is provided in a first layer, a logic chip 112B-2 is provided in a second layer, and a logic chip 113B is provided in a third layer, and has a configuration called F2B in which the front surface side of the sensor chip 111 and the rear surface side of the logic chip 112B-2 are bonded.

[0136] Then, the semiconductor device 101B-2 is configured so that the through electrode 11-2 is set to penetrate the semiconductor layer 21-2 of the logic chip 112B-2. Therefore, the semiconductor device 101B-2 can reduce the leakage in the depletion layer 34 of the PN junction part and narrow the forbidden area, as shown in FIG. Fig.16 As described.

[0137] Fig. 22 is a cross-sectional view showing a thirteenth configuration example of the semiconductor device.

[0138] Fig. 22 A semiconductor device 101C-2 having a double-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101C-2 has a double-layer structure in which a sensor chip 111 is provided in a first layer and a logic chip 112C-2 is provided in a second layer, and has a configuration called a monolithic chip in which the logic chip 112C-2 is provided in a wiring layer of a logic chip 114C-2.

[0139] Then, the semiconductor device 101C-2 is configured such that the through electrode 11-2 is provided to penetrate the semiconductor layer 21-2 of the logic chip 114C-2. Therefore, the semiconductor device 101C-2 can reduce the leakage in the depletion layer 34 of the PN junction part and reduce the forbidden area, as shown in FIG. Fig.16 described.

[0140] Fig.23 is a cross-sectional view showing a fourteenth configuration example of the semiconductor device.

[0141] Fig.23 A semiconductor device 101D-2 having a double-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101D-2 has a two-layer structure in which a sensor chip 111 is provided in a first layer and a logic chip 112D-2 is provided in a second layer, and has a configuration called a backside bump in which a bump 121 is provided on the backside side of the logic chip 112D-2.

[0142] Then, the semiconductor device 101D-2 is configured such that the through-electrode 11-2 is provided as an electrode connected to the bump 121 in the semiconductor layer 21-2 of the logic chip 112D-2 and penetrates at least Fig.16 Therefore, the semiconductor device 101D-2 can reduce the leakage in the depletion layer 34 of the PN junction and reduce the forbidden zone, as shown in FIG. Fig.16 described.

[0143] Fig.24 is a cross-sectional view showing a fifteenth configuration example of the semiconductor device.

[0144] Fig.24 A semiconductor device 101E-2 having a four-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101E-2 has a four-layer structure in which a memory chip 115E-2 is provided in a first layer, a memory chip 116E-2 is provided in a second layer, a memory chip 117E-2 is provided in a third layer, and a logic chip 113E-2 is provided in a fourth layer, and has a configuration called multi-level memory / logic. Note that the semiconductor device 101E-2 may be mounted on a supporting substrate (not shown) with a bump 121 provided on the back side of the logic chip 113E-2 interposed therebetween. Of course, the semiconductor device 101E-2 may have a layered structure of four or more layers.

[0145] Then, the semiconductor device 101E-2 is configured such that the through electrode 11-2 is set to penetrate the semiconductor layer 21-2 of the memory chip 115E-2, the through electrode 11-2 is set to penetrate the semiconductor layer 21-2 of the memory chip 116E-2, the through electrode 11-2 is set to penetrate the semiconductor layer 21-2 of the memory chip 117E-2, and the through electrode 11-2 is set to penetrate the semiconductor layer 21-2 of the logic chip 113E-2 and connected to the bump 121. Therefore, the semiconductor device 101E-2 can reduce the leakage in the depletion layer 34 of the PN junction part and narrow the forbidden area, as shown in reference Fig.16 described.

[0146] Fig.25 is a cross-sectional view showing a sixteenth configuration example of the semiconductor device.

[0147] Fig.25 A semiconductor device 101F-2 having a double-layer structure bonded at a bonding surface indicated by a single-dot chain line is shown. The semiconductor device 101F-2 has a two-layer structure in which a memory chip 115F-2 is provided in a first layer and a logic chip 112F-2 is provided in a second layer, and has a configuration in which a wiring 122 for power supply is provided in a wiring layer of the logic chip 112F-2.

[0148] Then, the semiconductor device 101F-2 is configured such that the through electrode 11-2 is provided to penetrate the semiconductor layer 21-2 of the memory chip 115F-2. Furthermore, the semiconductor device 101F-2 is configured such that the through electrode 11-2 is provided to be connected to the wiring 122 in the semiconductor layer 21-2 of the logic chip 112F-2 and penetrates at least Figure 1 Therefore, the semiconductor device 101F-2 can reduce the leakage in the depletion layer 34 of the PN junction and reduce the forbidden zone, as shown in FIG. Fig.16 described.

[0149] Fig.26 is a cross-sectional view showing a seventeenth configuration example of the semiconductor device.

[0150] Fig.26 A semiconductor device 101G-2 having a single-layer structure is shown. The semiconductor device 101G-2 has a so-called monolithic configuration in which a logic chip 112G-2 is provided in a wiring layer of a logic chip 114G-2.

[0151] Then, the semiconductor device 101G-2 is configured such that the through electrode 11-2 is provided to penetrate the semiconductor layer 21-2 of the logic chip 114G-2. Therefore, the semiconductor device 101G-2 can reduce the leakage in the depletion layer 34 of the PN junction part and reduce the forbidden area, as shown in FIG. Fig.16 described.

[0152] Fig. 27 is a cross-sectional view showing an eighteenth configuration example of the semiconductor device.

[0153] Fig. 27 A semiconductor device 101H-2 having a single-layer structure is shown. The semiconductor device 101H-2 includes a logic chip 112H-2. Note that the semiconductor layer 21-2 of the logic chip 112H-2 has a thickness of several μm or less.

[0154] Then, the semiconductor device 101H-2 is configured such that the through electrode 11-2 is provided to penetrate the semiconductor layer 21-2 of the logic chip 112H-2, and the through electrode 11-2 is connected to the electrode of the bump 121. Therefore, the semiconductor device 101H-2 can reduce the leakage in the depletion layer 34 of the PN junction part and narrow the forbidden area, as shown in FIG. Fig.16 described.

[0155] As described above, the through-electrode 11 - 2 to which the present technology is applied can be applied to imaging element chips such as the semiconductor devices 101 - 2 to 101D- 2 , signal processing chips such as the semiconductor devices 101E- 2 to 101H- 2 , and the like.

[0156] <Method for manufacturing semiconductor device>

[0157] Will refer to Figure 28 to Figure 31 Description of manufacturing Fig. 20 A method for a semiconductor device 101A-2 in FIG.

[0158] In the eleventh step, if Fig.28 As shown in the first part of FIG. 1 , the semiconductor layer 21 having the front surface on which the element separator 35 is formed is prepared by another process.

[0159] In the twelfth step, if Fig.28 As shown in the second part of FIG. 1 , a TSV hole 52 is formed to penetrate the element isolator 35 and to a predetermined depth in the semiconductor layer 21. Then, a thermal oxidation film 46 is formed on the inner side of the inner wall surface of the semiconductor layer 21-2 in the TSV hole 52 by performing thermal oxidation treatment.

[0160] In the thirteenth step, if Fig.28 As shown in the third part of FIG. 1 , the conductor 44 is embedded in the TSV hole 52 to form the through electrode 11 - 2. Note that although not shown in the figure, Fig.17 As shown, before embedding the conductor 44, the insulating film 42 and the barrier metal 43 are formed in the TSV hole 52. In addition, the back side of the semiconductor layer 21-2 is subjected to chemical mechanical polishing (CMP) to be thinned.

[0161] In the fourteenth step, if Fig.28As shown in the fourth part of FIG. 2 , elements such as transistors are formed on the front surface of the semiconductor layer 21 , and an interlayer film as the wiring layer 22 is stacked.

[0162] In the fifteenth step, if Fig.29 As shown in the upper part of FIG. 2 , multilayer wiring is formed inside the wiring layer 22 , and a Cu pad 124 is formed on the front surface of the wiring layer 22 .

[0163] In the sixteenth step, if Fig.29 As shown in the lower part of , the sensor chip 111 prepared by another process is stacked by Cu-Cu bonding.

[0164] In the seventeenth step, if Fig.30 As shown in the upper part of FIG. 1 , the back side of the semiconductor layer 21 - 2 is subjected to CMP to be thinned until the tip of the through electrode 11 - 2 is exposed.

[0165] In the eighteenth step, if Fig.30 As shown in the lower section of FIG. 1 , an insulating film 24 is formed on the rear surface of the semiconductor layer 21 - 2 , and a Cu pad 125 is embedded in a portion of the insulating film 24 so as to be connected to the through-electrode 11 - 2 . In this way, a logic chip 112A- 2 is formed.

[0166] In the nineteenth step, if Fig.31 As shown, the logic chip 112A-2 and the logic chip 113A prepared by another process are Cu-Cu bonded and stacked. Thereafter, a color filter, an on-chip lens, etc. are formed on the rear surface side of the sensor chip 111 to manufacture the semiconductor device 101A-2, as shown in FIG. Fig. 20 shown.

[0167] The above steps make it possible to manufacture the semiconductor device 101A- 2 having a three-layer structure in which the sensor chip 111 , the logic chip 112A- 2 , and the logic chip 113A are stacked and connected by using the through-electrode 11 - 2 .

[0168] It should be noted that in this embodiment, a configuration in which a PN junction is provided by forming an N well layer 33 on a P substrate 31 has been described, but the present technology can be applied to a configuration in which a PN junction is provided by forming a P well layer on an N-type substrate. That is, a PN junction is provided by forming a well having impurities of a type different from that of the substrate type.

[0169] <Configuration Example of Electronic Device>

[0170] For example, the semiconductor device 101 described above can be applied to various electronic devices such as an imaging system such as a digital still camera and a digital video camera, a mobile phone having an imaging function, or another device having an imaging function.

[0171] Fig.32 is a block diagram showing a configuration example of an imaging device mounted on an electronic device.

[0172] like Fig.32 As shown, the imaging device 201 includes an optical system 202, an imaging element 203, a signal processing circuit 204, a monitor 205, and a memory 206, and can capture still images and moving images.

[0173] The optical system 202 including one or more lenses guides image light (incident light) from an object to the imaging element 203 to form an image on a light receiving surface (sensor unit) of the imaging element 203 .

[0174] As the imaging element 203, the semiconductor device 101 described above is applied. Electrons are accumulated for a certain time in the imaging element 203 according to an image formed on the light receiving surface via the optical system 202. Then, a signal corresponding to the electrons accumulated in the imaging element 203 is supplied to the signal processing circuit 204.

[0175] The signal processing circuit 204 performs various types of signal processing on the pixel signal output from the imaging element 203. An image (image data) obtained by the signal processing applied by the signal processing circuit 204 is supplied to the monitor 205 to be displayed or to the memory 206 to be stored (recorded).

[0176] By applying the semiconductor device 101 as described above, the imaging apparatus 201 configured in this manner can further achieve, for example, higher functions.

[0177] <Examples of using image sensors>

[0178] Fig.33 It is a diagram showing a usage example of the above-mentioned image sensor (imaging element).

[0179] For example, the image sensor described above may be used in various situations for sensing light such as visible light, infrared light, ultraviolet light, and X-rays as described below.

[0180] - Devices that capture images to be viewed, such as digital cameras and portable devices with camera functionality.

[0181] -Devices for traffic purposes, such as on-board sensors that capture images of the front, rear, surroundings, interior, etc. of a car, surveillance cameras for monitoring moving vehicles and roads, and ranging sensors that measure the distance between vehicles, etc. for safe driving (such as automatic stopping, recognition of driver conditions, etc.).

[0182] -A device for home appliances (such as televisions, refrigerators, and air conditioners) that images a user's gesture and performs device operations according to the gesture.

[0183] - Devices for medical and healthcare purposes, such as endoscopes and devices for performing angiography by receiving infrared light.

[0184] -Devices used for security purposes, such as security surveillance cameras and personal authentication cameras.

[0185] - Devices for beauty care, such as skin measuring instruments for imaging the skin, and microscopes for imaging the scalp.

[0186] -Devices for sports, such as action cameras or wearable cameras for sports applications.

[0187] - Devices used in agriculture, such as cameras for monitoring the condition of fields or crops.

[0188] <Configuration combination example>

[0189] It should be noted that the present technology may also have the following configurations.

[0190] (1) A semiconductor device comprising:

[0191] a first semiconductor chip;

[0192] a second semiconductor chip stacked on the first semiconductor chip and provided with a PN junction portion in a depth direction by forming an N-type well on a front surface of a P-type substrate or forming a P-type well on a front surface of an N-type substrate; and

[0193] The through electrode is arranged in a through hole penetrating the substrate, wherein:

[0194] The through electrode is configured such that a first insulating film having insulating properties at least with respect to a PN junction portion is provided along an inner wall surface of the through hole.

[0195] (2) The semiconductor device according to (1) above, wherein:

[0196] The first insulating film includes a ferroelectric film stacked on the front surface of the substrate on the inner wall surface of the through hole.

[0197] (3) The semiconductor device according to (2) above, wherein:

[0198] The ferroelectric film includes a structure having a ferroelectric and having a negative fixed charge or a positive fixed charge.

[0199] (4) The semiconductor device according to (2) or (3) above, wherein:

[0200] The ferroelectric film includes BaTiO3, Pb(Zr,Ti)O3, BiFeO3, SrBi2Ta2O9, (Bi,La)4Ti3O12, or high-k ferroelectric.

[0201] (5) The semiconductor device according to any one of (2) to (4) above, wherein:

[0202] The ferroelectric film is provided with a depletion layer having a length at least covering the PN junction portion.

[0203] (6) The semiconductor device according to any one of (2) to (5) above, wherein:

[0204] The ferroelectric film is formed as a single layer or a multilayer.

[0205] (7) The semiconductor device according to any one of (2) to (6) above, wherein:

[0206] The through electrode is stacked on the ferroelectric film and includes a second insulating film containing at least oxygen.

[0207] (8) The semiconductor device according to any one of (1) to (7) above, wherein:

[0208] At least one end of the through-electrode is connected to a wiring forming a part of an internal circuit provided in the second semiconductor chip.

[0209] (9) The semiconductor device according to (1) above, wherein:

[0210] The first insulating film includes a thermal oxidation film which is provided in the front surface of the substrate on the inner wall surface of the through hole and is formed on the substrate by a thermal oxidation process.

[0211] (10) The semiconductor device according to (9) above, wherein:

[0212] The thermal oxide film is formed by oxidizing silicon on the front surface of the substrate to change it into a silicon oxide film by heating in a thermal oxidation process.

[0213] (11) The semiconductor device according to (9) or (10) above, wherein:

[0214] The thermal oxide film is formed only in a portion of the substrate in the through hole.

[0215] (12) The semiconductor device according to any one of (9) to (11) above, wherein:

[0216] The through hole penetrates the element separator provided on the front surface of the substrate, and

[0217] The thermal oxide film is provided at a position deeper than the element separator.

[0218] (13) The semiconductor device according to any one of (9) to (12) above, wherein:

[0219] The thermal oxide film is provided with a length at least sufficient to cover the depletion layer of the PN junction portion.

[0220] (14) The semiconductor device according to any one of (9) to (13) above, wherein:

[0221] The through electrode is stacked on the thermal oxide film and includes a second insulating film containing at least oxygen.

[0222] (15) The semiconductor device according to any one of (1) to (14) above, wherein:

[0223] The first semiconductor chip includes an image sensor, and

[0224] The second semiconductor chip is provided with a signal processing circuit that performs signal processing on an image captured by the image sensor.

[0225] (16) The semiconductor device according to any one of (1) to (15) above, wherein:

[0226] The first semiconductor chip and the second semiconductor chip are provided with a signal processing circuit including a logic circuit and a memory.

[0227] (17) The semiconductor device according to any one of (1) to (16) above, wherein:

[0228] At least one or more layers of other semiconductor chips are further stacked on the second semiconductor chip.

[0229] (18) An electronic device comprising a semiconductor device, the semiconductor device comprising:

[0230] a first semiconductor chip;

[0231] a second semiconductor chip stacked on the first semiconductor chip and provided with a PN junction portion in a depth direction by forming an N-type well on a front surface of a P-type substrate or forming a P-type well on a front surface of an N-type substrate; and

[0232] The through electrode is arranged in a through hole penetrating the substrate, wherein:

[0233] The through electrode is configured such that a first insulating film having insulating properties at least with respect to a PN junction portion is provided along an inner wall surface of the through hole.

[0234] (19) A method for manufacturing a semiconductor device, the method comprising:

[0235] forming a through hole penetrating a substrate of a second semiconductor chip stacked on the first semiconductor chip, and the second semiconductor chip is provided with a PN junction portion in a depth direction by forming an N-type well on a front surface of a P-type substrate or forming a P-type well on a front surface of an N-type substrate; and

[0236] A through electrode is formed, the through electrode having a configuration in which a first insulating film having insulating properties at least with respect to a PN junction portion is provided along an inner wall surface of the through hole.

[0237] It should be noted that the present embodiment is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present disclosure. In addition, the effects described in this specification are merely examples and are not limited, and other effects can be provided.

[0238] Reference Symbols List

[0239] 11 Through electrode

[0240] 21 Semiconductor layer

[0241] 22 Wiring Layer

[0242] 23 Wire

[0243] 24 Insulation film

[0244] 31 P substrate

[0245] 32 deep N well layer

[0246] 33 N well layer

[0247] 34 Depletion layer

[0248] 35 Component Isolator

[0249] 41 Ferroelectric film

[0250] 42 Insulation film

[0251] 43 Barrier Metal

[0252] 44 Conductor

[0253] 45 Insulation film

[0254] 46 Thermal Oxidation Film

[0255] 101 Semiconductor Devices

[0256] 111 Sensor Chip

[0257] 112 to 114 logic chips

[0258] 115 to 117 memory chips

[0259] 121 Bump

[0260] 122 Wire

[0261] 123 to 125Cu pad.

Claims

1. A semiconductor device, comprising: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip and provided with a PN junction portion in a depth direction by forming an N-type well on a front surface of a P-type substrate or forming a P-type well on a front surface of an N-type substrate; and A through electrode is provided in a through hole penetrating the substrate, wherein: The through electrode is configured such that a first insulating film having insulating properties with respect to at least the PN junction portion is provided along an inner wall surface of the through hole.

2. The semiconductor device according to claim 1, wherein The first insulating film includes a ferroelectric film stacked on the front surface of the substrate on the inner wall surface of the through hole.

3. The semiconductor device according to claim 2, wherein: The ferroelectric film includes a structure having a ferroelectric and having a negative fixed charge or a positive fixed charge.

4. The semiconductor device according to claim 2, wherein: The ferroelectric film includes BaTiO3, Pb(Zr,Ti)O3, BiFeO3, SrBi2Ta2O9, (Bi,La)4Ti3O12, or high-k ferroelectric.

5. The semiconductor device according to claim 2, wherein: The ferroelectric film is provided with a length at least sufficient to cover a depletion layer of the PN junction portion.

6. The semiconductor device according to claim 2, wherein: The ferroelectric film is formed as a single layer or a multilayer.

7. The semiconductor device according to claim 2, wherein: The through electrode is stacked on the ferroelectric film and includes a second insulating film containing at least oxygen.

8. The semiconductor device according to claim 1, wherein At least one end of the through-electrode is connected to a wiring forming a part of an internal circuit provided in the second semiconductor chip.

9. The semiconductor device according to claim 1, wherein: The first insulating film includes a thermal oxidation film which is provided inside the front surface of the substrate on the inner wall surface of the through hole and is formed on the substrate by a thermal oxidation process.

10. The semiconductor device according to claim 9, wherein The thermal oxide film is formed by oxidizing silicon on the front surface of the substrate to change it into a silicon oxide film by heating in the thermal oxidation process.

11. The semiconductor device according to claim 9, wherein: A thermal oxide film is formed only in a portion of the substrate in the through hole.

12. The semiconductor device according to claim 9, wherein: The through hole penetrates an element separator provided on the front surface of the substrate, and the thermal oxide film is provided at a position deeper than the element separator.

13. The semiconductor device according to claim 9, wherein: The thermal oxide film is provided with a length at least sufficient to cover a depletion layer of a PN junction portion.

14. The semiconductor device according to claim 9, wherein: The through electrode is stacked on the thermal oxide film and includes a second insulating film containing at least oxygen.

15. The semiconductor device according to claim 1, wherein The first semiconductor chip includes an image sensor, and The second semiconductor chip is provided with a signal processing circuit that performs signal processing on an image captured by the image sensor.

16. The semiconductor device according to claim 1, wherein The first semiconductor chip and the second semiconductor chip are provided with a signal processing circuit including a logic circuit and a memory.

17. The semiconductor device according to claim 1, wherein At least one or more layers of other semiconductor chips are further stacked on the second semiconductor chip.

18. An electronic device, comprising a semiconductor device, wherein the semiconductor device comprises: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip and provided with a PN junction portion in a depth direction by forming an N-type well on a front surface of a P-type substrate or forming a P-type well on a front surface of an N-type substrate; and A through electrode is provided in a through hole penetrating the substrate, wherein: The through electrode is configured such that a first insulating film having insulating properties with respect to at least the PN junction portion is provided along an inner wall surface of the through hole.

19. A method for manufacturing a semiconductor device, the method comprising: forming a through hole penetrating a substrate of a second semiconductor chip, the second semiconductor chip being stacked on the first semiconductor chip and provided with a PN junction in a depth direction by forming an N-type well on a front surface of a P-type substrate or forming a P-type well on a front surface of an N-type substrate; and A through electrode is formed, the through electrode having a configuration in which a first insulating film having insulating properties at least with respect to the PN junction portion is provided along an inner wall surface of the through hole.

Images