Semiconductor device including lateral super junction field effect transistor

Abstract

A semiconductor device includes: a substrate (1) of a first conductivity type, which is a base of the semiconductor device; a high voltage junction field effect transistor (JFET) on the substrate (1), where the JFET comprises a plurality of parallel conductive layers (p; n); the parallel conductive layer (p; a first conductive layer (n1) of a second conductivity type extending on the substrate (1, 2); wherein a plurality of layers forming a parallel conductive layer having a channel formed by a plurality of doped epitaxial layers (n2-n6) of the second conductivity type are arranged on top of a first conductive layer (n1) of the second conductivity type, and a plurality of gate layers (p1-p5) of the first conductivity type are arranged on both sides of the channel; wherein the lowermost layer (p1) of the first conductivity type is arranged in the form of consecutive points (5) having different lengths and distances (6) between the consecutive points.

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a lateral super junction field effect transistor (JFET), which can be realized by placing a plurality of alternating n-type layers and p-type layers on top of each other and connecting them in parallel. Background Art

[0002] Such devices have been previously described in many patent documents, for example in US11,031,480B2, US2019 / 0198609A1, US2017 / 0222043A1 and US2011 / 0127606A1.

[0003] If the alternating n- and p-layers are matched in charge, their stack will completely deplete each other and a uniform electric field can be formed in the material, making almost optimal use of the material in terms of breakdown voltage. The stack of alternating n- and p-layers needs to be terminated at the bottom, and since the substrate is grounded and has a constant potential along the entire drift region, the electric field needs to be turned 90 degrees. This will increase the electric field locally, and this increase in the electric field will cause a lower electrical breakdown than the breakdown in the stack. Several different attempts to shape the electric field have been demonstrated.

[0004] US2011 / 0127606A1 suggests an n-buffer layer (160) that is entirely located below the bottom channel between the source and drain, or a portion of the n-buffer layer (160-1) is located between the source and drain. Another suggestion is to place a floating n+ region (661) in the substrate below the drain to shield the drain from high electric fields.

[0005] US2017 / 0222043A1 suggests a diffused p-region (253) and / or a diffused n-region (252) below the source and drain, respectively, which are also used to shape the electric field and reduce the maximum electric field.

[0006] US2019 / 0198609A1 suggests a region (202) where the thickness increases linearly or nonlinearly from the source to the drain. This is also to shape the electric field.

[0007] Previously in several places in the literature cited above, stacking of n-layers and p-layers was shown. Typically, the bottom channel ends abruptly at the drain, and below the channel the substrate acts as the bottom gate and is also the substrate that should support the breakdown voltage of the device. In the channel, the electric field is completely lateral, but below the drain, the electric field must turn vertical due to the backside grounding. This means that the electric field must be turned 90 degrees below the bottom channel in the substrate. If nothing is done, the electric field distribution from source to drain will form a U-shape with the electric field highest near the drain. The U-shape means that the electric field distribution is not uniform and the breakdown voltage will be lower than it could be. Summary of the invention

[0008] The object of the present invention is to reduce the above mentioned disadvantages and to obtain a higher breakdown voltage.

[0009] This object is achieved by the device according to the invention, wherein the lowermost layer of the first conductivity type is arranged in the form of consecutive points having different lengths and distances between deep polycrystalline trenches of the second conductivity type in the bottom of the JFET.

[0010] Further improvements are obtained by means of the devices defined in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The invention will now be explained with the aid of several non-limiting embodiments of semiconductor devices, focusing on the JFET portion shown in the accompanying drawings, in which Figure 1 A first embodiment of the present invention is shown, Figure 2 A second embodiment is shown which is a further development of the invention. DETAILED DESCRIPTION

[0012] Figure 1 The present invention is shown, starting with a highly doped substrate 1 of the first conductivity type connected to a back contact to ground. A thick low-doped layer 2 of the first conductivity type is epitaxially grown on the substrate. The thickness of the epitaxial layer should be large enough to support the breakdown voltage of the device. A layer n1 of the second conductivity type is epitaxially grown on the low-doped layer 2 of the first conductivity type. An implantation mask is placed on the epitaxial layer n1 and ion implantation is performed to form a mask layer p1 of the first conductivity type. By dividing the layer and changing the length and distance of the p-regions produced in the mask layer p1 of the first conductivity type, the effective amount of charge of the first conductivity type will be reduced toward the drain side D of the structure. This will reduce the electric field near the drain, thereby achieving a more uniform electric field and a higher breakdown voltage. Now, an epitaxial layer n2 of the second conductivity type is placed on top of the structure, and a first gate of the first conductivity type is implanted or epitaxially grown on the channel n2. The two layers are then repeated upward, as demonstrated in multiple earlier publications (e.g., the patent documents cited above).

[0013] Deep trenches are etched from the surface and then filled with highly doped silicon. Two filled trenches 3 of the second conductivity type and connecting the second conductivity type trenches n2-n6 are shown in the accompanying drawings. The filled trenches 4 of the first conductivity type are used to connect the layers p1-p5 of the first conductivity type. The gates p2-p5 are connected to the ground in the third dimension, for example by making an interruption in the source trench, as demonstrated in US11,031,480B2, or by making a filled trench column of the first conductivity type, as shown in US2019 / 0198609A1 and US2017 / 0222043A1.

[0014] The semiconductor device according to the invention can be combined with another isolation region X arranged on the substrate, which isolation region X includes logic and analog control functions, on the left side of the part shown in the figure, and is isolated on both sides by deep polycrystalline trenches 4 of the first conductivity type. Such a semiconductor device is described, for example, in US 11,031,480 B2.

[0015] Preferably, consecutive dots 5 of different length have a decreasing length in the direction towards the drain side D of the structure, and the distance 6 between the dots 5 increases in the direction towards the drain side D of the structure.

[0016] The entire structure is mirrored around the symmetry line L, which allows a high voltage to be generated across the drain trench.

[0017] Figure 2 An improved device is shown in which the gate layers p2-p5 are made by ion implantation through a photoresist mask in the layers p2-p5 of the first conductivity type to produce interruptions 7. The doping in the interruptions is the same as the doping in the adjacent channel regions n2-n5 of the second conductivity type. The interruptions 7 are evenly distributed along the drift region. The interruptions 7 in the layer will divide the region into a plurality of shorter regions 8 of the first conductivity type. The leftmost region of the shorter regions is connected to the ground as described above, and the other regions are floating regions. For smaller drain voltages, the floating region of the first conductivity type has less loss to the channel region than the long p-type gate that is grounded along the entire drift region. For lower drain voltages, this will increase the current through the device. For higher voltages, the current will flow through the shorter regions and connect them together.

[0018] To achieve this, the length of the interruption 7 should not be too large. For example, the distance 7 between the regions 8 may be about 0.3 μm, and the length of the region 8 may be about 5 μm.

[0019] In the drawings, the device according to the present invention has been described when the first conductivity type is p type and the second conductivity type is n type. However, the device according to the present invention can also be implemented so that the first conductivity type is n type and the second conductivity type is p type.

Claims

1. A semiconductor device comprising: A substrate (1) of a first conductivity type, which is a base of a semiconductor device; A high voltage junction field effect transistor JFET on a substrate (1), wherein the JFET comprises a plurality of parallel conductive layers (p; n), the JFET being isolated on the source side (S) of the JFET by a deep polycrystalline trench (4) of a first conductivity type; a first conductive layer (n1) of a second conductivity type parallel to the conductive layers (p; n) extending on the substrate (1, 2); wherein a plurality of layers forming parallel conductive layers are arranged on top of a first conductive layer (n1) of a second conductive type, the parallel conductive layers having a channel formed by a plurality of doped epitaxial layers (n2-n6) of a second conductive type, and a plurality of gate layers (p1-p5) of a first conductive type are provided on both sides of the channel; It is characterized in that The lowermost layer (p1) of the first conductivity type is arranged in the form of continuous dots (5) having different lengths and distances (6) between the continuous dots.

2. The semiconductor device according to claim 1, It is characterized in that Successive dots (5) of different length have decreasing lengths in the direction towards the drain side of the structure, and the distance (6) between the dots (5) increases in the direction towards the drain side of the structure.

3. The semiconductor device according to claim 1 or 2, It is characterized in that A conductive layer (p2-p5) of the first conductivity type above the first conductive layer (p1) of the first conductivity type consists of a continuous region (8) having different lengths and distances (7) between each region and a deep polycrystalline trench (3) of the second conductivity type.

4. The semiconductor device according to claim 1, It is characterized in that A further isolation region (X) is arranged on the substrate, the isolation region comprising logic and analog control functions, and is isolated on both sides by deep polycrystalline trenches (4) of the first conductivity type.

5. The semiconductor device according to claim 1, It is characterized in that The first conductivity type is p-type, and the second conductivity type is n-type.

6. The semiconductor device according to any one of claims 1 to 4, It is characterized in that The first conductivity type is n-type, and the second conductivity type is p-type.

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