Over-current detection circuit and frequency converter

Abstract

The invention relates to an overcurrent detection circuit for a frequency converter and a frequency converter used as a power supply. According to one embodiment of the disclosure, the overcurrent detection circuit is used for detecting whether overcurrent occurs in a power switch of the frequency converter for controlling power output of the frequency converter. The over-current detection circuit comprises a comparison module which comprises a comparator with an in-phase input end and an inverted input end; the switch module comprises a controlled switch coupled with the comparator; wherein the controlled switch comprises a first control electrode and a first electrode pair; one electrode in the first electrode pair is coupled with the non-inverting input end, and the other electrode in the first electrode pair is coupled with the inverting input end; the first control electrode is connected to receive a first driving signal for switching a connection state of the first electrode pair between an on state and an off state; the first driving signal is associated with a second driving signal of the power switch; the controlled switch is connected such that a first comparator output of the comparator when the power switch is in an overcurrent state is different from a second comparator output of the comparator when the power switch is in a normal state.

Description

Technical Field

[0001] The present disclosure relates generally to power supplies, and more particularly to an overcurrent detection circuit for a frequency converter and a frequency converter used as a power supply. Background Art

[0002] Frequency converter is a common power control device. It can control AC motor by changing the working power frequency of the motor.

[0003] The frequency converter generally includes a power switch and a microprocessor (e.g., a single chip microcomputer) for controlling the power output of the frequency converter. When the frequency converter is working, the current flowing through the power switch may be greater than a threshold value, and such a current is called an overcurrent. Overcurrent may damage the power switch. Therefore, when it is determined that an overcurrent occurs, the power switch needs to be cut off in time. In order to prevent the power switch from being damaged by overcurrent, a comparator is configured for the frequency converter. The comparator receives a voltage signal related to the power switch. For example, the non-inverting input terminal of the comparator is coupled to the source of the power switch, and the inverting input terminal is coupled to the drain of the power switch. Thus, when an overcurrent occurs, the comparator outputs a low-level signal, when the power switch is normally turned on, the comparator outputs a high-level signal, and when the power switch is normally turned off, the comparator outputs a low-level signal. Therefore, when the output of the comparator is a low-level signal, the power switch may be in a normal cutoff state or in an overcurrent state. That is, the output of the comparator is a low-level signal, which means that the power switch may be in an overcurrent state. As for whether it is in an overcurrent state, it needs to be further judged based on other parameters. That is to say, the microprocessor cannot determine whether an overcurrent occurs based only on a low-level signal. Therefore, the microprocessor needs to perform software judgment before it can determine whether an overcurrent has occurred. When the inverter is working, in order to achieve a high power factor, the power switch (transistor) has a high switching frequency, which causes the microprocessor to be overloaded (overutilized) due to software judgment and unable to adjust the control parameters in time, resulting in output over- and under-regulation, deteriorating the reliability of the microprocessor, and adversely affecting the EMC performance of the device. Summary of the invention

[0004] A brief overview of the present disclosure will be given below in order to provide a basic understanding of certain aspects of the present disclosure. It should be understood that this overview is not an exhaustive overview of the present disclosure. It is not intended to identify key or important parts of the present disclosure, nor is it intended to limit the scope of the present disclosure. Its purpose is simply to give certain concepts in a simplified form as a prelude to a more detailed description discussed later.

[0005] In order to reduce the workload of the microprocessor of the frequency converter, the inventor studied the working principle of the frequency converter and proposed the solution of the present disclosure.

[0006] According to one aspect of the present disclosure, an overcurrent detection circuit for a frequency converter is provided, the overcurrent detection circuit being used to detect whether an overcurrent occurs in a power switch of the frequency converter that controls the power output of the frequency converter. The overcurrent detection circuit includes: a comparison module, including a comparator having a non-inverting input terminal and an inverting input terminal; and a switch module, including a controlled switch coupled to the comparator; wherein the controlled switch includes a first control electrode and a first electrode pair; one electrode in the first electrode pair is coupled to the non-inverting input terminal, and the other electrode in the first electrode pair is coupled to the inverting input terminal; the first control electrode is connected to receive a first drive signal for switching the connection state of the first electrode pair between an on state and an off state; the first drive signal is associated with a second drive signal of the power switch; the controlled switch is connected so that a first comparator output of the comparator when the power switch is in an overcurrent state is different from a second comparator output of the comparator when the power switch is in a normal state, wherein the normal state includes a normal on state and a normal off state when the power switch is in a non-overcurrent state; and the controlled switch is connected so that the comparator generates the same comparator output when the power switch is in a normal on state and a normal off state.

[0007] According to one aspect of the present disclosure, a frequency converter is provided. The frequency converter includes: the aforementioned overcurrent detection circuit; a power switch for controlling the power output of the frequency converter; and a drive signal generation circuit for generating a second drive signal for driving the power switch; wherein the drive signal generation circuit is configured to generate a drive signal for turning off the power switch in response to a first comparator output.

[0008] The overcurrent detection circuit disclosed in the present invention can reduce the workload of the single chip microcomputer (microprocessor) of the frequency converter, improve the reliability and EMC performance of the frequency converter, and reduce undershoot and overshoot. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following description of the embodiments of the present disclosure will help to more easily understand the above and other purposes, features and advantages of the present disclosure with reference to the accompanying drawings. The accompanying drawings are only for the purpose of illustrating the principles of the present disclosure. The sizes and relative positions of the elements in the accompanying drawings are not necessarily drawn to scale. The same reference numerals may represent the same features. In the accompanying drawings:

[0010] Figure 1 An exemplary block diagram of an overcurrent detection circuit for a frequency converter according to an embodiment of the present disclosure is shown;

[0011] Figure 2 An exemplary block diagram of an overcurrent detection circuit for a frequency converter according to an embodiment of the present disclosure is shown;

[0012] Figure 3An exemplary circuit diagram of a comparison module according to one embodiment of the present disclosure is shown;

[0013] Figure 4 An exemplary block diagram of a frequency converter according to an embodiment of the present disclosure is shown;

[0014] Figure 5 An exemplary block diagram of a frequency converter according to an embodiment of the present disclosure is shown; and

[0015] Figure 6 The comparator output of the overcurrent detection circuit for the frequency converter according to one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0016] Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings. For the sake of clarity and conciseness, not all features of the actual embodiments are described in the specification. However, it should be understood that many implementation-specific decisions may be made in the process of developing any such actual embodiments in order to achieve the specific goals of the developer, and these decisions may vary from embodiment to embodiment.

[0017] It is also necessary to explain here that, in order to avoid obscuring the contents of the present disclosure due to unnecessary details, only the device structure closely related to the scheme according to the contents of the present disclosure is shown in the accompanying drawings, while other details that are not closely related to the contents of the present disclosure are omitted.

[0018] It should be understood that the present disclosure is not limited to the described implementation forms due to the following description with reference to the accompanying drawings. In this article, where feasible, the embodiments can be combined with each other, features between different embodiments can be replaced or borrowed, and one or more features can be omitted in one embodiment.

[0019] One aspect of the present disclosure provides an overcurrent detection circuit for a frequency converter. Figure 1 An exemplary description is given.

[0020] Figure 1 FIG. 1 is an exemplary block diagram of an overcurrent detection circuit 100 for a frequency converter according to an embodiment of the present disclosure. The overcurrent detection circuit 100 is used to detect a power switch Q2 (refer to FIG. 1 ) of the frequency converter that controls the power output of the frequency converter. Figure 5) whether an overcurrent occurs. The power factor of the frequency converter (power supply) can be corrected by controlling the power switch. The overcurrent detection circuit 100 includes: a comparison module cM and a switch module sM. The comparison module cM includes a comparator C having a non-inverting input terminal P3 and an inverting input terminal P4. The switch module sM includes a controlled switch SW1 coupled to the comparator C. The controlled switch SW1 includes a first control electrode G1 and a first electrode pair Es1 composed of electrodes D1 and S1. One electrode in the first electrode pair Es1 is coupled to the non-inverting input terminal P3, and the other electrode in the first electrode pair is coupled to the inverting input terminal P4, that is, the two input terminals of the comparator C are coupled one-to-one with the two non-controlled electrodes of the controlled switch SW1. The first control electrode G1 is connected to receive a first drive signal Dv1 for switching the connection state of the first electrode pair between an on state ON and an off state OFF. The first drive signal Dv1 is associated with the second drive signal Dv2 of the power switch (in the figure, "Dv1(Dv2)" is used to represent this association); the controlled switch is connected so that the first comparator output SC_oc of the comparator C when the power switch Q2 is in the overcurrent state Soc is different from the second comparator output SC_nm of the comparator when the power switch Q2 is in the normal state Snm. The power switch Q2 has three states when working: normal conduction state Nm_ON, normal cut-off state Nm_OFF, and overcurrent state OC_ON. In other words, the normal state refers to the working state of the power switch in the non-overcurrent state. The normal conduction state Nm_ON and the normal cut-off state Nm_OFF both belong to the normal state Snm. The controlled switch is connected so that the comparator generates the same comparator output (i.e., the second comparator output SC_nm) when the power switch is in the normal conduction state and the normal cut-off state.

[0021] For example, if the first comparator output SC_oc is a low level state represented by "0", the second comparator output SC_nm is a high level state represented by "1". Alternatively, if the first comparator output SC_oc is a high level state represented by "1", the second comparator output SC_nm is a low level state represented by "0". For example, the controlled switch is connected so that the comparator generates a high level comparator output represented by "1" when the power switch is in a normal on state and a normal off state, and generates a low level comparator output represented by "0" when the power switch is in an overcurrent state.

[0022] That is to say, only the comparator output SC of the circuit 100 can be used to determine whether an overcurrent has occurred. Therefore, it is no longer necessary for the microprocessor of the frequency converter to perform software judgment based on other parameters to determine whether an overcurrent has occurred after receiving the indication signal of "possible overcurrent". Moreover, when the power switch is working normally, the comparator output does not flip, which reduces the flip frequency of the comparator output and reduces the interference caused by flipping. Therefore, the overcurrent detection circuit of the present disclosure can reduce the workload of the single-chip microcomputer (microprocessor) of the frequency converter, improve the reliability and EMC performance of the frequency converter, and reduce undershoot and overshoot.

[0023] The controlled switch SW1 may be a triode or a MOS transistor.

[0024] For example, the controlled switch SW1 is an NMOS transistor, which can be called a "first NMOS transistor". In this case, the first control electrode G1 can be called a first gate; and the first electrode pair Es1 includes a first source corresponding to the electrode S1 and a first drain corresponding to the electrode D1. The power switch Q2 can also be an NMOS transistor, which can be called a "second NMOS transistor". The gate, drain, and source of the second NMOS transistor are represented by G2, D2, and S2, respectively.

[0025] In addition to the controlled switch, the switch module in the present disclosure may also include other components. Figure 2 An exemplary block diagram of an overcurrent detection circuit 200 for a frequency converter according to an embodiment of the present disclosure is shown, "VCC" represents a power supply terminal, "Out" represents an output terminal, "In" represents an input terminal, "GND" represents a circuit ground, "Vl" represents a first power supply voltage, and "Vh" represents a second power supply voltage. The circuit 200 may correspond to an example circuit in which the controlled switch and the power switch in the overcurrent detection circuit of the present disclosure are both NMOS transistors. Figure 2As shown in , the first NMOS transistor Q1 is a controlled switch. The overcurrent detection circuit 200 includes: a comparison module cMa and a switch module sMa. The comparison module cMa includes a comparator having a non-inverting input terminal P3 and an inverting input terminal P4. The switch module sMa includes a first NMOS transistor Q1 coupled to the comparator. The first NMOS transistor Q1 includes a first control electrode G1, an electrode D1, and an electrode S1. The electrode S1 is coupled to the non-inverting input terminal P3 through the circuit ground GND, and the electrode D1 is coupled to the inverting input terminal P4. The first control electrode G1 is connected to receive a first drive signal Dv1 for switching the connection state of the first electrode pair between the on state ON and the off state OFF. The first drive signal Dv1 is associated with the second drive signal Dv2 of the power switch Q2. The first NMOS transistor Q1 is connected so that the first comparator output SC_oc of the comparator when the power switch Q2 is in the overcurrent state Soc is low level (output "0"). The second comparator output SC_nm of the comparator is high level (output "1") when the power switch Q2 is in the normal state Snm (including the normal conduction state Nm_ON and the normal cut-off state Nm_OFF). The comparison module cMa is applied with a first power supply voltage Vl (for example, 3.3V). The electrode D1 is applied with a second power supply voltage Vh (for example, 15V), and the second power supply voltage Vh is higher than the first power supply voltage Vl. The second power supply voltage Vh can be the voltage output after the first-stage BUCK circuit (buck conversion circuit) of the inverter steps down the voltage output by the AC / DC converter, and the first voltage Vl can be the voltage output after the second-stage BUCK circuit of the inverter steps down the voltage Vh. The electrode D1 of the first NMOS transistor Q1 is coupled to the drain D2 of the power transistor Q2 via a diode d1. A filter capacitor C415 is coupled between the electrode D1 and the electrode S1. The electrode D1 is coupled to the inverting input terminal P4 via a resistor R4. The switch module sMa also includes an inverter Inverter. The inverter can be implemented by a NOT gate. The inverter receives a control signal Ctrl associated with the second drive signal Dv2 of the power switch Q2, and inverts Ctrl and outputs it as the first drive signal Dv1 of the first NMOS transistor Q1. The driver of the frequency converter generates the second drive signal Dv2 of the second NMOS transistor Q2 based on the control signal Ctrl provided by the microprocessor. That is, both Dv1 and Dv2 are generated based on the control signal Ctrl, and Dv1 and Dv2 are associated through the control signal Ctrl.Through such a configuration, the working states of Q1 and Q2 can be opposite. When the drive signal Dv2 ("1"; for example, the corresponding control signal Ctrl is a high level) turns on Q2, due to the action of the inverter, the drive signal Dv1 is a low level ("0"), so Q1 is cut off; and when the drive signal Dv2 ("0"; for example, the corresponding control signal Ctrl is a low level) turns off Q2, due to the action of the inverter, Q1 is turned on.

[0026] In addition to the comparator, the comparison module of the present disclosure may also be configured with more components (eg, resistors and capacitors) to achieve a predetermined potential at a predetermined node and implement a predetermined logic function. Figure 3 An exemplary circuit diagram of a comparison module cMb according to an embodiment of the present disclosure is shown. The non-inverting input terminal P3 is connected to a 3.3V power supply voltage via a resistor R537. The non-inverting input terminal P3 is connected to the circuit ground via resistors R539 and R538. The non-inverting input terminal P3 is also connected to the circuit ground via a resistor R540. The comparison module cMb includes a hysteresis circuit composed of a resistor R543 and a resistor R544 arranged between the inverting input terminal P4 and the circuit ground to suppress the output flip caused by a small fluctuation of the input, and at the same time, reduce the requirements for the voltage climb rate of the input signal. The inverting input terminal P4 is coupled to the electrode D1 of the first NMOS transistor via resistors R542, R541, and R4. Capacitors C408, C407, and C409 are also coupled between the input terminals P3 and P4. The input terminal P3 is coupled to the comparator output terminal via a resistor R536. The comparator C is also coupled to a capacitor C406.

[0027] The present disclosure also provides a frequency converter. Figure 4 The frequency converter of the present disclosure is described exemplarily. Figure 4 An exemplary block diagram of a frequency converter 400 according to an embodiment of the present disclosure is shown. The frequency converter 400 includes: a drive signal generating circuit 401, a power switch 403 and an overcurrent detection circuit 405. The power switch 403 is used to control the power output of the frequency converter, which can be the power switch Q2 mentioned when describing the overcurrent detection circuit 100. The overcurrent detection circuit 405 can be the circuit 100 or the circuit 200 mentioned above. The drive signal generating circuit 401 is used to generate a second drive signal Dv2 for driving the power switch 403. The overcurrent detection circuit 405 includes a comparator. The drive signal generating circuit 401 is configured to generate a drive signal for turning off the power switch 403 in response to the first comparator output SC_oc.

[0028] In one embodiment, the drive signal generating circuit 401 includes a microprocessor and a driver. The microprocessor is used to generate a control signal Ctrl associated with the second drive signal Dv2 of the power switch 403; and the driver is used to generate the second drive signal Dv2 for driving the power switch 403 based on the control signal Ctrl.

[0029] In one embodiment, the frequency converter further comprises an alarm circuit. The alarm circuit is configured to perform at least one of the following operations in response to the first comparator output: output an audible alarm; output a visible light alarm; and display an alarm message.

[0030] The power switch and the controlled switch of the frequency converter may be MOS transistors, such as NMOS transistors. Figure 5 An exemplary block diagram of a frequency converter 500 according to one embodiment of the present disclosure is shown. Figure 5 An exemplary block diagram of a frequency converter is shown when the power switch and the controlled switch of the frequency converter are NMOS transistors.

[0031] The frequency converter 500 includes: an AC / DC converter, a first-stage buck conversion circuit BUCK1, a second-stage buck conversion circuit BUCK2, a drive signal generating circuit 501, a power switch Q2, a switch module 503 and a comparison module 505, and a DC / AC converter. The frequency converter 500 is connected to a load Load. The load is, for example, a motor of a compressor. The drive signal generating circuit 501 includes a microprocessor MCU and a driver Driver. The AC / DC converter converts, for example, 220V 50Hz AC power into DC power, wherein the L terminal is connected to the live wire and the N terminal is connected to the neutral wire. The microprocessor MCU generates a control signal Ctrl associated with a second drive signal Dv2 of the power switch Q2. The driver Driver generates a second drive signal Dv2 for driving the power switch Q2 based on the control signal Ctrl. Dv2 is provided to the control electrode G2 of the power switch Q2 via a resistor R1. The DC / AC converter converts the DC power into an AC power of a desired frequency. The switch module 503 includes an inverter and a first NMOS transistor Q1 (acting as a controlled switch). The inverter receives a control signal Ctrl associated with the second drive signal Dv2 of the power switch Q2, and outputs an inverted signal of the control signal as a first drive signal Dv1. Dv1 is provided to a control electrode G1 of the first NMOS transistor Q1 via a resistor R3. The comparison module 505 includes a comparator having a non-inverting input terminal P3 and an inverting input terminal P4. The electrode S1 of the first NMOS transistor Q1 is coupled to the non-inverting input terminal P3 through a circuit ground GND, and the electrode D1 of the controlled switch Q1 is coupled to the inverting input terminal P4 via a resistor R4. The first NMOS transistor Q1 is connected so that the first comparator output SC_oc of the comparator when the power switch Q2 is in an overcurrent state Soc is different from the second comparator output SC_nm of the comparator when the power switch Q2 is in a normal state Snm. The first NMOS transistor enables the comparator to generate the same comparator output (ie, the second comparator output SC_nm) when the power switch is in a normally on state and a normally off state.

[0032] The inventors tested the overcurrent detection circuit of the present disclosure. Figure 6 The figure shows the comparator output of the overcurrent detection circuit for the inverter according to an embodiment of the present disclosure. The horizontal axis is time and the vertical axis is intensity. Other related quantities are also shown in the figure for reference. The upper figure is the original measurement result, including the waveform of the second drive signal Dv2 of the power switch Q2, the input current Input_I and the waveform of the comparator output SC, wherein Input_I represents the input current of the inverter. The lower figure is a partial enlarged view of the waveform near the moment indicated by the vertical dotted line in the upper figure. Figure 6As shown in the partial enlarged diagram (b), when the second drive signal Dv2 flips from a low level (the corresponding comparator output SC is a high level) to a high level (Q2 changes from cut-off to on), at the beginning, the comparator output SC maintains a high level (comparator output "1"). At around time t0, an overcurrent occurs in the power switch Q2, and the comparator output SC changes to a low level, indicating that an overcurrent has occurred. The microprocessor responds to the low-level comparator output SC (comparator output "0") and instructs the driver to output a low-level second drive signal, thereby turning off Q2, and the input current Input_I slowly decreases. The test results show that the overcurrent detection circuit can achieve the expected effect.

[0033] The overcurrent detection circuit of the present disclosure can reduce the workload of the single-chip microcomputer (microprocessor) of the frequency converter, improve the reliability and EMC performance of the frequency converter, and reduce undershoot and overshoot. The frequency converter equipped with the overcurrent detection circuit of the present disclosure will have corresponding improvements in reliability, EMC performance, and output power quality.

[0034] As described above, according to the present disclosure, the principle of overcurrent detection is provided. It should be noted that the effects of the scheme of the present disclosure are not necessarily limited to the above-mentioned effects, and in addition to or instead of the effects described in the previous paragraphs, any effect shown in this specification or other effects that can be understood from this specification can be obtained.

[0035] Although the present invention has been disclosed above by describing the specific embodiments of the present invention, it should be understood that those skilled in the art can design various modifications (including, in the case of failure, the combination or replacement of features between the various embodiments), improvements or equivalents of the present invention within the spirit and scope of the appended claims. These modifications, improvements or equivalents should also be considered to be included in the protection scope of the present disclosure.

[0036] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, elements, steps or components, but does not exclude the presence or addition of one or more other features, elements, steps or components.

Claims

1. An overcurrent detection circuit for a frequency converter, the overcurrent detection circuit is used to detect whether an overcurrent occurs in a power switch of the frequency converter that controls the power output of the frequency converter, characterized in that: The overcurrent detection circuit comprises: A comparison module, comprising a comparator having a non-inverting input terminal and an inverting input terminal; and a switch module, comprising a controlled switch coupled to the comparator; Wherein, the controlled switch comprises a first control electrode and a first electrode pair; One electrode of the first electrode pair is coupled to the non-inverting input terminal, and the other electrode of the first electrode pair is coupled to the inverting input terminal; The first control electrode is connected to receive a first drive signal for switching a connection state of the first electrode pair between an on state and an off state; The first drive signal is associated with a second drive signal of the power switch; The controlled switch is connected so that a first comparator output of the comparator when the power switch is in an overcurrent state is different from a second comparator output of the comparator when the power switch is in a normal state; Wherein, the normal state includes a normal on-state and a normal off-state when the power switch is in a non-overcurrent state; and The controlled switch is connected such that the comparator generates the same comparator output when the power switch is in the normally on-state and the normally off-state.

2. The overcurrent detection circuit according to claim 1, wherein: The controlled switch is a first NMOS transistor; The first control electrode is a first gate; and The first electrode pair includes a first source electrode and a first drain electrode.

3. The overcurrent detection circuit according to claim 2, wherein: The switch module includes a diode; The power switch is a second NMOS transistor; The second NMOS transistor includes a second gate, a second source and a second drain; A first source of the first NMOS transistor is connected to a circuit ground; A first drain of the first NMOS transistor is coupled to an inverting input terminal of the comparator; and The first drain of the first NMOS transistor is also coupled to the second drain of the second NMOS transistor via the diode.

4. The overcurrent detection circuit according to claim 3, wherein: The non-inverting input terminal of the comparator is coupled to the second source of the second NMOS transistor; and A second source of the second NMOS transistor is connected to the circuit ground.

5. The overcurrent detection circuit according to claim 4, wherein: The switch module includes an inverter; The inverter is connected to receive a control signal associated with the second drive signal of the power switch and output an inverted signal of the control signal as the first drive signal.

6. The overcurrent detection circuit according to claim 4, wherein: The switch module includes a filter capacitor arranged between the first drain and the first source.

7. The overcurrent detection circuit according to claim 4, wherein: The comparison module includes a hysteresis circuit disposed between the inverting input terminal and the circuit ground.

8. The overcurrent detection circuit according to claim 4, wherein: The comparator is configured to: A first comparator output outputting a first level when the power switch is in an overcurrent state; outputting a second comparator output of a second level when the power switch is in a normally on state; and outputting the second comparator output of the second level when the power switch is in an off-on state; The first level is lower than the second level.

9. A frequency converter, characterized in that: include: The overcurrent detection circuit according to any one of claims 1 to 8; The power switch is used to control the power output of the inverter; as well as A drive signal generating circuit, used for generating the second drive signal for driving the power switch; The drive signal generating circuit is configured to generate a drive signal for turning off the power switch in response to the first comparator output.

10. The frequency converter according to claim 9, wherein: The driving signal generating circuit includes a microprocessor and a driver; wherein the microprocessor is used to generate a control signal associated with a second drive signal of the power switch; and The driver is configured to generate the second driving signal for driving the power switch based on the control signal.

11. The frequency converter according to claim 9, characterized in that: It also includes an alarm circuit; The alarm circuit is configured to perform at least one of the following operations in response to the first comparator output: Output sound alarm; outputting a visible light alarm; and Displays alarm information.

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