Life prediction method and device and computer equipment

Abstract

The invention relates to a service life prediction method and device and computer equipment, and the method comprises the steps: testing an integrated current under a preset test condition, obtaining the electrical stress parameters of a plurality of target devices in an integrated circuit in a test process, and then calculating the service life of the integrated circuit according to the condition parameters of the test condition and the electrical stress parameters of each target device. And respectively determining the degradation parameters of each target device, so as to determine the weak device of the integrated circuit from the plurality of target devices, and finally determining the life of the integrated circuit according to the life of the weak device based on the short plate effect. The weak device is the most easily damaged device in the integrated circuit, so that the service life of the weak device can truly and effectively reflect the actual service life of the integrated circuit, and the weak device of the integrated circuit is found based on the actual operation parameters of each target device in the operation process of the integrated circuit. The service life of the integrated circuit is determined according to the service life of the weak device, and the service life of the integrated circuit can be accurately predicted.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a life prediction method, device and computer equipment. Background Art

[0002] With the development of science and technology, more and more integrated circuit devices are used in the control system, data transmission system and telemetry system of aerospace devices such as Beidou-3, Shenzhou series spacecraft and space station. Integrated circuit devices play an important role in aerospace devices, and the life of aerospace devices is closely related to the life of integrated circuit devices therein.

[0003] Currently, there is a lack of a method that can accurately predict the life of integrated circuit devices. Summary of the invention

[0004] Based on this, it is necessary to provide a life prediction method, device and computer equipment that can accurately predict the life of integrated circuit devices in response to the above technical problems.

[0005] In a first aspect, the present application provides a lifespan prediction method, the method comprising:

[0006] Obtaining electrical stress parameters of multiple target devices in an integrated circuit during a test process under preset test conditions;

[0007] Determining degradation parameters of each of the target devices respectively according to condition parameters of the test conditions and electrical stress parameters of each of the target devices;

[0008] Determining a weak device among the multiple target devices according to the degradation parameters of each of the target devices; wherein the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices;

[0009] The lifetime of the integrated circuit is determined based on the weak component.

[0010] In one embodiment, the condition parameters of the test condition include temperature parameters, frequency parameters and timing parameters, and the step of determining the degradation parameters of each target device according to the condition parameters of the test condition and the electrical stress parameters of each target device includes:

[0011] According to the temperature parameters and the electrical stress parameters of each of the target devices, correspondingly determining the life of each of the target devices under the failure mechanism;

[0012] Degradation parameters of each of the target components corresponding to the failure mechanism are determined respectively according to the frequency parameters, the timing parameters and the life of each of the target components.

[0013] In one of the embodiments, the electrical stress parameters include drain current, substrate current and gate voltage, the failure mechanism includes at least one of a hot carrier injection mechanism, a bias temperature instability mechanism and a time breakdown mechanism, and the lifetime of the target device includes at least one of a first sub-lifetime, a second sub-lifetime and a third sub-lifetime;

[0014] The determining, according to the temperature parameter and the electrical stress parameter of each target device, the life of each target device under the failure mechanism includes:

[0015] Determining the first sub-lifetime of each of the target devices under the hot carrier injection mechanism according to the drain current and the substrate current; and / or,

[0016] Determining the second sub-lifetime of each of the target devices under the bias temperature instability mechanism according to the gate voltage and the test temperature; and / or,

[0017] The third sub-lifetime of each of the target devices under the time-dependent breakdown mechanism is determined according to the gate voltage and the test temperature.

[0018] In one embodiment, the test process includes a plurality of test sub-processes; and determining the life of each target device under a failure mechanism according to the temperature parameter and the electrical stress parameter of each target device includes:

[0019] According to the temperature parameters and the electrical stress parameters of each of the target devices, the life of each of the devices corresponding to each of the test sub-processes under the failure mechanism is determined respectively.

[0020] In one embodiment, the test process includes a plurality of test sub-processes, the degradation parameter includes at least one of a first degradation parameter, a second degradation parameter, and a third degradation parameter; and determining the degradation parameter of each target device corresponding to the failure mechanism according to the frequency parameter, the timing parameter, and the life of each target device, respectively, includes:

[0021] Determining the number of the test sub-processes according to the timing parameters;

[0022] Determining the time of the test sub-process according to the frequency parameter;

[0023] Determining the first degradation parameter of each target device corresponding to the hot carrier injection mechanism according to the number of the test sub-processes, the time of the test sub-processes and the first sub-lifetime of each target device; and / or,

[0024] Determining the second degradation parameter of each target device corresponding to the bias temperature instability mechanism according to the number of the test sub-processes, the time of the test sub-processes and the second sub-lifetime of each target device; and / or,

[0025] The third degradation parameter of each target device corresponding to the time-dependent breakdown mechanism is determined according to the number of the test sub-processes, the time of the test sub-processes and the third sub-lifetime of each target device.

[0026] In one embodiment, determining weak devices among the plurality of target devices according to the degradation parameters of each of the target devices includes:

[0027] Determining the sum of the degradation parameters of each of the target devices according to the first degradation parameter and / or the second degradation parameter and / or the third degradation parameter of each of the target devices;

[0028] Determining the maximum value of the sum of the degradation parameters as the target degradation parameter;

[0029] A target component corresponding to the target degradation parameter is determined as the weak component.

[0030] In one embodiment, determining the life of the integrated circuit according to the weak component includes:

[0031] Determine the minimum value among the first sub-lifetime, the second sub-lifetime and the third sub-lifetime of the weak device under the failure mechanism as the target lifetime of the weak device;

[0032] The target lifetime of the weak component is determined as the lifetime of the integrated circuit.

[0033] In one embodiment, the step of obtaining electrical stress parameters of a plurality of target devices in an integrated circuit during a test under preset test conditions includes:

[0034] Acquire preset test conditions, wherein the preset test conditions include test temperature, test frequency and test timing;

[0035] Testing the integrated circuit at the test temperature according to the test frequency and the test timing;

[0036] The electrical stress parameters of the target device in the integrated circuit during the test are obtained.

[0037] In a second aspect, the present application provides a life prediction device, the device comprising:

[0038] An information acquisition module, used to obtain electrical stress parameters of multiple devices in an integrated circuit during a test process under preset test conditions;

[0039] A first determination module is used to obtain electrical stress parameters of multiple target devices in an integrated circuit during a test process under preset test conditions;

[0040] A second determination module is used to determine a weak device among the multiple target devices according to the degradation parameters of each of the target devices; wherein the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices;

[0041] The third determination module is used to determine the life of the integrated circuit according to the weak component.

[0042] In a third aspect, the present application provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the method described in any one of the above embodiments when executing the computer program.

[0043] The above-mentioned life prediction method, device and computer equipment first test the integrated current under preset test conditions to obtain the electrical stress parameters of multiple target devices in the integrated circuit during the test process, and then determine the degradation parameters of each target device respectively according to the condition parameters of the test conditions and the electrical stress parameters of each target device, so as to determine the weak device of the integrated circuit from the multiple target devices, and finally determine the life of the integrated circuit based on the life of the weak device based on the short board effect. The weak device is the most vulnerable device in the integrated circuit, so the life of the weak device can truly and effectively reflect the actual life of the integrated circuit. The present application finds the weak device of the integrated circuit based on the actual operating parameters of each target device during the operation of the integrated circuit, determines the life of the integrated circuit according to the life of the weak device, and can accurately predict the life of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A schematic diagram of a life prediction method in one embodiment;

[0046] Figure 2 is a flow chart of step S101 in one embodiment;

[0047] Figure 3 is a flow chart of step S102 in one embodiment;

[0048] Figure 4 is a schematic diagram of the process of S302 in one embodiment;

[0049] Figure 5 is a schematic diagram of the process of S103 in one embodiment;

[0050] Figure 6 is a schematic diagram of the process of S104 in one embodiment;

[0051] Figure 7 is a structural block diagram of a life prediction device in one embodiment;

[0052] Figure 8 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] Integrated circuit devices generally include ADC (Analog to Digital Converter) chips, DAC (Digital to Analog Converter) chips, SRAM (Static Random Access Memory), etc. In the related art, the life of integrated circuit devices is generally predicted by a reliability prediction model based on mathematical statistics or a reliability block diagram (RBD) method. The reliability prediction model based on mathematical statistics uses the failure rate of the statistical industry average level as an evaluation index, and the predicted result is far from the actual engineering practice. If a reliability block diagram is used to establish a reliability model that reflects the functional logical relationship of integrated circuit devices, since integrated circuit devices are composed of at least millions of single-tube MOS devices, each single tube has a different working state, resulting in different stress magnitudes. If the reliability model of the integrated circuit device is simply considered to be a series model of millions of single tubes, it is impossible to accurately describe the working state of the single tube. Even if the working state of each single tube can be obtained through simulation, the workload of the simulation analysis is huge, which ultimately leads to a huge deviation between the reliability prediction result of the integrated circuit device and the actual situation.

[0055] Based on the above technical problems, the present application proposes a life prediction method that can accurately predict the life of an integrated circuit device, making the life prediction result of the integrated circuit device closer to the actual situation. In an exemplary embodiment, please refer to Figure 1The present application provides a life prediction method, which is described by taking the SRAM memory as an example of the integrated circuit in the following text. The method includes steps S101 to S104. It can be understood that the SRAM memory is only used as an example in the present application. In the application, the life prediction method of the present application is also applicable to other integrated circuit devices such as ADC chips and DAC chips.

[0056] S101: Obtaining electrical stress parameters of a plurality of target devices in an integrated circuit during a test process under preset test conditions.

[0057] In applications, SRAM memory is usually composed of a storage array circuit, a sensitive amplifier circuit, a decoding circuit, a control circuit, an input and output circuit, and other parts. Among them, the storage array circuit is the core of the SRAM memory, and the transistors therein account for more than 80% of the total number of transistors in the SRAM memory, while the sensitive amplifier circuit mainly realizes the amplification of the storage unit signal and is the key circuit for reading SRAM data. Therefore, when predicting the life of the SRAM memory, the storage array circuit and the sensitive amplifier circuit of the SRAM memory can be used as target detection objects. Specifically, the storage array circuit and the sensitive amplifier circuit have multiple transistors, so each transistor in the storage array circuit and the sensitive amplifier circuit can be marked as a target device. After that, the SRAM memory can be read and written according to the preset test conditions, and the electrical stress parameters of each target device during the read and write control process, that is, the test process, can be obtained.

[0058] S102: Determine degradation parameters of each target device according to condition parameters of the test conditions and electrical stress parameters of each target device.

[0059] After obtaining the electrical stress parameters of each target device, the life of each target device can be calculated according to the electrical stress conditions to which each target device is subjected during the test and the conditional parameters of the test conditions, and then the degradation parameters of each target device can be calculated. The degradation parameters of the target device are negatively correlated with the life of the target device.

[0060] S103: determining a weak device among the multiple target devices according to the degradation parameters of each target device; wherein the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices.

[0061] It can be understood that the degradation parameter indicates the degree of degradation of the device during the test process. The larger the degradation parameter of a device, the shorter the life of the device. Therefore, the target device with the shortest life, that is, the weak device, can be determined from the target devices according to the degradation parameters of the target devices.

[0062] S104: Determine the life of the integrated circuit based on the weak components.

[0063] Due to the existence of the short-board effect, the life of the weakest circuit in the SRAM memory can determine the life of the SRAM memory, and the life of the weakest transistor in the circuit can determine the life of the circuit. Therefore, after determining the weak device in the SRAM memory, the life of the SRAM memory can be determined based on the weak device.

[0064] The above-mentioned life prediction method first tests the integrated current under preset test conditions to obtain the electrical stress parameters of multiple target devices in the integrated circuit during the test process, and then determines the degradation parameters of each target device according to the condition parameters of the test conditions and the electrical stress parameters of each target device, so as to determine the weak device of the integrated circuit from the multiple target devices, and finally determines the life of the integrated circuit based on the short board effect according to the life of the weak device. The weak device is the most vulnerable device in the integrated circuit, so the life of the weak device can truly and effectively reflect the actual life of the integrated circuit. The present application finds the weak device of the integrated circuit based on the actual operating parameters of each target device during the operation of the integrated circuit, determines the life of the integrated circuit according to the life of the weak device, and can accurately predict the life of the integrated circuit.

[0065] In an exemplary embodiment, see Figure 2 , step S101, obtaining electrical stress parameters of multiple target devices in an integrated circuit during a test process under preset test conditions, including steps S201 to S203.

[0066] S201: Obtaining preset test conditions, wherein the preset test conditions include test temperature, test frequency, and test sequence.

[0067] Before predicting the life of an SRAM memory, the test conditions of the SRAM memory, such as the test temperature, test frequency, and test timing, can be determined first. In an example, the most commonly used timing of the SRAM memory can be set as the test timing of the SRAM memory, such as using "write 0, read 0, write 1, read 1" as the test timing, the test temperature of the SRAM memory can be set to normal temperature, such as 25°C, and the most commonly used operating frequency of the SRAM memory can be set as the test frequency.

[0068] S202: Testing the integrated circuit at a test temperature according to a test frequency and a test sequence.

[0069] After the test conditions are obtained, the SRAM memory can be read and written according to the test conditions.

[0070] S203: Obtaining electrical stress parameters of a target device in the integrated circuit during the test process.

[0071] The test process may include multiple test sub-processes. During the process of reading and writing control of the SRAM memory, the electrical stress parameters of each target device in the SRAM memory in each test sub-process may be obtained, so that the life of each target device may be predicted based on the obtained electrical stress parameters.

[0072] In an exemplary embodiment, see Figure 3 , step S102, determining the degradation parameters of each target device according to the condition parameters of the test conditions and the electrical stress parameters of each target device, including step S301 and step S302.

[0073] S301: Determine the life of each target device under a failure mechanism according to the temperature parameter and the electrical stress parameter of each target device.

[0074] In this embodiment, the preset test conditions may include the ambient temperature of the SRAM memory to be tested, the operating frequency of the SRAM memory to be tested and the test timing of the SRAM memory to be tested, that is, the condition parameters of the test conditions include temperature parameters, frequency parameters and timing parameters. First, the failure mechanism of the SRAM memory can be determined, and then the life of each target device under the corresponding failure mechanism can be determined according to the temperature parameters and the electrical stress parameters of each target device.

[0075] S302: Determine degradation parameters of failure mechanisms corresponding to the target components according to frequency parameters, timing parameters and the life of the target components.

[0076] After determining the lifetime of each target device, since the degradation parameter of the target device is inversely correlated with the lifetime of the target device, the degradation parameter of the failure mechanism corresponding to each target device can be calculated based on the lifetime of each target device in combination with the frequency parameters and timing parameters of the test.

[0077] In an exemplary embodiment, the electrical stress parameters include drain current, substrate current and gate voltage, the failure mechanism includes at least one of a hot carrier injection mechanism, a bias temperature instability mechanism and a time breakdown mechanism, and the lifetime of the target device includes at least one of a first sub-lifetime, a second sub-lifetime and a third sub-lifetime.

[0078] Step S301, according to the temperature parameters and the electrical stress parameters of each target device, the lifetime of each target device under the failure mechanism is determined accordingly, including the steps of determining the first sub-lifetime of each target device under the hot carrier injection mechanism according to the drain current and the substrate current, and / or determining the second sub-lifetime of each target device under the bias temperature instability mechanism according to the gate voltage and the test temperature, and / or determining the third sub-lifetime of each target device under the time breakdown mechanism according to the gate voltage and the test temperature.

[0079] In one example, the failure mechanism includes a hot carrier injection mechanism, a bias temperature instability mechanism, and a time-dependent breakdown mechanism.

[0080] Under the hot carrier injection mechanism, the drain current I D , substrate current I sub and the first failure model to determine the first sub-lifetime τ of the target device HCI , the first failure model is: Among them, ρ 1 is the first constant coefficient, and m is the second constant coefficient.

[0081] Under the bias temperature instability mechanism, the gate voltage V g , test temperature T and the second failure model to determine the second sub-lifetime τ of the target device TDDB , the second failure model is: Where n is the third constant coefficient, Ea is the activation energy, and k is the Boltzmann constant.

[0082] Under the time-dependent breakdown mechanism, the gate voltage V g , test temperature T and the third failure model determine the third sub-lifetime τ of the target device BTI , the third failure model is: Among them, ρ 2 is the fourth constant coefficient.

[0083] In an exemplary embodiment, step S301, based on the temperature parameters and the electrical stress parameters of each target device, determines the lifetime of each target device under the failure mechanism, and also includes: based on the temperature parameters and the electrical stress parameters of each target device, determines the lifetime of each test sub-process corresponding to each device under the failure mechanism.

[0084] In the application, the test process may include multiple test sub-processes, and the number of test sub-processes is related to the test sequence. Taking the test sequence of "write 0, read 0, write 1, read 1" as an example, the test process includes four test sub-processes: "write 0", "read 0", "write 1" and "read 1". Obtaining the electrical stress parameters of multiple target devices in the integrated circuit during the test process under preset test conditions includes the step of obtaining the electrical stress parameters of each target device in each test sub-process. Furthermore, for each target device, its life in each test sub-process can be calculated.

[0085] In an exemplary embodiment, the test process includes a plurality of test sub-processes, and the degradation parameter includes at least one of a first degradation parameter, a second degradation parameter, and a third degradation parameter. Figure 4, step S302, determining the degradation parameters of the failure mechanism corresponding to each target device according to the frequency parameters, timing parameters and the life of each target device, including steps S401 to S405.

[0086] S401: Determine the number of test sub-processes according to timing parameters.

[0087] It can be understood that the number of test sub-processes is related to the test sequence. Assuming the test sequence is "write 0, read 0, write 1, read 1" as an example, the number of test sub-processes is four: "write 0", "read 0", "write 1" and "read 1".

[0088] S402: Determine the time of the test sub-process according to the frequency parameter.

[0089] Assuming the frequency parameter f is 100 MHz, the time of the test sub-process is 1 / f=10 ns.

[0090] S403: Determine first degradation parameters of hot carrier injection mechanisms corresponding to each target device according to the number of test sub-processes, the time of the test sub-processes, and the first sub-lifetime of each target device.

[0091] In the application, the first degradation parameter of the target device in the hot carrier injection mechanism can be determined according to the number of test sub-processes, the time of the test sub-processes, the first sub-lifetime of the target device and the first formula. The first formula is Among them, D HCI is the first degradation parameter, n is the number of test subprocesses, t c is the time of the test subprocess, τ HCIi is the first sub-lifetime of the target device in the i-th sub-process.

[0092] S404: Determine the second degradation parameter of the bias temperature instability mechanism corresponding to each target device according to the number of test sub-processes, the time of the test sub-processes and the second sub-lifetime of each target device.

[0093] Similarly, the second degradation parameter of the target device in the hot carrier injection mechanism can be determined according to the number of test sub-processes, the time of the test sub-processes, the second sub-lifetime of the target device and the second formula. The second formula is: Among them, D TDDB is the second degradation parameter, n is the number of test subprocesses, t c is the time of the test subprocess, τ TDDBi is the second sub-lifetime of the target device in the i-th sub-process.

[0094] S405: Determine the third degradation parameter of each target device corresponding to the time-dependent breakdown mechanism according to the number of test sub-processes, the time of the test sub-processes and the third sub-lifetime of each target device.

[0095] Similarly, the third degradation parameter of the target device in the hot carrier injection mechanism can be determined according to the number of test sub-processes, the time of the test sub-processes, the third sub-lifetime of the target device and the third formula. The second formula is: Among them, D BTI is the third degradation parameter, n is the number of test subprocesses, t c is the time of the test subprocess, τ BTIi is the third sub-lifetime of the target device in the i-th sub-process.

[0096] In an exemplary embodiment, see Figure 5 , step S103, determining weak devices among the multiple target devices according to the degradation parameters of each target device, including step S501 and step S502.

[0097] S501: Determine the sum of degradation parameters of each target device according to the first degradation parameter and / or the second degradation parameter and / or the third degradation parameter of each target device.

[0098] Assuming that the failure mechanism includes hot carrier injection mechanism, bias temperature instability mechanism and time breakdown mechanism, after calculating the first degradation parameter, the second degradation parameter and the third degradation parameter of each target device, the total degradation parameter of each target device can be further calculated, that is, the sum of the degradation parameters of each target device.

[0099] S502: Determine the maximum value of the sum of the degradation parameters as a target degradation parameter, and determine the target device corresponding to the target degradation parameter as a weak device.

[0100] It can be understood that the higher the total degradation parameter of the target device is, the more serious the degradation degree of the target device is and the shorter the life span is. Therefore, the calculated sums of the degradation parameters of the target devices can be sorted, and the maximum value of the sums of the degradation parameters can be determined as the target degradation parameter, and the target device corresponding to the target degradation parameter can be determined as a weak device.

[0101] In an exemplary embodiment, see Figure 6 , step S104, determining the life of the integrated circuit according to the weak components, including step S601 and step S602.

[0102] S601: Determine a minimum value among a first sub-lifetime, a second sub-lifetime and a third sub-lifetime of a weak component under a failure mechanism as a target lifetime of the weak component.

[0103] After the weak device is determined, the first sub-lifetimes, the second sub-lifetimes and the third sub-lifetimes calculated during the test of the weak device may be sorted, and the minimum value may be selected as the target lifetime of the weak device.

[0104] S602: Determine the target life of the weak component as the life of the integrated circuit.

[0105] Due to the existence of the short-board effect, the life of the weakest circuit in the SRAM memory can determine the life of the SRAM memory, and the life of the weakest transistor in the circuit can determine the life of the circuit. Therefore, after determining the weak device in the SRAM memory, the target life of the weak device is determined as the life of the SRAM memory.

[0106] In a detailed embodiment, taking the test sequence of "write 0, read 0, write 1, read 1", the temperature parameter of 25°C, and the frequency parameter of 100MHz as an example, the following Table 1 shows the electrical stress parameters of some target devices in the SRAM memory during the test process. It can be seen that the following table records the electrical stress parameters of the target devices B1 to B12 in the four test sub-processes. Among them, Vgd represents the gate-drain voltage of the target device, Vg represents the gate voltage of the target device, Igate represents the gate current of the target device, Id represents the drain current of the target device, and Isub represents the substrate current of the target device.

[0107] Based on the electrical stress parameters of each target device in each test sub-process, combined with the temperature parameters, frequency parameters, the first failure model, the second failure model and the third failure model, the first sub-lifetime τ of each target device in each test sub-process can be calculated. HCI , each second sub-lifetime τ TDDB and the lifetime of each third child τ BTI Afterwards, the first sub-lifetime τ of each target device can be calculated. HCI , each second sub-lifetime τ TDDB and the lifetime of each third child τ BTI , combined with the time and number of the test sub-processes, the total degradation parameters of each target device are calculated, and finally the weak devices in each target device can be determined according to the total degradation parameters of each target device, and the life of the SRAM memory can be determined according to the shortest life of the weak devices.

[0108] Table 1 Electrical stress parameters of some target devices of SRAM memory

[0109]

[0110] To sum up, the life prediction method of the present application can perform targeted tests on the key circuit parts of the SRAM memory, and analyze and determine the weak devices from the key circuit parts of the SRAM memory, and finally determine the life of the SRAM memory according to the life of the weak devices. Through the life prediction method of the present application, the weak parts of the SRAM memory can be analyzed in detail, and the life of the SRAM memory can be predicted more realistically.

[0111] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0112] Based on the same inventive concept, the embodiment of the present application also provides a life prediction device for implementing the life prediction method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more life prediction device embodiments provided below can refer to the limitations of the life prediction method above, and will not be repeated here.

[0113] In one embodiment, see Figure 7 The present application provides a life prediction device, which includes an information acquisition module 701, a first determination module 702, a second determination module 703 and a third determination module 704.

[0114] The information acquisition module 701 is used to acquire electrical stress parameters of multiple devices in an integrated circuit during a test process under preset test conditions.

[0115] The first determination module 702 is used to determine the degradation parameters of each of the target devices according to the condition parameters of the test conditions and the electrical stress parameters of each of the target devices.

[0116] The second determination module 703 is used to determine a weak device among the multiple target devices according to the degradation parameters of each of the target devices; wherein the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices.

[0117] The third determination module 704 is used to determine the life of the integrated circuit according to the weak components.

[0118] In one embodiment, the condition parameters of the test condition include temperature parameters, frequency parameters and timing parameters, and the first determination module 702 includes a first determination submodule and a second determination submodule.

[0119] The first determination submodule is used to determine the life of each target device under the failure mechanism according to the temperature parameter and the electrical stress parameter of each target device;

[0120] The second determination submodule is used to determine the degradation parameters of the failure mechanisms corresponding to the target components according to the frequency parameters, the timing parameters and the life of the target components.

[0121] In one embodiment, the electrical stress parameters include drain current, substrate current and gate voltage, the failure mechanism includes at least one of hot carrier injection mechanism, bias temperature instability mechanism and time breakdown mechanism, and the life of the target device includes at least one of a first sub-lifetime, a second sub-lifetime and a third sub-lifetime. The first determination submodule includes a first determination unit.

[0122] The first determination unit is used to determine the first sub-lifetime of each target device under the hot carrier injection mechanism according to the drain current and the substrate current, and / or to determine the second sub-lifetime of each target device under the bias temperature instability mechanism according to the gate voltage and the test temperature, and / or to determine the third sub-lifetime of each target device under the time breakdown mechanism according to the gate voltage and the test temperature.

[0123] In one embodiment, the test process includes multiple test sub-processes; the first determination sub-module also includes: a second determination unit, the second determination unit is used to determine the life of each device corresponding to each test sub-process under the failure mechanism according to the temperature parameters and the electrical stress parameters of each target device.

[0124] In one embodiment, the test process includes a plurality of test sub-processes, and the degradation parameter includes at least one of a first degradation parameter, a second degradation parameter, and a third degradation parameter. The second determination submodule includes: a third determination unit, a fourth determination unit, and a fifth determination unit.

[0125] The third determining unit is used to determine the number of test sub-processes according to the timing parameters.

[0126] The fourth determining unit is used to determine the time of the test sub-process according to the frequency parameter.

[0127] The fifth determination unit is used to determine the first degradation parameter of the hot carrier injection mechanism corresponding to each target device according to the number of test sub-processes, the time of the test sub-processes and the first sub-lifetime of each target device, and / or, to determine the second degradation parameter of the bias temperature instability mechanism corresponding to each target device according to the number of test sub-processes, the time of the test sub-processes and the second sub-lifetime of each target device, and / or, to determine the third degradation parameter of the time-dependent breakdown mechanism corresponding to each target device according to the number of test sub-processes, the time of the test sub-processes and the third sub-lifetime of each target device.

[0128] In one embodiment, the second determination module 703 includes a third determination submodule, a fourth determination submodule and a fifth determination submodule.

[0129] The third determination submodule is used to determine the sum of the degradation parameters of each target device according to the first degradation parameter and / or the second degradation parameter and / or the third degradation parameter of each target device.

[0130] The fourth determination submodule is used to determine the maximum value of the sum of the degradation parameters as the target degradation parameter.

[0131] The fifth determination submodule is used to determine the target component corresponding to the target degradation parameter as a weak component.

[0132] In one embodiment, the third determination module 704 includes a sixth determination submodule and a seventh determination submodule.

[0133] The sixth determination submodule is used to determine the minimum value among the first sub-lifetime, the second sub-lifetime and the third sub-lifetime of the weak component under the failure mechanism as the target lifetime of the weak component.

[0134] The seventh determination submodule is used to determine the target lifetime of the weak component as the lifetime of the integrated circuit.

[0135] In one embodiment, the information acquisition module 701 includes a first acquisition submodule, a test submodule and a second acquisition submodule.

[0136] The first acquisition submodule is used to acquire preset test conditions, wherein the preset test conditions include test temperature, test frequency and test timing.

[0137] The test submodule is used to test the integrated circuit at a test temperature according to a test frequency and a test sequence.

[0138] The second acquisition submodule is used to acquire the electrical stress parameters of the target device in the integrated circuit during the test process.

[0139] Each module in the above-mentioned life prediction device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0140] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps of the method in any one of the above embodiments when executing the computer program.

[0141] The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 8 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (Near Field Communication, NFC) or other technologies. When the computer program is executed by the processor, a life prediction method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0142] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method described in any of the above embodiments are implemented.

[0143] In one embodiment, a computer program product is provided, including a computer program, which implements the steps of the method described in any one of the above embodiments when executed by a processor.

[0144] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0145] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0146] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0147] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A life prediction method, characterized in that: The method comprises: Obtaining electrical stress parameters of multiple target devices in an integrated circuit during a test process under preset test conditions; Determining degradation parameters of each of the target devices respectively according to condition parameters of the test conditions and electrical stress parameters of each of the target devices; Determining a weak device among the multiple target devices according to the degradation parameters of each of the target devices; wherein the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices; The lifetime of the integrated circuit is determined based on the weak component.

2. The life prediction method according to claim 1, characterized in that: The condition parameters of the test conditions include temperature parameters, frequency parameters and timing parameters, and the degradation parameters of each target device are determined according to the condition parameters of the test conditions and the electrical stress parameters of each target device, including: According to the temperature parameters and the electrical stress parameters of each of the target devices, correspondingly determining the life of each of the target devices under the failure mechanism; Degradation parameters of each of the target components corresponding to the failure mechanism are determined respectively according to the frequency parameters, the timing parameters and the life of each of the target components.

3. The life prediction method according to claim 2, characterized in that: The electrical stress parameters include drain current, substrate current and gate voltage, the failure mechanism includes at least one of a hot carrier injection mechanism, a bias temperature instability mechanism and a time breakdown mechanism, and the lifespan of the target device includes at least one of a first sub-lifespan, a second sub-lifespan and a third sub-lifespan; The determining, according to the temperature parameter and the electrical stress parameter of each target device, the life of each target device under the failure mechanism includes: Determining the first sub-lifetime of each of the target devices under a hot carrier injection mechanism according to the drain current and the substrate current; and / or, Determining the second sub-lifetime of each of the target devices under the bias temperature instability mechanism according to the gate voltage and the test temperature; and / or, The third sub-lifetime of each target device under the time-dependent breakdown mechanism is determined according to the gate voltage and the test temperature.

4. The life prediction method according to claim 2, characterized in that: The test process includes a plurality of test sub-processes; The determining, according to the temperature parameter and the electrical stress parameter of each target device, the life of each target device under the failure mechanism includes: According to the temperature parameters and the electrical stress parameters of each of the target devices, the life of each of the devices corresponding to each of the test sub-processes under the failure mechanism is determined respectively.

5. The life prediction method according to claim 3, characterized in that: The test process includes a plurality of test sub-processes, the degradation parameter includes at least one of a first degradation parameter, a second degradation parameter, and a third degradation parameter; and determining the degradation parameter of each target device corresponding to the failure mechanism according to the frequency parameter, the timing parameter, and the life of each target device, respectively, includes: Determining the number of the test sub-processes according to the timing parameters; Determining the time of the test sub-process according to the frequency parameter; Determining the first degradation parameter of each target device corresponding to the hot carrier injection mechanism according to the number of the test sub-processes, the time of the test sub-processes and the first sub-lifetime of each target device; and / or, Determining the second degradation parameter of each target device corresponding to the bias temperature instability mechanism according to the number of the test sub-processes, the time of the test sub-processes and the second sub-lifetime of each target device; and / or, The third degradation parameter of each target device corresponding to the time-dependent breakdown mechanism is determined according to the number of the test sub-processes, the time of the test sub-processes and the third sub-lifetime of each target device.

6. The life prediction method according to claim 5, characterized in that: The step of determining weak devices among the plurality of target devices according to the degradation parameters of the target devices comprises: Determining the sum of the degradation parameters of each of the target devices according to the first degradation parameter and / or the second degradation parameter and / or the third degradation parameter of each of the target devices; Determining the maximum value of the sum of the degradation parameters as the target degradation parameter; A target component corresponding to the target degradation parameter is determined as the weak component.

7. The life prediction method according to claim 3, characterized in that: The determining the life of the integrated circuit according to the weak component comprises: Determine the minimum value among the first sub-lifetime, the second sub-lifetime and the third sub-lifetime of the weak device under the failure mechanism as the target lifetime of the weak device; The target lifetime of the weak component is determined as the lifetime of the integrated circuit.

8. The life prediction method according to any one of claims 1 to 7, characterized in that: The obtaining of electrical stress parameters of a plurality of target devices in an integrated circuit during a test process under preset test conditions includes: Acquire preset test conditions, wherein the preset test conditions include test temperature, test frequency and test timing; Testing the integrated circuit at the test temperature according to the test frequency and the test timing; The electrical stress parameters of the target device in the integrated circuit during the test are obtained.

9. A life prediction device, characterized in that: The device comprises: An information acquisition module, used to obtain electrical stress parameters of multiple devices in an integrated circuit during a test process under preset test conditions; A first determination module is used to obtain electrical stress parameters of multiple target devices in an integrated circuit during a test process under preset test conditions; A second determination module is used to determine a weak device among the multiple target devices according to the degradation parameters of each of the target devices; wherein the degradation parameter of the weak device is greater than the degradation parameters of the remaining devices among the multiple target devices; The third determination module is used to determine the life of the integrated circuit according to the weak component.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

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