Equivalent application working condition experimental circuit and its experimental method

Abstract

The present disclosure relates to an equivalent application condition experiment circuit and an experiment method thereof. The equivalent application condition experiment circuit includes: a device under test and an integrated voltage-current source. The integrated voltage-current source is coupled to both ends of the device under test and one end is coupled to a reference ground, and is configured to: generate a voltage stress at both ends of the device under test when the device under test is in a blocking state; and generate a current stress at both ends of the device under test when the device under test is in a conducting state; wherein, the waveform changes of the voltage stress and the current stress both conform to the waveform changes of the corresponding electrical stress of the device under test in the actual application condition. The present disclosure simplifies the circuit structure, which is beneficial to reducing the construction and operation costs of the experimental platform.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics technology, and particularly to an equivalent application condition experiment circuit and an experiment method thereof. Background Art

[0002] Equivalent application condition experiment is to use a dedicated circuit and method to generate stress conditions similar to the application conditions of the device under test or the core device in the device under test, so as to verify the functional integrity and long-term reliability of the device under test during actual operation. In the example where the device under test is a power semiconductor device or a component of a converter valve group, a converter valve equivalent application condition experiment circuit can be used for the experiment to verify the power semiconductor device or the component of the converter valve group. However, in the related art, the topology of the existing converter valve equivalent application condition experiment circuit is complex, the number of power semiconductor devices is large, and the requirement for the control timing coordination accuracy is high, resulting in high construction and operation costs of the experiment platform. This not only is not conducive to the popularization and development of the converter valve equivalent stress condition experiment, but also raises the research and development and optimization thresholds of the power semiconductor devices and components used in the converter valve, and easily hinders the high-quality and rapid development of the UHV DC field. Summary of the Invention

[0003] Based on this, some embodiments of the present disclosure provide an equivalent application condition experiment circuit and an experiment method thereof, which simplify the circuit structure, are beneficial to reducing the construction and operation costs of the experiment platform, so as to promote the application of the converter valve equivalent stress condition experiment, and thus promote the high-quality and rapid development of the UHV DC field.

[0004] To achieve the above object, in a first aspect, some embodiments of the present disclosure provide an equivalent application condition experiment circuit, including: a device under test and an integrated voltage-current source. The integrated voltage-current source is coupled to both ends of the device under test and one end is coupled to the reference ground, and is configured to: generate a voltage stress at both ends of the device under test when the device under test is in a blocking state; and generate a current stress at both ends of the device under test when the device under test is in a conducting state; wherein the waveform changes of the voltage stress and the current stress both conform to the waveform changes of the corresponding electrical stress of the device under test in the actual application condition.

[0005] In some embodiments of the present disclosure, the integrated voltage-current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first semi-controlled power device, a second semi-controlled power device, and a reverse-blocking fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the reverse-blocking fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor and the cathode of the reverse-blocking fully-controlled device, and the other end is coupled to the cathodes of the first semi-controlled power device and the second semi-controlled power device; the other end of the first capacitor, the anode of the reverse-blocking fully-controlled device, and the anode of the first semi-controlled power device are all coupled to the negative pole of the DC voltage source; the anode of the second semi-controlled power device is coupled to the positive pole of the DC voltage source.

[0006] In some embodiments of the present disclosure, the module further includes a second capacitor. The second capacitor is coupled in parallel with the DC voltage source.

[0007] In some embodiments of the present disclosure, the first capacitor and / or the second capacitor includes: a single capacitor or multiple groups of capacitors connected in series and / or in parallel.

[0008] In some other embodiments of the present disclosure, the integrated voltage-current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first reverse-blocking fully-controlled device, a semi-controlled power device, and a second reverse-blocking fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the second reverse-blocking fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor and the cathode of the second reverse-blocking fully-controlled device, and the other end is coupled to the cathodes of the first reverse-blocking fully-controlled device and the semi-controlled power device; the other end of the first capacitor, the anode of the second reverse-blocking fully-controlled device, and the anode of the first reverse-blocking fully-controlled device are all coupled to the negative pole of the DC voltage source; the anode of the semi-controlled power device is coupled to the positive pole of the DC voltage source.

[0009] In some other embodiments of the present disclosure, the integrated voltage-current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a semi-controlled power device, a fully-controlled switch, and a reverse-blocking fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the reverse-blocking fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor and the cathode of the reverse-blocking fully-controlled device, and the other end is coupled to the cathode of the semi-controlled power device; the other end of the first capacitor, the anode of the reverse-blocking fully-controlled device, and the anode of the semi-controlled power device are all coupled to the negative pole of the DC voltage source. And, one end of the fully-controlled switch is coupled to the positive pole of the DC voltage source, and the other end is coupled to the cathode of the semi-controlled power device; or, one end of the fully-controlled switch is coupled to the negative pole of the DC voltage source, and the other end is coupled to the anode of the semi-controlled power device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the positive pole of the DC voltage source and the cathode of the semi-controlled power device, and a second fully-controlled switch connected in series between the negative pole of the DC voltage source and the anode of the semi-controlled power device.

[0010] In some other embodiments of the present disclosure, the integrated voltage-current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first reverse-blocking fully-controlled device, a fully-controlled switch, and a second reverse-blocking fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the second reverse-blocking fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor and the cathode of the second reverse-blocking fully-controlled device, and the other end is coupled to the cathode of the first reverse-blocking fully-controlled device; the other end of the first capacitor, the anode of the second reverse-blocking fully-controlled device, and the anode of the first reverse-blocking fully-controlled device are all coupled to the negative pole of the DC voltage source. And, one end of the fully-controlled switch is coupled to the positive pole of the DC voltage source, and the other end is coupled to the cathode of the first reverse-blocking fully-controlled device; or, one end of the fully-controlled switch is coupled to the negative pole of the DC voltage source, and the other end is coupled to the anode of the first reverse-blocking fully-controlled device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the positive pole of the DC voltage source and the cathode of the first reverse-blocking fully-controlled device, and a second fully-controlled switch connected in series between the negative pole of the DC voltage source and the anode of the first reverse-blocking fully-controlled device.

[0011] In some other embodiments of the present disclosure, the integrated voltage-current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a current-limiting resistor, a semi-controlled power device, a fully-controlled switch, and a reverse-blocking fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the reverse-blocking fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor, the cathode of the reverse-blocking fully-controlled device, and one end of the current-limiting resistor, and the other end is coupled to the cathode of the semi-controlled power device; the other end of the current-limiting resistor is coupled to the positive electrode of the DC voltage source; the other end of the first capacitor, the anode of the reverse-blocking fully-controlled device, and the anode of the semi-controlled power device are all coupled to the negative electrode of the DC voltage source. And, the fully-controlled switch is connected in series between the second inductor and the current-limiting resistor; or, the fully-controlled switch is connected in series between the negative electrode of the DC voltage source and the anode of the semi-controlled power device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the second inductor and the current-limiting resistor, and a second fully-controlled switch between the negative electrode of the DC voltage source and the anode of the semi-controlled power device.

[0012] In some other embodiments of the present disclosure, the integrated voltage-current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a current-limiting resistor, a first reverse-blocking fully-controlled device, a fully-controlled switch, and a second reverse-blocking fully-controlled device; wherein, one end of the first inductor is coupled to the cathode of the second reverse-blocking fully-controlled device, and the other end is the output end of the module; one end of the second inductor is coupled to one end of the first capacitor, the cathode of the second reverse-blocking fully-controlled device, and one end of the current-limiting resistor, and the other end is coupled to the cathode of the first reverse-blocking fully-controlled device; the other end of the current-limiting resistor is coupled to the positive electrode of the DC voltage source; the other end of the first capacitor, the anode of the second reverse-blocking fully-controlled device, and the anode of the first reverse-blocking fully-controlled device are all coupled to the negative electrode of the DC voltage source. And, the fully-controlled switch is connected in series between the second inductor and the current-limiting resistor; or, the fully-controlled switch is connected in series between the negative electrode of the DC voltage source and the anode of the first reverse-blocking fully-controlled device; or, the fully-controlled switch includes: a first fully-controlled switch connected in series between the second inductor and the current-limiting resistor, and a second fully-controlled switch between the negative electrode of the DC voltage source and the anode of the first reverse-blocking fully-controlled device.

[0013] In some embodiments of the present disclosure, the reference ground is the negative electrode of the DC voltage source.

[0014] In some embodiments of the present disclosure, the integrated voltage-current source includes a plurality of modules; the implementation manners of the integrated voltage-current source include any one of the following:

[0015] Embodiment 1: A plurality of the modules are connected in parallel; wherein, the grounding ends of the modules connected to the reference ground are mutually coupled, and the output ends of the modules are mutually coupled;

[0016] Embodiment 2: A plurality of the modules are connected in series; wherein, the output end of the latter-stage module is coupled to the grounding end of the former-stage module connected to the reference ground; the output end of the last-stage module is the output end of the integrated voltage-current source;

[0017] Embodiment 3: A plurality of the modules are connected in series-parallel; wherein, a plurality of the modules are connected in series to form multiple series experimental circuits with the same output voltage, and the multiple series experimental circuits are connected in parallel at both ends of the device under test.

[0018] In some embodiments of the present disclosure, the equivalent application condition experimental circuit further includes: a current source connected in parallel at both ends of the device under test; the integrated voltage-current source is multiplexed as a voltage source.

[0019] Optionally, the current source includes: a single-group six-pulse bridge current source, a two-group six-pulse thyristor bridge opposing inductor current source, or a fully controlled bridge current source.

[0020] In some embodiments of the present disclosure, the equivalent application condition experimental circuit further includes: a voltage source connected in parallel at both ends of the device under test; the integrated voltage-current source is multiplexed as a current source.

[0021] Optionally, the voltage source includes: a synthetic test voltage source, a DC modular multilevel topology voltage source, an AC modular multilevel topology voltage source, an AC energy-taking modular multilevel topology voltage source, or a multilevel DC link topology voltage source.

[0022] In a second aspect, some embodiments of the present disclosure further provide an experimental method for an equivalent application condition experimental circuit, which is used to perform an equivalent application condition experiment on the equivalent application condition experimental circuit in the above-mentioned some embodiments. The experimental method includes the following steps.

[0023] When the device under test is in a blocking state, the integrated voltage-current source generates a voltage stress at both ends of the device under test.

[0024] When the device under test is in a conducting state, the integrated voltage-current source generates a current stress at both ends of the device under test.

[0025] The waveform changes of the above voltage stress and current stress are both consistent with the waveform changes of the corresponding electrical stress of the device under test in the actual application conditions.

[0026] In some embodiments of the present disclosure, the equivalent application condition experimental circuit further includes: a current source connected in parallel across the device under test; wherein, the integrated voltage-current source can be reused as a voltage source.

[0027] In some other embodiments of the present disclosure, the equivalent application condition experimental circuit further includes: a voltage source connected in parallel across the device under test; wherein, the integrated voltage-current source can be reused as a current source.

[0028] The embodiments of the present disclosure may / at least have the following advantages:

[0029] In the embodiments of the present disclosure, by connecting an integrated voltage-current power supply across the device under test, and enabling the integrated voltage-current to generate a voltage stress across the device under test when the device under test is in a blocking state, and generating a current stress across the device under test when the device under test is in a conducting state, while ensuring that the waveform changes of the voltage stress and the current stress both conform to the waveform changes of the corresponding electrical stresses in the actual application conditions of the device under test. In this way, the embodiments of the present disclosure can, by combining the functions of a voltage source and a current source, generate all the current and voltage stress waveforms required for the experiment with only a small number of components and the open-loop logic cooperation of the sequence, simplify the circuit structure, and is conducive to reducing the construction and operation costs of the experimental platform, so as to promote the application of stress condition experiments such as converter valves, thereby promoting the high-quality and rapid development of the UHV DC field.

[0030] Furthermore, the experimental circuit provided by the embodiments of the present disclosure is modularly arranged, that is: multiple groups of modules can be directly cascaded, so as to achieve a doubling of the voltage and current experimental test ranges. In this way, the experimental platform can configure the number of modules according to the experimental requirements, and can also increase the number of modules according to its development requirements, having better construction flexibility.

[0031] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0033] Figure 1 It is a schematic diagram of the topological structure of an equivalent application condition experimental circuit provided in some embodiments;

[0034] Figure 2For Figure 1 Schematic diagram of an electrical stress waveform generated by the equivalent application condition experimental circuit shown;

[0035] Figure 3 Schematic diagram of the topology of the voltage source in an equivalent application condition experimental circuit provided in some embodiments;

[0036] Figure 4 Schematic diagram of the topology of the current source in an equivalent application condition experimental circuit provided in some embodiments;

[0037] Figure 5 Schematic diagram of the topology of another equivalent application condition experimental circuit provided in some embodiments;

[0038] Figure 6 Schematic diagram of the topology of a single module in another equivalent application condition experimental circuit provided in some embodiments;

[0039] Figure 7 For Figure 6 Schematic diagram of an electrical stress waveform generated by the equivalent application condition experimental circuit shown;

[0040] Figure 8 Schematic diagram of the topology of another single module in another equivalent application condition experimental circuit provided in some embodiments;

[0041] Figure 9 For Figure 8 Schematic diagram of an electrical stress waveform generated by the equivalent application condition experimental circuit shown;

[0042] Figure 10 Schematic diagram of the topology of another single module in another equivalent application condition experimental circuit provided in some embodiments;

[0043] Figure 11 Schematic diagram of the topology of another single module in another equivalent application condition experimental circuit provided in some embodiments;

[0044] Figure 12 Schematic diagram of the topology of another single module in another equivalent application condition experimental circuit provided in some embodiments;

[0045] Figure 13 Schematic diagram of the topology of another single module in another equivalent application condition experimental circuit provided in some embodiments;

[0046] Figure 14 Schematic diagram of the topology of another single module in another equivalent application condition experimental circuit provided in some embodiments;

[0047] Figure 15 Schematic diagram of another topological structure of a single module in another equivalent application condition experimental circuit provided in some embodiments;

[0048] Figure 16 Schematic diagram of another topological structure of a single module in another equivalent application condition experimental circuit provided in some embodiments;

[0049] Figure 17 Schematic diagram of another topological structure of a single module in another equivalent application condition experimental circuit provided in some embodiments;

[0050] Figure 18 Schematic diagram of another topological structure of a single module in another equivalent application condition experimental circuit provided in some embodiments;

[0051] Figure 19 Schematic diagram of another topological structure of a single module in another equivalent application condition experimental circuit provided in some embodiments;

[0052] Figure 20 Schematic diagram of another topological structure of a single module in another equivalent application condition experimental circuit provided in some embodiments;

[0053] Figure 21 Schematic diagram of another topological structure of a single module in another equivalent application condition experimental circuit provided in some embodiments;

[0054] Figure 22 Schematic diagram of a topological structure of cascaded multiple modules in another equivalent application condition experimental circuit provided in some embodiments;

[0055] Figure 23 Schematic diagram of another topological structure of cascaded multiple modules in another equivalent application condition experimental circuit provided in some embodiments;

[0056] Figure 24 Schematic diagram of another topological structure of cascaded multiple modules in another equivalent application condition experimental circuit provided in some embodiments;

[0057] Figure 25 Schematic diagram of a topological structure of parallel-connected multiple modules in another equivalent application condition experimental circuit provided in some embodiments;

[0058] Figure 26 Schematic diagram of a topological structure of series-connected multiple modules in another equivalent application condition experimental circuit provided in some embodiments;

[0059] Figure 27 Schematic diagram of a topological structure of another equivalent application condition experimental circuit provided in some embodiments;

[0060] Figure 28 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0061] Figure 29 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0062] Figure 30 For Figure 29 Schematic diagram of an electrical stress waveform generated by the equivalent application condition experimental circuit shown;

[0063] Figure 31 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0064] Figure 32 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0065] Figure 33 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0066] Figure 34 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0067] Figure 35 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0068] Figure 36 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0069] Figure 37 For Figure 26 Schematic diagram of an electrical stress waveform generated by the equivalent application condition experimental circuit shown;

[0070] Figure 38 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0071] Figure 39 For Figure 38 Schematic diagram of an electrical stress waveform generated by the equivalent application condition experimental circuit shown;

[0072] Figure 40 Schematic diagram of the topology of yet another equivalent application condition experimental circuit provided in some embodiments;

[0073] Figure 41Schematic diagram of the topology structure of another equivalent application condition experimental circuit provided in some embodiments;

[0074] Figure 42 Schematic diagram of the topology structure of another equivalent application condition experimental circuit provided in some embodiments;

[0075] Figure 43 Schematic diagram of the topology structure of another equivalent application condition experimental circuit provided in some embodiments;

[0076] Figure 44 Schematic diagram of the topology structure of another equivalent application condition experimental circuit provided in some embodiments;

[0077] Figure 45 Schematic diagram of the topology structure of another equivalent application condition experimental circuit provided in some embodiments;

[0078] Figure 46 Schematic diagram of the topology structure of another equivalent application condition experimental circuit provided in some embodiments;

[0079] Figure 47 Schematic diagram of the topology structure of another equivalent application condition experimental circuit provided in some embodiments. Detailed implementation manners

[0080] For ease of understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is more thorough and comprehensive.

[0081] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein in the description of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0082] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, or part discussed below may be denoted as the second element, component, region, layer, or part.

[0083] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In addition, in the following embodiments, "connection", if there is transmission of electrical signals or data between the connected objects, should be understood as "electrical connection", "communication connection", etc.

[0084] It should be understood that the singular forms of "a", "an" and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprise / include" or "have", etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the related listed items.

[0085] The equivalent application condition experiment uses a dedicated circuit and method to generate stress conditions similar to the application conditions of the device under test or the core device in the device under test, so as to verify the functional integrity and long-term reliability of the device under test during actual operation. Currently, in the example where the device under test is a power semiconductor device or a component of a converter valve group, a converter valve equivalent application condition experiment circuit can be used for the experiment to verify the power semiconductor device or the component of the converter valve group.

[0086] The equivalent application condition experiment is an important means to verify the functional integrity and long-term reliability of power semiconductor devices or components of converter valve groups during actual operation.

[0087] In some embodiments, the components of the equivalent application condition experiment circuit are schematically shown as Figure 1 , where the voltage source, current source and the device under test are in a parallel relationship in terms of topology. During the equivalent application condition experiment, the control instructions of the voltage source, current source and the device under test cooperate with each other in terms of timing. Among them, the voltage source applies voltage stress to the device under test when it is in the blocking state, and the current source applies current stress to the device under test when it is in the conducting state. The electrical stress waveforms generated by the two are as shown in Figure 2 to be used for the actual operation conditions of the equivalent converter valve.

[0088] Exemplarily, Figure 3 shows the topology of a voltage source in an equivalent application condition experiment circuit. The voltage stress output by the voltage source comes from the voltage of capacitor C 1 , where capacitor C 1 and inductor L 1 and inductor L 2 form two pairs of series resonance circuits. The semi-controlled power devices V 3 and V 5Respectively used to start the aforementioned two groups of series resonance circuits, the semi-controlled power device V 2 Used to control the DC voltage source u DC Is the capacitor C 1 Recovery voltage, the semi-controlled power device V 4 Used to provide a negative voltage stress output channel when the voltage of the capacitor C 1 Is negative. At Figure 2 The shown t 1 To t 2 During the time period, the voltage of the capacitor C 1 Is positive; at t 2 Moment, the semi-controlled power device V 3 Conducts, the inductor L 1 Is in series resonance with the capacitor C 1 The inductor L 1 The current increases first and then decreases sinusoidally, and the voltage of the capacitor C 1 Decreases from positive to negative; at t 3 Moment, the current of the inductor L 1 Negatively crosses zero, the semi-controlled power device V 3 Automatically turns off, the voltage of the capacitor C 1 Reaches the minimum value, the semi-controlled power device V 4 Conducts, and the voltage source outputs negative voltage stress; at t 4 Moment, the semi-controlled power device V 5 Conducts, the capacitor C 1 Is in series resonance with the inductor L 2 The inductor L 2 The current increases first and then decreases sinusoidally, and the voltage of the inductor capacitor C 1 Increases from negative to positive; at t 5 Moment, the semi-controlled power device V 3 Conducts, and the voltage source outputs positive voltage stress; at t 6 Moment, the semi-controlled power device V 2 Conducts, the DC voltage source u DC1 Charges the capacitor C 2 Through the inductor L 1 The capacitor C 1 The voltage finally becomes consistent with the voltage of the DC voltage source u DC1 Voltage.

[0089] Exemplarily, Figure 4 The topology structure of a current source in an equivalent application condition experiment circuit is shown in 3 The working principle of this current source is that two groups of six-pulse bridge converters operate in a counter-towing manner, generating a constant current on the inductor L Figure 2 In the shown t 1 To t 3 During the time period, the device under test and the semi-controlled power device V 1The bridge arm is in the commutation conduction period, and the inductor L 3 The current of the semi-controlled power device V 1 To prevent the voltage stress of the voltage source from affecting the isolation valve of the current source operation, the device under test is 1 They are triggered to conduct at the same time.

[0090] As mentioned above, the topological structure of the equivalent application condition experimental circuit is complex, the number of power semiconductor devices is large, and the control timing coordination accuracy requirements are high, resulting in high construction and operation costs of the experimental platform. This is not only not conducive to the promotion and development of equivalent stress condition experiments for converter valves, but also raises the research and development and optimization threshold for power semiconductor devices and components for converter valves, which is likely to hinder the high-quality and rapid development of the UHV DC field.

[0091] Based on this, in order to reduce the construction and operation costs of the converter valve equivalent application condition experimental platform, the embodiment of the present disclosure provides a concise equivalent application condition experimental circuit and experimental method, which can generate all the current and voltage stress waveforms required for the experiment by the same circuit by combining the voltage source and current source functions, with only a small number of components and sequential open-loop logic coordination. Furthermore, the experimental circuit provided by the embodiment of the present disclosure is modular, that is, multiple groups of circuit modules can be directly cascaded to achieve a doubling of the voltage and current experimental test range. In this way, the experimental platform can configure the number of modules according to the experimental requirements, and can also increase the number of modules according to its development requirements, with better construction flexibility.

[0092] In some embodiments of the present disclosure, please refer to Figure 5 The equivalent application condition experimental circuit includes: a device under test and an integrated voltage and current power supply. The integrated voltage and current source is coupled to both ends of the device under test and one end is coupled to the reference ground, and is configured to: generate voltage stress at both ends of the device under test when the device under test is in a blocking state; and generate current stress at both ends of the device under test when the device under test is in a conducting state; wherein the waveform changes of the voltage stress and the current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions.

[0093] Accordingly, some embodiments of the present disclosure further provide an experimental method for an equivalent application working condition experimental circuit, which is used to perform an equivalent application working condition experiment on the equivalent application working condition experimental circuit described in some of the above embodiments. The experimental method includes the following steps S100 and S200.

[0094] S100, when the device under test is in a blocking state, the integrated voltage and current power supply generates voltage stress at both ends of the device under test.

[0095] S200. When the device under test is in the conducting state, the integrated voltage-current power supply generates current stress at both ends of the device under test.

[0096] Here, the waveform changes of the voltage stress and the current stress both conform to the waveform changes of the corresponding electrical stress of the device under test in the actual application working condition, which means that: the waveform changes of the voltage stress and the current stress are equivalent and the same as the waveform changes of the corresponding electrical stress of the device under test in the actual application working condition, or they are similar within the target deviation range, or the waveforms of the voltage stress and the current stress are the accelerated degradation stress waveforms of the corresponding electrical stress of the device under test in the actual application working condition.

[0097] Exemplarily, the voltage stress and the current stress are the equivalent electrical stress or the accelerated degradation stress of the corresponding electrical stress of the device under test in the actual application working condition.

[0098] In the embodiments of the present disclosure, by connecting an integrated voltage-current power supply to both ends of the device under test, and enabling the integrated voltage-current to generate voltage stress at both ends of the device under test when the device under test is in the blocking state and generate current stress at both ends of the device under test when the device under test is in the conducting state, while ensuring that the waveform changes of the voltage stress and the current stress both conform to the waveform changes of the corresponding electrical stress of the device under test in the actual application working condition. Thus, the embodiments of the present disclosure can, by combining the functions of the voltage source and the current source, generate all the current and voltage stress waveforms required for the experiment with only a small number of components and the open-loop logic cooperation of the sequence, simplify the circuit structure, be beneficial to reducing the construction and operation costs of the experimental platform, so as to promote the application of the stress condition experiments such as converter valves, and thus promote the high-quality and rapid development of the UHV DC field.

[0099] In some embodiments of the present disclosure, please refer to Figure 6 , the integrated voltage-current source includes at least one module, and the module includes: a DC voltage source u DC2 , a first inductor L 4 , a second inductor L 5 , a first capacitor C 3 , a first semi-controlled power device V 7 , a second semi-controlled power device V 8 , and a reverse-blocking fully-controlled device V 6 . Among them, one end of the first inductor L 4 is coupled to the cathode of the reverse-blocking fully-controlled device V 6 , and the other end is the output end of the module. One end of the second inductor L 5 is coupled to one end of the first capacitor C 3 and the cathode of the reverse-blocking fully-controlled device V 6 , and the other end is coupled to the cathode of the first semi-controlled power device V 7 and the cathode of the second semi-controlled power device V 8is coupled to the cathode. The first capacitor C 3 The other end of, the reverse-blocking fully-controlled device V 6 The anode of and the first semi-controlled power device V 7 The anode of are all coupled to the negative pole of the DC voltage source u DC2 The second semi-controlled power device V 8 The anode of is coupled to the positive pole of the DC voltage source u DC2

[0100] In some embodiments of the present disclosure, please continue to refer to Figure 6 , the module of the integrated voltage-current source further includes a second capacitor C 4 . The second capacitor C 4 Is coupled in parallel with the DC voltage source u DC2 Thus, when the DC voltage source u DC2 Is a non-ideal DC voltage source, the second capacitor C 4 Is coupled in parallel with the non-ideal DC voltage source u DC2 And can serve as a voltage stabilizing capacitor to provide a stable input DC voltage for the circuit.

[0101] In some embodiments of the present disclosure, the semi-controlled power device refers to: a power semiconductor device and combination that can only be controlled to turn on but not turn off through the gate. Exemplarily, the first semi-controlled power device V 7 And / or the second semi-controlled power device V 8 Includes but is not limited to: thyristors.

[0102] In some embodiments of the present disclosure, the reverse-blocking fully-controlled device refers to: a power semiconductor device and combination that has bidirectional voltage blocking ability and can be controlled to turn on and off through the gate.

[0103] Exemplarily, the reverse-blocking fully-controlled device V 6 Includes but is not limited to: gate turn-off thyristors, integrated gate-commutated thyristors, reverse-blocking insulated-gate bipolar transistors (Insulate-Gate Bipolar Transistor, abbreviated as IGBT), power semiconductor devices with series diodes for blocking unidirectional voltage and controlling the switch through the gate, metal-oxide semiconductor field-effect thyristors (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as MOSFET) in series with the common source / emitter, insulated-gate bipolar transistors in series with the common source / emitter, metal-oxide semiconductor field-effect thyristors in series with the common drain / collector, insulated-gate bipolar transistors in series with the common drain / collector, insulated-gate bipolar transistors in series with the common collector and anti-parallel diodes, or insulated-gate bipolar transistors in series with the common emitter and anti-parallel diodes.

[0104] ​In some embodiments of the present disclosure, the first inductor L 4 and / or the second inductor L 5 include, but are not limited to: a single inductor composed of a fixed inductor or a tunable inductor, or multiple sets of inductors formed by series-parallel connection of either a fixed inductor or a tunable inductor.

[0105] In some embodiments of the present disclosure, the first capacitor C 3 and / or the second capacitor C 4 include, but are not limited to: a single capacitor or multiple sets of capacitors connected in series or parallel.

[0106] In some embodiments of the present disclosure, the reference ground is the negative pole of the DC voltage source u DC2 of.

[0107] As described above, the equivalent operating condition application experimental circuit provided by the embodiments of the present disclosure adopts a modular setting, that is: its integrated voltage-current source can adopt a single module or multiple sets of modules directly cascaded to achieve a doubling of the voltage-current experimental range.

[0108] In some embodiments, the structure of the integrated voltage-current source is as Figure 6 shown, and a single module is adopted. After performing the equivalent application operating condition experiment based on the integrated voltage-current source shown in Figure 6 , the integrated voltage-current source composed of the single module can generate a voltage-current stress waveform as shown in Figure 7 on the device under test.

[0109] Exemplarily, please refer to Figure 6 and Figure 7 for understanding. In the equivalent application operating condition experimental circuit with the integrated voltage-current source shown in Figure 6 , the process of generating voltage-current stress by the integrated voltage-current source in its experimental method can be specifically referred to the relevant descriptions at each of the following moments.

[0110] Before the moment of t 1 , the device under test is in a blocking state, and the first capacitor C 3 applies a positive voltage stress to the device under test.

[0111] At the moment of t 1 , the device under test is in a conducting state, and the first capacitor C 3 is in series resonance with the first inductor L 4 , the voltage of the first capacitor C 3 drops, and the current of the first inductor L 4 rises and starts to apply a current stress to the device under test.

[0112] At the moment of t 2 , the voltage of the first capacitor C 3 drops to zero, and the first inductor L4 The current of 6 rises to the maximum value, and the reverse-blocking fully-controlled device V

[0113] conducts. 2 From the moment of t 3 to the moment of t 4 the first inductor L 6 continues to conduct current through the device under test and the reverse-blocking fully-controlled device V 4 and the current of the first inductor L

[0114] and the current stress of the device under test are approximately maintained unchanged. 3 At the moment of t 6 the current stress duration of the device under test reaches the equivalent condition, and the reverse-blocking fully-controlled device V 4 actively shuts off, and the first inductor L 3 continues to resonate in series with the device under test and the first capacitor C 3 the voltage of the first capacitor C 4 negatively increases, and the current of the first inductor L

[0115] and the current stress of the device under test decrease sinusoidally. 4 At the moment of t 4 the current of the first inductor L 3 and the current stress of the device under test drop to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C

[0116] drops to the minimum value and outputs a continuous negative voltage stress for the device under test. 5 At the moment of t 7 the first semi-controlled power device V 5 conducts, and the second inductor L 3 resonates in series with the first capacitor C 7 the first semi-controlled power device V 5 resumes the blocking state when the current of the second inductor L 3 drops through zero, and the voltage of the first capacitor C

[0117] and the voltage stress of the device under test change from negative to positive during the resonance process. 6 At the moment of t 8 the second semi-controlled power device V DC2 conducts, and the DC voltage source u 5 charges the first capacitor C 3 to supplement the loss consumption, and the voltage of the first capacitor C 3 eventually becomes consistent with the voltage of the DC voltage source u DC2 to have the ability to repeat the test in the next cycle.

[0118] The above moment of t 1 ~t6 The time points of the moments only represent the sequence of occurrence, and the time intervals between the moments can be adjusted according to the experimental requirements and circuit parameters.

[0119] In some other embodiments of the present disclosure, please refer to Figure 8 , the integrated voltage-current source includes at least one module, and the module includes: a DC voltage source u DC2 , a first inductor L 4 , a second inductor L 5 , a first capacitor C 3 , a first reverse-blocking fully-controlled device V 7 , a semi-controlled power device V 8 , and a second reverse-blocking fully-controlled device V 6 . Among them, one end of the first inductor L 4 is coupled to the cathode of the second reverse-blocking fully-controlled device V 6 , and the other end is the output end of the module. One end of the second inductor L 5 is coupled to one end of the first capacitor C 3 and the cathode of the second reverse-blocking fully-controlled device V 6 , and the other end is coupled to the cathode of the first reverse-blocking fully-controlled device V 7 and the cathode of the semi-controlled power device V 8 . The other end of the first capacitor C 3 , the anode of the second reverse-blocking fully-controlled device V 6 and the anode of the first reverse-blocking fully-controlled device V 7 are all coupled to the negative pole of the DC voltage source u DC2 . The anode of the semi-controlled power device V 8 is coupled to the positive pole of the DC voltage source u DC2 .

[0120] Compared with Figure 6 the integrated voltage-current source shown, the integrated voltage-current source in the embodiments of the present disclosure uses the first reverse-blocking fully-controlled device V 7 to replace the first semi-controlled power device V 7 . After performing the equivalent application condition experiment based on Figure 8 the integrated voltage-current source shown, the integrated voltage-current source composed of this single module can generate the voltage-current stress waveform as shown in Figure 9 on the device under test.

[0121] Before the moment of t 1 , the device under test is in a blocking state, and the first capacitor C 3 applies a positive voltage stress to the device under test.

[0122] At the moment of t 1 , the device under test is in a conducting state, and the first capacitor C3 in series resonance with the first inductor L 4 the voltage of the first capacitor C drops, and the current of the first inductor L 3 rises and begins to apply current stress to the device under test. 4

[0123] At time t 2 the voltage of the first capacitor C 3 drops to zero, the current of the first inductor L 4 rises to the maximum value, and the second reverse-blocking fully-controlled device V 6 turns on.

[0124] At time t 2 to time t 3 the first inductor L 4 continues to conduct current through the device under test and the second reverse-blocking fully-controlled device V 6 and the current of the first inductor L 4 and the current stress of the device under test are approximately maintained constant.

[0125] At time t 3 the duration of the current stress of the device under test reaches the equivalent condition, the second reverse-blocking fully-controlled device V 6 actively turns off, and the first inductor L 4 continues to resonate in series with the device under test and the first capacitor C 3 the voltage of the first capacitor C 3 increases negatively, and the current of the first inductor L 4 and the current stress of the device under test decrease sinusoidally.

[0126] At time t 4 the current of the first inductor L 4 and the current stress of the device under test drop to zero, the device under test resumes the blocking state, and at this time the voltage of the first capacitor C 3 drops to the minimum value and outputs a continuous negative voltage stress to the device under test.

[0127] At time t 5 the first reverse-blocking fully-controlled device V 7 turns on, the second inductor L 5 resonates in series with the first capacitor C 3 the current of the second inductor L 5 decreases sinusoidally, and the voltage of the first capacitor C 3 increases sinusoidally.

[0128] At time t 6 the current of the second inductor L 5 negatively crosses zero, and the first capacitor C 3 ​The voltage and the positive voltage stress of the device under test reach the maximum value, and the first reverse-blocking fully-controlled device V 7 actively shuts down to cut off the series resonance of this branch.

[0129] At time t 7 , the second semi-controlled power device V 8 conducts, and the DC voltage source u DC2 charges the first capacitor C 5 through the second inductor L 3 to supplement the loss consumption. The voltage of the first capacitor C 3 eventually becomes consistent with the voltage of the DC voltage source u DC2 to have the ability to repeat the test in the next cycle.

[0130] The time points from the above-mentioned time t 1 to time t 7 only represent the sequence of occurrence, and the time intervals between each time point can be adjusted according to the experimental requirements and circuit parameters.

[0131] In some other embodiments of the present disclosure, please refer to Figures 10 - 12 , the integrated voltage-current source includes at least one module, and the module includes: a DC voltage source u DC2 , a first inductor L 4 , a second inductor L 5 , a first capacitor C 3 , a semi-controlled power device V 7 , a fully-controlled switch V 8 , and a reverse-blocking fully-controlled device V 6 . Among them, one end of the first inductor L 4 is coupled to the cathode of the reverse-blocking fully-controlled device V 6 , and the other end is the output end of the module. One end of the second inductor L 5 is coupled to one end of the first capacitor C 3 and the cathode of the reverse-blocking fully-controlled device V 6 , and the other end is coupled to the cathode of the semi-controlled power device V 7 . The other end of the first capacitor C 3 , the anode of the reverse-blocking fully-controlled device V 6 , and the anode of the semi-controlled power device V 7 are all coupled to the negative pole of the DC voltage source u DC2 .

[0132] Optionally, as shown in Figure 10 , one end of the fully-controlled switch V 8 is coupled to the positive pole of the DC voltage source u DC2 , and the other end is coupled to the cathode of the semi-controlled power device V 7 .

[0133] Optionally, as shown in Figure 11 , one end of the fully controlled switch V 8 is coupled to the negative pole of the DC voltage source u DC2 , and the other end is coupled to the anode of the semi-controlled power device V 7 .

[0134] Optionally, as shown in Figure 12 , the fully controlled switch includes: a first fully controlled switch V DC2 connected in series between the positive pole of the DC voltage source u 7 and the cathode of the semi-controlled power device V 81 , and a second fully controlled switch V DC2 connected in series between the negative pole of the DC voltage source u 7 and the anode of the semi-controlled power device V 82 .

[0135] Compared with the integrated voltage-current source shown in Figure 6 , the integrated voltage-current source in the embodiments of the present disclosure uses the fully controlled switch V 8 to replace the second semi-controlled power device V 8 . The fully controlled switch V 8 refers to: an element that can control the on and off of the branch where it is located through a signal, including but not limited to relays, contactors, and fully controlled power semiconductor devices, etc. After performing equivalent application condition experiments based on the integrated voltage-current source shown in Figures 10 - 12 , the voltage-current stress waveform that the integrated voltage-current source composed of this single module can generate on the device under test can be understood with reference to Figure 9 .

[0136] Before the moment t 1 , the device under test is in the blocking state, and the first capacitor C 3 applies a positive voltage stress to the device under test.

[0137] At the moment t 1 , the device under test is in the on state, and the first capacitor C 3 resonates in series with the first inductor L 4 . The voltage of the first capacitor C 3 drops, and the current of the first inductor L 4 rises and starts to apply current stress to the device under test.

[0138] At the moment t 2 , the voltage of the first capacitor C 3 drops to zero, the current of the first inductor L 4 rises to the maximum value, and the reverse-blocking fully controlled device V 6 turns on.

[0139] At the moment t 2From the moment to t 3 During the time period of the moment, the first inductor L 4 Continues to flow through the device under test and the reverse-blocking fully-controlled device V 6 For freewheeling, the current of the first inductor L 4 And the current stress of the device under test approximately remain unchanged.

[0140] At t 3 When the moment arrives, the current stress duration of the device under test reaches the equivalent condition, and the reverse-blocking fully-controlled device V 6 Actively shuts off, and the first inductor L 4 Continues to resonate in series through the device under test and the first capacitor C 3 The voltage of the first capacitor C 3 Negatively increases, and the current of the first inductor L 4 And the current stress of the device under test sinusoidally decrease.

[0141] At t 4 When the moment arrives, the current of the first inductor L 4 And the current stress of the device under test decrease to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C 3 Decreases to the minimum value and outputs a continuous negative voltage stress for the device under test.

[0142] At t 5 When the moment arrives, the semi-controlled power device V 7 Conducts, and the second inductor L 5 Resonates in series with the first capacitor C 3 The semi-controlled power device V 7 Resumes the blocking state when the current of the second inductor L 5 Decreases through zero. The voltage of the first capacitor C 3 And the voltage stress of the device under test change from negative to positive during the resonance process and reach the maximum value at t 6 When the moment arrives.

[0143] At t 7 When the moment arrives, the fully-controlled switch V 8 Conducts, and the DC voltage source u DC2 Charges the first capacitor C 5 Through the second inductor L to supplement the consumed losses. The voltage of the first capacitor C 3 Ultimately becomes consistent with the voltage of the DC voltage source u 3 And the fully-controlled switch V DC2 Disconnects this charging branch before the t 8 Moment of the next experimental cycle to have the ability to repeat the test in the next cycle. 1 In some other embodiments of the present disclosure, please refer to

[0144] In some other embodiments of the present disclosure, please refer to Figures 13 - 15, the integrated voltage-current source includes at least one module, and the module includes: a DC voltage source u DC2 , a first inductor L 4 , a second inductor L 5 , a first capacitor C 3 , a first reverse-blocking fully-controlled device V 7 , a fully-controlled switch V 8 and a second reverse-blocking fully-controlled device V 6 . Among them, one end of the first inductor L 4 is coupled to the cathode of the second reverse-blocking fully-controlled device V 6 , and the other end is the output end of the module. One end of the second inductor L 5 is coupled to one end of the first capacitor C 3 and the cathode of the second reverse-blocking fully-controlled device V 6 , and the other end is coupled to the cathode of the first reverse-blocking fully-controlled device V 7 . The other end of the first capacitor C 3 , the anode of the second reverse-blocking fully-controlled device V 6 and the anode of the first reverse-blocking fully-controlled device V 7 are all coupled to the negative pole of the DC voltage source u DC2 .

[0145] Optionally, as shown in Figure 13 , one end of the fully-controlled switch V 8 is coupled to the positive pole of the DC voltage source u DC2 , and the other end is coupled to the cathode of the first reverse-blocking fully-controlled device V 7 .

[0146] Optionally, as shown in Figure 14 , one end of the fully-controlled switch V 8 is coupled to the negative pole of the DC voltage source u DC2 , and the other end is coupled to the anode of the first reverse-blocking fully-controlled device V 7 .

[0147] Optionally, as shown in Figure 15 , the fully-controlled switch includes: a first fully-controlled switch V DC2 connected in series between the positive pole of the DC voltage source u 7 and the cathode of the first reverse-blocking fully-controlled device V 81 , and a second fully-controlled switch V DC2 connected in series between the negative pole of the DC voltage source u 7 and the anode of the first reverse-blocking fully-controlled device V 82 .

[0148] Compared with the integrated voltage-current source shown in Figure 6 , the integrated voltage-current source in the embodiments of the present disclosure uses the first reverse-blocking fully-controlled device V7 replaces the first semi-controlled power device V 7 , and at the same time, a fully controlled switch V 8 replaces the second semi-controlled power device V 8 . After conducting an equivalent application condition experiment based on the integrated voltage-current source shown in Figures 13 - 15 , the voltage-current stress waveforms that the integrated voltage-current source composed of this single module can generate on the device under test can be understood with reference to Figure 9 .

[0149] Before time t 1 , the device under test is in a blocking state, and the first capacitor C 3 applies a positive voltage stress to the device under test.

[0150] At time t 1 , the device under test is in a conducting state, and the first capacitor C 3 is in series resonance with the first inductor L 4 . The voltage of the first capacitor C 3 drops, and the current of the first inductor L 4 rises and starts to apply a current stress to the device under test.

[0151] At time t 2 , the voltage of the first capacitor C 3 drops to zero, the current of the first inductor L 4 rises to the maximum value, and the second reverse-blocking fully controlled device V 6 conducts.

[0152] During the time period from time t 2 to time t 3 , the first inductor L 4 continues to conduct current through the device under test and the second reverse-blocking fully controlled device V 6 . The current of the first inductor L 4 and the current stress of the device under test approximately remain unchanged.

[0153] At time t 3 , the duration of the current stress of the device under test reaches the equivalent condition, the second reverse-blocking fully controlled device V 6 actively shuts off, and the first inductor L 4 continues to be in series resonance with the first capacitor C 3 through the device under test. The voltage of the first capacitor C 3 increases negatively, and the current of the first inductor L 4 and the current stress of the device under test decrease sinusoidally.

[0154] At time t 4 , the first inductor L 4The current of and the current stress of the device under test drop to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C 3 drops to the minimum value and outputs a continuous negative voltage stress to the device under test.

[0155] At time t 5 , the first reverse-blocking fully controlled power device V 7 conducts, and the second inductor L 5 resonates in series with the first capacitor C 3 . The current of the second inductor L 5 decreases sinusoidally, and the voltage of the first capacitor C 3 increases sinusoidally.

[0156] At time t 6 , the current of the second inductor L 5 negatively crosses zero, the voltage of the first capacitor C 3 and the positive voltage stress of the device under test reach the maximum value, and the first reverse-blocking fully controlled device V 7 actively shuts off to cut off the series resonance of this branch.

[0157] At time t 7 , the fully controlled switch V 8 conducts, and the DC voltage source u DC2 charges the first capacitor C 5 through the second inductor L 3 to supplement the loss consumption. The voltage of the first capacitor C 3 eventually becomes consistent with the voltage of the DC voltage source u DC2 , and the fully controlled switch V 8 disconnects this charging branch before time t 1 of the next experimental cycle to have the ability to repeat the test in the next cycle.

[0158] In some other embodiments of the present disclosure, please refer to Figures 16 - 18 . The integrated voltage-current source includes at least one module, and the module includes: a DC voltage source u DC2 , a first inductor L 4 , a second inductor L 5 , a first capacitor C 3 , a current-limiting resistor R 1 , a semi-controlled power device V 7 , a fully controlled switch V 8 , and a reverse-blocking fully controlled device V 6 . Among them, one end of the first inductor L 4 is coupled to the cathode of the reverse-blocking fully controlled device V 6 , and the other end is the output end of the module. One end of the second inductor L 5 is connected to one end of the first capacitor C 3 , the cathode of the reverse-blocking fully controlled device V6 and the current-limiting resistor R of the cathode 1 is coupled to one end, and the other end is connected to the semi-controlled power device V 7 of the cathode. The current-limiting resistor R 1 is connected to the other end of the DC voltage source u DC2 of the positive electrode. The first capacitor C 3 is connected to the other end, the reverse-blocking fully-controlled device V 6 is connected to the anode, and the semi-controlled power device V 7 is connected to the anode of the DC voltage source u DC2 of the negative electrode.

[0159] Optionally, as shown in Figure 16 , the fully-controlled switch V 8 is connected in series between the second inductor L 5 and the current-limiting resistor R 1 .

[0160] Optionally, as shown in Figure 17 , the fully-controlled switch V 8 is connected in series between the negative electrode of the DC voltage source u DC2 and the anode of the semi-controlled power device V 7 .

[0161] Optionally, as shown in Figure 18 , the fully-controlled switch includes: connected in series between the second inductor L 5 and the current-limiting resistor R 1 the first fully-controlled switch V 81 , and connected in series between the negative electrode of the DC voltage source u DC2 and the anode of the semi-controlled power device V 7 the second fully-controlled switch V 82 .

[0162] Compared with Figure 6 the integrated voltage-current source shown, the integrated voltage-current source in the embodiments of the present disclosure adds a current-limiting resistor R 1 , and uses a fully-controlled switch V 8 to replace the second semi-controlled power device V 8 . It can charge the first capacitor C 1 under the control of the fully-controlled switch V 8 for replacing the charging branch of the second inductor L 3 . The embodiments of the present disclosure adopt a resistor-capacitor charging method, which can ensure that the voltage stress of the device under test increases more smoothly and with less oscillation and less generation of spikes during the voltage recovery process of the first capacitor C 5 . Correspondingly, the embodiments of the present disclosure adopt a fully-controlled switch V 3 8 ​, it can not only avoid the problem that the blocking state cannot be reliably restored due to the lack of the zero-crossing point of current oscillation when using semi-controlled power devices, but also effectively reduce the risk of the working state being damaged by the re-conduction of the semi-controlled power device and the introduction of a DC voltage source when the voltage of the first capacitor C 3 drops significantly due to series resonance.

[0163] After the equivalent application condition experiment is carried out based on the integrated voltage-current source shown in Figures 16 - 18 , the voltage-current stress waveform that can be generated by the integrated voltage-current source composed of this single module on the device under test can be referred to Figure 9 for understanding.

[0164] Before the moment of t 1 , the device under test is in the blocking state, and the first capacitor C 3 applies a positive voltage stress to the device under test.

[0165] At the moment of t 1 , the device under test is in the conducting state, and the first capacitor C 3 is in series resonance with the first inductor L 4 , the voltage of the first capacitor C 3 drops, and the current of the first inductor L 4 rises and begins to apply a current stress to the device under test.

[0166] At the moment of t 2 , the voltage of the first capacitor C 3 drops to zero, the current of the first inductor L 4 rises to the maximum value, and the reverse-blocking fully-controlled device V 6 conducts.

[0167] At the time period from the moment of t 2 to the moment of t 3 , the first inductor L 4 continues to conduct current through the device under test and the reverse-blocking fully-controlled device V 6 , and the current of the first inductor L 4 and the current stress of the device under test are approximately maintained unchanged.

[0168] At the moment of t 3 , the duration of the current stress of the device under test reaches the equivalent condition, the reverse-blocking fully-controlled device V 6 actively turns off, and the first inductor L 4 continues to be in series resonance with the first capacitor C 3 through the device under test, the voltage of the first capacitor C 3 increases negatively, and the current of the first inductor L 4 and the current stress of the device under test decrease sinusoidally.

[0169] At t4 At this moment, the current of the first inductor L 4 and the current stress of the device under test drop to zero, and the device under test resumes the blocking state. At this time, the voltage of the first capacitor C 3 drops to the minimum value and outputs a continuous negative voltage stress to the device under test.

[0170] At time t 5 , the semi-controlled power device V 7 conducts, and the second inductor L 5 resonates in series with the first capacitor C 3 . The semi-controlled power device V 7 resumes the blocking state when the current of the second inductor L 5 drops through zero. The voltage of the first capacitor C 3 and the voltage stress of the device under test change from negative to positive during the resonance process and reach the maximum value at time t 6 .

[0171] At time t 7 , the fully-controlled switch V 8 conducts, and the DC voltage source u DC2 charges the first capacitor C 1 through the current-limiting resistor R 3 to supplement the loss consumption. The voltage of the first capacitor C 3 eventually becomes consistent with the voltage of the DC voltage source u DC2 , and the fully-controlled switch V 8 disconnects this charging branch before time t 1 of the next experimental cycle to enable the repetitive test ability of the next cycle.

[0172] In some other embodiments of the present disclosure, please refer to Figures 19 - 21 , the integrated voltage-current source includes at least one module, and the module includes: a DC voltage source u DC2 , a first inductor L 4 , a second inductor L 5 , a first capacitor C 3 , a current-limiting resistor R 1 , a first reverse-blocking fully-controlled device V 7 , a fully-controlled switch V 8 , and a second reverse-blocking fully-controlled device V 6 . Among them, one end of the first inductor L 4 is coupled to the cathode of the second reverse-blocking fully-controlled device V 6 , and the other end is the output end of the module. One end of the second inductor L 5 is connected to one end of the first capacitor C 3 , the cathode of the second reverse-blocking fully-controlled device V 6 , and the current-limiting resistor R 1One end is coupled, and the other end is connected to the first reverse-blocking fully-controlled device V 7 's cathode. The current-limiting resistor R 1 's other end is coupled to the positive electrode of the DC voltage source u DC2 The other end of the first capacitor C 3 , the anode of the second reverse-blocking fully-controlled device V 6 , and the anode of the first reverse-blocking fully-controlled device V 7 are all coupled to the negative electrode of the DC voltage source u DC2 .

[0173] Optionally, as shown in Figure 19 , the fully-controlled switch V 8 is connected in series between the second inductor L 5 and the current-limiting resistor R 1 .

[0174] Optionally, as shown in Figure 20 , the fully-controlled switch V 8 is connected in series between the negative electrode of the DC voltage source u DC2 and the anode of the first reverse-blocking fully-controlled device V 7 .

[0175] Optionally, as shown in Figure 21 , the fully-controlled switch includes: the first fully-controlled switch V 5 connected in series between the second inductor L 1 and the current-limiting resistor R 81 , and the second fully-controlled switch V DC2 connected in series between the negative electrode of the DC voltage source u 7 and the anode of the first reverse-blocking fully-controlled device V 82 .

[0176] Compared with the integrated voltage-current source shown in Figures 16 - 18 , the integrated voltage-current source in the embodiments of the present disclosure uses the first reverse-blocking fully-controlled device V 7 to replace the semi-controlled power device V 7 . After performing equivalent application condition experiments based on the integrated voltage-current source shown in Figures 19 - 21 , the integrated voltage-current source composed of this single module can generate voltage-current stress waveforms on the device under test, which can be understood with reference to Figure 9 .

[0177] Before the moment t 1 , the device under test is in a blocking state, and the first capacitor C 3 applies a positive voltage stress to the device under test.

[0178] At the moment t 1 , the device under test is in a conducting state, and the first capacitor C 3In series resonance with the first inductor L 4 The voltage of the first capacitor C 3 drops, and the current of the first inductor L 4 rises and starts to apply current stress to the device under test.

[0179] At time t 2 the voltage of the first capacitor C 3 drops to zero, the current of the first inductor L 4 rises to the maximum value, and the second reverse-blocking fully controlled device V 6 turns on.

[0180] At time t 2 to time t 3 the first inductor L 4 continues to conduct current through the device under test and the second reverse-blocking fully controlled device V 6 and the current of the first inductor L 4 and the current stress of the device under test are approximately maintained constant.

[0181] At time t 3 the current stress duration of the device under test reaches the equivalent condition, the second reverse-blocking fully controlled device V 6 actively turns off, and the first inductor L 4 continues to resonate in series with the device under test and the first capacitor C 3 the voltage of the first capacitor C 3 increases negatively, and the current of the first inductor L 4 and the current stress of the device under test decrease sinusoidally.

[0182] At time t 4 the current of the first inductor L 4 and the current stress of the device under test drop to zero, the device under test resumes the blocking state, and at this time the voltage of the first capacitor C 3 drops to the minimum value and outputs a continuous negative voltage stress to the device under test.

[0183] At time t 5 the first reverse-blocking fully controlled device V 7 turns on, the second inductor L 5 resonates in series with the first capacitor C 3 the current of the second inductor L 5 decreases sinusoidally, and the voltage of the first capacitor C 3 increases sinusoidally.

[0184] At time t 6 the current of the second inductor L 5 crosses zero negatively, the voltage of the first capacitor C 3 and the positive voltage stress of the device under test reach the maximum value, and the first reverse-blocking fully controlled device V7 Actively turn off to cut off the series resonance of this branch.

[0185] At time t 7 , the fully controlled switch V 8 conducts, and the DC voltage source u DC2 charges the first capacitor C 1 through the current-limiting resistor R 3 to supplement the loss consumption. The voltage of the first capacitor C 3 eventually becomes consistent with the voltage of the DC voltage source u DC2 , and the fully controlled switch V 8 disconnects the charging branch before time t 1 in the next experimental cycle to enable repeated testing in the next cycle.

[0186] It is worth mentioning that when multiple groups of modules are directly cascaded in the integrated voltage-current source, the electrical stress range output by the experimental circuit of the equivalent application conditions of the converter valve to the device under test can be effectively expanded. The following embodiments of the present disclosure exemplarily give some possible implementation manners of the multi-group module cascade of the integrated voltage-current source, but are not limited thereto.

[0187] Embodiment 1, as shown in Figure 22 , multiple modules are connected in parallel; wherein, the grounding ends of each module connected to the reference ground are mutually coupled, and the output ends of each module are mutually coupled. In this way, after the grounding ends of each module connected to the reference ground are mutually coupled, they can be used as the total reference ground end of the integrated voltage-current source, and after the output ends of each module are mutually coupled, they can be used as the total output end of the integrated voltage-current source, so that the output current stresses of each module can be superimposed and applied to the device under test.

[0188] Embodiment 2, as shown in Figure 23 , multiple modules are connected in series; wherein, the output end of the latter-stage module is coupled to the grounding end of the previous-stage module connected to the reference ground. In this way, the grounding end of the first-stage module connected to the reference ground can be used as the grounding end of the integrated voltage-current source, and the output end of the last-stage module can be used as the output end of the integrated voltage-current source, so that the output current stresses of each module can be superimposed and applied to the device under test.

[0189] Embodiment 3, as shown in Figure 24As shown in the figure, multiple modules are connected in series and parallel; among them, multiple modules are connected in series to form multiple sets of series experimental circuits U with the same output voltage, and multiple sets of series experimental circuits U are connected in parallel at both ends of the device under test. In this way, the grounding ends of each series experimental circuit U connected to the reference ground are mutually coupled and can be used as the grounding end of the integrated voltage-current source, and the output ends of each series experimental circuit U are mutually coupled and can be used as the output end of the integrated voltage-current source, so that the voltage stress and current stress output by each module can be correspondingly superimposed and then applied to the device under test to simultaneously realize the expansion of voltage stress and current stress.

[0190] In addition, it can be understood that the DC voltage source or other external electronic components can be adjusted adaptively to match the cascading method of multiple sets of modules in the integrated voltage-current source. For example, a voltage-doubling rectifier power supply can be used as the DC voltage source when multiple sets of modules are connected in series. The embodiments of the present disclosure do not make specific limitations on this.

[0191] To more clearly illustrate the equivalent application condition experimental circuit and its experimental method provided by the embodiments of the present disclosure, Figure 25 and Figure 26 respectively exemplify two different multi-module cascading topologies, and the experimental method of this equivalent application condition experimental circuit is schematically illustrated by taking the module structure shown in Figure 6 as an example.

[0192] In some embodiments, as shown in Figure 25 , the integrated voltage-current source adopts two modules in parallel to expand the experimental current stress. Among them, Module 1 includes a first inductor L 4_1 , a second inductor L 5_1 , a first capacitor C 3_1 , a second capacitor C 4_1 , a first semi-controlled power device V 7_1 , a second semi-controlled power device V 8_1 , and a reverse-blocking fully-controlled device V 6_1 . Module 2 includes a first inductor L 4_2 , a second inductor L 5_2 , a first capacitor C 3_2 , a second capacitor C 4_2 , a first semi-controlled power device V 7_2 , a second semi-controlled power device V 8_2 , and a reverse-blocking fully-controlled device V 6_2 . Moreover, Module 1 and Module 2 can share the same DC voltage source u DC3 .

[0193] Exemplarily, the second capacitor C 4_1 of Module 1 and the second capacitor C 4_2 of Module 2 are connected in parallel with the DC voltage source u DC3 . The second semi-controlled power device V of Module 18_1 The anode of Module 1 and the second semi-controlled power device V of Module 2 8_2 The anodes of are respectively coupled to the positive pole of the DC voltage source u DC3 The cathode of the second semi-controlled power device V of Module 1 8_1 The cathode of the second semi-controlled power device V of Module 2 8_2 The cathode of the first semi-controlled power device V of Module 1 7_1 The cathode of the first semi-controlled power device V of Module 2 7_2 The cathodes are mutually coupled. The anode of the first semi-controlled power device V of Module 1 7_1 The anode of the first semi-controlled power device V of Module 2 7_1 The anode of and the negative pole of the DC power supply u DC3 are mutually coupled.

[0194] The second inductor L of Module 1 5_1 One end of is coupled to the cathode of its first semi-controlled power device V 7_1 The other end is coupled to one end of its first capacitor C 3_1 And the cathode of the inverse-blocking fully-controlled device V 6_1 The cathode of the first capacitor C of Module 1 3_1 The other end of and the anode of its inverse-blocking fully-controlled device V 6_1 Are both coupled to the negative pole of the DC power supply u DC3 Similarly, one end of the second inductor L of Module 2 5_2 Is coupled to the cathode of its first semi-controlled power device V 7_2 The other end is coupled to one end of its first capacitor C 3_2 And the cathode of its inverse-blocking fully-controlled device V 6_2 The cathode of the first capacitor C of Module 2 3_2 The other end of and the anode of its inverse-blocking fully-controlled device V 6_2 Are both coupled to the negative pole of the DC power supply u DC3

[0195] One end of the first inductor L of Module 1 4_1 Is coupled to the cathode of its inverse-blocking fully-controlled device V 6_1 One end of the first inductor L of Module 2 4_2 Is coupled to the cathode of its inverse-blocking fully-controlled device V 6_2 One end of the first inductor L of Module 1 4_1 The other end of is coupled to the other end of the first inductor L of Module 2 4_2 After that, it can be used as the output terminal of the integrated voltage-current source, and the reference ground connected by the integrated voltage-current source is the negative pole of the DC power supply u DC3

[0196] It can be understood that Figure 25 ​​The integrated voltage-current source shown is composed of two single modules in parallel. The voltage-current stress waveform that can be generated on the device under test can also be referred to Figure 7 the voltage-current stress waveform shown in Figure 6 , but only the current stress amplitude is higher than that of the single module shown in

[0197] Exemplarily, in the experimental circuit of the equivalent application working condition with the integrated voltage-current source shown in Figure 25 , the process of the integrated voltage-current source generating voltage-current stress in its experimental method can specifically refer to the relevant descriptions at each of the following times.

[0198] Before the t 1 moment, the device under test is in the blocking state, and the first capacitor C of Module 1 3_1 and the first capacitor C of Module 2 3_2 apply the same positive voltage stress to the device under test.

[0199] At the t 1 moment, the device under test is in the conducting state. The first capacitor C of Module 1 3_1 resonates in series with its first inductor L 4_1 , and the first capacitor C of Module 2 3_2 resonates in series with its first inductor L 4_2 . The voltage of the first capacitor C of Module 1 3_1 and the first capacitor C of Module 2 3_2 drops, and the current of the first inductor L of Module 1 4_1 and the first inductor L of Module 2 4_2 rises. Since the two resonant currents both pass through the device under test, the current stress of the device under test at this time is the superposition of the currents of the two.

[0200] At the t 2 moment, the voltage of the first capacitor C of Module 1 3_1 and the first capacitor C of Module 2 3_2 drops to zero, and the current of the first inductor L of Module 1 4_1 and the first inductor L of Module 2 4_2 rises to the maximum value. The reverse-blocking fully controlled device V of Module 1 6_1 and the reverse-blocking fully controlled device V of Module 2 6_2 conduct simultaneously.

[0201] During the time period from the t 2 moment to the t 3 moment, the first inductor L of Module 1 4_1 and the first inductor L of Module 2 4_2 pass through the device under test and the corresponding reverse-blocking fully controlled devices V 6_1 and V 6_2The freewheeling current of the first inductor L of Module 1 4_1 The current of the first inductor L of Module 2 4_2 The current stress of the device under test approximately remains unchanged.

[0202] At time t 3 When the current stress duration of the device under test reaches the equivalent condition, the reverse-blocking fully-controlled device V of Module 1 6_1 And the reverse-blocking fully-controlled device V of Module 2 6_2 Are actively turned off. The first inductor L of Module 1 4_1 Continues to resonate in series with the device under test and its first capacitor C 3_1 The first inductor L of Module 2 4_2 Continues to resonate in series with the device under test and its first capacitor C 3_2 The first capacitor C of Module 1 3_1 The voltage of the first capacitor C of Module 2 3_2 The voltage of the first inductor L of Module 1 4_1 The current of the first inductor L of Module 2 4_2 The current stress of the device under test decreases sinusoidally.

[0203] At time t 4 When the current of the first inductor L of Module 1 4_1 The current of the first inductor L of Module 2 4_2 The current stress of the device under test drops to zero, and the device under test resumes the blocking state. At this time, the first capacitor C of Module 1 3_1 And the first capacitor C of Module 2 3_2 The voltage drops to the minimum value and outputs a continuous negative voltage stress to the device under test.

[0204] At time t 5 When the first semi-controlled power device V of Module 1 7_1 And the first semi-controlled power device V of Module 2 7_2 Conduct, the second inductor L of Module 1 5_1 Resonates in series with its first capacitor C 3_1 The second inductor L of Module 2 5_2 Resonates in series with its first capacitor C 3_2 The first semi-controlled power device V of Module 1 7_1 And the first semi-controlled power device V of Module 2 7_2 Resume the blocking state when the current of the corresponding second inductor L 5_1 And L 5_2 Drops through zero. The voltage of the first capacitor C of Module 1 3_1 The voltage of the first capacitor C of Module 2 3_2 The voltage stress of the device under test changes from negative to positive during the resonance process.

[0205] At time t 6 moment, the second semi-controlled power device V of Module 1 8_1 and the second semi-controlled power device V of Module 2 8_2 are turned on, and the DC voltage source u DC3 charges the corresponding first capacitors C 5_1 and L 5_2 through the second inductors L 3_1 and C 3_2 respectively to supplement the loss consumption, so that the voltages of the first capacitors C of Module 1 3_1 and the voltages of the first capacitors C of Module 2 3_2 are finally consistent with the voltage of the DC voltage source u DC3 to have the ability to repeat the test in the next cycle.

[0206] The above time points from time t 1 moment to t 6 moment only represent the order of occurrence, and the time intervals between each moment can be adjusted according to the experimental requirements and circuit parameters.

[0207] In some other embodiments, as Figure 26 shown, the integrated voltage-current source adopts two modules in series to expand the experimental voltage stress. Among them, Module 1 includes the first inductor L 4_3 , the second inductor L 5_3 , the first capacitor C 3_3 , the second capacitor C 4_3 , the first semi-controlled power device V 7_3 , the second semi-controlled power device V 8_3 and the inverse-resistance fully-controlled device V 6_3 . Module 2 includes the first inductor L 4_4 , the second inductor L 5_4 , the first capacitor C 3_4 , the second capacitor C 4_4 , the first semi-controlled power device V 7_4 , the second semi-controlled power device V 8_4 and the inverse-resistance fully-controlled device V 6_4 . And, Module 1 and Module 2 can share the same DC voltage source, and this DC voltage source is, for example, a voltage-doubling rectifier power supply. The internal circuit structure of the voltage-doubling rectifier power supply is not limited in the embodiments of the present disclosure, Figure 26 and it is only schematically expressed in Figure 26 , that is: the voltage-doubling rectifier power supply can have a structure different from that shown in

[0208] Here, when the voltage-doubling rectifier power supply is in the no-load state, the voltage-doubling rectifier power supply can generate an amplitude twice that of the AC voltage source u on the first capacitor C of Module 1 4_3 and the first capacitor C of Module 2 4_4 ​AC Peak DC voltage.

[0209] Exemplarily, the first capacitor C of Module 2 4_4 The negative electrode is coupled to the low-voltage end of the voltage-doubling rectifier power supply, and the first capacitor C of Module 1 4_3 The positive electrode is coupled to the high-voltage end of the voltage-doubling rectifier power supply, and the first capacitor C of Module 1 4_3 The negative electrode is coupled to the first capacitor C of Module 2 4_4 The positive electrode is coupled, and the first capacitor C of Module 2 4_4 The negative electrode can be used as the grounding terminal of the integrated voltage-current source connected to the reference ground.

[0210] The second semi-controlled power device V of Module 1 8_3 The anode is coupled to its first capacitor C 4_3 The positive electrode is coupled, and the second semi-controlled power device V of Module 2 8_4 The anode is coupled to its first capacitor C 4_4 The positive electrode is coupled, and the second semi-controlled power device V of Module 1 8_3 The cathode, the second semi-controlled power device V of Module 2 8_4 The cathode, the first semi-controlled power device V of Module 1 7_3 The cathode and the first semi-controlled power device V of Module 2 7_4 The cathodes are mutually coupled. The first semi-controlled power device V of Module 1 7_3 The anode, the first semi-controlled power device V of Module 2 7_4 The anode, the first capacitor C of Module 1 4_3 The negative electrode and the first capacitor C of Module 2 4_4 The negative electrodes are mutually coupled.

[0211] The second inductor L of Module 1 5_3 One end is coupled to its first semi-controlled power device V 7_3 The cathode, and the other end is coupled to its first capacitor C 3_3 One end and the reverse-blocking fully-controlled device V 6_3 The cathode is coupled. The first capacitor C of Module 1 3_3 The other end and its reverse-blocking fully-controlled device V 6_3 The anode, the second capacitor C 4_3 The negative electrode is coupled. Similarly, the second inductor L of Module 2 5_4 One end is coupled to its first semi-controlled power device V 7_4 The cathode, and the other end is coupled to its first capacitor C 3_4 One end and the reverse-blocking fully-controlled device V 6_4 The cathode is coupled. The first capacitor C of Module 2 3_4 The other end and its reverse-blocking fully-controlled device V 6_4 The anode, the second capacitor C 4_4 The negative electrode is coupled.

[0212] The first inductor L of Module 2 4_4 One end is coupled to the cathode of its reverse-blocking fully-controlled device V 6_4 and the other end is coupled to the anode of the reverse-blocking fully-controlled device V of Module 1 6_3 The first inductor L of Module 1 4_3 One end is coupled to the cathode of its reverse-blocking fully-controlled device V 6_3 and the other end serves as the output terminal of the integrated voltage-current source.

[0213] It can be understood that Figure 26 the integrated voltage-current source shown is composed of two monomer modules connected in series, and the voltage-current stress waveform that it can generate on the device under test can also refer to Figure 7 the voltage-current stress waveform shown in Figure 6 However, only the voltage stress amplitude is higher than that of the monomer module shown

[0214] Exemplarily, in the experimental circuit of the equivalent application working condition with the Figure 26 shown integrated voltage-current source, the process of the integrated voltage-current source generating voltage-current stress in its experimental method can specifically refer to the relevant descriptions at each of the following moments.

[0215] Before the moment of t 1 , the device under test is in the blocking state, and the series total voltage of the first capacitor C of Module 1 3_3 and the first capacitor C of Module 2 3_4 applies a positive voltage stress to the device under test.

[0216] At the moment of t 1 , the device under test is in the conducting state, and the first capacitor C of Module 1 3_3 , the first capacitor C of Module 2 3_4 , the first inductor L of Module 1 4_3 and the first inductor L of Module 2 4_4 are in series resonance. The voltages of the first capacitors C 3_3 and C 3_4 drop, and the currents of the first inductors L 4_3 and L 4_4 rise. The current stress of the device under test is the series resonance current.

[0217] At the moment of t 2 , the total voltage of the first capacitors C 3_3 and C 3_4 drops to zero, the currents of the first inductors L 4_3 and L 4_4 rise to the maximum value, and the reverse-blocking fully-controlled devices V of Module 1 6_3 and the reverse-blocking fully-controlled devices V of Module 2 6_4 conduct simultaneously.

[0218] During t 2 to t 3 time period, the first inductors L 4_3 and L 4_4 carry out freewheeling through the device under test and the corresponding reverse-blocking fully-controlled devices V 6_3 and V 6_4 The current of the first inductor L 4_3 of Module 1, the current of the first inductor L 4_4 of Module 2, and the current stress of the device under test approximately remain unchanged.

[0219] At the moment of t 3 , the current stress duration of the device under test reaches the equivalent condition. The reverse-blocking fully-controlled devices V 6_3 of Module 1 and the reverse-blocking fully-controlled devices V 6_4 of Module 2 are actively turned off. The first capacitors C 3_3 and C 3_4 and the first inductors L 4_3 and L 4_4 continue to resonate in series. The voltages of the first capacitors C 3_3 and C 3_4 negatively increase. The current of the first inductor L 4_3 of Module 1, the current of the first inductor L 4_4 of Module 2, and the current stress of the device under test decrease sinusoidally.

[0220] At the moment of t 4 , the current of the first inductor L 4_3 of Module 1, the current of the first inductor L 4_4 of Module 2, and the current stress of the device under test decrease to zero. The device under test resumes the blocking state. At this time, the voltages of the first capacitors C 3_3 and C 3_4 decrease to the minimum value and output a continuous negative voltage stress for the device under test after being connected in series.

[0221] At the moment of t 5 , the first semi-controlled power devices V 7_3 of Module 1 and the first semi-controlled power devices V 7_4 of Module 2 are turned on. The second inductor L 5_3 of Module 1 resonates in series with its first capacitor C 3_3 . The second inductor L 5_4 of Module 2 resonates in series with its first capacitor C 3_4 . The first semi-controlled power device V 7_3 of Module 1 resumes the blocking state when the current of its second inductor L 5_3 decreases through zero. The first semi-controlled power device V 7_4 of Module 2 resumes the blocking state when the current of its second inductor L 5_4When the current drops to zero, the blocking state is restored, and the first capacitor C of Module 1 3_3 voltage, the first capacitor C of Module 2 3_4 voltage, and the voltage stress of the device under test change from negative to positive during the resonance process.

[0222] At time t 6 , the second semi-controlled power device V of Module 1 8_3 and the second semi-controlled power device V of Module 2 8_4 conduct. The second capacitor C of Module 1 4_3 charges the first capacitor C through its second inductor L 5_3 . The second capacitor C of Module 2 3_3 charges the first capacitor C through its second inductor L 4_4 to supplement the loss consumption. The voltage of the first capacitor C of Module 1 5_4 and the voltage of the second capacitor C 3_4 eventually become consistent with the voltage of the first capacitor C and the second capacitor C of Module 2 3_3 to have the ability to repeat the test in the next cycle. 3_4 4_3 4_4 1 6 The time points from the above-mentioned time t

[0223] to time t 1 only represent the sequence of occurrence, and the time intervals between each time point can be adjusted according to the experimental requirements and circuit parameters.

[0224] In summary, the equivalent application condition experimental circuit topology provided by the embodiments of the present disclosure is simple, the number of components is less than that of the existing equivalent application condition experimental circuit, and the construction cost of the required experimental platform is also relatively low. In the embodiments of the present disclosure, only the order of the trigger signals of each power semiconductor device needs to be executed regularly, which can avoid the mutual cooperation of the current source and the voltage source, and its control logic is simple. In the example where mature thyristor devices are used for each power semiconductor element in the circuit, the overall operation reliability is relatively high. Moreover, in the embodiments of the present disclosure, the DC voltage power supply for power supply only needs to supplement the voltage drop of the capacitor caused by the loss, which can eliminate a large amount of reactive power caused by the drag inductor in the current source, and can also avoid a large amount of active power caused by directly charging the negative voltage capacitor, thereby effectively reducing the operation cost and facilitating the development of long-term equivalent reliability verification experiments. In addition, the equivalent application condition experimental circuit provided by the embodiments of the present disclosure has a high degree of modularity, the number of modules can be configured according to experimental needs, and the number of modules can also be increased according to the development requirements of the commutation valve assembly, with high construction flexibility and can effectively reduce repeated investment.

[0225] It is worth mentioning that, on the basis of the above embodiments, please refer to Figure 27 and Figure 28 ​​, the equivalent application condition test circuit further includes: a current source or a voltage source connected in parallel across the device under test.

[0226] It can be understood that the integrated voltage-current source mentioned in the foregoing embodiments of the present disclosure has the functions of both a voltage source and a current source at the same time. Therefore, when the equivalent application condition test circuit further includes a current source connected in parallel across the device under test, the integrated voltage-current source can be reused as a voltage source; when the equivalent application condition test circuit further includes a voltage source connected in parallel across the device under test, the integrated voltage-current source can be reused as a current source. In other words, the integrated voltage-current source mentioned in the foregoing embodiments of the present disclosure can be singly replaced by a voltage source or a current source, and at the same time cooperate with traditional or new circuits to achieve the corresponding other function. For the convenience of description, the integrated voltage-current source in the following some embodiments is schematically shown in the Figure 6 module structure shown, but the integrated voltage-current source can adopt various different implementations in the foregoing embodiments.

[0227] As described above, whether the integrated voltage-current source is singly replaced by a voltage source or a current source, or the voltage source or current source added in parallel, it is in a parallel relationship with the device under test in terms of topology. Moreover, the control timings of the voltage source, the current source, and the device under test cooperate with each other during the experiment. The voltage source applies voltage stress to the device under test when it is in the blocking state, and the current source applies current stress to the device under test when it is in the conducting state.

[0228] In some embodiments, when the single module of the integrated voltage-current source is replaced by a voltage source, there can be various different implementations for the correspondingly parallel current source. For example, the current source connected in parallel outside the integrated voltage-current source includes but is not limited to: a single-group six-pulse bridge current source, two groups of six-pulse thyristor bridge counter-towing inductor current sources, or a fully controlled bridge current source.

[0229] Exemplarily, please refer to Figure 29 and Figure 30 , the current source connected in parallel outside the integrated voltage-current source is two groups of six-pulse thyristor bridge counter-towing inductor current sources. Among them, one group of six-pulse thyristor bridges operates in the rectification mode, and the other group of thyristor bridges operates in the inversion mode. The device under test is connected in series with the isolation valve V 1 as a bridge arm of the inversion thyristor bridge. The isolation valve V 1 plays a role in blocking the grid voltage and preventing the current from flowing backward. The DC sides of the two groups of thyristor bridges are connected through the load inductor L 3 , the AC sides of the two groups of thyristor bridges are connected to the same AC grid, and the energy circulates between the AC grid and the load inductor L 3 through the two groups of thyristor bridges. By adjusting the trigger angle, the average current of the load inductor L 3 and the device under test can be changed.

[0230] Exemplarily, inFigure 29 In the equivalent application condition test circuit shown, the voltage and current stress waveforms generated by its test method on the device under test are as Figure 30 shown in

[0231] Before time t 1 , the device under test is in the blocking state, and the first capacitor C 3 applies a positive voltage stress to the device under test.

[0232] At time t 1 , the isolation valve V 1 and the device under test are in the conducting state. The first capacitor C in the integrated voltage-current source (reused as a voltage source) 3 is in series resonance with the first inductor L 4 . The voltage of the first capacitor C 3 drops, and the current of the first inductor L 4 rises and starts to apply a current stress to the device under test. At the same time, the rectifier thyristor bridge in the current source starts commutation, and the current of the isolation valve V 1 rises and applies a current stress to the device under test. Also, during the time period from time t 1 to time t 6 , the current stress of the device under test consists of two parts, coming from the integrated voltage-current source (reused as a voltage source) and the current source respectively.

[0233] At time t 2 , the voltage of the first capacitor C 3 drops to zero, the current of the first inductor L 4 rises to the maximum value, and the reverse-blocking fully controlled device V 6 conducts. Also, during the time period from time t 2 to time t 5 , the first inductor L 4 continues to conduct current through the device under test and the reverse-blocking fully controlled device V 6 . The current of the first inductor L 4 and the current stress of the device under test are approximately maintained unchanged.

[0234] At time t 3 , the rectifier thyristor bridge of the current source completes commutation, and all the current of the current source flows through the device under test. During the time period from time t 3 to time t 4 , the current source is the main source of the current stress in the device under test.

[0235] At time t 5 , the reverse-blocking fully controlled device V 6 actively turns off, and the first inductor L 4 continues to be in series resonance with the first capacitor C 3 through the device under test.3 As the voltage increases negatively, the current of the first inductor L 4 and the current stress of the device under test both decrease sinusoidally.

[0236] At time t 6 , the isolation valve V 1 , the first inductor L 4 and the current of the device under test drop to zero, the device under test resumes the blocking state, and the voltage of the first capacitor C 3 drops to the minimum value and outputs a continuous negative voltage stress to the device under test.

[0237] At time t 7 , the first semi-controlled power device V 7 conducts, the second inductor L 5 resonates in series with the first capacitor C 3 , the current of the second inductor L 5 first rises and then drops sinusoidally, and the voltage of the first capacitor C 3 rises sinusoidally.

[0238] At time t 8 , the current of the second inductor L 5 negatively crosses zero, the voltage of the first capacitor C 3 and the positive voltage stress of the device under test reach the maximum value, and the first semi-controlled power device V 7 automatically resumes blocking, cutting off the series resonance of this branch.

[0239] At time t 9 , the second semi-controlled power device V 8 conducts, and the DC voltage source u DC2 charges the first capacitor C 5 through the second inductor L 3 to supplement the loss consumption, and the voltage of the first capacitor C 3 eventually becomes consistent with the voltage of the DC voltage source u DC2 to have the ability to repeat the test in the next cycle.

[0240] The time points from the above time t 1 to time t 9 only represent the order of occurrence, and the time intervals between each moment can be adjusted according to the experimental requirements and circuit parameters.

[0241] Exemplarily, please refer to Figure 31 , the current source connected in parallel outside the integrated voltage-current source is a single-group six-pulse bridge current source. The six-pulse thyristor bridge operates in the inverter mode, and the isolation valve V 1 plays a role in blocking the grid voltage and preventing the current from reversing. The energy passes through the six-pulse thyristor bridge in the load inductor L 3Circulate with the AC power grid. Adjusting the trigger angle can change the load inductance L 3 and the average current of the device under test. And, in Figure 31 the equivalent application condition experimental circuit shown, the voltage and current stress waveforms generated by its experimental method on the device under test can be referred to Figure 30 , and the control timing of its experimental method is also the same as that of the aforementioned two groups of six-pulse thyristor bridges dragging the inductive current source. This will not be elaborated here.

[0242] Exemplarily, please refer to Figure 32 , the current source connected in parallel outside the integrated voltage-current source is a fully controlled bridge current source. In the fully controlled bridge current source, the switches S 2 , S 3 and S 5 are used to switch the charge and discharge circuit paths of the inductors L 31 and L 32 . The diodes D 1 , D 4 and D 6 provide a freewheeling path for the inductors L 31 and L 32 . The isolation valve V 1 plays a role in blocking the grid voltage and preventing current reversal. Energy circulates between the DC power supply u DC1 and the inductors L 31 , L 32 . By adjusting the action timing and on-time of each switch, the current stress of the device under test can be changed.

[0243] Exemplarily, in Figure 32 the equivalent application condition experimental circuit shown, the voltage and current stress waveforms generated by its experimental method on the device under test can be referred to Figure 30 .

[0244] Before the moment t 1 , the device under test is in the blocking state, and the first capacitor C 3 applies a positive voltage stress to the device under test.

[0245] At the moment t 1 , the isolation valve V 1 and the device under test are in the conducting state. The first capacitor C 3 in the integrated voltage-current source (reused as a voltage source) resonates in series with the first inductor L 4 . The voltage of the first capacitor C 3 drops, and the current of the first inductor L 4 rises and starts to apply a current stress to the device under test. At the same time, the switches S 2 and S 5 in the current source conduct, and the DC power supply u DC1 passes through the switch S 5, isolation valve V 1 , device under test and switch S 2 is inductor L 32 Charging, the current of inductor L 32 rises linearly and applies current stress to the device under test. Also, within the time period from t 1 moment to t 6 moment, the current stress of the device under test consists of two parts, respectively from the integrated voltage-current source (reused as a voltage source) and the current source.

[0246] At t 2 moment, the voltage of the first capacitor C 3 drops to zero, the current of the first inductor L 4 rises to the maximum value, and the reverse-blocking fully-controlled device V 6 turns on. Also, within the time period from t 2 moment to t 5 moment, the first inductor L 4 continues to flow through the device under test and the reverse-blocking fully-controlled device V 6 , and the current of the first inductor L 4 and the current stress of the device under test approximately remain unchanged.

[0247] At t 3 moment, the amplitude of the current stress of the device under test reaches the experimental requirement, switches S 2 and S 5 turn off, and the current of inductor L 32 flows through diode D 6 , isolation valve V 1 and the device under test to continue to flow, and the current stress of the device under test remains unchanged.

[0248] At t 3 moment, the current stress time of the device under test reaches the experimental requirement, switches S 2 and S 3 turn on, and the DC power supply u DC1 passes through switches S 2 and S 3 , inductor L 32 to charge inductor L 31 , and the current of inductor L 31 rises from zero, but there is still current on inductor L 32 at this time, and the part of the current of inductor L 32 greater than that of inductor L 31 continues to flow through isolation valve V 1 and the device under test, and the current stress of the device under test decreases linearly.

[0249] At t 5 moment, the reverse-blocking fully-controlled device V 6 actively turns off, and the first inductor L4 Through the device under test and the first capacitor C 3 Continue series resonance, the voltage of the first capacitor C 3 Negatively increases, the current of the first inductor L 4 And the current stress of the device under test both decrease sinusoidally.

[0250] Before time t 6 The current of the inductor L 31 Exceeds the inductor L 32 The current of the inductor L 32 No longer passes through the isolation valve V 1 And the device under test for freewheeling, the isolation valve V 1 Automatically resumes the blocking state after the current is zero, and the current stress of the device under test is only the part provided by the voltage source; After that, turn off the switches S 2 And S 3 The inductor L 31 And the inductor L 32 Discharge and freewheel through the diodes D 1 And D 4 To the DC voltage source u DC1 Discharge and freewheel, the current of the inductor L 31 And the inductor L 32 After the current drops to zero, the diodes D 1 And D 4 Resume blocking.

[0251] At time t 6 The isolation valve V 1 The first inductor L 4 And the current of the device under test drop to zero, the device under test resumes the blocking state, and the voltage of the first capacitor C 3 Drops to the minimum value and outputs a continuous negative voltage stress to the device under test.

[0252] At time t 7 The first semi-controlled power device V 7 Conducts, and the second inductor L 5 Is in series resonance with the first capacitor C 3 The current of the second inductor L 5 Sinusoidally rises first and then falls, and the voltage of the first capacitor C 3 Sinusoidally rises.

[0253] At time t 8 The current of the second inductor L 5 Negatively crosses zero, the voltage of the first capacitor C 3 And the positive voltage stress of the device under test reach the maximum value, and the first semi-controlled power device V 7 Automatically resumes blocking, cutting off the series resonance of this branch.

[0254] At time t9 At this moment, the second half-controlled power device V 8 On, DC voltage source u DC2 Through the second inductor L 5 The first capacitor C 3 To charge and replenish the loss, the first capacitor C 3 The voltage of the DC voltage source u DC2 The voltage is consistent to enable repeated testing in the next cycle.

[0255] It should be added that, in some embodiments, the integrated voltage and current source can be composed of multiple modules connected in series and reused as a voltage source to expand the experimental voltage output capacity. Accordingly, the current source connected in parallel outside the integrated voltage and current source can refer to the relevant records in some of the aforementioned embodiments, and the control method of the integrated voltage and current source is the same as the control method of the integrated voltage and current source of the aforementioned single module, which will not be described in detail here.

[0256] For example, see Figure 33 The integrated voltage and current source can be formed by connecting multiple modules in series. The current source connected in parallel outside the integrated voltage and current source is two groups of six-pulse thyristor bridge-drag inductor current sources.

[0257] For example, see Figure 34 The integrated voltage and current source can be composed of multiple modules connected in series. The current source connected in parallel outside the integrated voltage and current source is a single group of six-pulse bridge current sources.

[0258] For example, see Figure 35 The integrated voltage and current source can be composed of multiple modules connected in series. The current source connected in parallel with the integrated voltage and current source is a fully controlled bridge current source.

[0259] Similarly, in other embodiments, a single module of the integrated voltage and current source is replaced by a current source, and the corresponding parallel voltage source can be implemented in a variety of different ways. For example, the voltage source connected in parallel with the integrated voltage and current source includes, but is not limited to: a synthetic test voltage source, a DC modular multi-level topology voltage source, an AC modular multi-level topology voltage source, an AC energy modular multi-level topology voltage source, or a multi-level DC link topology voltage source.

[0260] For example, see Figure 36 The voltage source connected in parallel with the integrated voltage and current source is the synthetic test voltage source. The voltage and current stress waveforms generated by the equivalent application working condition experimental circuit on the device under test are as follows: Figure 37 as shown in .

[0261] In t 1 Before the moment, the device under test, the semi-controlled power device V 3 and isolation valve V 1In the blocking state, a constant positive voltage stress is applied to the parasitic capacitance of the device under test.

[0262] At time t 1 , the isolation valve V 1 conducts with the device under test, and the capacitance C 3 of the integrated voltage-current source (reused as a current source) resonates in series with the inductor L 4 . The voltage of the capacitance C 3 drops, and the current of the inductor L 4 rises and starts to apply current stress to the device under test.

[0263] At time t 2 , the voltage of the capacitance C 3 drops to zero, the current of the inductor L 4 rises to the maximum value, and the reverse-blocking fully-controlled device V 6 conducts. Moreover, during the time period from time t 2 to time t 3 , the inductor L 4 continues to conduct current through the device under test and the reverse-blocking fully-controlled device V 6 , and the current of the inductor L 4 and the current stress of the device under test approximately remain unchanged.

[0264] At time t 3 , the duration of the current stress of the device under test reaches the equivalent condition, the reverse-blocking fully-controlled device V 6 actively shuts off, and the inductor L 4 continues to resonate in series with the capacitance C 3 through the device under test. The voltage of the capacitance C 3 increases negatively, and the current of the inductor L 4 and the current stress of the device under test decrease sinusoidally.

[0265] At time t 4 , the semi-controlled power device V 3 conducts, and the inductor L 1 resonates in series with the capacitance C 1 . The current of the inductor L 1 increases first and then decreases sinusoidally, the voltage of the capacitance C 1 decreases from positive to negative, and the current of the inductor L 1 superimposes with the current of the current source and acts on the device under test.

[0266] During the time period from time t 4 to time t 5 , the current of the inductor L 4 and the device under test drop to zero, the isolation valve V 1 automatically resumes the blocking state, and at this time the voltage of the capacitance C 3 drops to the minimum negative value.

[0267] At time t 5 , the current of inductor L 1 negatively crosses zero, and the semi-controlled power device V 3 automatically turns off. The voltage of capacitor C 1 reaches the minimum value, and the semi-controlled power device V 4 conducts, and the voltage source outputs a negative voltage stress.

[0268] At time t 6 , the semi-controlled power device V 5 conducts. Capacitor C 1 and inductor L 2 are in series resonance. The current of inductor L 2 first increases and then decreases sinusoidally. The voltage of capacitor C 1 increases from negative to positive. At the same time, the semi-controlled power device V 7 conducts. Inductor L 5 and capacitor C 3 are in series resonance. The current of inductor L 5 first rises and then falls sinusoidally. The voltage of capacitor C 3 rises sinusoidally, and the current of inductor L 5 crosses zero, and then the semi-controlled power device V 7 automatically resumes the blocking state. At this time, the voltage of capacitor C 3 reaches the maximum positive value.

[0269] At time t 7 , the voltage of capacitor C 1 positively crosses zero, and the semi-controlled power device V 3 conducts, and the voltage source outputs a positive voltage stress.

[0270] At time t 8 , the semi-controlled power device V 2 and the semi-controlled power device V 8 conduct. The DC voltage source u DC1 charges capacitor C 2 through inductor L 1 to supplement the loss consumption. The DC voltage source u DC2 charges capacitor C 5 through inductor L 3 to supplement the loss consumption. The final voltages of capacitor C 1 and capacitor C 3 are respectively consistent with the voltages of the DC voltage source u DC1 and the DC voltage source u DC2 to have the ability to repeat the test in the next cycle.

[0271] For example, please refer to Figure 38, the voltage source connected in parallel outside the integrated voltage-current source is a DC modular multilevel topology voltage source. The DC modular multilevel topology voltage source consists of a DC voltage source u DC1 , commutation equivalent inductor L 1 and N full-bridge sub-modules SM1 - SMN of modular multilevel converters. Each full-bridge sub-module includes a support capacitor C SM1 - C SMN and a full-bridge structure composed of fully controlled power devices with anti-parallel diodes. The DC port of the full-bridge structure is connected to the support capacitor. One side of the AC port of the first-stage full-bridge sub-module SM1 is connected to the positive pole of the DC voltage source u DC1 . One side of the AC port of the last-stage full-bridge sub-module SMN is connected to one end of the inductor L 1 . The AC ports of the remaining full-bridge sub-modules are connected in series with each other. The other end of the inductor L 1 is connected to one end of the device under test, and the other end of the device under test is connected to the reference ground and the negative pole of the DC voltage source u DC1 . The support capacitors C SM1 - C SMN obtain energy from the DC voltage source u DC1 during operation through modulation control, and their voltages are kept consistent with the voltage of the DC voltage source u DC1 . By controlling the on-off combination of each fully controlled power device of the full-bridge sub-module, three levels can be output on its AC side: u DC1 , -u DC1 and 0. By coordinating the output levels of each full-bridge sub-module, an arbitrary programmable voltage stress waveform can be generated for the device under test in the range from -(N - 1)u DC1 to (N + 1)u DC1 .

[0272] Exemplarily, in the equivalent application condition experimental circuit shown in Figure 33 , the voltage and current stress waveforms generated by its experimental method on the device under test can be referred to Figure 39 .

[0273] Before the moment of t 1 , the isolation valve V 1 and the device under test are in the blocked state, and the voltage source applies a positive voltage stress to the device under test.

[0274] At the moment of t 1 , the device under test conducts, the voltage source outputs zero level, and the capacitor C 3 of the current source is in series resonance with the inductor L 4 . The voltage of the capacitor C 3 drops, and the current of the inductor L 4 rises and starts to apply current stress to the device under test.

[0275] At the moment of t 2At the moment, capacitor C 3 The voltage drops to zero, and the current of inductor L 4 rises to the maximum value, and the reverse-blocking fully-controlled device V 6 conducts.

[0276] At time t 2 to time t 3 During this time period, the inductor L 4 continues to conduct current through the device under test and the reverse-blocking fully-controlled device V 6 The current of inductor L 4 and the current stress of the device under test approximately remain unchanged.

[0277] At time t 3 When the current stress duration of the device under test reaches the equivalent condition, the reverse-blocking fully-controlled device V 6 actively shuts off, and the inductor L 4 continues to resonate in series through the device under test and the capacitor C 3 The voltage of capacitor C 3 increases negatively, and the current of inductor L 4 and the current stress of the device under test decrease sinusoidally.

[0278] At time t 4 When the current of inductor L 4 and the current stress of the device under test drop to zero, the device under test and the isolation valve V 1 return to the blocking state. At this time, the voltage of capacitor C of the current source 3 drops to the minimum negative value.

[0279] At time t 4 and later, the voltage source starts to output the corresponding voltage stress for the device under test according to the setting.

[0280] Exemplarily, please refer to Figure 40 , the voltage source connected in parallel outside the integrated voltage-current source is an AC-powered modular multilevel topology voltage source. The AC-powered modular multilevel topology voltage source consists of an AC voltage source, a commutation equivalent inductor L 1 and N full-bridge sub-modules SM1 - SMN of multilevel converters with diode rectifier bridges; among them, each sub-module includes a support capacitor C SM1 -C SMN , an AC isolation transformer T SM1 -T SMN, an uncontrolled rectifier bridge composed of diodes and a full-bridge structure composed of fully controlled power devices. The DC ports of the uncontrolled rectifier bridge and the full-bridge structure are connected to the support capacitor. The AC port of the uncontrolled rectifier bridge is connected to the secondary side of the AC isolation transformer, and the primary side of the AC isolation transformer is connected to the AC voltage source. The AC isolation transformer provides potential isolation between sub-modules and supplies energy to the support capacitor through the uncontrolled rectifier bridge during operation. One side of the AC port of the first-stage sub-module SM1 is connected to one end of the device under test and the reference ground. One side of the AC port of the last-stage sub-module SMN is connected to one end of the inductor L 1 One end is connected, and the AC ports of the remaining full-bridge sub-modules are connected in series. The other end of the inductor L 1 Is connected to one end of the device under test. The voltage of the support capacitor C SM1 -C SMN Is consistent with the DC voltage u DC1 After the AC voltage is rectified. By controlling the on-off combination of the fully controlled power devices of each full-bridge sub-module, three levels can be output on its AC side: u DC1 , -u DC1 And 0. By coordinating the output levels of each full-bridge sub-module, an arbitrary programmable voltage stress waveform can be generated for the device under test in the range from -Nu DC1 To Nu DC1 .

[0281] Exemplarily, in the equivalent application condition experimental circuit shown in Figure 40 , the voltage and current stress waveforms generated by its experimental method on the device under test can be referred to Figure 39 .

[0282] Before the moment of t 1 , the isolation valve V 1 And the device under test are in the blocking state, and the voltage source applies a positive voltage stress to the device under test.

[0283] At the moment of t 1 , the device under test conducts, the voltage source outputs zero level, and the capacitor C of the current source 3 Is in series resonance with the inductor L 4 , the voltage of the capacitor C 3 Drops, and the current of the inductor L 4 Rises and begins to apply current stress to the device under test.

[0284] At the moment of t 2 , the voltage of the capacitor C 3 Drops to zero, the current of the inductor L 4 Rises to the maximum value, and the reverse-blocking fully controlled device V 6 Conducts.

[0285] During the time period from the moment of t 2 To the moment of t 3 , the inductor L4 Through the device under test and the reverse-blocking fully-controlled device V 6 Freewheeling, inductor L 4 The current and the current stress of the device under test are approximately maintained constant.

[0286] At time t 3 When the current stress duration of the device under test reaches the equivalent condition, the reverse-blocking fully-controlled device V 6 Actively shuts off, and inductor L 4 Continues to resonate in series through the device under test and capacitor C 3 Capacitor C 3 The voltage increases negatively, and the current of inductor L 4 The current and the current stress of the device under test decrease sinusoidally.

[0287] At time t 4 When the current of inductor L 4 The current and the current stress of the device under test drop to zero, and the device under test and the isolation valve V 1 Return to the blocking state. At this time, the capacitor C of the current source 3 The voltage drops to the minimum negative value.

[0288] At time t 4 And after that, the voltage source starts to output the corresponding voltage stress for the device under test according to the setting.

[0289] Exemplarily, please refer to Figure 41 , the voltage source connected in parallel outside the integrated voltage-current source is a multi-level DC-link topology voltage source. The multi-level DC-link topology voltage source consists of an AC voltage source, a commutation equivalent inductor L 1 , a high-voltage full-bridge structure composed of fully-controlled power devices, and N multi-level converter full-bridge sub-modules SM1 - SMN with diode rectifier bridges. Each sub-module includes a support capacitor C SM1 -C SMN , an AC isolation transformer T SM1 -T SMN , an uncontrolled rectifier bridge composed of diodes, and a half-bridge structure composed of fully-controlled power devices.

[0290] In each sub-module, the DC ports of the uncontrolled rectifier bridge and the half-bridge structure are connected to the support capacitor, the AC port of the uncontrolled rectifier bridge is connected to the secondary side of the AC isolation transformer, the primary side of the AC isolation transformer is connected to the AC voltage source, and the AC isolation transformer provides potential isolation between sub-modules and energizes the support capacitor through the uncontrolled rectifier bridge during operation. The low-voltage DC port of the first-stage sub-module SM1 is connected to the low-voltage side of the high-voltage full-bridge structure, the AC port of the last-stage sub-module SMN is connected to the high-voltage side of the high-voltage full-bridge structure, and the AC ports of the remaining full-bridge sub-modules are connected in series with the low-voltage DC port of the next-stage sub-module.

[0291] Support capacitor C SM1 -C SMN The voltage of is consistent with the DC voltage u after the AC voltage is rectified. DC1 By controlling the on-off combination of all fully controlled power devices in the full-bridge sub-module, two levels can be output on its AC side: u DC1 and 0. The voltages of all sub-modules are connected in series and superimposed to form the DC voltage input of the high-voltage full-bridge structure.

[0292] The AC side of the high-voltage full-bridge structure can secondarily adjust the voltage direction of the total output of the sub-module. The AC side voltage can directly output or invert the output of its DC port voltage. One end of the AC side of the high-voltage full-bridge structure is connected to one end of the device under test through an inductor L 1 , and the other end of the AC side of the high-voltage full-bridge structure is connected to the other end of the device under test and the reference ground. Therefore, by coordinating the output levels of each sub-module and the state of the high-voltage full-bridge structure, an arbitrary programmable voltage stress waveform can be generated for the device under test in the range of -Nu DC1 to Nu DC1 .

[0293] Exemplarily, in the equivalent application condition experimental circuit shown in Figure 41 , the voltage and current stress waveforms generated by its experimental method on the device under test can be referred to Figure 39 .

[0294] Before the moment of t 1 , the isolation valve V 1 and the device under test are in the blocking state, and the voltage source applies a positive voltage stress to the device under test.

[0295] At the moment of t 1 , the device under test conducts, the voltage source outputs zero level, and the capacitor C of the current source 3 is in series resonance with the inductor L 4 . The voltage of the capacitor C 3 drops, and the current of the inductor L 4 rises and begins to apply current stress to the device under test.

[0296] At the moment of t 2 , the voltage of the capacitor C 3 drops to zero, the current of the inductor L 4 rises to the maximum value, and the reverse-blocking fully controlled device V 6 conducts.

[0297] During the time period from the moment of t 2 to the moment of t 3 , the inductor L 4 continues to flow through the device under test and the reverse-blocking fully controlled device V 6 . The current of the inductor L 4 and the current stress of the device under test are approximately maintained unchanged.

[0298] At time t 3 , the current stress duration of the device under test reaches the equivalent condition, and the reverse-blocking fully-controlled device V 6 actively shuts down, and the inductor L 4 continues to resonate in series with the device under test and the capacitor C 3 . The voltage of the capacitor C 3 increases negatively, and the current of the inductor L 4 and the current stress of the device under test decrease sinusoidally.

[0299] At time t 4 , the current of the inductor L 4 and the current stress of the device under test drop to zero, and the device under test and the isolation valve V 1 restore the blocking state. At this time, the voltage of the capacitor C 3 of the current source drops to the minimum negative value.

[0300] At time t 4 and later, the voltage source starts to output the corresponding voltage stress for the device under test according to the setting.

[0301] Exemplarily, please refer to Figure 42 . The voltage source connected in parallel outside the integrated voltage-current source is an AC modular multilevel topology voltage source. The AC modular multilevel topology voltage source consists of positive and negative DC voltage sources u DC1P and u DC1N , positive and negative commutation equivalent inductors L 1P and L 1N , and N positive and negative multilevel converter sub-modules SMP1 - SMPN and SMN1 - SMNN respectively. Each sub-module includes a support capacitor C SMP1 -C SMPN , C SMN1 -C SMNN and a bridge structure composed of fully-controlled power devices. Among them, the positive and negative DC voltage sources u DC1P and u DC1N can be combined into a unified DC voltage source u DC1 after canceling the neutral line. The bridge structure of the sub-module can be variants such as half-bridge, full-bridge, multilevel half-bridge, and multilevel full-bridge. Only the topology and working principle of the half-bridge structure will be detailed subsequently.

[0302] In each sub-module, the DC port of the half-bridge structure is connected to the support capacitor. The low-voltage DC port of the first-stage positive sub-module SMP1 is connected to the neutral line through the positive inductor L 1P . The neutral line is connected to one end of the device under test, the low-voltage end of the positive DC voltage source u DC1P and the high-voltage port of the negative DC voltage source u DC1N . The AC port of the last-stage positive sub-module SMPN is connected to the positive DC voltage source uDC1P is connected to the high-voltage port. The AC port of the last-stage sub-module SMNN of the negative electrode is connected to the neutral line through the positive inductor L 1P . The low-voltage DC port of the first-stage sub-module SMN1 of the negative electrode is connected to the low-voltage end of the negative DC voltage source u DC1P and the other end of the device under test. The AC ports of the remaining sub-modules are connected to the low-voltage DC ports of the next-stage sub-modules.

[0303] The voltage of the positive support capacitor C SMP1 -C SMPN is consistent with the DC voltage u DC1P / N. The voltage of the negative support capacitor C SMN1 -C SMNN is consistent with the DC voltage u DC1N / N. By controlling the on-off combination of all full-controlled power devices in the positive half-bridge sub-module, two levels can be output on its AC side: u DC1P / N and 0. By controlling the on-off combination of all full-controlled power devices in the negative half-bridge sub-module, two levels can be output on its AC side: u DC1N / N and 0. The voltages of all sub-modules are connected in series with the DC voltage source and act on the inductor and the device under test. Therefore, by coordinating the output levels of each sub-module, an arbitrary programmable voltage stress waveform can be generated for the device under test in the range from -u DC1N to u DC1P .

[0304] Exemplarily, in the equivalent application condition experimental circuit shown in Figure 42 , the voltage and current stress waveforms generated by its experimental method on the device under test can be referred to Figure 39 .

[0305] Before the moment of t 1 , the isolation valve V 1 and the device under test are in the blocking state, and the voltage source applies a positive voltage stress to the device under test.

[0306] At the moment of t 1 , the device under test conducts, the voltage source outputs zero level, and the capacitor C 3 of the current source is in series resonance with the inductor L 4 . The voltage of the capacitor C 3 drops, and the current of the inductor L 4 rises and starts to apply current stress to the device under test.

[0307] At the moment of t 2 , the voltage of the capacitor C 3 drops to zero, the current of the inductor L 4 rises to the maximum value, and the reverse-blocking full-controlled device V 6 conducts.

[0308] During the time period from 2 time t 3 to time t 4 , the inductor L 6 continues to conduct current through the device under test and the reverse-blocking fully-controlled device V 4 , and the current of the inductor L and the current stress of the device under test approximately remain unchanged.

[0309] At time t 3 , the duration of the current stress of the device under test reaches the equivalent condition, and the reverse-blocking fully-controlled device V 6 actively shuts off. The inductor L 4 continues to resonate in series with the device under test and the capacitor C 3 . The voltage of the capacitor C 3 increases negatively, and the current of the inductor L 4 and the current stress of the device under test decrease sinusoidally.

[0310] At time t 4 , the current of the inductor L 4 and the current stress of the device under test drop to zero, and the device under test and the isolation valve V 1 restore the blocking state. At this time, the voltage of the capacitor C of the current source 3 drops to the minimum negative value.

[0311] At time t 4 and later, the voltage source starts to output the corresponding voltage stress for the device under test according to the setting.

[0312] It should be added that in some embodiments, the integrated voltage-current source can be composed of multiple stages of modules connected in parallel and reused as a current source to expand the experimental current output capacity. Correspondingly, the voltage source connected in parallel outside the integrated voltage-current source can refer to the relevant records in the foregoing embodiments, and the control method of the integrated voltage-current source is the same as that of the single-module integrated voltage-current source described above, which will not be elaborated here.

[0313] Exemplarily, please refer to Figure 43 , the integrated voltage-current source can be composed of multiple stages of modules connected in parallel. The voltage source connected in parallel outside the integrated voltage-current source is a synthetic test voltage source.

[0314] Exemplarily, please refer to Figure 44 , the integrated voltage-current source can be composed of multiple stages of modules connected in parallel. The voltage source connected in parallel outside the integrated voltage-current source is a DC modular multilevel topology voltage source.

[0315] Exemplarily, please refer to Figure 45 , the integrated voltage-current source can be composed of multiple stages of modules connected in parallel. The voltage source connected in parallel outside the integrated voltage-current source is an AC energy-taking modular multilevel topology voltage source.

[0316] By way of example, refer to Figure 46 , the integrated voltage-current source can be formed by connecting multiple-stage modules in parallel. The voltage source connected in parallel outside the integrated voltage-current source is a multi-level DC-link topology voltage source.

[0317] By way of example, refer to Figure 47 , the integrated voltage-current source can be formed by connecting multiple-stage modules in parallel. The voltage source connected in parallel outside the integrated voltage-current source is an AC modular multi-level topology voltage source.

[0318] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0319] The above-described embodiments only represent several implementation manners of the present disclosure, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. An equivalent application working condition experimental circuit, characterized in that: include: Device under test; An integrated voltage and current source is coupled to both ends of the device under test and one end is coupled to a reference ground, and is configured to: generate voltage stress at both ends of the device under test when the device under test is in a blocking state; and generate current stress at both ends of the device under test when the device under test is in a conducting state; wherein the waveform changes of the voltage stress and the current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions; The integrated voltage and current source includes at least one module; the module includes: a DC voltage source, a first inductor, a second inductor, a first capacitor, a first half-controlled power device, a second half-controlled power device and a reverse resistance fully controlled device; One end of the first inductor is coupled to the cathode of the reverse resistance fully controlled device, and the other end is the output end of the module; One end of the second inductor is coupled to one end of the first capacitor and the cathode of the reverse resistance fully-controlled device, and the other end is coupled to the cathode of the first half-controlled power device and the cathode of the second half-controlled power device; the other end of the first capacitor, the anode of the reverse resistance fully-controlled device and the anode of the first half-controlled power device are all coupled to the negative electrode of the DC voltage source; the anode of the second half-controlled power device is coupled to the positive electrode of the DC voltage source.

2. The equivalent application working condition experimental circuit according to claim 1 is characterized in that: The module also includes a second capacitor; the second capacitor is coupled in parallel with the DC voltage source.

3. The equivalent application working condition experimental circuit according to claim 2 is characterized in that: The first capacitor and / or the second capacitor includes: a single capacitor or a plurality of capacitors connected in series and parallel.

4. The equivalent application working condition experimental circuit according to any one of claims 1 to 3, characterized in that: The reference ground is the negative electrode of the DC voltage source.

5. The equivalent application working condition experimental circuit according to any one of claims 1 to 3, characterized in that: The integrated voltage and current source includes a plurality of modules; the implementation method of the integrated voltage and current source includes any one of the following: In the first embodiment, a plurality of the modules are connected in parallel; wherein the ground terminals of the modules connected to the reference ground are coupled to each other, and the output terminals of the modules are coupled to each other; Embodiment 2: A plurality of the modules are connected in series; wherein the output end of the module of the next stage is coupled to the ground end of the module of the previous stage connected to the reference ground; and the output end of the module of the last stage is the output end of the integrated voltage and current source; In the third implementation mode, a plurality of the modules are connected in series and in parallel; wherein, the plurality of modules are connected in series to form a plurality of series experimental circuits with the same output voltage, and the plurality of series experimental circuits are connected in parallel to both ends of the device under test.

6. An experimental method for an equivalent application working condition experimental circuit, characterized in that: Applicable to the equivalent application working condition experimental circuit according to any one of claims 1 to 5, the experimental method comprises: When the device under test is in a blocking state, the voltage stress is generated at both ends of the device under test by the integrated voltage and current source; When the device under test is in a conducting state, the integrated voltage and current source generates the current stress at both ends of the device under test; The waveform changes of the voltage stress and the current stress are consistent with the waveform changes of the corresponding electrical stress of the device under test in actual application conditions.

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