Method for manufacturing semiconductor device, semiconductor wafer, and semiconductor device

Abstract

The invention relates to a manufacturing method of a semiconductor device, a semiconductor wafer and the semiconductor device. The purpose of the present disclosure is to provide a method for manufacturing a semiconductor device capable of accurately measuring positional displacement of upper and lower layers on a wafer. A method of manufacturing a semiconductor device according to the present disclosure includes: a first step of forming a first layer on a main surface of a wafer, the first layer forming a reference mark for measuring a positional displacement of a photoresist with respect to a first element pattern for a semiconductor element; a second step of forming a photoresist on the first layer so as to cover the reference mark and the first element pattern; a third step for forming, using the photoresist, a positional deviation determination pattern overlapping the reference mark in plan view, a peripheral pattern surrounding the positional deviation determination pattern in plan view, and a second element pattern for the semiconductor element by exposing and developing the photoresist; and a fourth step for determining the positional shift of the second element pattern with respect to the first element pattern by measuring the relative position of the positional shift determination pattern with respect to the reference mark.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, a semiconductor wafer and a semiconductor device. Background Art

[0002] Patent document 1 discloses a semiconductor device, comprising a first trench structure and a second trench structure, wherein the first trench structure comprises a chip having a first main surface on one side and a second main surface on the other side; a first region of a first conductivity type formed on the second main surface side of the chip; a second region of a second conductivity type formed on the first main surface side of the chip and forming a pn junction with the first region; a device region arranged on the first main surface; a first trench penetrating the pn junction from the first main surface; and a first insulating region. The device region is divided by a first trench structure having a first insulating film, a second insulating film, and a first polysilicon buried in the first trench through the first insulating film; and the device region is divided by a second trench structure having a second trench extending from the first main surface to the pn junction; a second insulating film, and the first region is exposed from the wall of the second trench; and a second polysilicon buried in the second trench through the second insulating film; and the device region is divided by a side closer to the device region than the first trench structure.

[0003] [Background Technology Literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2023-32332 Summary of the invention

[0006] [summary]

[0007] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device capable of measuring positional deviation of upper and lower layers on a wafer with high accuracy.

[0008] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes: a first step of forming a first layer on a main surface of a wafer, the first layer forming a reference mark for measuring a positional offset of the photoresist relative to a first element pattern for a semiconductor element; a second step of forming a photoresist on the first layer in a manner covering the reference mark and the first element pattern; a third step of exposing and developing the photoresist to form a positional offset determination pattern overlapping with the reference mark when viewed from above, a surrounding pattern surrounding the reference mark when viewed from above, and a second element pattern for the semiconductor element; and a fourth step of determining a positional offset of the second element pattern relative to the first element pattern by measuring the relative position of the positional offset determination pattern relative to the reference mark. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a schematic diagram showing a wafer used to manufacture a semiconductor device.

[0010] Figure 2 yes Figure 1 An enlarged view of the main part of the wafer.

[0011] Figure 3 It is a diagram showing the structure of a device formed on the wafer.

[0012] Figure 4A It is a diagram showing an example of a method for manufacturing the semiconductor device.

[0013] Figure 4B Yes means Figure 4A The diagram of the subsequent process.

[0014] Figure 4C Yes means Figure 4B The diagram of the subsequent process.

[0015] Figure 4D Yes means Figure 4C The diagram of the subsequent process.

[0016] Figure 4E Yes means Figure 4D The diagram of the subsequent process.

[0017] Figure 4F Yes means Figure 4E The diagram of the subsequent process.

[0018] Figure 4G Yes means Figure 4F The diagram of the subsequent process.

[0019] Figure 4H Yes means Figure 4G The diagram of the subsequent process.

[0020] Fig. 4I Yes means Figure 4H The diagram of the subsequent process.

[0021] Figure 4J Yes means Fig. 4I The diagram of the subsequent process.

[0022] Figure 4K Yes means Figure 4J The diagram of the subsequent process.

[0023] Figure 4L Yes means Figure 4K The diagram of the subsequent process.

[0024] Figure 4M Yes means Figure 4L The diagram of the subsequent process.

[0025] Figure 4N Yes means Figure 4M The diagram of the subsequent process.

[0026] Fig.4O Yes means Figure 4N The diagram of the subsequent process.

[0027] Figure 4P Yes means Fig.4O The diagram of the subsequent process.

[0028] Figure 5A It is a diagram showing a planar pattern (first embodiment) of the first photoresist film.

[0029] Figure 5B It is a diagram showing a cross-sectional pattern (first embodiment) of the first photoresist film.

[0030] Fig. 6A It is a diagram showing a planar pattern (second embodiment) of the first photoresist film.

[0031] Figure 6B It is a diagram showing a cross-sectional pattern (second embodiment) of the first photoresist film.

[0032] Fig. 7A It is a diagram showing a planar pattern of the second photoresist film.

[0033] Figure 7B It is a diagram showing a cross-sectional pattern of the second photoresist film.

[0034] Figure 8 This is an enlarged view of the main part of the wafer after the element structure is formed.

[0035] Fig. 9 So Figure 8 An enlarged view of the portion enclosed by the two-dot chain line IX.

[0036] Fig.10 is a schematic top view of the semiconductor device.

[0037] Fig.11 So Fig.10 An enlarged view of the portion surrounded by the two-dot chain line XI.

[0038] Fig. 12A This is a diagram showing the measurement results of the positional deviation of the photoresist film of Sample 1.

[0039] Fig. 12B This is a diagram showing the measurement results of the positional deviation of the photoresist film of Sample 2.

[0040] Fig.13A It is a diagram showing an example of a method for manufacturing the semiconductor device.

[0041] Fig. 13B Yes means Fig.13A The diagram of the subsequent process.

[0042] Fig. 13C Yes means Fig. 13B The diagram of the subsequent process.

[0043] Fig.13D Yes means Fig. 13C The diagram of the subsequent process.

[0044] Fig.13E Yes means Fig.13D The diagram of the subsequent process.

[0045] Fig.13F Yes means Fig.13E The diagram of the subsequent process.

[0046] Fig.14A It is a diagram showing an example of a method for manufacturing the semiconductor device.

[0047] Fig. 14B Yes means Fig.14A The diagram of the subsequent process.

[0048] Fig. 14C Yes means Fig. 14B The diagram of the subsequent process.

[0049] Fig.14D Yes means Fig. 14C The diagram of the subsequent process.

[0050] Fig.14E Yes means Fig.14D The diagram of the subsequent process.

[0051] Fig.14F Yes means Fig.14E The diagram of the subsequent process.

[0052] Fig.15 It is a diagram showing a cross-sectional pattern (third embodiment) of the first photoresist film.

[0053] Fig.16 It is a diagram showing a planar pattern (fourth aspect) of the first photoresist film. DETAILED DESCRIPTION

[0054] [Details]

[0055] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0056] Figure 1 1 is a schematic diagram showing a wafer 1 for manufacturing a semiconductor device 100 .

[0057] Wafer 1 may also be a semiconductor wafer such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), diamond (C), gallium oxide (Ga2O3), etc. Wafer 1 is formed into a flat disk shape. Of course, wafer 1 may also be formed into a flat rectangular parallelepiped shape. Wafer 1 has a first wafer main surface 2 on one side, a second wafer main surface 3 on the other side, and a wafer side surface 4 connecting the first wafer main surface 2 and the second wafer main surface 3.

[0058] The wafer 1 has a mark 5 indicating the crystal orientation of the wafer on the side surface 4 of the wafer. The mark 5 may include one or both of an orientation plane and an orientation notch. The orientation plane includes a notch portion cut out in a straight line when viewed from above. The orientation notch includes a notch portion cut out in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 2 when viewed from above.

[0059] For example, a plurality of device regions 6 and a plurality of planned cutting lines 7 are set on the wafer 1. Each device region 6 corresponds to a semiconductor device 100 (described later) to be finally obtained. Each of the plurality of device regions 6 is set to have a quadrilateral shape in plan view.

[0060] In the above-described method, the plurality of element regions 6 are arranged in a matrix along the first direction X and the second direction Y when viewed from above. The plurality of element regions 6 are arranged with intervals inward from the periphery of the first wafer main surface 2 when viewed from above. The plurality of predetermined cutting lines 7 are arranged in a grid shape extending along the first direction X and the second direction Y in order to divide the plurality of element regions 6.

[0061] Figure 2 yes Figure 1 An enlarged view of the main part of wafer 1. Figure 2 The predetermined cutting line 7 is formed as a strip region of a fixed width. The predetermined cutting line 7 may also be referred to as a "predetermined cutting region". A determination mark region 8 is formed in the predetermined cutting line 7. A determination mark for determining whether there is a pattern deviation in the process of forming the element structure is formed in the determination mark region 8.

[0062] For example, in the process of forming the element structure in the element region 6, a plurality of layers are stacked on the first wafer main surface 2. For each layer, an impurity region, a wiring layer, a contact hole, etc. are formed according to a designed pattern. Each layer is patterned independently of each other (e.g., photolithography). When a position shift occurs between the upper and lower layers, problems such as poor connection will occur, so it is necessary to determine whether the layers are positionally shifted from each other. The determination mark is used to determine whether the position shift occurs.

[0063] In the above-described method, a plurality of determination mark regions 8 are formed on the scheduled cutting line 7. The plurality of determination mark regions 8 are aligned along the length direction of the scheduled cutting line 7 in the portion sandwiched by the adjacent element regions 6. One determination mark region 8 is allocated to the positional deviation determination marks of the upper and lower layers connected to each other. For example, one determination mark region 8 is allocated to the positional deviation determination marks between the first layer and the second layer, and another determination mark region 8 is allocated to the positional deviation determination marks between the second layer and the third layer.

[0064] Figure 3 1 is a diagram showing an element structure 54 formed on a wafer 1. A variety of functional elements are formed in an element region 6. The various functional elements can form, for example, LSI (Large Scale Integration). Examples of such functional elements include CMIS (Complementary MIS (Metal Insulator Semiconductor): complementary metal insulator semiconductor), BJT (Bipolar Junction Transistor): bipolar junction transistor), IGBT (Insulated Gate Bipolar Transistor): insulated gate bipolar junction transistor), JFET (Junction Field Effect Transistor): junction field effect transistor, nonvolatile memory, capacitor, resistor, etc. As an example of these element structures 54, in Figure 3 The structure of the CMIS transistor 9 is described in detail.

[0065] The wafer 1 includes a substrate 10 and an epitaxial layer 11. The substrate 10 may be a p-type silicon substrate. The impurity concentration of the substrate 10 may be, for example, 1.0×10 13 cm -3 Above 1.0×10 20 cm -3 In the above embodiment, the epitaxial layer 11 may be an n-type silicon semiconductor layer. The epitaxial layer 11 is deposited on the substrate 10. The impurity concentration of the epitaxial layer 11 may be, for example, 1.0×10 13 cm -3 Above 1.0×10 17 cm -3 the following.

[0066] In the device region 6, a device isolation portion 12 for dividing the region on the first wafer main surface 2 into a plurality of active regions is formed in the epitaxial layer 11. The device isolation portion 12 may be, for example, an STI (Shallow Trench Isolation) structure. Figure 3In the embodiment, an n-side active region 15 for the n-type first MISFET 13 and a p-side active region 16 for the p-type second MISFET 14 are divided by the element separation portion 12. The CMIS transistor 9 is configured by connecting the first MISFET 13 and the second MISFET 14 complementarily.

[0067] A p-type well 17 is formed on the first wafer main surface 2 of the n-side active region 15. The impurity concentration of the p-type well 17 is higher than the impurity concentration of the epitaxial layer 11, for example, 1.0×10 17 cm -3 Above 1.0×10 19 cm -3 the following.

[0068] In the n-side active region 15, an n-side planar gate structure is formed in the first wafer main surface 2 of the epitaxial layer 11. The n-side planar gate structure includes an n-side gate insulating film 18 and an n-side gate electrode 19 which are stacked in order from the first wafer main surface 2 side. The n-side gate insulating film 18 may include a silicon oxide film. Preferably, the n-side gate insulating film 18 includes a silicon oxide film containing an oxide of the epitaxial layer 11. Preferably, the n-side gate electrode 19 includes conductive polysilicon.

[0069] In the surface layer of the p-type well 17, an n-type source region 20 and an n-type drain region 21 are formed with a gap. The impurity concentration of the n-type source region 20 and the n-type drain region 21 is higher than the impurity concentration of the p-type well 17, for example, 1.0×10 19 cm -3 Above 1.0×10 21 cm -3 Next, the n-type source region 20 and the n-type drain region 21 are formed in self-alignment with respect to the n-side sidewall 22 .

[0070] The n-side active region 15 also includes an n-type source extension region 23 and an n-type drain extension region 24 extending from each of the n-type source region 20 and the n-type drain region 21. The impurity concentration of the n-type source extension region 23 and the n-type drain extension region 24 is lower than the impurity concentration of the n-type source region 20 and the n-type drain region 21, and can be, for example, 1.0×10 18 cm -3 Above 1.0×10 21 cm -3 Next, the n-type source extension region 23 and the n-type drain extension region 24 are formed in self-alignment with respect to the n-side gate electrode 19 .

[0071] The n-side active region 15 also includes a p-type source pocket implant region 25 and a p-type drain pocket implant region 26 extending from each of the n-type source region 20 and the n-type drain region 21. The impurity concentration of the p-type source pocket implant region 25 and the p-type drain pocket implant region 26 is higher than that of the p-type well 17, for example, 1.0×10 18 cm -3 Above 1.0×10 20 cm -3 The p-type source pocket implant region 25 and the p-type drain pocket implant region 26 cross the boundary between the n-side side wall 22 and the n-side gate electrode 19 , and face the n-side gate electrode 19 via the n-side gate insulating film 18 .

[0072] The p-type source pocket implant region 25 and the p-type drain pocket implant region 26 respectively cover the bottom and side of the n-type source extension region 23 and the n-type drain extension region 24. In the central portion of the n-side active region 15, the region sandwiched between the p-type source pocket implant region 25 and the p-type drain pocket implant region 26 is an n-side channel region 27 formed by a portion of the p-type well 17. The n-side gate electrode 19 faces the n-side channel region 27 via the n-side gate insulating film 18.

[0073] In the p-side active region 16, a p-side planar gate structure is formed on the first wafer main surface 2 of the epitaxial layer 11. The p-side planar gate structure includes a p-side gate insulating film 28 and a p-side gate electrode 29 which are stacked in order from the first wafer main surface 2 side. The p-side gate insulating film 28 may include a silicon oxide film. Preferably, the p-side gate insulating film 28 includes a silicon oxide film containing an oxide of the epitaxial layer 11. Preferably, the p-side gate electrode 29 includes conductive polysilicon.

[0074] In the epitaxial layer 11, a p-type source region 30 and a p-type drain region 31 are formed with a gap. The impurity concentration of the p-type source region 30 and the p-type drain region 31 is higher than the impurity concentration of the n-type well, for example, 1.0×10 19 cm -3 Above 1.0×10 21 cm -3 Next, the p-type source region 30 and the p-type drain region 31 are formed in self-alignment with respect to the n-side side wall 32 .

[0075] The p-side active region 16 also includes a p-type source extension region 33 and a p-type drain extension region 34 extending from each of the p-type source region 30 and the p-type drain region 31. The impurity concentration of the p-type source extension region 33 and the p-type drain extension region 34 is lower than the impurity concentration of the p-type source region 30 and the p-type drain region 31, and can be, for example, 1.0×10 18 cm -3 Above 1.0×1021 cm -3 Next, the p-type source extension region 33 and the p-type drain extension region 34 are formed in self-alignment with respect to the p-side gate electrode 29 .

[0076] The p-side active region 16 also includes an n-type source pocket implant region 35 and an n-type drain pocket implant region 36 extending from each of the p-type source region 30 and the p-type drain region 31. The impurity concentration of the n-type source pocket implant region 35 and the n-type drain pocket implant region 36 is higher than that of the epitaxial layer 11, for example, 1.0×10 18 cm -3 Above 1.0×10 20 cm -3 Next, the n-type source pocket implant region 35 and the n-type drain pocket implant region 36 cross the boundary between the p-side side wall 32 and the p-side gate electrode 29 , and face the n-side gate electrode 19 via the p-side gate insulating film 28 .

[0077] The n-type source pocket implant region 35 and the n-type drain pocket implant region 36 respectively cover the bottom and side of the p-type source extension region 33 and the p-type drain extension region 34. In the central part of the p-side active region 16, the region sandwiched between the n-type source pocket implant region 35 and the n-type drain pocket implant region 36 is a p-side channel region 37 formed by a part of the epitaxial layer 11. The p-side gate electrode 29 faces the p-side channel region 37 via the p-side gate insulating film 28.

[0078] An interlayer insulating layer 38 is formed on the first wafer main surface 2 of the epitaxial layer 11. The interlayer insulating layer 38 covers the entire device region 6 and the planned cutting line 7. The interlayer insulating film 38 includes a plurality of insulating layers 39 to 41. In the above embodiment, the first insulating layer 39, the second insulating layer 40, and the third insulating layer 41 are stacked in order from the first wafer main surface 2 side. Each of the insulating layers 39 to 41 may include a silicon oxide film.

[0079] A first conductive layer 42 is formed on the first insulating layer 39. The first conductive layer 42 is covered by the second insulating layer 40. The first conductive layer 42 includes a first wiring layer 43 on the device region 6 side and a first outer layer 44 on the cutting schedule line 7 side. Some of the plurality of first wiring layers 43 are electrically connected to the n-type source region 20, the n-type drain region 21, the p-type source region 30, and the p-type drain region 31 via a first channel electrode 45 embedded in the first insulating layer 39.

[0080] A second conductive layer 46 is formed on the second insulating layer 40. The second conductive layer 46 is covered by the third insulating layer 41. The second conductive layer 46 includes a second wiring layer 47 on the device region 6 side and a second outer layer 48 on the cutting schedule line 7 side. Some of the plurality of second wiring layers 47 are electrically connected to the first wiring layer 43 via second channel electrodes 49 embedded in the second insulating layer 40.

[0081] A third conductive layer 50 is formed on the third insulating layer 41. The third conductive layer 50 includes a third wiring layer 51 on the device region 6 side and a third outer layer 52 on the cutting schedule line 7 side. Some of the plurality of third wiring layers 51 are electrically connected to the second wiring layer 47 via third channel electrodes 53 embedded in the third insulating layer 41.

[0082] Next, refer to Figure 4A to Figure 4P , a process of forming the semiconductor device 100 in the element region 6 of the wafer 1 is described. Figure 4A to Figure 4P The diagram shows an example of a method for manufacturing the semiconductor device 100 in order of steps. Figure 4A to Figure 4P Indicates that the corresponding Figure 3 A cross section of wafer 1.

[0083] refer to Figure 4A After forming the device isolation portion 12 in the device region 6 of the wafer 1, a device structure 54 including the CMIS transistor 9 is formed. Various impurity regions, gate insulating films 18, 28 and gate electrodes 19, 29 of the CMIS transistor 9 are formed by a well-known semiconductor manufacturing technology.

[0084] Next, refer to Figure 4B A first insulating layer 39 as an example of a first layer is formed on the first wafer main surface 2 so as to cover the device structure 54 including the CMIS transistor 9. The first insulating layer 39 can be formed by, for example, CVD (Chemical Vapor Deposition).

[0085] Next, refer to Figure 4C , the first channel electrode 45 is embedded in the first insulating layer 39. For example, a plurality of channel holes are selectively formed in the first insulating layer 39, and each channel hole is backfilled with a conductive material, thereby forming the first channel electrode 45. The first channel electrode 45 may also be formed of tungsten (W), for example.

[0086] Next, refer to Figure 4D, a first conductive layer 42 is formed on the first insulating layer 39. For example, after depositing a conductive material on the first insulating layer 39 by sputtering, the conductive material is patterned, thereby obtaining the first conductive layer 42 selectively formed on the first insulating layer 39. The first conductive layer 42 includes a first wiring layer 43 as an example of a first element pattern on the element region 6 side, and a first outer layer 44 on the cutting schedule line 7 side.

[0087] Here, reference Figure 5A and Figure 5B , the formation process of the first conductive layer 42 is described in more detail. Figure 5A and Figure 5B These are diagrams showing a planar pattern and a cross-sectional pattern of the first photoresist film 55 , respectively. Figure 5B This is a diagram showing an enlarged structure of the planned cutting line 7.

[0088] refer to Figure 5A and Figure 5B , the first outer layer 44 is formed in a ring shape when viewed from above. The first outer layer 44 is a mark that serves as a reference for determining the positional deviation of the first photoresist film 55 in the subsequent process, and may also be referred to as a first reference mark 56. In the above-described method, the first reference mark 56 is a mark that is formed on the main surface of the first insulating layer 39 and is formed in a ring shape when viewed from above. The first reference mark 56 is as shown in FIG. Figure 5A As shown in FIG. 1 , it may be an endless ring or an end ring. The first reference mark 56 may be, for example, Figure 5A The first reference mark 56 may be a ring having an end that is broken by a portion of the ring (e.g., four corners, etc.). Figure 5A The shown four-sided ring shape when viewed from above may also be a perfect circular ring shape, an elliptical ring shape, or a triangular ring shape.

[0089] Next, refer to Figure 4E The second insulating layer 40 is formed on the first insulating layer 39 so as to cover the first conductive layer 42. The second insulating layer 40 can be formed by, for example, a CVD method.

[0090] Next, refer to Figure 4F , the second channel electrode 49 is embedded in the second insulating layer 40. For example, a plurality of channel holes are selectively formed in the second insulating layer 40, and each channel hole is backfilled with a conductive material, thereby forming the second channel electrode 49. The second channel electrode 49 may also be formed of tungsten (W), for example.

[0091] Next, refer to Figure 4G , a first photoresist film 55 is formed on the second insulating layer 40. The first photoresist film 55 is separated from the second insulating layer 40 and indirectly covers the first wiring layer 43 and the first outer layer 44. The first photoresist film 55 may also be a well-known photoresist (either positive or negative). The thickness of the first photoresist film 55 may be, for example, above For example, the material of the first photoresist film 55 is applied to the entire surface of the second insulating layer 40, and after pre-baking, the photoresist material is exposed. The first photoresist film 55 can be obtained by developing the exposed photoresist material. After development, a cleaning (washing) process and a post-baking process can also be performed as needed.

[0092] The first photoresist film 55 after development has a first element-side opening 57 and a first outer opening 58. The first element-side opening 57 matches the pattern of the second wiring layer 47. The first outer opening 58 matches the pattern of the second outer layer 48.

[0093] Here, reference Figure 5A and Figure 5B , the first outer opening 58 is described in detail. Figure 5A , the opening portion of the first photoresist film 55 is indicated by blank, and the film portion of the first photoresist film 55 is indicated by gray. The first outer opening 58 includes a first determination pattern 59, a first surrounding pattern 60, and a second surrounding pattern 61. The first determination pattern 59, the first surrounding pattern 60, and the second surrounding pattern 61 may also be referred to as a first determination opening, a first surrounding opening, and a second surrounding opening, respectively.

[0094] The first determination pattern 59 is formed in a region overlapping with the first reference mark 56 in a plan view. The region overlapping with the first reference mark 56 may be a region including an annular region that coincides with the first reference mark 56 and an inner region of the first reference mark 56 surrounded by the annular region in a plan view. In other words, the entire inner region surrounded by the outer periphery of the first reference mark 56 may be referred to as a region overlapping with the first reference mark 56. In the above embodiment, the first determination pattern 59 is formed in a region that is spaced inward from the first reference mark 56. The first determination pattern 59 may be an island shape in a plan view.

[0095] The first determination pattern 59 is used to confirm whether the first photoresist film 55 is displaced relative to the first wiring layer 43 that has just been formed. Figure 5A As shown, if the distance L1 from the center C1 of the first determination pattern 59 to the width center of the annular first reference mark 56 is substantially constant throughout the circumference of the first reference mark 56 , it can be determined that there is no positional deviation.

[0096] The first surrounding pattern 60 is formed in a ring shape larger than the first reference mark 56 in a plan view, and surrounds the first reference mark 56. The second surrounding pattern 61 is formed in a ring shape larger than the first surrounding pattern 60 in a plan view, and further surrounds the first surrounding pattern 60.

[0097] The first peripheral pattern 60 and the second peripheral pattern 61 are auxiliary opening patterns for suppressing light interference caused by the influence of the plurality of element regions 6 around the line to cut 7. Figure 3 In addition to the CMIS transistor 9 shown, a plurality of functional elements are formed. Therefore, when the first judgment pattern 59 is formed in the judgment mark region 8, optical interference may occur due to the influence of the element structure 54 in the element region 6, and the patterning accuracy of the first judgment pattern 59 may be reduced.

[0098] For example, Fig. 6A and Figure 6B As shown in FIG. 1 , in the aspect of forming only the first judgment pattern 59 as the first outer opening 58, the precision of the exposure process may be reduced due to interference from the surrounding light, and the taper angle θ of the side wall of the first judgment pattern 59 may be offset. Therefore, there is a concern that the position image where the center C1 of the first judgment pattern 59 is offset from the actual center C1 may be mistakenly recognized as the center C1' and judged as positional offset. In particular, the first photoresist film 55 is above Below the relatively thick case, the deviation of the taper angle θ becomes significant.

[0099] In contrast, Figure 5A and Figure 5B As shown in FIG. 1 , if the first surrounding pattern 60 and the second surrounding pattern 61 surrounding the first determination pattern 59 are formed, the light interference caused by the influence of the element structure 54 of the element region 6 can be suppressed. Thus, the cone angle θ in the first determination pattern 59 can be set to be constant. As a result, the accuracy of position shift determination can be improved. In addition, only one of the first surrounding pattern 60 and the second surrounding pattern 61 may be used, but by doubly surrounding the first determination pattern 59, the position determination accuracy can be further improved.

[0100] Next, refer to Figure 4H , the second conductive layer 46 is formed on the second insulating layer 40. For example, by sputtering, a conductive material is deposited on the second insulating layer 40 via the first photoresist film 55. Thus, the second conductive layer 46 including the conductive material deposited inside the first element side opening 57 and the first outer opening 58 is formed. The second conductive layer 46 includes a second wiring layer 47 as an example of a second element pattern on the element region 6 side, and a second outer layer 48 on the cutting schedule line 7 side. Next, referring to Fig. 4I , and remove the first photoresist film 55.

[0101] Here, reference Fig. 7A and Figure 7B , the formation process of the second conductive layer 46 is described in more detail. Fig. 7A and Figure 7B These are diagrams showing a planar pattern and a cross-sectional pattern of the second photoresist film 62 , respectively. Figure 7B This is a diagram showing an enlarged structure of the planned cutting line 7.

[0102] refer to Fig. 7A and Figure 7B The second outer layer 48 includes a second reference mark 63, a first peripheral mark 64, and a second peripheral mark 65. The second reference mark 63 is consistent with the planar shape of the first determination pattern 59, and may be an island shape when viewed from above. The first peripheral mark 64 is consistent with the planar shape of the first peripheral pattern 60, and is formed into a ring shape larger than the second reference mark 63 when viewed from above, and surrounds the second reference mark 63. The second peripheral mark 65 is consistent with the planar shape of the second peripheral pattern 61, and is formed into a ring shape larger than the first peripheral mark 64 when viewed from above, and further surrounds the first peripheral mark 64.

[0103] Next, refer to Figure 4J The third insulating layer 41 is formed on the second insulating layer 40 so as to cover the second conductive layer 46. The third insulating layer 41 can be formed by, for example, a CVD method.

[0104] Next, refer to Figure 4K , a third channel electrode 53 is embedded in the third insulating layer 41. For example, a plurality of channel holes are selectively formed in the third insulating layer 41, and each channel hole is backfilled with a conductive material, thereby forming the third channel electrode 53. The third channel electrode 53 can be formed of tungsten (W), for example.

[0105] Next, refer to Figure 4L , a second photoresist film 62 is formed on the third insulating layer 41. The second photoresist film 62 is separated from the third insulating layer 41 and indirectly covers the second wiring layer 47 and the second outer layer 48. The second photoresist film 62 can be a well-known photoresist (can be either positive or negative). The thickness of the second photoresist film 62 can be, for example, above For example, the material of the second photoresist film 62 is applied to the entire surface of the third insulating layer 41, and after pre-baking, the photoresist material is exposed. The second photoresist film 62 can be obtained by developing the exposed photoresist material. After development, a cleaning (washing) process and a post-baking process can be performed as needed.

[0106] The developed second photoresist film 62 has a second element-side opening 66 and a second outer opening 67 . The second element-side opening 66 matches the pattern of the third wiring layer 51 . The second outer opening 67 matches the pattern of the third outer layer 52 .

[0107] Here, reference Fig. 7A and Figure 7B , the second outer opening 67 is described in detail. Fig. 7AIn FIG. 6 , the opening portion of the second photoresist film 62 is shown as blank, and the film portion of the second photoresist film 62 is shown as gray. The second outer opening 67 includes a second determination pattern 68 , a first surrounding pattern 69 , and a second surrounding pattern 70 .

[0108] The second determination pattern 68 is formed in a region overlapping the second reference mark 63 in a plan view. In the above embodiment, the second determination pattern 68 is formed to cover the entire second reference mark 63. The second determination pattern 68 may be an island shape larger than the second reference mark 63 in a plan view.

[0109] The second determination pattern 68 is used to confirm whether the second photoresist film 62 is displaced relative to the second wiring layer 47 that has just been formed. Fig. 7A As shown, if the distance L2 from the center C2 of the second reference mark 63 to the side wall of the second determination pattern 68 is substantially constant throughout the circumferential direction of the second determination pattern 68, it can be determined that there is no positional deviation.

[0110] The first surrounding pattern 69 is formed in a ring shape larger than the second reference mark 63 in a plan view, and surrounds the second reference mark 63. The second surrounding pattern 70 is formed in a ring shape larger than the first surrounding pattern 69 in a plan view, and further surrounds the first surrounding pattern 69.

[0111] The first peripheral pattern 69 and the second peripheral pattern 70 are auxiliary opening patterns for suppressing light interference caused by the influence of the plurality of device regions 6 around the cutting schedule line 7 , similarly to the first peripheral pattern 60 and the second peripheral pattern 61 of the first photoresist film 55 .

[0112] Therefore, if the first surrounding pattern 69 and the second surrounding pattern 70 surrounding the second determination pattern 68 are formed, the light interference caused by the influence of the element structure 54 of the element region 6 can be suppressed. As a result, the taper angle θ in the second determination pattern 68 can be set to be constant. As a result, the accuracy of positional deviation determination can be improved. In addition, only one of the first surrounding pattern 69 and the second surrounding pattern 70 may be used, but by doubly surrounding the second determination pattern 68, the accuracy of positional deviation determination can be further improved.

[0113] Next, refer to Figure 4M , the third conductive layer 50 is formed on the third insulating layer 41. For example, by sputtering, a conductive material is deposited on the third insulating layer 41 via the second photoresist film 62. Thus, the third conductive layer 50 including the conductive material deposited inside the second element side opening 66 and the second outer opening 67 is formed. The third conductive layer 50 includes the third wiring layer 51 on the element region 6 side and the third outer layer 52 on the cutting scheduled line 7 side. Next, referring to Figure 4N , and remove the second photoresist film 62.

[0114] Next, refer to Fig.4O A surface insulating film 71 is formed on the third insulating layer 41 in such a manner as to cover the third conductive layer 50. The surface insulating film 71 can be formed by, for example, a CVD method. The surface insulating film 71 can be, for example, a silicon oxide film, a silicon nitride film, etc. Thereafter, an opening is selectively formed in the surface insulating film 71, and an external connection pad 72 is formed in each element region 6. Figure 8 2 shows the state of the first wafer main surface 2 of the wafer 1 after the bonding pad 72 is formed.

[0115] Figure 8 This is an enlarged view of a main part of the wafer 1 (wafer device 200 ) after the element structure 54 is formed. Fig. 9 So Figure 8 An enlarged view of the portion enclosed by the two-dot chain line IX.

[0116] refer to Figure 8 and Fig. 9 The wafer device 200 is a wafer 1 in which a device structure 54 is formed in each device region 6. The wafer device 200 may be a wafer 1 after the device structure 54 is formed and before being cut along the predetermined cutting line 7. In the wafer device 200, a semiconductor device 100 having the same device structure 54 is formed in each device region 6. In the determination mark region 8 between adjacent semiconductor devices 100 (device regions 6), a reference mark used for determining the positional deviation of each layer of the photoresist film remains.

[0117] Fig. 9 In the drawing, in the determination mark region 8A at the top of the paper, the first reference mark 56 for determining the positional deviation of the first photoresist film 55 and the second outer layer 48 formed by being deposited in the first outer opening 58 of the first photoresist film 55 remain. In addition, in the determination mark region 8B adjacent to the lower side of the determination mark region 8A, the second reference mark 63 for determining the positional deviation of the second photoresist film 62 and the third outer layer 52 formed by being deposited in the second outer opening 67 of the second photoresist film 62 remain.

[0118] Next, refer to Figure 4P The wafer 1 (wafer device 200 ) is cut along the planned cutting line 7 . Through the above-mentioned steps, a plurality of semiconductor devices 100 are manufactured from one wafer 1 .

[0119] Fig.10 is a schematic top view of the semiconductor device 100 . Fig.11 So Fig.10 An enlarged view of the portion surrounded by the two-dot chain line XI.

[0120] refer to Fig.10 and Fig.11The semiconductor device 100 includes a chip 74 having a device region 6 and a peripheral region 73, a plurality of device structures 54 formed in the device region 6, and a pad 72 electrically connected to each device structure 54. The chip 74 is formed by the substrate 10 and the epitaxial layer 11. The peripheral region 73 surrounding the device region 6 is a remaining portion of the planned cutting line 7.

[0121] In the peripheral region 73, a portion of the second outer layer 48 that is not removed and remains when the wafer 1 is cut is formed as a peripheral pattern 75. Fig.11 As shown, the outer peripheral pattern 75 is formed in a ring shape with an end. In the above embodiment, the outer peripheral pattern 75 includes a first outer peripheral pattern 76 and a second outer peripheral pattern 77 surrounding the first outer peripheral pattern 76.

[0122] One end 78 and the other end 79 of the first peripheral pattern 76 are exposed to the outside from the same end surface 84 of the chip 74, and the middle portion 80 between the one end 78 and the other end 79 is arranged inside the end surface 84 of the chip 74. Similarly, one end 81 and the other end 82 of the second peripheral pattern 77 are exposed to the outside from the same end surface 84 of the chip 74, and the middle portion 83 between the one end 81 and the other end 82 is arranged inside the end surface 84 of the chip 74.

[0123] in addition, Fig.11 In FIG. 7 , only the second outer layer 48 is shown, but a portion of the third outer layer 52 also remains in the outer peripheral region 73 .

[0124] Fig. 12A and Fig. 12B This is a diagram showing the measurement results of the positional deviation of the photoresist film in Sample 1. Fig. 12A and Fig. 12B In the figure, each quadrilateral block represents a region exposed by one light irradiation (one shot) of an exposure device (stepper).

[0125] Fig. 12A Sample 1 is modeled after Figure 5A and Figure 5B For positional deviation determination, a photoresist having a first determination pattern 59 and a first peripheral pattern 60 surrounding the first determination pattern 59 is used. Fig. 12B Sample 2 is modeled after Fig. 6A and Figure 6B For positional deviation determination, a photoresist formed with only the first determination pattern 59 is used.

[0126] exist Fig. 12A and Fig. 12BThe positional offsets in the cross-hatched areas are compared between the two. The amount and direction of the positional offset are indicated by arrows extending from each area. The longer the arrow, the greater the amount of positional offset in the area. More specifically, the residual error of each area is measured, and the measurement results are indicated by arrows in each area. And, by comparing Fig. 12A and Fig. 12B The length of the arrow in the figure is used to determine which area has a larger positional offset. Here, the "residual error" can represent the offset of components other than the stepper's shift offset, rotation offset, magnification offset, etc. that cannot be further corrected.

[0127] Depend on Fig. 12A and Fig. 12B It is understood that the residual error of the sample 1 formed with the first peripheral pattern 60 is smaller than that of the sample 2. As an example, by adopting the configuration of the sample 1, the residual error of the sample 2 in a certain area can be reduced to about 1 / 3.

[0128] Next, refer to Figures 13A to 13F , another embodiment of the method for manufacturing the semiconductor device 100 is described. Figures 13A to 13F In, for 4A~ Figure 4P The same structures as shown are denoted by the same reference numerals, and the description thereof will be omitted. Figures 13A to 13F The process and Figure 4A to Figure 4P The biggest difference between the processes is that Figures 13A to 13F In the step of , the first reference mark opening 85 and the first reference mark embedding layer 86 formed in the second insulating layer 40 are used as reference marks for determining the positional deviation of the first photoresist film 55 .

[0129] In more detail, first, refer to Fig.13A , implementation and Figure 4A to Figure 4E Next, refer to Fig. 13B , a first opening 87 is formed in the second insulating layer 40 as an example of the first layer. The first opening 87 includes a first contact opening 88 on the side of the element region 6 and a first reference mark opening 85 on the side of the predetermined cutting line 7. The first opening 87 is formed by selectively etching the second insulating layer 40. The first wiring layer 43 is exposed from the first contact opening 88, and the first outer layer 44 is exposed from the first reference mark opening 85. The first reference mark opening 85 may also be annular in plan view (see FIG. 1 ), similarly to the first reference mark 56. Figure 5A ).

[0130] Next, refer to Fig. 13CBy depositing a conductive material on the second insulating layer 40, a conductive material is embedded in the first contact opening 88 and the first reference mark opening 85. Thus, the second channel electrode 49 embedded in the first contact opening 88 and the first reference mark embedding layer 86 embedded in the first reference mark opening 85 can be obtained. Since the first reference mark embedding layer 86 is embedded in the first reference mark opening 85, it is formed into a ring shape in plan view.

[0131] Next, refer to Fig.13D The third insulating layer 41 is formed on the second insulating layer 40 so as to cover the second channel electrode 49 and the first reference mark embedded layer 86. The third insulating layer 41 can also be formed by, for example, the CVD method.

[0132] Next, refer to Fig.13E , a first photoresist film 55 is formed on the third insulating layer 41. The first photoresist film 55 is separated from the third insulating layer 41 and indirectly covers the second channel electrode 49 and the first reference mark embedding layer 86. Figure 4G The first photoresist film 55 after development has a first element-side opening 57 and a first outer side opening 58.

[0133] Fig.13E In the process, Figure 5A and Figure 5B Similarly to the first photoresist film 55 shown in the figure, the first outer opening 58 includes the first determination pattern 59, the first surrounding pattern 60, and the second surrounding pattern 61. The positional displacement of the first photoresist film 55 can be determined based on the positional relationship between the first determination pattern 59 and the first reference mark embedding layer 86. In addition, since the first surrounding pattern 60 and the second surrounding pattern 61 surrounding the first determination pattern 59 are formed, the accuracy of the positional displacement determination can be improved.

[0134] Next, refer to Fig.13F The second opening 89 is formed by selectively etching the third insulating layer 41 through the first photoresist film 55. The second opening 89 includes a second contact opening 90 on the device region 6 side and a second reference mark opening 91 on the cutting schedule line 7 side. The second contact opening 90 is an opening for the third channel electrode 53. The second reference mark opening 91 corresponds to Fig. 7A and Figure 7B The second reference mark 63, the first peripheral mark 64 and the second peripheral mark 65 are provided with openings for embedding electrodes. Figure 4H to Figure 4P Each semiconductor device 100 can be obtained through the same process.

[0135] Next, refer to Figures 14A to 14F , another method of manufacturing the semiconductor device 100 is described. Figures 14A to 14F In, with Figure 4A to Figure 4P The same structures as shown are denoted by the same reference numerals, and the description thereof will be omitted. Figures 14A to 14F The process and Figure 4A to Figure 4P The biggest difference between the processes is that Figures 14A to 14F In the process, the position shift determination of the first photoresist film 55 is not performed when forming the wiring but is performed when forming the impurity region and the gate structure.

[0136] For more details, refer to Fig.14A After forming the element isolation portion 12 and the p-type well 17 in the element region 6 of the wafer 1, the impurities are selectively injected into the first wafer main surface 2 through the photoresist film 92. The photoresist film 92 has an opening 93 for selectively exposing the first wafer main surface 2. The opening 93 includes an element side opening 94 on the element region 6 side and an outer side opening 95 on the cutting scheduled line 7 side.

[0137] By implanting impurities through the element side opening 94, a p-type source pocket implant region 25, a p-type drain pocket implant region 26, an n-type source pocket implant region 35, and an n-type drain pocket implant region 36 of a predetermined pattern are formed on the first wafer main surface 2. On the other hand, by implanting impurities through the outer opening 95, a reference mark impurity region 96 of a predetermined pattern is formed on the first wafer main surface 2. The reference mark impurity region 96 may also be annular in plan view (see FIG. 1 ), similarly to the first reference mark 56. Figure 5A ).

[0138] Next, refer to Fig. 14B , a reference conductive layer 97 as an example of the first layer is formed on the first wafer main surface 2. For example, by sputtering, a conductive material is deposited on the first wafer main surface 2 via the photoresist film 92. Thus, a reference conductive layer 97 including a conductive material deposited inside the element side opening 94 and the outer opening 95 is formed. The reference conductive layer 97 of the element side opening 94 is formed in a ring shape when viewed from above.

[0139] Next, refer to Fig. 14C , the photoresist film 92 is removed, and then the reference conductive layer 97 on the device region 6 side is removed. Thus, the reference conductive layer 97 selectively remains as a reference mark 99 on the planned cutting line 7.

[0140] Next, refer to Fig.14D A base insulating film 98 is formed on the first wafer main surface 2 so as to cover the reference conductive layer 97 . The base insulating film 98 is a film that serves as a base for the p-side gate insulating film 28 and the n-side gate insulating film 18 .

[0141] Next, refer to Fig.14E , a first photoresist film 55 is formed on the base insulating film 98. The first photoresist film 55 indirectly covers the reference mark 99 via the base insulating film 98. Figure 4G The first photoresist film 55 after development has a first element-side opening 57 and a first outer side opening 58.

[0142] Fig.14E In the process, Figure 5A and Figure 5B Similarly to the first photoresist film 55 shown in the figure, the first outer opening 58 includes the first determination pattern 59, the first surrounding pattern 60, and the second surrounding pattern 61. The positional displacement of the first photoresist film 55 can be determined based on the positional relationship between the first determination pattern 59 and the reference mark 99. In addition, since the first surrounding pattern 60 and the second surrounding pattern 61 surrounding the first determination pattern 59 are formed, the accuracy of the positional displacement determination can be improved.

[0143] Next, refer to Fig.14F The base insulating film 98 is selectively etched through the first photoresist film 55 to form the p-side gate insulating film 28 and the n-side gate insulating film 18 in the element region 6. After that, the element structure 54 including the CMIS transistor 9 is formed, and then the CMIS transistor 9 is connected to the device region 6. Figure 4A to Figure 4P Each semiconductor device 100 can be obtained by the same process.

[0144] Although the embodiments of the present disclosure have been described, the present disclosure may also be implemented in other forms.

[0145] For example, in the above-described embodiment, the first photoresist film 55 has a first determination pattern 59 as a positional deviation determination pattern, and has a first surrounding pattern 60 and a second surrounding pattern 61 as auxiliary patterns for suppressing light interference. The first determination pattern 59, the first surrounding pattern 60, and the second surrounding pattern 61 are all opening patterns formed in the first photoresist film 55.

[0146] In contrast, Fig.15 As shown in FIG. 1 , the first photoresist film 55 may also have a mesa pattern as a position shift determination pattern and an auxiliary pattern. Figure 5A and Figure 5B For example, the first photoresist film 55 may include a first determination mesa pattern 101 corresponding to the first determination pattern 59, a first peripheral mesa pattern 102 corresponding to the first peripheral pattern 60, and a second peripheral mesa pattern 103 corresponding to the second peripheral pattern 61. In this case, if the distance L1 from the center C1 of the first determination mesa pattern 101 to the width center of the annular first reference mark 56 is substantially constant throughout the circumference of the first reference mark 56, it can be determined that there is no positional deviation.

[0147] In addition, in the above-described embodiment, the first reference mark 56 is annular in plan view, but Fig.16As shown, it can also be formed into an island shape when viewed from above.

[0148] In the above embodiment, the positional deviation of the first photoresist film 55 is determined based on whether the distance L1 from the center C1 of the first determination pattern 59 to the center in the width direction of the annular first reference mark 56 is constant, but it can also be determined by other methods. For example, it can also be determined based on the center of the first determination pattern 59 and the center of the first reference mark 56 ( Figure 5A The position offset is determined by whether the intersection of a pair of diagonal lines is consistent.

[0149] In addition, in the above-described embodiment, the auxiliary pattern for suppressing light interference is a double surrounding structure of the first surrounding pattern 60 and the second surrounding pattern 61, but a third surrounding pattern, a fourth surrounding pattern, ... an nth surrounding pattern (n is a natural number) may be further formed.

[0150] In the above-described embodiment, only the CMIS transistor 9 is shown as an example of the element structure 54 formed on the wafer 1 , but various structures including various functional elements can be adopted as the element structure 54 .

[0151] The embodiments of the present disclosure are illustrative in all points and should not be interpreted restrictively. All points are intended to include modifications.

[0152] The following additional features can be extracted from the description of this specification and the accompanying drawings.

[0153] [Additional Note 1-1]

[0154] A method for manufacturing a semiconductor device (100), comprising:

[0155] In a first step, a first layer (39, 40, 99) is formed on a main surface of a wafer (1), wherein the first layer forms a reference mark (56) for measuring a positional displacement of a photoresist (55) relative to a first element pattern (25, 26, 35, 36, 43) for a semiconductor element (9, 54);

[0156] A second step of forming a photoresist (55) on the first layer (39, 40, 99) in a manner to cover the reference mark (56) and the first element pattern (25, 26, 35, 36, 43);

[0157] In a third step, the photoresist (55) is exposed and developed to form a position shift determination pattern (59, 101) overlapping with the reference mark (56) when viewed from above, a surrounding pattern (60, 61, 102, 103) surrounding the position shift determination pattern (59, 101) when viewed from above, and a second element pattern (47) for the semiconductor element (9, 54) using the photoresist (55); and

[0158] In the fourth step, the position offset of the second element pattern (47) relative to the first element pattern (5, 26, 35, 36, 43) is determined by measuring the relative position of the position offset determination pattern (59, 101) relative to the reference mark (56).

[0159] According to the method, since the surrounding pattern (60, 61, 102, 103) surrounding the position deviation determination pattern (59, 101) is formed outside the reference mark (56), light interference caused by the influence of the surrounding element structure can be suppressed. As a result, the accuracy of the position deviation determination of the photoresist (55) relative to the first element pattern (25, 26, 35, 36, 43) can be improved.

[0160] [Additional Notes 1-2]

[0161] According to the manufacturing method of the semiconductor device (100) described in Note 1-1, in the third step, the photoresist (55) is used to form a plurality of surrounding patterns (61, 103) including a first surrounding pattern (60, 102) surrounding the position offset determination pattern (59, 101) and a second surrounding pattern (61, 103) further surrounding the first surrounding pattern (60, 102).

[0162] According to the method, the accuracy of positional deviation determination can be further improved by doubly surrounding the positional deviation determination pattern (59, 101) with at least the first surrounding pattern (60, 102) and the second surrounding pattern (61, 103).

[0163] [Notes 1-3]

[0164] A method for manufacturing a semiconductor device (100) according to Supplement 1-2, wherein the wafer (1) includes a plurality of element regions (6) for forming the semiconductor elements (9, 54), and a predetermined cutting region (7) for dividing the plurality of element regions (6), and

[0165] The reference mark (56) is formed in the planned cutting area (7).

[0166] [Notes 1-4]

[0167] According to the manufacturing method of the semiconductor device (100) described in Supplement 1-2 or 1-3, the position shift determination pattern (59), the first peripheral pattern (60) and the second peripheral pattern (61) are all opening patterns formed in the photoresist (55).

[0168] [Notes 1-5]

[0169] According to the manufacturing method of the semiconductor device (100) described in Note 1-2 or 1-3, the position shift determination pattern (101), the first surrounding pattern (102) and the second surrounding pattern (103) are all mesa patterns divided by an opening pattern formed in the photoresist (55).

[0170] [Appendix 1-6]

[0171] The method for manufacturing a semiconductor device (100) according to any one of Notes 1-1 to 1-5, wherein the thickness of the photoresist (55) is above the following.

[0172] [Appendix 1-7]

[0173] The method for manufacturing a semiconductor device (100) according to any one of Supplements 1-1 to 1-6, wherein the first step comprises:

[0174] In a first step, an insulating layer (39) is formed as the first layer (39) on the main surface of the wafer (1); and

[0175] In the second step, a conductive material is selectively deposited on the insulating layer (39) to form an element wiring (43) corresponding to the first element pattern (43) and a reference mark conductive layer (56) corresponding to the reference mark (56).

[0176] [Appendix 1-8]

[0177] The method for manufacturing a semiconductor device (100) according to Supplementary Notes 1 to 7, wherein in the first step, the reference mark conductive layer (56) is formed into a ring shape in plan view,

[0178] In the third step, the island-shaped position deviation determination pattern (59, 101) is formed in a region surrounded by the reference mark conductive layer (56) when viewed from above, and the surrounding pattern (60, 61, 102, 103) is formed in a ring shape when viewed from above that surrounds the reference mark conductive layer (56).

[0179] [Appendix 1-9]

[0180] The method for manufacturing a semiconductor device (100) according to any one of Supplements 1-1 to 1-6, wherein the first step comprises:

[0181] In a first step, an insulating layer (40) is formed as the first layer (40) on the main surface of the wafer (1);

[0182] A second step is to form a device wiring opening (88) corresponding to the first device pattern (43) and a reference mark opening (85) corresponding to the reference mark (56) by selectively removing the insulating layer (40); and

[0183] In the third step, the component embedding wiring (49) is embedded in the component wiring opening (88), and the reference mark embedding layer (86) is embedded in the reference mark opening (85).

[0184] [Notes 1-10]

[0185] The method for manufacturing a semiconductor device (100) according to Supplementary Notes 1 to 9, wherein in the first step, the reference mark embedding layer (86) is formed into a ring shape in plan view,

[0186] In the third step, the island-shaped position deviation determination pattern (59, 101) is formed in a region surrounded by the reference mark embedding layer (86) when viewed from above, and the surrounding pattern (60, 61, 102, 103) is formed in a ring shape when viewed from above that surrounds the reference mark embedding layer (86).

[0187] [Appendix 1-11]

[0188] The method for manufacturing a semiconductor device (100) according to any one of Supplements 1-1 to 1-6, wherein the first step comprises:

[0189] The first step is to selectively implant impurities into the main surface of the wafer (1) to form element impurity regions (25, 26, 35, 36) corresponding to the first element pattern (25, 26, 35, 36) and an impurity region (96) for a reference mark; and

[0190] In the second step, the reference mark (99) is formed by selectively leaving the first layer (99) on the reference mark impurity region (96) on the main surface of the wafer (1).

[0191] [Appendix 1-12]

[0192] The method for manufacturing a semiconductor device (100) according to Supplementary Notes 1 to 11, wherein in the first step, the reference mark (99) is formed into a ring shape in a plan view,

[0193] In the third step, the position deviation determination pattern (59, 101) in an island shape when viewed from above is formed on an area surrounded by the reference mark (99), and the surrounding pattern (60, 61, 102, 103) is formed in a ring shape when viewed from above that surrounds the reference mark (99).

[0194] [Appendix 1-13]

[0195] A semiconductor wafer (200), comprising:

[0196] A wafer body (1) having a plurality of component regions (6) and a predetermined cutting region (7) for dividing the plurality of component regions (6);

[0197] A first element pattern (43) formed in each of the element regions (6);

[0198] An outer mark (56) is formed in the same layer as the first element pattern (43) and in the predetermined cutting region (7);

[0199] A second element pattern (47) formed in an upper region of the first element pattern (43);

[0200] The outer pattern (63) and the surrounding patterns (64, 65) are formed in the predetermined cutting area (7) in the same layer as the second element pattern (47), wherein the outer pattern (63) overlaps with the outer mark (56) when viewed from above, and the surrounding patterns (64, 65) surround the outer mark when viewed from above.

[0201] [Appendix 1-14]

[0202] A semiconductor device (100), comprising:

[0203] A chip (74) having a component region (6) and a peripheral region (73);

[0204] A device pattern (47) formed in the device region (6); and

[0205] The peripheral patterns (75, 76, 77) are formed in the peripheral region (73) in the same layer as the element pattern (47) and are formed into a ring shape with ends when viewed from above; and

[0206] One end (78, 81) and the other end (79, 82) of the peripheral pattern (75, 76, 77) with an end ring are exposed to the outside from the same end surface (84) of the chip, and the portion (80, 83) between the one end (78, 81) and the other end (79, 82) is arranged on the inner side of the end surface (84) of the chip (74).

[0207] [Note 1-15]

[0208] The semiconductor device (100) according to Supplementary Notes 1 to 14, wherein the peripheral pattern (75, 76, 77) includes a first peripheral pattern (76) and a second peripheral pattern (77) surrounding the first peripheral pattern (76).

[0209] [Explanation of symbols]

[0210] 1 Wafer

[0211] 2 Main surface of wafer 1

[0212] 3. Second wafer main surface

[0213] 4 Wafer side

[0214] 5 Mark

[0215] 6 Component Area

[0216] 7 Cutting off the predetermined line

[0217] 8 Determine the marked area

[0218] 8A Determine the marked area

[0219] 8B determination mark area

[0220] 9CMIS transistor

[0221] 10 substrate

[0222] 11 Epitaxial layer

[0223] 12 Component separation unit

[0224] 15n side active area

[0225] 16p side active region

[0226] 17p-type well

[0227] 18n side gate insulation film

[0228] 19n-side gate electrode

[0229] 20n-type source region

[0230] 21n-type drain region

[0231] 22n side wall

[0232] 23n-type source extension region

[0233] 24n-type drain extension region

[0234] 25p source pocket implant region

[0235] 26p type drain pocket implant region

[0236] 27n side channel region

[0237] 28p side gate insulation film

[0238] 29p side gate electrode

[0239] 30p type source region

[0240] 31p type drain region

[0241] 32p side wall

[0242] 33p-type source extension region

[0243] 34p-type drain extension region

[0244] 35n-type source pocket implant area

[0245] 36n-type drain pocket implant region

[0246] 37p side channel region

[0247] 38 interlayer insulation layer

[0248] 39 1st insulation layer

[0249] 40 2nd insulation layer

[0250] 41 3rd insulation layer

[0251] 42 1st conductive layer

[0252] 431st wiring layer

[0253] 44 1st outer layer

[0254] 45 Channel 1 Electrode

[0255] 46 2nd conductive layer

[0256] 47 2nd wiring layer

[0257] 48 2nd outer layer

[0258] 49 Channel 2 Electrode

[0259] 50 3rd conductive layer

[0260] 51 3rd wiring layer

[0261] 52 3rd outer layer

[0262] 53 Channel 3 Electrode

[0263] 54-component construction

[0264] 55 1st photoresist film

[0265] 561st reference mark

[0266] 57 1st element side opening

[0267] 58 1st outer opening

[0268] 59 1st judgment pattern

[0269] 60 1st surrounding pattern

[0270] 61 Second surrounding pattern

[0271] 62 2nd photoresist film

[0272] 63 2nd reference mark

[0273] 64 1st surrounding mark

[0274] 65 2nd surrounding mark

[0275] 66 2nd element side opening

[0276] 67 2nd outer opening

[0277] 68 2nd judgment pattern

[0278] 69 1st surrounding pattern

[0279] 70 2nd surrounding pattern

[0280] 71 Surface insulation layer

[0281] 72 solder pads

[0282] 73 Peripheral area

[0283] 74 chips

[0284] 75 peripheral pattern

[0285] 76 1st outer pattern

[0286] 77 2nd peripheral pattern

[0287] 78 one end

[0288] 79 The other end

[0289] 80 Middle

[0290] 81 one end

[0291] 82 The other end

[0292] 83 Middle

[0293] 84 end face

[0294] 85 1st reference mark opening

[0295] 86 1st reference mark embedding layer

[0296] 87 Opening 1

[0297] 88 1st contact opening

[0298] 89 Opening 2

[0299] 90 2nd contact opening

[0300] 91 2nd reference mark opening

[0301] 92 Photoresist film

[0302] 93 Open

[0303] 94 Component side opening

[0304] 95 outside opening

[0305] 96 Impurity area for reference mark

[0306] 97 reference conductive layer

[0307] 98 base insulation film

[0308] 99 Benchmarks

[0309] 100Semiconductor devices

[0310] 101 No. 1 Determination of the Board Pattern

[0311] 102 1st surrounding table pattern

[0312] 103 2nd surrounding table pattern

[0313] 200 wafer devices.

Claims

1. A method for manufacturing a semiconductor device, comprising: In a first step, a first layer is formed on a main surface of a wafer, wherein the first layer has a reference mark for measuring a positional shift of a photoresist relative to a first element pattern for a semiconductor element; A second step of forming a photoresist on the first layer in a manner covering the reference mark and the first element pattern; A third step is to form a position shift determination pattern overlapping with the reference mark when viewed from above, a peripheral pattern surrounding the position shift determination pattern when viewed from above, and a second element pattern for the semiconductor element using the photoresist by exposing and developing the photoresist; and In a fourth step, a relative position of the positional deviation determination pattern with respect to the reference mark is measured to thereby determine a positional deviation of the second element pattern with respect to the first element pattern.

2. The method for manufacturing a semiconductor device according to claim 1, wherein in the third step, the photoresist is used to form a plurality of the peripheral patterns including a first peripheral pattern surrounding the positional deviation determination pattern and a second peripheral pattern further surrounding the first peripheral pattern.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the wafer includes a plurality of device regions for forming the semiconductor device and a predetermined cutting region for dividing the plurality of device regions, The reference mark is formed on the planned cutting region. 4 . The method for manufacturing a semiconductor device according to claim 2 , wherein the positional deviation determination pattern, the first surrounding pattern, and the second surrounding pattern are all opening patterns formed in the photoresist. 5 . 5 . The method for manufacturing a semiconductor device according to claim 2 , wherein the positional deviation determination pattern, the first surrounding pattern, and the second surrounding pattern are all mesa patterns partitioned by an opening pattern formed in the photoresist.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the thickness of the photoresist is above the following.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first step comprises: In a first step, an insulating layer as the first layer is formed on the main surface of the wafer; and In the second step, a conductive material is selectively deposited on the insulating layer to form a device wiring corresponding to the first device pattern and a reference mark conductive layer corresponding to the reference mark.

8. The method for manufacturing a semiconductor device according to claim 7, wherein in the first step, the reference mark conductive layer is formed into a ring shape in plan view, In the third step, the positional deviation determination pattern having an island shape in plan view is formed in a region surrounded by the reference mark conductive layer, and the surrounding pattern is formed in a ring shape in plan view surrounding the reference mark conductive layer.

9. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first step comprises: In the first step, an insulating layer as the first layer is formed on the main surface of the wafer; The second step is to form a component wiring opening corresponding to the first component pattern and a reference mark opening corresponding to the reference mark by selectively removing the insulating layer; and In a third step, a component embedding wiring is embedded in the component wiring opening, and a reference mark embedding layer is embedded in the reference mark opening.

10. The method for manufacturing a semiconductor device according to claim 9, wherein in the first step, the reference mark embedding layer is formed into a ring shape in plan view, In the third step, the positional deviation determination pattern having an island shape in plan view is formed in a region surrounded by the reference mark embedding layer, and the surrounding pattern is formed in a ring shape in plan view surrounding the reference mark embedding layer.

11. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first step comprises: The first step is to form an element impurity region corresponding to the first element pattern and an impurity region for a reference mark by selectively implanting impurities into the main surface of the wafer; and In the second step, the reference mark is formed by selectively leaving the first layer on the reference mark impurity region on the main surface of the wafer.

12. The method for manufacturing a semiconductor device according to claim 11, wherein in the first step, the reference mark is formed in a ring shape in plan view, In the third step, the positional deviation determination pattern having an island shape in plan view is formed in a region surrounded by the reference mark, and the surrounding pattern is formed in a ring shape in plan view surrounding the reference mark.

13. A semiconductor wafer comprising: A wafer body having a plurality of component regions and predetermined cutting regions for dividing the plurality of component regions; A first device pattern is formed in each of the device regions; An outer mark is formed in the same layer as the first element pattern and in the predetermined cutting area; a second element pattern formed in an area above the first element pattern; The outer pattern and the peripheral pattern are formed in the same layer as the second element pattern in the predetermined cutting region, wherein the outer pattern overlaps the outer mark in a plan view, and the peripheral pattern surrounds the outer mark in a plan view.

14. A semiconductor device comprising: A chip having a component area and a peripheral area; A device pattern is formed in the device region; and The peripheral pattern is formed in the same layer as the element pattern in the peripheral region and is formed into a ring shape with ends when viewed from above; and One end and the other end of the end ring of the outer peripheral pattern are exposed to the outside from the same end surface of the chip, and a portion between the one end and the other end is arranged inside the end surface of the chip. 15 . The semiconductor device according to claim 14 , wherein the outer peripheral pattern includes a first outer peripheral pattern and a second outer peripheral pattern surrounding the first outer peripheral pattern.

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