Buffer circuit and method for providing floating reference signal, and voltage generation circuit

Abstract

The invention relates to a buffer circuit and method for providing a floating reference signal, and a voltage generation circuit. In one embodiment, a buffer circuit for providing a floating reference signal includes an operational amplifier including a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input represents a non-inverting input and is configured to receive a first input signal. The second input represents another non-inverting input and is configured to receive a second input signal. And the third input end represents an inverted input end. And the output end forms the output of the buffer circuit. The operational amplifier is configured as a voltage follower. The buffer circuit is configured to provide a first input signal or a second input signal at its output such that the lower one of the first input signal and the second input signal is provided as the floating reference signal.

Description

Technical Field

[0001] The present disclosure relates to electronic circuits, and more particularly to the generation of reference signals. Specifically, the present disclosure relates to a buffer circuit for providing a floating reference signal, a voltage generating circuit, and a method for providing a floating reference signal. Background Art

[0002] Many circuits, such as integrated circuits, require reference signals, which are usually generated internally by a source external to the chip. The source may be implemented as a supply voltage source. The generated reference signal may represent a reference current or a reference voltage. The reference signal is designed to maintain a constant level over supply voltage variations, temperature range variations, and manufacturing process variations.

[0003] The reference signal is usually used to control transistors within the circuit, such as metal oxide semiconductors, MOS transistors or bipolar transistors. The transistor has a defined operating range, which in the case of MOS transistors is defined by the maximum gate-source voltage of the transistor. In circuits using high voltage power supplies, the high voltage value on the power supply exceeds the operating range of the transistor used, i.e., the gate-source voltage. As a result, simple digital circuit elements based on complementary MOS, CMOS technology (such as inverters) cannot be used to control the gate terminal of a switching transistor, where a signal switching from the highest value of the supply voltage (usually referred to as VDD) to the lowest value of the supply voltage (usually referred to as VSS, i.e., zero volts) should control both the p-channel MOS (PMOS) and n-channel MOS (NMOS) transistors involved.

[0004] In contrast, for these high voltage circuits, separate signals must be provided to the control inputs or gate terminals of the NMOS and PMOS transistors. The signals are level-shifted from each other in order to keep both transistor types within their safe operating ranges. For example, the signal controlling the PMOS gate ideally switches from VDD when the transistor is turned off to VDD minus the maximum gate-source voltage when the transistor is turned on. To this end, circuit designers must conceptualize a so-called floating reference signal, which serves as a "lower" reference for controlling the gate terminal of the PMOS transistor. The floating reference signal is defined with respect to the supply voltage. For example, it tracks a supply voltage slightly higher than VDD minus the maximum gate-source voltage. The margin of VDD minus the maximum gate-source voltage is usually set to ensure that the reference signal does not fall below VDD minus the maximum gate-source voltage even in the case of environmental and process variations. The smaller the variation in the generation of the floating reference, the closer the voltage value of the signal can be set to VDD minus the maximum gate-source voltage.

[0005] A common approach is to use a bandgap circuit to get a highly accurate reference of VDD minus the maximum gate-source voltage. The bandgap circuit nominally provides a reference signal that is completely unaffected by supply voltage and environmental or process variations. Typically, such a bandgap circuit operates on a low voltage circuit and outputs a reference signal that is X volts above ground. This reference voltage is transferred to a high voltage circuit using a current mirror and a matched resistor to form a new reference signal that is VDD minus k times X volts, where k is some constant. The reference signal is then buffered by a reference buffer on the VDD (i.e., high voltage) domain.

[0006] The inventors have found that this solution is feasible in principle, but it has the disadvantage that the bandgap circuit is slow to turn on. Bandgap circuits usually use very large resistors internally in order to minimize their power consumption. However, large resistors lead to long stabilization times during power-up. In the case where a PMOS transistor in the circuit that relies on a reference signal provided by the bandgap needs to remain on during startup, the circuit design of the prior art fails because it takes some time before the bandgap starts and provides a reference signal of the required level. Moreover, if a low voltage difference LDO circuit is used as an additional power supply to reduce the power consumption of the bandgap circuit, the LDO requires a reference signal, which is usually provided by the bandgap circuit. This leads to a chicken-and-egg problem at least during the power-up of the circuit.

[0007] Therefore, it is an object of the present invention to provide a solution that overcomes the disadvantages of prior art circuit designs. In particular, a solution should be provided that enables a suitable reference signal to be provided as quickly as possible during startup for transistors operating in a voltage range outside their operating range.

[0008] This object is achieved by the subject matter of the present invention. Embodiments and developments are defined in further aspects.

[0009] Unless stated otherwise, the definitions provided above also apply to the following description. Summary of the invention

[0010] In one embodiment, a buffer circuit for providing a floating reference signal includes an operational amplifier having a first input terminal, a second input terminal, a third input terminal and an output terminal. The first input terminal represents a non-inverting input terminal, which is configured to receive a first input signal. The second input terminal represents another non-inverting input terminal, which is configured to receive a second input signal. The third input terminal represents an inverting input terminal. The output terminal forms the output of the buffer circuit. The operational amplifier is configured as a voltage follower, and the output terminal of the operational amplifier is connected to its third input terminal. The buffer circuit is configured to provide a first input signal or a second input signal at its output terminal, so that the lower one of the first input signal and the second input signal is provided as the floating reference signal.

[0011] The floating reference provided by the operational amplifier comprises the first input signal or the second input signal, depending on which of the two input signals is lower at the moment of providing the output signal. In other words, the operational amplifier of the buffer circuit buffers the lower of the first input signal and the second input signal. Thus, one input signal can be provided by, for example, a bandgap circuit, while the other input signal can be provided by a simple and less precise but fast starting voltage source. The resulting floating reference signal can be used to control a transistor operating in the high voltage range at an early point in time during the start-up process. Temporary overloading of the transistor is thereby avoided.

[0012] In one development, the floating reference signal is configured to control at least one transistor coupled to a high voltage supply terminal. The supply voltage on the high voltage supply terminal is outside an operating range of the transistor.

[0013] The at least one transistor can be implemented as a MOS or bipolar transistor. For example, the operating range of a PMOS transistor is substantially defined by its gate-source voltage. An example value for such a PMOS transistor is about 1.8 V. The value is determined by the oxide used. An example value for the supply voltage at the high voltage supply terminal is between 3.3 and 3.6 V. The floating reference signal provided by the proposed buffer circuit can be used to control at least one PMOS transistor, in particular its gate terminal, during startup, even if the supply voltage exceeds the operating range of the PMOS transistor.

[0014] In one development, the buffer circuit is configured to operate in a first operating mode or in a second operating mode. In the first mode, the first input signal is buffered and provided as the floating reference signal. In the second mode, the second input signal is buffered and provided as the floating reference signal.

[0015] The buffer circuit starts operating in the first mode and then directly enters the second mode.

[0016] According to one development, in the first mode, the supply voltage is configured to be switched on, the first input signal and the second input signal are configured to start after the supply voltage. The voltage component of the first input signal is configured to obtain a value lower than the supply voltage by at least one threshold voltage of the at least one transistor after an initial delay. Furthermore, in the first mode, the voltage component of the second input signal is configured to track the supply voltage and subsequently decrease to the level of the voltage component of the first input signal.

[0017] In the first mode, the supply voltage is turned on, and the first input signal and the second input signal are started with the increased levels of their respective voltage components. In the first mode, the level of the voltage component of the first input signal is always lower than the level of the voltage component of the second input signal. The first input signal obtains or adopts or assumes a value of at least one threshold voltage of at least one transistor (e.g., a PMOS transistor) lower than the supply voltage, which is controlled by a floating reference signal. The level of the voltage component of the second input signal rises with the supply voltage and then decreases. Once the level of the voltage component of the first input signal is reached in this decrease, it is switched to the second mode.

[0018] Thereby it is ensured that the gate terminal of the at least one PMOS transistor is controlled when the buffer circuit starts operating.For example, the PMOS transistor is intentionally switched on in a controlled manner by using the first input signal as a floating reference signal and supplying it to the gate of the PMOS transistor.

[0019] According to one development, in the second mode, the voltage component of the first input signal is configured to obtain a value lower than the supply voltage by at least one threshold voltage of the at least one transistor. Furthermore, in the second mode, the voltage component of the second input signal is adjusted to a value lower than the value of the voltage component of the first input signal in the second mode.

[0020] Thus, in the second mode, the level of the voltage component of the second input signal is always lower than the level of the voltage component of the first input signal, so that the buffer circuit provides the second input signal as a floating reference signal. In the second mode, the voltage component of the first input signal remains more or less at the level reached at the end of the first mode, i.e., one or two or three threshold voltages below the supply voltage of at least one transistor. The level of the voltage component of the second input signal decreases to a level lower than the level of the first input signal, for example to a value lower than the supply voltage by about the maximum gate-source voltage of at least one PMOS transistor. The buffer circuit continues to operate in the second mode.

[0021] Therefore, the proposed buffer circuit provides a floating reference signal so that especially the PMOS transistor can be fully controlled immediately after power-up, even in the high voltage domain.

[0022] In one development, the first input signal is configured to be provided by a first voltage source. The first voltage source comprises one of the following: at least one other transistor configured as a diode-connected transistor, a pn diode or a resistor. The second signal is configured to be provided by a second voltage source comprising a bandgap circuit.

[0023] The implementation of the bandgap circuit is known to those skilled in the art. It is basically in accordance with the bandgap circuits described above in the background section, which have a slow turn-on speed. The bandgap circuit may or may not have an internal so-called startup circuit, as known to those skilled in the art. The first voltage source is implemented in a simple manner, for example by providing one or two or even three (depending on the operating range of the transistor and the supply voltage) diode-connected transistors (e.g. PMOS transistors), or pn diodes, or resistors in series to a suitable current source. Each of these implementations provides a first input signal whose voltage component has a level of about one or two or even three threshold voltages of the transistor controlled by the floating reference signal. Thus, the first input signal is provided as a rough reference with a floating reference signal, while the second input signal is a precise reference signal. Once the supply voltage reaches a level that enables its components to operate, the first input signal is provided at the required level. The rough reference signal (i.e., the first input signal) is buffered and provided as a floating reference signal for controlling one or more downstream connected transistors (e.g. PMOS transistors) until the bandgap circuit of the second voltage source is properly started and can provide the second input signal of the required level. It is thereby ensured that even during the start-up of the bandgap circuit of the second voltage source, the transistor connected downstream is still controlled by using the first input signal as a floating reference signal in an auxiliary manner. Due to its simple implementation, the first voltage source starts faster than the second voltage source. Thus, only from the moment of switching on the supply voltage, at least one PMOS transistor can be turned on by control of the floating reference signal without damaging it. The above-mentioned chicken and egg problem is thus also solved.

[0024] In one development, the operational amplifier comprises a first transistor, a second transistor and a third transistor, a current source, a first current mirror, a second current mirror and a third current mirror. The first transistor comprises a control terminal representing a first input of the operational amplifier. The second transistor comprises a control terminal representing a second input of the operational amplifier. The third transistor comprises a control terminal representing a third input of the operational amplifier. The current source is connected to the high voltage supply terminal on the one hand and to the respective second terminals of the first transistor, the second transistor and the third transistor on the other hand. The first current mirror has an input terminal connected to the respective third terminals of the first transistor and the second transistor, and an output terminal representing an output of the operational amplifier. The second current mirror comprises an input terminal connected to the third terminal of the third transistor, and an output terminal. The third current mirror comprises an input terminal connected to the output terminal of the second current mirror, and an output terminal connected to the output of the operational amplifier.

[0025] By means of transistors, current sources and current mirrors, a buffer circuit is implemented such that the input terminal of the first input terminal and the second input terminal receiving a lower input signal turns on the transistor involved more. Therefore, the current provided by the current source flows to the transistor and is mirrored toward the output terminal by the first current mirror or alternatively by the second current mirror and the third current mirror. Therefore, the output is pulled up or pulled down. Due to negative feedback (i.e., the output terminal is connected to the third input terminal), the output follows the negative input. By using a second transistor (whose gate terminal represents the second input terminal of the operational amplifier), the current provided by the current source swings to the side that pulls the output low because the first input or the second input is lower than the third input.

[0026] The first transistor, the second transistor and the third transistor can all be implemented by PMOS transistors. The current source can be implemented by another current mirror composed of PMOS transistors, for example.

[0027] In one development, the first current mirror and the second current mirror each comprise at least two transistors of the same type. The third current mirror comprises at least two transistors of a type complementary to the type of transistors of the first current mirror and the second current mirror. In each case, the transistors are connected in a current mirror configuration known to those skilled in the art.

[0028] In one embodiment, a voltage generating circuit includes the buffer circuit as described above, a first voltage source, and a second voltage source. The first voltage source is configured to provide the first input signal and is coupled to the first input terminal of the operational amplifier of the buffer circuit. The second voltage source is configured to provide the second input signal and is coupled to the second input terminal of the operational amplifier of the buffer circuit.

[0029] The first voltage source may be implemented by using at least one PMOS transistor configured as a diode-connected transistor, a pn diode or a resistor in series with a current source as described above. The second voltage source may include a bandgap circuit, also as described above.

[0030] Thus, the voltage generating circuit is enabled to provide a floating reference signal in a first mode by providing a first input signal generated by a first voltage source and in a second mode by providing a second input signal generated by a second voltage source. Thus, in the first mode, the first input signal is provided as a floating reference signal immediately after startup of the supply voltage, i.e. as a less precise reference derived from, for example, the threshold voltage of a PMOS transistor. As soon as the second voltage source (i.e. the bandgap circuit) is stable and fully operational, the precise output signal of the bandgap circuit is used as the floating reference signal. This simple solution enables at least one downstream connected transistor (e.g. a PMOS transistor) to be controlled in the high voltage domain even during startup of the bandgap circuit.

[0031] The proposed buffer circuit and / or voltage generating circuit can be applied to or implemented by a circuit using CMOS or bipolar transistor technology.

[0032] In one embodiment, a method for providing a floating reference signal comprises the following steps:

[0033] - receiving a first input signal,

[0034] - receiving a second input signal, and

[0035] - providing the first input signal or the second input signal such that a lower one of the first input signal and the second input signal is provided as the floating reference signal.

[0036] The method may be implemented by a buffer circuit according to one of the above embodiments.

[0037] In one development, the method further comprises the following steps:

[0038] In the first operating mode:

[0039] - turning on a high voltage power supply and ramping up the supply voltage provided by said high voltage power supply,

[0040] - using said supply voltage to generate said first input signal and said second input signal,

[0041] - ramping up the first input signal and providing it as the floating reference signal, the first input signal comprising a voltage component whose value is at least a threshold voltage lower than the supply voltage

[0042] - ramping up the second input signal until its voltage component approximately reaches the value of the supply voltage and subsequently ramping down the voltage component of the second input signal to the level of the voltage component of the first input signal.

[0043] The threshold voltage represents a threshold voltage of at least one transistor controlled by a floating reference signal.

[0044] In one development, the method comprises the following steps:

[0045] In the second operating mode:

[0046] - providing said first input signal, the value of a voltage component of which is at least a threshold voltage lower than said supply voltage,

[0047] - further ramping down the voltage component of the second input signal to a value lower than the value of the voltage component of the first input signal in the second mode, and

[0048] - providing said second input signal as said floating reference signal,

[0049] The second operation mode follows the first operation mode.

[0050] By using the proposed method, i.e. by using two different input signals to generate a floating reference signal, the reference signal can be used to control the operation of at least one transistor, e.g. a PMOS transistor, implemented in a downstream connected circuit which is powered by a voltage in a range outside the operating range of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The proposed solution will be explained in detail below using exemplary embodiments in conjunction with the accompanying drawings. Components and elements with the same function or the same effect have the same reference numerals. As long as the components or assemblies correspond to each other in function, their description will not be repeated in the following figures.

[0052] Figure 1 shows an exemplary embodiment of a voltage generating circuit having the proposed buffer circuit,

[0053] Figure 2 shows an exemplary implementation of the proposed operational amplifier,

[0054] Figure 3 shows an example signal diagram, and

[0055] Figure 4 shows an exemplary implementation of the buffer circuit proposed in the application example,

[0056] Figure 5 Another exemplary embodiment of the buffer circuit proposed in the application example is shown, and

[0057] Figure 6 An exemplary embodiment of the proposed method is shown.

[0058] Reference numerals list

[0059] Sin1, Sin2, Sfgnd signals

[0060] VS1, VS2 voltage sources

[0061] CS, CS1 current source

[0062] 10, 20 terminals

[0063] 100 Operational Amplifier

[0064] 101, 102, 103, 104, 105, 106, 107 terminals

[0065] 108, 109 terminals

[0066] TP1, TP2, TP3 transistors

[0067] N1, N2, N3, N4 transistors

[0068] P1, P2, M6, M61, MF, MG transistors

[0069] LS Level Shifter

[0070] INV Inverter

[0071] BGS startup circuit

[0072] CM1, CM2, CM3 current mirrors

[0073] t0, t1, t2, t3, t4, t5, t6 time points

[0074] Op1, Op2 mode

[0075] S1, S2, S3, S31, S32 Method Steps

[0076] VDD supply voltage DETAILED DESCRIPTION

[0077] Figure 1An exemplary embodiment of a voltage generating circuit with the proposed buffer circuit is shown. The buffer circuit includes an operational amplifier 100, which includes a first input terminal 101, a second input terminal 102, a third input terminal 103 and an output terminal 104. The first input terminal 101 represents a non-inverting input terminal p1, which is configured to receive a first input signal Sin1. The second input terminal 102 represents a second non-inverting input terminal p2, which is configured to receive a second input signal Sin2. The third input terminal 103 represents an inverting input terminal m1. The first input terminal 101 and the second input terminal 102 of the operational amplifier 100 implement the first input and the second input of the buffer circuit. The output terminal 104 forms the output of the buffer circuit. The output terminal 104 is connected to the third input terminal 103, which configures the operational amplifier 100 as a voltage follower. The buffer circuit is configured to provide the first input signal Sin1 or the second input signal Sin2 at an output terminal 104 thereof, such that a lower one of the first input signal Sin1 and the second input signal Sin2 is provided as a floating reference signal Sfgnd.

[0078] A floating reference is required for high voltage circuit designs which can operate in the 3.3V range using, for example, 1.8V devices (i.e., CMOS or bipolar transistors), as described above. For NMOS transistors, these devices are stacked between ground potential and the floating reference, while for PMOS transistors, these devices are stacked between the floating reference and a supply voltage of about 3.3V. By using the proposed buffer circuit comprising an operational amplifier 100 having two non-inverting input terminals p1 and p2, the lower of the first input signal Sin1 and the second input signal Sin2 is provided as a floating reference signal Sfgnd. This ensures the correct start-up of the floating reference signal Sfgnd, thereby preventing temporary overload of the devices (especially the PMOS transistors) controlled by the floating reference signal Sfgnd.

[0079] The depicted voltage generating circuit includes a buffer circuit and a first voltage source VS1 as described above, and a second voltage source VS2. The first voltage source VS1 is configured to provide a first input signal Sin1, and the second voltage source VS2 is configured to provide a second input signal Sin2. The first voltage source VS1 is connected to a first input terminal 101 of the operational amplifier 100. The first voltage source VS1 includes at least one PMOS transistor configured as a diode-connected transistor, or a pn diode or a resistor, each of which is connected in series with a current source to form a supply voltage, such as a high supply voltage. The second voltage source VS2 is connected to a second input terminal 102 of the operational amplifier 100. The second voltage source VS2 includes a bandgap circuit known to those skilled in the art. The second input signal Sin2 is provided by the second voltage source VS2 in a highly accurate manner and is not affected by changes in the supply voltage and / or environmental conditions or processes. For example, the first input signal Sin1 provided by the first voltage source VS1 is obtained based on the threshold voltage of the PMOS transistor used in the voltage source. A fixed current provided by the current source flows through at least one diode-connected PMOS transistor to generate the first input signal Sin1. Compared to the bandgap circuit of the second voltage source VS2 which starts up slowly, the first voltage source VS1 designed as described starts up faster.

[0080] The buffer circuit is configured to operate in a first mode or a second mode. In the first mode, the first input signal Sin1 is buffered by the operational amplifier 100 and provided as a floating reference signal Sfgnd. In the second mode, the second input signal Sin2 is buffered and provided as a floating reference signal Sfgnd. Thus, the first input signal Sin1 is used as an auxiliary reference and is provided as a floating reference signal Sfgnd from the start of operation of the buffer circuit in the first mode (i.e., power-on). Once the second voltage source VS2 is fully turned on and provides the second input signal Sin2 at a desired level, the buffer circuit enters the second mode and the second input signal Sin2 is provided as a floating reference signal Sfgnd. Among them, the first input signal Sin1 is designed so that during operation (i.e., in the second mode), it is always higher than the second input signal Sin2, so that the first input signal Sin1 is only used in the first operating mode until the bandgap circuit of the second voltage source VS2 is turned on and the second input signal Sin2 is provided at a desired level.

[0081] The detailed function of the buffer circuit will be referred to below. Figure 2 and Figure 3 Further description.

[0082] Figure 2An exemplary implementation of the proposed operational amplifier is shown. The operational amplifier 100 herein is implemented using CMOS technology and includes a first PMOS transistor TP1, a second PMOS transistor TP2, a third PMOS transistor TP3, a current source CS, a first current mirror CM1, a second current mirror CM2, and a third current mirror CM3. The current source CS is connected to a high voltage power supply terminal 20 carrying a supply voltage VDD. The first PMOS transistor TP1 includes a control terminal, i.e., a gate terminal, which represents a first input terminal 101. The second PMOS transistor TP2 includes a gate terminal, which represents a second input terminal 102. The respective second terminals (i.e., source terminals) of the first PMOS transistor TP1 and the second PMOS transistor TP2 are connected to each other and to the current source CS. The respective third terminals (i.e., drain terminals) of the first PMOS transistor TP1 and the second PMOS transistor TP2 are connected to each other and to the input terminal 105 of the first current mirror CM1. The first current mirror CM1 includes two NMOS transistors N1 and N2 connected in a current mirror configuration between an input terminal 105 , a reference potential terminal 10 and an output terminal 104 of the first current mirror CM1 , so that the current at the input terminal 105 is mirrored toward the output terminal 104 .

[0083] The third PMOS transistor TP3 is coupled to the current source CS and the source terminals of the second PMOS transistor TP2 and the first PMOS transistor TP1 through its source terminal. The drain terminal of the third PMOS transistor TP3 is coupled to the input terminal 106 of the second current mirror CM2. The second current mirror CM2 includes two NMOS transistors N3 and N4. The NMOS transistors N3 and N4 are coupled to each other in a current mirror configuration between the input terminal 106, the reference potential terminal 10 and the output terminal 107 of the second current mirror CM2, so that the current at the input terminal 106 is mirrored to the output terminal 107 of the second current mirror CM2. The third current mirror CM3 includes two PMOS transistors P1, P2, which are coupled in a current mirror configuration between the input terminal 108, the high voltage power supply terminal 20 and the output terminal 109 of the third current mirror CM3. The input terminal 108 of the third current mirror CM3 is connected to the output terminal 107 of the second current mirror CM2. The output terminal 109 of the third current mirror CM3 is connected to the output terminal 104 of the operational amplifier 100 , so that the current at the input terminal 108 of the third current mirror CM3 is mirrored from the transistor P1 to the output terminal 109 of the third current mirror CM3 , ie, the output terminal 104 , via the transistor P2 .

[0084] In addition to the differential pair of the second PMOS transistor TP2 and the third PMOS transistor TP3, the first PMOS transistor TP1 is added to achieve the selection of the lower input voltage provided to the gate terminal of the first PMOS transistor TP1 and the gate terminal of the second PMOS transistor TP2 by the first input signal Sin1 and the second input signal Sin2, respectively. The transistor with the lower gate voltage among these transistors will be turned on more. Therefore, the transistor controls the source voltage of the differential pair. The common source voltage (that is, the source voltage of transistors TP1, TP2 and TP3) is one source-gate voltage higher than the lowest gate voltage. This is because if something disturbs the common source node and the voltage on the node increases, the PMOS transistor with the lowest gate voltage will be turned on more and pull it back. If the voltage on the node decreases, all PMOS transistors will be turned off and the node will be recharged. In short, the common source node of the three PMOS transistors TP1, TP2 and TP3 is one source-gate voltage higher than the lowest gate terminal of these PMOS transistors. At this time, the source gate voltage on the other two transistors with higher gate voltages will be lower, so they will not be fully turned on. Therefore, the current provided by the current source CS flows through the PMOS transistor with the lowest gate voltage. Due to the configuration of the operational amplifier 100 (achieved by connecting the output terminal 104 to the third input terminal 103), the output terminal 104 follows the first input terminal 101 or the second input terminal 102. This causes two PMOS transistors (i.e., one of the two p-side PMOS transistors TP1 and TP2 and the n-side PMOS TP3) to have low voltages on their respective gate terminals, which essentially separates the current from the current source CS. The input of the remaining PMOS on the p-side is essentially ignored.

[0085] In other words, in the case where the first input 101 is lower than the second input 102 and the third input 103, the current flows from the current source CS through the first PMOS transistor TP1, is mirrored in the first current mirror CM1 and pulls the output terminal 104 to the level of the first input terminal 101. This occurs during the first operation mode. If the second input 102 is lower than the first input 101 and the third input 103, the current from the current source CS flows through the second PMOS transistor TP2, is mirrored in the first current mirror CM1 and pulls the output terminal 104 down to the level of the voltage component of the second input signal Sin2 at the second input terminal 102. This occurs during the second operation mode.

[0086] Figure 3 An exemplary signal diagram is shown. Figure 1 and Figure 2FIG. 4 is a diagram showing a time-dependent variation process of voltage components of a first input signal Sin, a second input signal Sin2, a floating reference signal Sfgnd and a power supply voltage VDD in a circuit.

[0087] At time point t0, the supply voltage VDD is switched on. The first input signal Sin1 and the second input signal Sin2 start to ramp up. Due to the slower startup process of the bandgap circuit providing the second input signal Sin2, in the first operation mode Op1, the signals follow or track the supply voltage VDD. After an initial delay, for example until the supply voltage VDD has a sufficiently high level to turn on the PMOS transistor of the first voltage source, the first input signal Sin1 also follows the supply voltage VDD at time point t1, with its voltage component taking a value lower than the supply voltage VDD by at least one threshold voltage of at least one PMOS transistor. The floating reference signal Sfgnd, in particular its voltage component, follows the level of the first input signal Sin1. A small delay represented by the difference between t1 and t2 may occur before the floating reference signal Sfgnd tracks the first input signal Sin1. At time point t3, the supply voltage VDD reaches its final value, for example 3.3V. A typical value of the threshold voltage is, for example, 0.5V. Therefore, at time point t3, the first input signal Sin1 and the floating reference signal Sfgnd have a voltage level of about 2.8V in this example. At time point t4 (still occurring in the first mode Op1), the bandgap circuit of the second voltage source starts to operate, which causes the voltage level of the second input Sin2 to decrease. At time point t5, the voltage level of the second input signal Sin2 crosses the level of the first input signal Sin1, which marks the end of the first mode Op1. From time point t5, the buffer circuit operates in the second mode Op2, in which the second input signal Sin2 is provided as the floating reference signal Sfgnd. At time point t6, the bandgap circuit of the second voltage source is fully operational and provides the second input signal Sin2 at the desired voltage level. In an example, the voltage level of the second input signal Sin2 is about 1.5V lower than the supply voltage VDD. In this example, the voltage component of the floating reference signal is 1.8V.

[0088] During the circuit startup, a coarse reference signal Sin1 provided by the first voltage source is used and provided as a floating reference signal Sfgnd in the first mode Op1. Once the bandgap circuit of the second voltage source has a significant current flow and can provide the second input signal Sin2 at a reasonable level (this means starting from the time point t5), the second input signal Sin2 is provided as a floating reference signal Sfgnd.

[0089] This ensures that the PMOS transistor whose gate terminal is controlled by the floating reference signal Sfgnd can be turned on during circuit startup without damaging the device.

[0090] Figure 4 An exemplary implementation of the buffer circuit proposed in the exemplary application circuit is shown. In this example, the first voltage source VS1 is implemented as a series connection of a PMOS transistor M6 and a current source CS1, which are connected between the high voltage supply terminal 20 and the ground potential terminal 10. The PMOS transistor M6 is configured as a diode-connected transistor. The first signal Sin1 is provided at the connection point between the current source CS1 and the gate and drain terminals of the PMOS transistor M6.

[0091] The second voltage source VS2 in this example is implemented as a bandgap circuit, which is configured to generate the second input signal Sin2, as known to those skilled in the art. The bandgap circuit of the second voltage source VS2 may also have a bootstrap core and a bandgap startup circuit BGS, such as Figure 4 shown.

[0092] The purpose of the circuit in this example is to control the gate terminal of the PMOS transistor MF as early as possible from the power-up of the supply voltage VDD. To this end, the floating reference signal Sfgnd generated by the proposed buffer circuit 100 is passed to the gate terminal of the PMOS transistor MF via the level shifter LS and the inverter INV, and the PMOS transistor MF represents an example of at least one PMOS transistor. By turning on at least one PMOS transistor MF, even during startup, as long as the LDO connected downstream is disabled, the pass gate transistor MG of the LDO is turned off in a controlled manner.

[0093] Figure 5 Another exemplary embodiment of the buffer circuit proposed in the exemplary application circuit is shown. Except for the implementation of the first voltage source VS1, this embodiment is similar to Figure 4 1. The embodiment shown in FIG. 1 is consistent with that shown in FIG. 1. In this example, the first voltage source VS1 is implemented as a series connection of a PMOS transistor M61, a PMOS transistor M6 and a current source CS1, which are connected between the high voltage supply terminal 20 and the ground potential terminal 10. The PMOS transistors M6 and M61 are both configured as diode-connected transistors. The first signal Sin1 is provided at a connection point between the current source CS1 and the gate and drain terminals of the PMOS transistor M6.

[0094] Figure 6 An exemplary implementation of the proposed method is shown. The method for providing a floating reference signal comprises the following steps:

[0095] S1: Receive the first input signal,

[0096] S2: receiving a second input signal, and

[0097] S3: Provide the first input signal or the second input signal so that a lower one of the first input signal and the second input signal is provided as a floating reference signal.

[0098] The method may be implemented by a buffer circuit according to one of the above embodiments.

[0099] The method may further comprise the following steps:

[0100] S31: operating in the first operating mode, and / or

[0101] S32: Operate in the second operation mode.

[0102] In the first mode, which occurs during power-up of the supply voltage, the first input signal is provided as a floating reference signal, and in the second mode, the second input signal is provided as a floating reference signal, as described above.

[0103] In the first mode, perform the following steps:

[0104] turning on the high voltage power supply and ramping up the supply voltage provided by the high voltage power supply,

[0105] generating a first input signal and a second input signal using a supply voltage,

[0106] ramping up a first input signal and providing it as a floating reference signal, the first input signal comprising a voltage component having a value lower than a supply voltage by at least a threshold voltage, wherein the threshold voltage represents a threshold voltage of at least one transistor controlled by the floating reference signal,

[0107] The second input signal is ramped up until its voltage component approximately reaches the value of the supply voltage, and then the voltage component of the second input signal is ramped down to the level of the voltage component of the first input signal.

[0108] In the second mode, perform the following steps:

[0109] providing a first input signal, the value of a voltage component of which is at least a threshold voltage lower than the supply voltage,

[0110] further ramping down the voltage component of the second input signal to a value lower than the value of the voltage component of the first input signal in the second mode, and

[0111] Provide a second input signal as a floating reference signal,

[0112] The second operation mode follows the first operation mode.

[0113] It should be understood that the present invention is not limited to the disclosed embodiments and what is particularly shown and described above. On the contrary, the features described in the separate dependent claims or the description may be advantageously combined. In addition, the scope of the present invention includes those changes and modifications that are obvious to those skilled in the art and fall within the scope of the appended claims. The term "comprising" used in the claims or the description does not exclude other elements or steps of the corresponding features or processes. Where the terms "a" or "an" are used with features, they do not exclude a plurality of such features. In addition, any figure marks in the claims should not be interpreted as limiting the scope.

Claims

1. A buffer circuit for providing a floating reference signal, the buffer circuit comprising an operational amplifier (100), the operational amplifier comprising: - a first input terminal (101), the first input terminal representing a non-inverting input terminal, the first input terminal being configured to receive a first input signal (Sin1), - a second input terminal (102), the second input terminal representing another non-inverting input terminal, the second input terminal being configured to receive a second input signal (Sin2), - a third input terminal (103), said third input terminal representing an inverting input terminal, and - an output terminal (104), which forms the output of the buffer circuit, - wherein the operational amplifier (100) is configured as a voltage follower, the output terminal (104) of the operational amplifier is connected to the third input terminal (103) of the operational amplifier, - wherein the buffer circuit is configured to provide the first input signal (Sin1) or the second input signal (Sin2) at its output terminal (104), so that the lower one of the first input signal (Sin1) and the second input signal (Sin2) is provided as the floating reference signal (Sfgnd).

2. The buffer circuit according to claim 1, in, The floating reference signal (Sfgnd) is configured to control at least one transistor (MF) coupled to a high voltage supply terminal (20), wherein a supply voltage (VDD) on the high voltage supply terminal (20) exceeds an operating range of the transistor.

3. The buffer circuit according to claim 2, in, The buffer circuit is configured to operate in a first operating mode (Op1) or a second operating mode (Op2), wherein in the first mode, the first input signal (Sin1) is buffered and provided as the floating reference signal (Sfgnd), and wherein, in the second mode, the second input signal (Sin2) is buffered and provided as the floating reference signal (Sfgnd).

4. The buffer circuit according to claim 3, in, In the first mode (Op1): The supply voltage (VDD) is configured to be turned on, and the first input signal (Sin1) and the second input signal (Sin2) are configured to start after the supply voltage (VDD), wherein the voltage component of the first input signal (Sin1) is configured to obtain a value that is lower than the supply voltage and at least one threshold voltage of the at least one transistor (MF) after an initial delay, and wherein the voltage component of the second input signal (Sin2) is configured to track the supply voltage and then decrease to the level of the voltage component of the first input signal (Sin1).

5. The buffer circuit according to claim 3 or 4, in, In the second mode (Op2): The voltage component of the first input signal (Sin1) is configured to obtain a value lower than the supply voltage by at least one threshold voltage of the at least one transistor (MF), and The voltage component of the second input signal (Sin2) is adjusted to a value lower than the value of the voltage component of the first input signal (Sin1) in the second mode.

6. The buffer circuit according to any one of claims 1 to 4, in, The first input signal (Sin1) is configured to be provided by a first voltage source (VS1), the first voltage source comprising one of the following: at least one other transistor configured as a diode-connected transistor, a pn diode or a resistor, Wherein, the second signal (Sin2) is configured to be provided by a second voltage source (VS2) including a bandgap circuit.

7. The buffer circuit according to any one of claims 1 to 4, in, The operational amplifier (100) comprises: a first transistor (TP1), the first transistor comprising a control terminal representing the first input terminal (101) of the operational amplifier (100), a second transistor (TP2), the second transistor comprising a control terminal representing the second input terminal (102) of the operational amplifier (100), a third transistor (TP3), said third transistor comprising a control terminal representing said third input terminal (103) of said operational amplifier (100), a current source (CS) connected between the high voltage supply terminal (20) and respective second terminals of the first transistor (TP1), the second transistor (TP2) and the third transistor (TP3), a first current mirror (CM1) comprising an input terminal (105) connected to respective third terminals of the first transistor (TP1) and the second transistor (TP2), and an output terminal representing the output terminal (104) of the operational amplifier (100), and a second current mirror (CM2) comprising an input terminal (106) connected to a third terminal of the third transistor (TP3), and an output terminal (107), A third current mirror (CM3), the third current mirror comprising an input terminal (108) connected to the output terminal (107) of the second current mirror (CM2), and an output terminal (109) connected to the output end (104) of the operational amplifier (100).

8. The buffer circuit according to claim 7, in, The first current mirror (CM1) and the second current mirror (CM2) each include at least two transistors (N1, N2, N3, N4) of the same type, and The third current mirror (CM3) includes at least two transistors (P1, P2) whose types are complementary to those of the transistors of the first current mirror and the second current mirror.

9. A voltage generating circuit, the voltage generating circuit comprising: The buffer circuit according to any one of claims 1 to 8, a first voltage source (VS1), the first voltage source being used to provide the first input signal (Sin1), the first voltage source (VS1) being connected to the first input terminal (101) of the operational amplifier (100) of the buffer circuit, and A second voltage source (VS2) for providing the second input signal (Sin2), the second voltage source (VS2) being coupled to the second input terminal (102) of the operational amplifier (100) of the buffer circuit.

10. A method for providing a floating reference signal, the method comprising the following steps: receiving (S1) a first input signal (Sin1), receiving (S2) a second input signal (Sin2), and The first input signal (Sin1) or the second input signal (Sin2) is provided (S3) such that a lower one of the first input signal (Sin1) and the second input signal (Sin2) is provided as the floating reference signal (Sfgnd).

11. The method according to claim 10, further comprising: In the first operation mode (S31): turning on a high voltage power supply and ramping up a supply voltage (VDD) provided by the high voltage power supply, generating the first input signal (Sin1) and the second input signal (Sin2) using the supply voltage, The first input signal (Sin1) is ramped up and provided as the floating reference signal (Sfgnd), the first input signal (Sin1) comprising a voltage component whose value is at least one threshold voltage lower than the supply voltage, wherein The threshold voltage represents a threshold voltage of at least one transistor (MF) controlled by the floating reference signal (Sfgnd), The second input signal (Sin2) is ramped up until its voltage component approximately reaches the value of the supply voltage and then the voltage component of the second input signal (Sin2) is ramped down to the level of the voltage component of the first input signal (Sin1).

12. The method according to claim 11, further comprising: In the second operation mode (S32): providing the first input signal (Sin1), the value of the voltage component of which is at least one threshold voltage lower than the supply voltage, further ramping down the voltage component of the second input signal (Sin2) to a value lower than the value of the voltage component of the first input signal (Sin1) in the second mode, and providing the second input signal (Sin2) as the floating reference signal (Sfgnd), in, The second operating mode is subsequent to the first operating mode.

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